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From: Simon Glass <sjg@chromium.org>
To: U-Boot Mailing List <u-boot@lists.denx.de>
Cc: "Ilias Apalodimas" <ilias.apalodimas@linaro.org>,
	"Tom Rini" <trini@konsulko.com>,
	"François Ozog" <francois.ozog@linaro.org>,
	"Heinrich Schuchardt" <xypron.glpk@gmx.de>,
	"Bill Mills" <bill.mills@linaro.org>,
	"Simon Glass" <sjg@chromium.org>,
	"Albert Aribaud" <albert.u.boot@aribaud.net>,
	"Chia-Wei Wang" <chiawei_wang@aspeedtech.com>
Subject: [PATCH v2 06/16] passage: arm: Accept a passage from the previous phase
Date: Mon, 17 Jan 2022 08:04:18 -0700	[thread overview]
Message-ID: <20220117080353.v2.6.I56d9d06e5d74724c963eaffbbe1c2aa400b60bb8@changeid> (raw)
In-Reply-To: <20220117150428.1580273-1-sjg@chromium.org>

Accept a bloblist and control devicetree from a previous phase in
registers r0 and r1

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2:
- Use three registers instead of two for the entry

 arch/arm/cpu/armv7/start.S | 7 ++++++-
 arch/arm/lib/crt0.S        | 5 +++++
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 698e15b8e18..494f4abdb1f 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -36,6 +36,11 @@
 #endif
 
 reset:
+	# Keep passage information in case it is provided
+	mov	r6, r1
+	mov	r7, r2
+	mov	r8, r3
+
 	/* Allow the board to save important registers */
 	b	save_boot_params
 save_boot_params_ret:
@@ -124,7 +129,7 @@ switch_to_hypervisor_ret:
 	bl	cpu_init_crit
 #endif
 #endif
-
+	# Note: r6-r8 are available to _main in case standard passage is used
 	bl	_main
 
 /*------------------------------------------------------------------------------*/
diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S
index ba312901f33..68282ebfd02 100644
--- a/arch/arm/lib/crt0.S
+++ b/arch/arm/lib/crt0.S
@@ -117,6 +117,11 @@ ENTRY(_main)
 	CLEAR_BSS
 #endif
 
+#if CONFIG_IS_ENABLED(PASSAGE_IN)
+	str	r6, [r9, #GD_PASSAGE_MACH]
+	str	r7, [r9, #GD_PASSAGE_DTB]
+	str	r8, [r9, #GD_PASSAGE_BLOBLIST]
+#endif
 	mov	r0, #0
 	bl	board_init_f
 
-- 
2.34.1.703.g22d0c6ccf7-goog


  parent reply	other threads:[~2022-01-17 15:05 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-17 15:04 [PATCH v2 00/16] passage: Define a standard for firmware data flow Simon Glass
2022-01-17 15:04 ` [PATCH v2 01/16] spl: Tidy up the header includes Simon Glass
2022-01-17 15:04 ` [PATCH v2 02/16] arm: qemu: Add an SPL build Simon Glass
2022-01-17 15:04 ` [PATCH v2 03/16] spl: Rename jump_to_image_no_args() Simon Glass
2022-01-17 15:04 ` [PATCH v2 04/16] passage: Support an incoming passage Simon Glass
2022-01-17 15:04 ` [PATCH v2 05/16] passage: Support a control devicetree Simon Glass
2022-01-17 15:04 ` Simon Glass [this message]
2022-01-17 15:04 ` [PATCH v2 07/16] passage: spl: Support adding the dtb to the passage bloblist Simon Glass
2022-01-17 15:04 ` [PATCH v2 08/16] passage: spl: Support passing the passage to U-Boot Simon Glass
2022-01-17 15:04 ` [PATCH v2 09/16] passage: arm: Add the arch-specific standard passage impl Simon Glass
2022-01-17 15:04 ` [PATCH v2 10/16] passage: Add a qemu test for ARM Simon Glass
2022-01-17 15:04 ` [PATCH v2 11/16] sandbox: Add a way of checking structs for standard passage Simon Glass
2022-01-17 15:04 ` [PATCH v2 12/16] passage: Add documentation Simon Glass
2022-01-17 16:39   ` Mark Kettenis
2022-01-17 15:04 ` [PATCH v2 13/16] passage: Add docs for spl_handoff Simon Glass
2022-01-17 15:04 ` [PATCH v2 14/16] x86: Move Intel GNVS file into the common include directory Simon Glass
2022-01-17 15:04 ` [PATCH v2 15/16] passage: Add checks for pre-existing blobs Simon Glass
2022-01-17 15:04 ` [PATCH v2 16/16] WIP: RFC: Add a gitlab test Simon Glass

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