All of lore.kernel.org
 help / color / mirror / Atom feed
From: Anup Patel <anup@brainfault.org>
To: Peter Maydell <peter.maydell@linaro.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: qemu-riscv@nongnu.org, Frank Chang <frank.chang@sifive.com>,
	Anup Patel <anup@brainfault.org>,
	qemu-devel@nongnu.org,
	Alistair Francis <alistair.francis@wdc.com>,
	Atish Patra <atishp@atishpatra.org>,
	Bin Meng <bmeng.cn@gmail.com>
Subject: [PATCH v7 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs
Date: Mon, 17 Jan 2022 18:58:26 +0530	[thread overview]
Message-ID: <20220117132826.426418-24-anup@brainfault.org> (raw)
In-Reply-To: <20220117132826.426418-1-anup@brainfault.org>

From: Anup Patel <anup.patel@wdc.com>

To facilitate software development of RISC-V systems with large number
of HARTs, we increase the maximum number of allowed CPUs to 512 (2^9).

We also add a detailed source level comments about limit defines which
impact the physical address space utilization.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
 hw/riscv/virt.c         | 10 ++++++++++
 include/hw/riscv/virt.h |  2 +-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 73b2be7b60..f9cf7551b4 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -44,6 +44,16 @@
 #include "hw/pci-host/gpex.h"
 #include "hw/display/ramfb.h"
 
+/*
+ * The virt machine physical address space used by some of the devices
+ * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets,
+ * number of CPUs, and number of IMSIC guest files.
+ *
+ * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS,
+ * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization
+ * of virt machine physical address space.
+ */
+
 #define VIRT_IMSIC_GROUP_MAX_SIZE      (1U << IMSIC_MMIO_GROUP_MIN_SHIFT)
 #if VIRT_IMSIC_GROUP_MAX_SIZE < \
     IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 7898c574af..78f450eb60 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -24,7 +24,7 @@
 #include "hw/block/flash.h"
 #include "qom/object.h"
 
-#define VIRT_CPUS_MAX_BITS             3
+#define VIRT_CPUS_MAX_BITS             9
 #define VIRT_CPUS_MAX                  (1 << VIRT_CPUS_MAX_BITS)
 #define VIRT_SOCKETS_MAX_BITS          2
 #define VIRT_SOCKETS_MAX               (1 << VIRT_SOCKETS_MAX_BITS)
-- 
2.25.1



WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <anup@brainfault.org>
To: Peter Maydell <peter.maydell@linaro.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Atish Patra <atishp@atishpatra.org>,
	Anup Patel <anup@brainfault.org>, Bin Meng <bmeng.cn@gmail.com>,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
	Alistair Francis <alistair.francis@wdc.com>,
	Frank Chang <frank.chang@sifive.com>
Subject: [PATCH v7 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs
Date: Mon, 17 Jan 2022 18:58:26 +0530	[thread overview]
Message-ID: <20220117132826.426418-24-anup@brainfault.org> (raw)
In-Reply-To: <20220117132826.426418-1-anup@brainfault.org>

From: Anup Patel <anup.patel@wdc.com>

To facilitate software development of RISC-V systems with large number
of HARTs, we increase the maximum number of allowed CPUs to 512 (2^9).

We also add a detailed source level comments about limit defines which
impact the physical address space utilization.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
 hw/riscv/virt.c         | 10 ++++++++++
 include/hw/riscv/virt.h |  2 +-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 73b2be7b60..f9cf7551b4 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -44,6 +44,16 @@
 #include "hw/pci-host/gpex.h"
 #include "hw/display/ramfb.h"
 
+/*
+ * The virt machine physical address space used by some of the devices
+ * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets,
+ * number of CPUs, and number of IMSIC guest files.
+ *
+ * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS,
+ * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization
+ * of virt machine physical address space.
+ */
+
 #define VIRT_IMSIC_GROUP_MAX_SIZE      (1U << IMSIC_MMIO_GROUP_MIN_SHIFT)
 #if VIRT_IMSIC_GROUP_MAX_SIZE < \
     IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 7898c574af..78f450eb60 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -24,7 +24,7 @@
 #include "hw/block/flash.h"
 #include "qom/object.h"
 
-#define VIRT_CPUS_MAX_BITS             3
+#define VIRT_CPUS_MAX_BITS             9
 #define VIRT_CPUS_MAX                  (1 << VIRT_CPUS_MAX_BITS)
 #define VIRT_SOCKETS_MAX_BITS          2
 #define VIRT_SOCKETS_MAX               (1 << VIRT_SOCKETS_MAX_BITS)
-- 
2.25.1



  parent reply	other threads:[~2022-01-17 14:57 UTC|newest]

Thread overview: 60+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-17 13:28 [PATCH v7 00/23] QEMU RISC-V AIA support Anup Patel
2022-01-17 13:28 ` Anup Patel
2022-01-17 13:28 ` [PATCH v7 01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode Anup Patel
2022-01-17 13:28   ` Anup Patel
2022-01-17 13:28 ` [PATCH v7 02/23] target/riscv: Implement SGEIP bit in hip and hie CSRs Anup Patel
2022-01-17 13:28   ` Anup Patel
2022-01-17 13:28 ` [PATCH v7 03/23] target/riscv: Implement hgeie and hgeip CSRs Anup Patel
2022-01-17 13:28   ` Anup Patel
2022-01-17 13:28 ` [PATCH v7 04/23] target/riscv: Improve delivery of guest external interrupts Anup Patel
2022-01-17 13:28   ` Anup Patel
2022-01-17 13:28 ` [PATCH v7 05/23] target/riscv: Allow setting CPU feature from machine/device emulation Anup Patel
2022-01-17 13:28   ` Anup Patel
2022-01-17 13:28 ` [PATCH v7 06/23] target/riscv: Add AIA cpu feature Anup Patel
2022-01-17 13:28   ` Anup Patel
2022-01-17 13:28 ` [PATCH v7 07/23] target/riscv: Add defines for AIA CSRs Anup Patel
2022-01-17 13:28   ` Anup Patel
2022-01-17 13:28 ` [PATCH v7 08/23] target/riscv: Allow AIA device emulation to set ireg rmw callback Anup Patel
2022-01-17 13:28   ` Anup Patel
2022-01-17 13:28 ` [PATCH v7 09/23] target/riscv: Implement AIA local interrupt priorities Anup Patel
2022-01-17 13:28   ` Anup Patel
2022-01-18  3:34   ` Frank Chang
2022-01-18  3:34     ` Frank Chang
2022-01-18  3:41     ` Anup Patel
2022-01-18  3:41       ` Anup Patel
2022-01-18  3:50       ` Frank Chang
2022-01-18  3:50         ` Frank Chang
2022-01-17 13:28 ` [PATCH v7 10/23] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 Anup Patel
2022-01-17 13:28   ` Anup Patel
2022-01-17 13:28 ` [PATCH v7 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs Anup Patel
2022-01-17 13:28   ` Anup Patel
2022-01-17 13:28 ` [PATCH v7 12/23] target/riscv: Implement AIA interrupt filtering CSRs Anup Patel
2022-01-17 13:28   ` Anup Patel
2022-01-17 13:28 ` [PATCH v7 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs Anup Patel
2022-01-17 13:28   ` Anup Patel
2022-01-17 13:28 ` [PATCH v7 14/23] target/riscv: Implement AIA xiselect and xireg CSRs Anup Patel
2022-01-17 13:28   ` Anup Patel
2022-01-17 13:28 ` [PATCH v7 15/23] target/riscv: Implement AIA IMSIC interface CSRs Anup Patel
2022-01-17 13:28   ` Anup Patel
2022-01-18  4:10   ` Frank Chang
2022-01-18  4:10     ` Frank Chang
2022-01-17 13:28 ` [PATCH v7 16/23] hw/riscv: virt: Use AIA INTC compatible string when available Anup Patel
2022-01-17 13:28   ` Anup Patel
2022-01-17 13:28 ` [PATCH v7 17/23] target/riscv: Allow users to force enable AIA CSRs in HART Anup Patel
2022-01-17 13:28   ` Anup Patel
2022-01-17 13:28 ` [PATCH v7 18/23] hw/intc: Add RISC-V AIA APLIC device emulation Anup Patel
2022-01-17 13:28   ` Anup Patel
2022-01-18  7:43   ` Frank Chang
2022-01-18  7:43     ` Frank Chang
2022-01-17 13:28 ` [PATCH v7 19/23] hw/riscv: virt: Add optional AIA APLIC support to virt machine Anup Patel
2022-01-17 13:28   ` Anup Patel
2022-01-17 13:28 ` [PATCH v7 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation Anup Patel
2022-01-17 13:28   ` Anup Patel
2022-01-18  4:02   ` Frank Chang
2022-01-18  4:02     ` Frank Chang
2022-01-17 13:28 ` [PATCH v7 21/23] hw/riscv: virt: Add optional AIA IMSIC support to virt machine Anup Patel
2022-01-17 13:28   ` Anup Patel
2022-01-17 13:28 ` [PATCH v7 22/23] docs/system: riscv: Document AIA options for " Anup Patel
2022-01-17 13:28   ` Anup Patel
2022-01-17 13:28 ` Anup Patel [this message]
2022-01-17 13:28   ` [PATCH v7 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs Anup Patel

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20220117132826.426418-24-anup@brainfault.org \
    --to=anup@brainfault.org \
    --cc=Alistair.Francis@wdc.com \
    --cc=atishp@atishpatra.org \
    --cc=bmeng.cn@gmail.com \
    --cc=frank.chang@sifive.com \
    --cc=palmer@dabbelt.com \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-riscv@nongnu.org \
    --cc=sagark@eecs.berkeley.edu \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.