[Intel-gfx] [PATCH 00/15] drm/i915: Fix bandwith related cdclk calculations

[Intel-gfx] [PATCH 00/15] drm/i915: Fix bandwith related cdclk calculations

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Fix up the dbuf bandwidth cdclk calculations to match the spec,
and also implement the cdclk based pipe max bandwidth limit.

TODO: intel_bw contains two orthogonal things (qgv vs. cdclk).
      We should probably just split it into two parts to life
      less confusing. But as usual naming is hard so I didn't
      go for that yet...

Ville Syrjälä (15):
  drm/i915: Drop pointless dev_priv argument
  drm/i915: Extract skl_ddb_entry_init()
  drm/i915: Fix plane relative_data_rate calculation
  drm/i915: Introduce skl_plane_ddb_iter
  drm/i915: Extract skl_allocate_plane_ddb()
  drm/i915: Extract skl_crtc_calc_dbuf_bw()
  drm/i915: Tweak plane ddb allocation tracking
  drm/i915: Split plane data_rate into data_rate+data_rate_y
  drm/i915: Pre-calculate plane relative data rate
  drm/i915: Remove total[] and uv_total[] from ddb allocation
  drm/i915: Nuke intel_bw_calc_min_cdclk()
  drm/i915: Round up when calculating display bandwidth requirements
  drm/i915: Properly write lock bw_state when it changes
  drm/i915: Fix DBUF bandwidth vs. cdclk handling
  drm/i915: Add "maximum pipe read bandwidth" checks

 .../gpu/drm/i915/display/intel_atomic_plane.c |  93 ++--
 .../gpu/drm/i915/display/intel_atomic_plane.h |   3 +-
 drivers/gpu/drm/i915/display/intel_bw.c       | 272 ++++++----
 drivers/gpu/drm/i915/display/intel_bw.h       |  12 +-
 drivers/gpu/drm/i915/display/intel_cdclk.c    |  96 ++--
 drivers/gpu/drm/i915/display/intel_cdclk.h    |   2 +
 drivers/gpu/drm/i915/display/intel_display.c  |  17 +-
 .../drm/i915/display/intel_display_debugfs.c  |   4 +-
 .../drm/i915/display/intel_display_types.h    |  16 +-
 drivers/gpu/drm/i915/intel_pm.c               | 471 ++++++------------
 10 files changed, 453 insertions(+), 533 deletions(-)

-- 
2.32.0

[Intel-gfx] [PATCH 01/15] drm/i915: Drop pointless dev_priv argument

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

skl_ddb_entry_init_from_hw() has no need for dev_priv.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 62fde21fac39..7185af0ff205 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4289,8 +4289,7 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
 	return max(num_active == 1 ? 32 : 8, min_ddb_alloc);
 }
 
-static void skl_ddb_entry_init_from_hw(struct drm_i915_private *dev_priv,
-				       struct skl_ddb_entry *entry, u32 reg)
+static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
 {
 	entry->start = REG_FIELD_GET(PLANE_BUF_START_MASK, reg);
 	entry->end = REG_FIELD_GET(PLANE_BUF_END_MASK, reg);
@@ -4311,7 +4310,7 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
 	/* Cursor doesn't support NV12/planar, so no extra calculation needed */
 	if (plane_id == PLANE_CURSOR) {
 		val = intel_uncore_read(&dev_priv->uncore, CUR_BUF_CFG(pipe));
-		skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
+		skl_ddb_entry_init_from_hw(ddb_y, val);
 		return;
 	}
 
@@ -4325,7 +4324,7 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
 
 	if (DISPLAY_VER(dev_priv) >= 11) {
 		val = intel_uncore_read(&dev_priv->uncore, PLANE_BUF_CFG(pipe, plane_id));
-		skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
+		skl_ddb_entry_init_from_hw(ddb_y, val);
 	} else {
 		val = intel_uncore_read(&dev_priv->uncore, PLANE_BUF_CFG(pipe, plane_id));
 		val2 = intel_uncore_read(&dev_priv->uncore, PLANE_NV12_BUF_CFG(pipe, plane_id));
@@ -4334,8 +4333,8 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
 		    drm_format_info_is_yuv_semiplanar(drm_format_info(fourcc)))
 			swap(val, val2);
 
-		skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
-		skl_ddb_entry_init_from_hw(dev_priv, ddb_uv, val2);
+		skl_ddb_entry_init_from_hw(ddb_y, val);
+		skl_ddb_entry_init_from_hw(ddb_uv, val2);
 	}
 }
 
-- 
2.32.0

[Intel-gfx] [PATCH 02/15] drm/i915: Extract skl_ddb_entry_init()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Extract a small helper to populate a ddb entry.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 44 +++++++++++++++++++--------------
 1 file changed, 25 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7185af0ff205..9a9d4acb2988 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4058,6 +4058,15 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
 	return 0;
 }
 
+static u16 skl_ddb_entry_init(struct skl_ddb_entry *entry,
+			      u16 start, u16 end)
+{
+	entry->start = start;
+	entry->end = end;
+
+	return end;
+}
+
 static int intel_dbuf_slice_size(struct drm_i915_private *dev_priv)
 {
 	return INTEL_INFO(dev_priv)->dbuf.size /
@@ -4196,8 +4205,7 @@ skl_crtc_allocate_ddb(struct intel_atomic_state *state, struct intel_crtc *crtc)
 	int ret;
 
 	if (new_dbuf_state->weight[pipe] == 0) {
-		new_dbuf_state->ddb[pipe].start = 0;
-		new_dbuf_state->ddb[pipe].end = 0;
+		skl_ddb_entry_init(&new_dbuf_state->ddb[pipe], 0, 0);
 		goto out;
 	}
 
@@ -4213,8 +4221,10 @@ skl_crtc_allocate_ddb(struct intel_atomic_state *state, struct intel_crtc *crtc)
 	start = ddb_range_size * weight_start / weight_total;
 	end = ddb_range_size * weight_end / weight_total;
 
-	new_dbuf_state->ddb[pipe].start = ddb_slices.start - mbus_offset + start;
-	new_dbuf_state->ddb[pipe].end = ddb_slices.start - mbus_offset + end;
+	skl_ddb_entry_init(&new_dbuf_state->ddb[pipe],
+			   ddb_slices.start - mbus_offset + start,
+			   ddb_slices.start - mbus_offset + end);
+
 out:
 	if (old_dbuf_state->slices[pipe] == new_dbuf_state->slices[pipe] &&
 	    skl_ddb_entry_equal(&old_dbuf_state->ddb[pipe],
@@ -4291,8 +4301,9 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
 
 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
 {
-	entry->start = REG_FIELD_GET(PLANE_BUF_START_MASK, reg);
-	entry->end = REG_FIELD_GET(PLANE_BUF_END_MASK, reg);
+	skl_ddb_entry_init(entry,
+			   REG_FIELD_GET(PLANE_BUF_START_MASK, reg),
+			   REG_FIELD_GET(PLANE_BUF_END_MASK, reg));
 	if (entry->end)
 		entry->end++;
 }
@@ -5154,9 +5165,8 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
 	/* Allocate fixed number of blocks for cursor. */
 	total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
 	alloc_size -= total[PLANE_CURSOR];
-	crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].start =
-		alloc->end - total[PLANE_CURSOR];
-	crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;
+	skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR],
+			   alloc->end - total[PLANE_CURSOR], alloc->end);
 
 	if (total_data_rate == 0)
 		return 0;
@@ -5257,17 +5267,13 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
 			    DISPLAY_VER(dev_priv) >= 11 && uv_total[plane_id]);
 
 		/* Leave disabled planes at (0,0) */
-		if (total[plane_id]) {
-			plane_alloc->start = start;
-			start += total[plane_id];
-			plane_alloc->end = start;
-		}
+		if (total[plane_id])
+			start = skl_ddb_entry_init(plane_alloc, start,
+						   start + total[plane_id]);
 
-		if (uv_total[plane_id]) {
-			uv_plane_alloc->start = start;
-			start += uv_total[plane_id];
-			uv_plane_alloc->end = start;
-		}
+		if (uv_total[plane_id])
+			start = skl_ddb_entry_init(uv_plane_alloc, start,
+						   start + uv_total[plane_id]);
 	}
 
 	/*
-- 
2.32.0

[Intel-gfx] [PATCH 03/15] drm/i915: Fix plane relative_data_rate calculation

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We are currently computing the relative data rates as
src_size * scale_factor where scale_factor is src_size / dst_size.
Thus relative data rate is src_size * src_size / dst_size,
which is just utter nonsense. What we really seem to want is
just a reasonable estimate on how much data will be fetched
which is just src_size. So let's do that instead.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 63 ++-------------------------------
 1 file changed, 2 insertions(+), 61 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9a9d4acb2988..e8fb56f288b4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4373,55 +4373,6 @@ void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
 	intel_display_power_put(dev_priv, power_domain, wakeref);
 }
 
-/*
- * Determines the downscale amount of a plane for the purposes of watermark calculations.
- * The bspec defines downscale amount as:
- *
- * """
- * Horizontal down scale amount = maximum[1, Horizontal source size /
- *                                           Horizontal destination size]
- * Vertical down scale amount = maximum[1, Vertical source size /
- *                                         Vertical destination size]
- * Total down scale amount = Horizontal down scale amount *
- *                           Vertical down scale amount
- * """
- *
- * Return value is provided in 16.16 fixed point form to retain fractional part.
- * Caller should take care of dividing & rounding off the value.
- */
-static uint_fixed_16_16_t
-skl_plane_downscale_amount(const struct intel_crtc_state *crtc_state,
-			   const struct intel_plane_state *plane_state)
-{
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
-	u32 src_w, src_h, dst_w, dst_h;
-	uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
-	uint_fixed_16_16_t downscale_h, downscale_w;
-
-	if (drm_WARN_ON(&dev_priv->drm,
-			!intel_wm_plane_visible(crtc_state, plane_state)))
-		return u32_to_fixed16(0);
-
-	/*
-	 * Src coordinates are already rotated by 270 degrees for
-	 * the 90/270 degree plane rotation cases (to match the
-	 * GTT mapping), hence no need to account for rotation here.
-	 *
-	 * n.b., src is 16.16 fixed point, dst is whole integer.
-	 */
-	src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
-	src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
-	dst_w = drm_rect_width(&plane_state->uapi.dst);
-	dst_h = drm_rect_height(&plane_state->uapi.dst);
-
-	fp_w_ratio = div_fixed16(src_w, dst_w);
-	fp_h_ratio = div_fixed16(src_h, dst_h);
-	downscale_w = max_fixed16(fp_w_ratio, u32_to_fixed16(1));
-	downscale_h = max_fixed16(fp_h_ratio, u32_to_fixed16(1));
-
-	return mul_fixed16(downscale_w, downscale_h);
-}
-
 struct dbuf_slice_conf_entry {
 	u8 active_pipes;
 	u8 dbuf_mask[I915_MAX_PIPES];
@@ -4932,10 +4883,7 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
 {
 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
-	u32 data_rate;
-	u32 width = 0, height = 0;
-	uint_fixed_16_16_t down_scale_amount;
-	u64 rate;
+	int width, height;
 
 	if (!plane_state->uapi.visible)
 		return 0;
@@ -4961,14 +4909,7 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
 		height /= 2;
 	}
 
-	data_rate = width * height;
-
-	down_scale_amount = skl_plane_downscale_amount(crtc_state, plane_state);
-
-	rate = mul_round_up_u32_fixed16(data_rate, down_scale_amount);
-
-	rate *= fb->format->cpp[color_plane];
-	return rate;
+	return width * height * fb->format->cpp[color_plane];
 }
 
 static u64
-- 
2.32.0

[Intel-gfx] [PATCH 04/15] drm/i915: Introduce skl_plane_ddb_iter

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Collect a bit of the stuff used during the plane ddb
allocation into a struct we can pass around.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 97 +++++++++++++++++----------------
 1 file changed, 49 insertions(+), 48 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e8fb56f288b4..cd1b5f09f241 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5066,6 +5066,13 @@ static bool icl_need_wm1_wa(struct drm_i915_private *i915,
 	       (IS_DISPLAY_VER(i915, 12, 13) && plane_id == PLANE_CURSOR);
 }
 
+struct skl_plane_ddb_iter {
+	u64 data_rate;
+	u16 total[I915_MAX_PLANES];
+	u16 uv_total[I915_MAX_PLANES];
+	u16 start, size;
+};
+
 static int
 skl_allocate_plane_ddb(struct intel_atomic_state *state,
 		       struct intel_crtc *crtc)
@@ -5077,10 +5084,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
 		intel_atomic_get_new_dbuf_state(state);
 	const struct skl_ddb_entry *alloc = &dbuf_state->ddb[crtc->pipe];
 	int num_active = hweight8(dbuf_state->active_pipes);
-	u16 alloc_size, start = 0;
-	u16 total[I915_MAX_PLANES] = {};
-	u16 uv_total[I915_MAX_PLANES] = {};
-	u64 total_data_rate;
+	struct skl_plane_ddb_iter iter = {};
 	enum plane_id plane_id;
 	u32 blocks;
 	int level;
@@ -5093,23 +5097,21 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
 		return 0;
 
 	if (DISPLAY_VER(dev_priv) >= 11)
-		total_data_rate =
-			icl_get_total_relative_data_rate(state, crtc);
+		iter.data_rate = icl_get_total_relative_data_rate(state, crtc);
 	else
-		total_data_rate =
-			skl_get_total_relative_data_rate(state, crtc);
+		iter.data_rate = skl_get_total_relative_data_rate(state, crtc);
 
-	alloc_size = skl_ddb_entry_size(alloc);
-	if (alloc_size == 0)
+	iter.size = skl_ddb_entry_size(alloc);
+	if (iter.size == 0)
 		return 0;
 
 	/* Allocate fixed number of blocks for cursor. */
-	total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
-	alloc_size -= total[PLANE_CURSOR];
+	iter.total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
+	iter.size -= iter.total[PLANE_CURSOR];
 	skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR],
-			   alloc->end - total[PLANE_CURSOR], alloc->end);
+			   alloc->end - iter.total[PLANE_CURSOR], alloc->end);
 
-	if (total_data_rate == 0)
+	if (iter.data_rate == 0)
 		return 0;
 
 	/*
@@ -5123,7 +5125,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
 				&crtc_state->wm.skl.optimal.planes[plane_id];
 
 			if (plane_id == PLANE_CURSOR) {
-				if (wm->wm[level].min_ddb_alloc > total[PLANE_CURSOR]) {
+				if (wm->wm[level].min_ddb_alloc > iter.total[PLANE_CURSOR]) {
 					drm_WARN_ON(&dev_priv->drm,
 						    wm->wm[level].min_ddb_alloc != U16_MAX);
 					blocks = U32_MAX;
@@ -5136,8 +5138,8 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
 			blocks += wm->uv_wm[level].min_ddb_alloc;
 		}
 
-		if (blocks <= alloc_size) {
-			alloc_size -= blocks;
+		if (blocks <= iter.size) {
+			iter.size -= blocks;
 			break;
 		}
 	}
@@ -5146,7 +5148,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
 		drm_dbg_kms(&dev_priv->drm,
 			    "Requested display configuration exceeds system DDB limitations");
 		drm_dbg_kms(&dev_priv->drm, "minimum required %d/%d\n",
-			    blocks, alloc_size);
+			    blocks, iter.size);
 		return -EINVAL;
 	}
 
@@ -5158,7 +5160,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
 	for_each_plane_id_on_crtc(crtc, plane_id) {
 		const struct skl_plane_wm *wm =
 			&crtc_state->wm.skl.optimal.planes[plane_id];
-		u64 rate;
+		u64 data_rate;
 		u16 extra;
 
 		if (plane_id == PLANE_CURSOR)
@@ -5168,32 +5170,30 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
 		 * We've accounted for all active planes; remaining planes are
 		 * all disabled.
 		 */
-		if (total_data_rate == 0)
+		if (iter.data_rate == 0)
 			break;
 
-		rate = crtc_state->plane_data_rate[plane_id];
-		extra = min_t(u16, alloc_size,
-			      DIV64_U64_ROUND_UP(alloc_size * rate,
-						 total_data_rate));
-		total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
-		alloc_size -= extra;
-		total_data_rate -= rate;
+		data_rate = crtc_state->plane_data_rate[plane_id];
+		extra = min_t(u16, iter.size,
+			      DIV64_U64_ROUND_UP(iter.size * data_rate, iter.data_rate));
+		iter.total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
+		iter.size -= extra;
+		iter.data_rate -= data_rate;
 
-		if (total_data_rate == 0)
+		if (iter.data_rate == 0)
 			break;
 
-		rate = crtc_state->uv_plane_data_rate[plane_id];
-		extra = min_t(u16, alloc_size,
-			      DIV64_U64_ROUND_UP(alloc_size * rate,
-						 total_data_rate));
-		uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
-		alloc_size -= extra;
-		total_data_rate -= rate;
+		data_rate = crtc_state->uv_plane_data_rate[plane_id];
+		extra = min_t(u16, iter.size,
+			      DIV64_U64_ROUND_UP(iter.size * data_rate, iter.data_rate));
+		iter.uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
+		iter.size -= extra;
+		iter.data_rate -= data_rate;
 	}
-	drm_WARN_ON(&dev_priv->drm, alloc_size != 0 || total_data_rate != 0);
+	drm_WARN_ON(&dev_priv->drm, iter.size != 0 || iter.data_rate != 0);
 
 	/* Set the actual DDB start/end points for each plane */
-	start = alloc->start;
+	iter.start = alloc->start;
 	for_each_plane_id_on_crtc(crtc, plane_id) {
 		struct skl_ddb_entry *plane_alloc =
 			&crtc_state->wm.skl.plane_ddb_y[plane_id];
@@ -5205,16 +5205,16 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
 
 		/* Gen11+ uses a separate plane for UV watermarks */
 		drm_WARN_ON(&dev_priv->drm,
-			    DISPLAY_VER(dev_priv) >= 11 && uv_total[plane_id]);
+			    DISPLAY_VER(dev_priv) >= 11 && iter.uv_total[plane_id]);
 
 		/* Leave disabled planes at (0,0) */
-		if (total[plane_id])
-			start = skl_ddb_entry_init(plane_alloc, start,
-						   start + total[plane_id]);
+		if (iter.total[plane_id])
+			iter.start = skl_ddb_entry_init(plane_alloc, iter.start,
+							iter.start + iter.total[plane_id]);
 
-		if (uv_total[plane_id])
-			start = skl_ddb_entry_init(uv_plane_alloc, start,
-						   start + uv_total[plane_id]);
+		if (iter.uv_total[plane_id])
+			iter.start = skl_ddb_entry_init(uv_plane_alloc, iter.start,
+							iter.start + iter.uv_total[plane_id]);
 	}
 
 	/*
@@ -5229,7 +5229,8 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
 				&crtc_state->wm.skl.optimal.planes[plane_id];
 
 			skl_check_nv12_wm_level(&wm->wm[level], &wm->uv_wm[level],
-						total[plane_id], uv_total[plane_id]);
+						iter.total[plane_id],
+						iter.uv_total[plane_id]);
 
 			if (icl_need_wm1_wa(dev_priv, plane_id) &&
 			    level == 1 && wm->wm[0].enable) {
@@ -5248,9 +5249,9 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
 		struct skl_plane_wm *wm =
 			&crtc_state->wm.skl.optimal.planes[plane_id];
 
-		skl_check_wm_level(&wm->trans_wm, total[plane_id]);
-		skl_check_wm_level(&wm->sagv.wm0, total[plane_id]);
-		skl_check_wm_level(&wm->sagv.trans_wm, total[plane_id]);
+		skl_check_wm_level(&wm->trans_wm, iter.total[plane_id]);
+		skl_check_wm_level(&wm->sagv.wm0, iter.total[plane_id]);
+		skl_check_wm_level(&wm->sagv.trans_wm, iter.total[plane_id]);
 	}
 
 	return 0;
-- 
2.32.0

[Intel-gfx] [PATCH 05/15] drm/i915: Extract skl_allocate_plane_ddb()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Replace some copy-pasta with a function.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 41 +++++++++++++++++++--------------
 1 file changed, 24 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index cd1b5f09f241..93ff07f6ef26 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5073,9 +5073,24 @@ struct skl_plane_ddb_iter {
 	u16 start, size;
 };
 
+static u16
+skl_allocate_plane_ddb(struct skl_plane_ddb_iter *iter,
+		       const struct skl_wm_level *wm,
+		       u64 data_rate)
+{
+	u16 extra;
+
+	extra = min_t(u16, iter->size,
+		      DIV64_U64_ROUND_UP(iter->size * data_rate, iter->data_rate));
+	iter->size -= extra;
+	iter->data_rate -= data_rate;
+
+	return wm->min_ddb_alloc + extra;
+}
+
 static int
-skl_allocate_plane_ddb(struct intel_atomic_state *state,
-		       struct intel_crtc *crtc)
+skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
+			    struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct intel_crtc_state *crtc_state =
@@ -5160,8 +5175,6 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
 	for_each_plane_id_on_crtc(crtc, plane_id) {
 		const struct skl_plane_wm *wm =
 			&crtc_state->wm.skl.optimal.planes[plane_id];
-		u64 data_rate;
-		u16 extra;
 
 		if (plane_id == PLANE_CURSOR)
 			continue;
@@ -5173,22 +5186,16 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
 		if (iter.data_rate == 0)
 			break;
 
-		data_rate = crtc_state->plane_data_rate[plane_id];
-		extra = min_t(u16, iter.size,
-			      DIV64_U64_ROUND_UP(iter.size * data_rate, iter.data_rate));
-		iter.total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
-		iter.size -= extra;
-		iter.data_rate -= data_rate;
+		iter.total[plane_id] =
+			skl_allocate_plane_ddb(&iter, &wm->wm[level],
+					       crtc_state->plane_data_rate[plane_id]);
 
 		if (iter.data_rate == 0)
 			break;
 
-		data_rate = crtc_state->uv_plane_data_rate[plane_id];
-		extra = min_t(u16, iter.size,
-			      DIV64_U64_ROUND_UP(iter.size * data_rate, iter.data_rate));
-		iter.uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
-		iter.size -= extra;
-		iter.data_rate -= data_rate;
+		iter.uv_total[plane_id] =
+			skl_allocate_plane_ddb(&iter, &wm->uv_wm[level],
+					       crtc_state->uv_plane_data_rate[plane_id]);
 	}
 	drm_WARN_ON(&dev_priv->drm, iter.size != 0 || iter.data_rate != 0);
 
@@ -6136,7 +6143,7 @@ skl_compute_ddb(struct intel_atomic_state *state)
 
 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
 					    new_crtc_state, i) {
-		ret = skl_allocate_plane_ddb(state, crtc);
+		ret = skl_crtc_allocate_plane_ddb(state, crtc);
 		if (ret)
 			return ret;
 
-- 
2.32.0

[Intel-gfx] [PATCH 06/15] drm/i915: Extract skl_crtc_calc_dbuf_bw()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Extract the dbuf slice data_rate calculation into a small
helper. Should make it a bit easier to handle the different
color planes of planar formats correctly.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 82 +++++++++++++------------
 1 file changed, 44 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index c35bad21b657..f0d6fad048c7 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -672,6 +672,49 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state)
 	return to_intel_bw_state(bw_state);
 }
 
+static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state,
+				  const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+	struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe];
+	enum plane_id plane_id;
+
+	memset(&crtc_bw->used_bw, 0, sizeof(crtc_bw->used_bw));
+
+	if (!crtc_state->hw.active)
+		return;
+
+	for_each_plane_id_on_crtc(crtc, plane_id) {
+		const struct skl_ddb_entry *ddb_y =
+			&crtc_state->wm.skl.plane_ddb_y[plane_id];
+		const struct skl_ddb_entry *ddb_uv =
+			&crtc_state->wm.skl.plane_ddb_uv[plane_id];
+		unsigned int data_rate = crtc_state->data_rate[plane_id];
+		unsigned int dbuf_mask = 0;
+		enum dbuf_slice slice;
+
+		dbuf_mask |= skl_ddb_dbuf_slice_mask(i915, ddb_y);
+		dbuf_mask |= skl_ddb_dbuf_slice_mask(i915, ddb_uv);
+
+		/*
+		 * FIXME: To calculate that more properly we probably
+		 * need to split per plane data_rate into data_rate_y
+		 * and data_rate_uv for multiplanar formats in order not
+		 * to get accounted those twice if they happen to reside
+		 * on different slices.
+		 * However for pre-icl this would work anyway because
+		 * we have only single slice and for icl+ uv plane has
+		 * non-zero data rate.
+		 * So in worst case those calculation are a bit
+		 * pessimistic, which shouldn't pose any significant
+		 * problem anyway.
+		 */
+		for_each_dbuf_slice_in_mask(i915, slice, dbuf_mask)
+			crtc_bw->used_bw[slice] += data_rate;
+	}
+}
+
 int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
 {
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
@@ -684,50 +727,13 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
 	int i;
 
 	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
-		enum plane_id plane_id;
-		struct intel_dbuf_bw *crtc_bw;
-
 		new_bw_state = intel_atomic_get_bw_state(state);
 		if (IS_ERR(new_bw_state))
 			return PTR_ERR(new_bw_state);
 
 		old_bw_state = intel_atomic_get_old_bw_state(state);
 
-		crtc_bw = &new_bw_state->dbuf_bw[crtc->pipe];
-
-		memset(&crtc_bw->used_bw, 0, sizeof(crtc_bw->used_bw));
-
-		if (!crtc_state->hw.active)
-			continue;
-
-		for_each_plane_id_on_crtc(crtc, plane_id) {
-			const struct skl_ddb_entry *plane_alloc =
-				&crtc_state->wm.skl.plane_ddb_y[plane_id];
-			const struct skl_ddb_entry *uv_plane_alloc =
-				&crtc_state->wm.skl.plane_ddb_uv[plane_id];
-			unsigned int data_rate = crtc_state->data_rate[plane_id];
-			unsigned int dbuf_mask = 0;
-			enum dbuf_slice slice;
-
-			dbuf_mask |= skl_ddb_dbuf_slice_mask(dev_priv, plane_alloc);
-			dbuf_mask |= skl_ddb_dbuf_slice_mask(dev_priv, uv_plane_alloc);
-
-			/*
-			 * FIXME: To calculate that more properly we probably
-			 * need to to split per plane data_rate into data_rate_y
-			 * and data_rate_uv for multiplanar formats in order not
-			 * to get accounted those twice if they happen to reside
-			 * on different slices.
-			 * However for pre-icl this would work anyway because
-			 * we have only single slice and for icl+ uv plane has
-			 * non-zero data rate.
-			 * So in worst case those calculation are a bit
-			 * pessimistic, which shouldn't pose any significant
-			 * problem anyway.
-			 */
-			for_each_dbuf_slice_in_mask(dev_priv, slice, dbuf_mask)
-				crtc_bw->used_bw[slice] += data_rate;
-		}
+		skl_crtc_calc_dbuf_bw(new_bw_state, crtc_state);
 	}
 
 	if (!old_bw_state)
-- 
2.32.0

[Intel-gfx] [PATCH 07/15] drm/i915: Tweak plane ddb allocation tracking

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Let's store the plane allocation in a manner which more closely
matches how the hw operates. That is, we store the packed/CbCr
ddb in one struct, and the Y ddb in another. Currently we're
storing packed/Y in one struct, CbCr in the other.

This also works pretty well for icl+ where the UV plane is
the main plane and the Y plane is subservient to it. Although
in this case we do not even use ddb_y as we do the ddb allocation
in terms of hw planes.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 .../gpu/drm/i915/display/intel_atomic_plane.c |  32 +++---
 drivers/gpu/drm/i915/display/intel_bw.c       |   6 +-
 drivers/gpu/drm/i915/display/intel_display.c  |   8 +-
 .../drm/i915/display/intel_display_debugfs.c  |   4 +-
 .../drm/i915/display/intel_display_types.h    |   7 +-
 drivers/gpu/drm/i915/intel_pm.c               | 108 ++++++++----------
 6 files changed, 74 insertions(+), 91 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index c2c512cd8ec0..52239351931c 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -430,8 +430,8 @@ int intel_plane_atomic_check(struct intel_atomic_state *state,
 static struct intel_plane *
 skl_next_plane_to_commit(struct intel_atomic_state *state,
 			 struct intel_crtc *crtc,
-			 struct skl_ddb_entry entries_y[I915_MAX_PLANES],
-			 struct skl_ddb_entry entries_uv[I915_MAX_PLANES],
+			 struct skl_ddb_entry ddb[I915_MAX_PLANES],
+			 struct skl_ddb_entry ddb_y[I915_MAX_PLANES],
 			 unsigned int *update_mask)
 {
 	struct intel_crtc_state *crtc_state =
@@ -450,17 +450,15 @@ skl_next_plane_to_commit(struct intel_atomic_state *state,
 		    !(*update_mask & BIT(plane_id)))
 			continue;
 
-		if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id],
-						entries_y,
-						I915_MAX_PLANES, plane_id) ||
-		    skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_uv[plane_id],
-						entries_uv,
-						I915_MAX_PLANES, plane_id))
+		if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb[plane_id],
+						ddb, I915_MAX_PLANES, plane_id) ||
+		    skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id],
+						ddb_y, I915_MAX_PLANES, plane_id))
 			continue;
 
 		*update_mask &= ~BIT(plane_id);
-		entries_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id];
-		entries_uv[plane_id] = crtc_state->wm.skl.plane_ddb_uv[plane_id];
+		ddb[plane_id] = crtc_state->wm.skl.plane_ddb[plane_id];
+		ddb_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id];
 
 		return plane;
 	}
@@ -542,19 +540,17 @@ void skl_arm_planes_on_crtc(struct intel_atomic_state *state,
 		intel_atomic_get_old_crtc_state(state, crtc);
 	struct intel_crtc_state *new_crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
-	struct skl_ddb_entry entries_y[I915_MAX_PLANES];
-	struct skl_ddb_entry entries_uv[I915_MAX_PLANES];
+	struct skl_ddb_entry ddb[I915_MAX_PLANES];
+	struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
 	u32 update_mask = new_crtc_state->update_planes;
 	struct intel_plane *plane;
 
-	memcpy(entries_y, old_crtc_state->wm.skl.plane_ddb_y,
+	memcpy(ddb, old_crtc_state->wm.skl.plane_ddb,
+	       sizeof(old_crtc_state->wm.skl.plane_ddb));
+	memcpy(ddb_y, old_crtc_state->wm.skl.plane_ddb_y,
 	       sizeof(old_crtc_state->wm.skl.plane_ddb_y));
-	memcpy(entries_uv, old_crtc_state->wm.skl.plane_ddb_uv,
-	       sizeof(old_crtc_state->wm.skl.plane_ddb_uv));
 
-	while ((plane = skl_next_plane_to_commit(state, crtc,
-						 entries_y, entries_uv,
-						 &update_mask))) {
+	while ((plane = skl_next_plane_to_commit(state, crtc, ddb, ddb_y, &update_mask))) {
 		struct intel_plane_state *new_plane_state =
 			intel_atomic_get_new_plane_state(state, plane);
 
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index f0d6fad048c7..82f0435bcb6d 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -686,16 +686,16 @@ static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state,
 		return;
 
 	for_each_plane_id_on_crtc(crtc, plane_id) {
+		const struct skl_ddb_entry *ddb =
+			&crtc_state->wm.skl.plane_ddb[plane_id];
 		const struct skl_ddb_entry *ddb_y =
 			&crtc_state->wm.skl.plane_ddb_y[plane_id];
-		const struct skl_ddb_entry *ddb_uv =
-			&crtc_state->wm.skl.plane_ddb_uv[plane_id];
 		unsigned int data_rate = crtc_state->data_rate[plane_id];
 		unsigned int dbuf_mask = 0;
 		enum dbuf_slice slice;
 
+		dbuf_mask |= skl_ddb_dbuf_slice_mask(i915, ddb);
 		dbuf_mask |= skl_ddb_dbuf_slice_mask(i915, ddb_y);
-		dbuf_mask |= skl_ddb_dbuf_slice_mask(i915, ddb_uv);
 
 		/*
 		 * FIXME: To calculate that more properly we probably
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0964b2403e2d..af23153f6502 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6750,8 +6750,8 @@ static void verify_wm_state(struct intel_crtc *crtc,
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct skl_hw_state {
+		struct skl_ddb_entry ddb[I915_MAX_PLANES];
 		struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
-		struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
 		struct skl_pipe_wm wm;
 	} *hw;
 	const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal;
@@ -6768,7 +6768,7 @@ static void verify_wm_state(struct intel_crtc *crtc,
 
 	skl_pipe_wm_get_hw_state(crtc, &hw->wm);
 
-	skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
+	skl_pipe_ddb_get_hw_state(crtc, hw->ddb, hw->ddb_y);
 
 	hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
 
@@ -6850,8 +6850,8 @@ static void verify_wm_state(struct intel_crtc *crtc,
 		}
 
 		/* DDB */
-		hw_ddb_entry = &hw->ddb_y[plane->id];
-		sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane->id];
+		hw_ddb_entry = &hw->ddb[PLANE_CURSOR];
+		sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb[PLANE_CURSOR];
 
 		if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
 			drm_err(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index f4de004d470f..5ef4a86ccf66 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1116,13 +1116,13 @@ static int i915_ddb_info(struct seq_file *m, void *unused)
 		seq_printf(m, "Pipe %c\n", pipe_name(pipe));
 
 		for_each_plane_id_on_crtc(crtc, plane_id) {
-			entry = &crtc_state->wm.skl.plane_ddb_y[plane_id];
+			entry = &crtc_state->wm.skl.plane_ddb[plane_id];
 			seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane_id + 1,
 				   entry->start, entry->end,
 				   skl_ddb_entry_size(entry));
 		}
 
-		entry = &crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
+		entry = &crtc_state->wm.skl.plane_ddb[PLANE_CURSOR];
 		seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
 			   entry->end, skl_ddb_entry_size(entry));
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 41e3dd25a78f..578c6069376b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -868,8 +868,13 @@ struct intel_crtc_wm_state {
 			/* gen9+ only needs 1-step wm programming */
 			struct skl_pipe_wm optimal;
 			struct skl_ddb_entry ddb;
+			/*
+			 * pre-icl: for packed/planar CbCr
+			 * icl+: for everything
+			 */
+			struct skl_ddb_entry plane_ddb[I915_MAX_PLANES];
+			/* pre-icl: for planar Y */
 			struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
-			struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
 		} skl;
 
 		struct {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 93ff07f6ef26..8a115b4c9e71 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4312,46 +4312,31 @@ static void
 skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
 			   const enum pipe pipe,
 			   const enum plane_id plane_id,
-			   struct skl_ddb_entry *ddb_y,
-			   struct skl_ddb_entry *ddb_uv)
+			   struct skl_ddb_entry *ddb,
+			   struct skl_ddb_entry *ddb_y)
 {
-	u32 val, val2;
-	u32 fourcc = 0;
+	u32 val;
 
 	/* Cursor doesn't support NV12/planar, so no extra calculation needed */
 	if (plane_id == PLANE_CURSOR) {
 		val = intel_uncore_read(&dev_priv->uncore, CUR_BUF_CFG(pipe));
-		skl_ddb_entry_init_from_hw(ddb_y, val);
+		skl_ddb_entry_init_from_hw(ddb, val);
 		return;
 	}
 
-	val = intel_uncore_read(&dev_priv->uncore, PLANE_CTL(pipe, plane_id));
+	val = intel_uncore_read(&dev_priv->uncore, PLANE_BUF_CFG(pipe, plane_id));
+	skl_ddb_entry_init_from_hw(ddb, val);
 
-	/* No DDB allocated for disabled planes */
-	if (val & PLANE_CTL_ENABLE)
-		fourcc = skl_format_to_fourcc(val & PLANE_CTL_FORMAT_MASK_SKL,
-					      val & PLANE_CTL_ORDER_RGBX,
-					      val & PLANE_CTL_ALPHA_MASK);
-
-	if (DISPLAY_VER(dev_priv) >= 11) {
-		val = intel_uncore_read(&dev_priv->uncore, PLANE_BUF_CFG(pipe, plane_id));
-		skl_ddb_entry_init_from_hw(ddb_y, val);
-	} else {
-		val = intel_uncore_read(&dev_priv->uncore, PLANE_BUF_CFG(pipe, plane_id));
-		val2 = intel_uncore_read(&dev_priv->uncore, PLANE_NV12_BUF_CFG(pipe, plane_id));
-
-		if (fourcc &&
-		    drm_format_info_is_yuv_semiplanar(drm_format_info(fourcc)))
-			swap(val, val2);
+	if (DISPLAY_VER(dev_priv) >= 11)
+		return;
 
-		skl_ddb_entry_init_from_hw(ddb_y, val);
-		skl_ddb_entry_init_from_hw(ddb_uv, val2);
-	}
+	val = intel_uncore_read(&dev_priv->uncore, PLANE_NV12_BUF_CFG(pipe, plane_id));
+	skl_ddb_entry_init_from_hw(ddb_y, val);
 }
 
 void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
-			       struct skl_ddb_entry *ddb_y,
-			       struct skl_ddb_entry *ddb_uv)
+			       struct skl_ddb_entry *ddb,
+			       struct skl_ddb_entry *ddb_y)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum intel_display_power_domain power_domain;
@@ -4367,8 +4352,8 @@ void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
 	for_each_plane_id_on_crtc(crtc, plane_id)
 		skl_ddb_get_hw_plane_state(dev_priv, pipe,
 					   plane_id,
-					   &ddb_y[plane_id],
-					   &ddb_uv[plane_id]);
+					   &ddb[plane_id],
+					   &ddb_y[plane_id]);
 
 	intel_display_power_put(dev_priv, power_domain, wakeref);
 }
@@ -5105,8 +5090,8 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
 	int level;
 
 	/* Clear the partitioning for disabled planes. */
+	memset(crtc_state->wm.skl.plane_ddb, 0, sizeof(crtc_state->wm.skl.plane_ddb));
 	memset(crtc_state->wm.skl.plane_ddb_y, 0, sizeof(crtc_state->wm.skl.plane_ddb_y));
-	memset(crtc_state->wm.skl.plane_ddb_uv, 0, sizeof(crtc_state->wm.skl.plane_ddb_uv));
 
 	if (!crtc_state->hw.active)
 		return 0;
@@ -5123,7 +5108,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
 	/* Allocate fixed number of blocks for cursor. */
 	iter.total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
 	iter.size -= iter.total[PLANE_CURSOR];
-	skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR],
+	skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[PLANE_CURSOR],
 			   alloc->end - iter.total[PLANE_CURSOR], alloc->end);
 
 	if (iter.data_rate == 0)
@@ -5202,10 +5187,10 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
 	/* Set the actual DDB start/end points for each plane */
 	iter.start = alloc->start;
 	for_each_plane_id_on_crtc(crtc, plane_id) {
-		struct skl_ddb_entry *plane_alloc =
+		struct skl_ddb_entry *ddb =
+			&crtc_state->wm.skl.plane_ddb[plane_id];
+		struct skl_ddb_entry *ddb_y =
 			&crtc_state->wm.skl.plane_ddb_y[plane_id];
-		struct skl_ddb_entry *uv_plane_alloc =
-			&crtc_state->wm.skl.plane_ddb_uv[plane_id];
 
 		if (plane_id == PLANE_CURSOR)
 			continue;
@@ -5216,12 +5201,15 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
 
 		/* Leave disabled planes at (0,0) */
 		if (iter.total[plane_id])
-			iter.start = skl_ddb_entry_init(plane_alloc, iter.start,
+			iter.start = skl_ddb_entry_init(ddb, iter.start,
 							iter.start + iter.total[plane_id]);
 
-		if (iter.uv_total[plane_id])
-			iter.start = skl_ddb_entry_init(uv_plane_alloc, iter.start,
+		if (iter.uv_total[plane_id]) {
+			/* hardware wants these swapped */
+			*ddb_y = *ddb;
+			iter.start = skl_ddb_entry_init(ddb, iter.start,
 							iter.start + iter.uv_total[plane_id]);
+		}
 	}
 
 	/*
@@ -5874,11 +5862,10 @@ void skl_write_plane_wm(struct intel_plane *plane,
 	enum plane_id plane_id = plane->id;
 	enum pipe pipe = plane->pipe;
 	const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
-	const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
+	const struct skl_ddb_entry *ddb =
+		&crtc_state->wm.skl.plane_ddb[plane_id];
 	const struct skl_ddb_entry *ddb_y =
 		&crtc_state->wm.skl.plane_ddb_y[plane_id];
-	const struct skl_ddb_entry *ddb_uv =
-		&crtc_state->wm.skl.plane_ddb_uv[plane_id];
 
 	for (level = 0; level <= max_level; level++)
 		skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
@@ -5888,25 +5875,20 @@ void skl_write_plane_wm(struct intel_plane *plane,
 			   skl_plane_trans_wm(pipe_wm, plane_id));
 
 	if (HAS_HW_SAGV_WM(dev_priv)) {
+		const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
+
 		skl_write_wm_level(dev_priv, PLANE_WM_SAGV(pipe, plane_id),
 				   &wm->sagv.wm0);
 		skl_write_wm_level(dev_priv, PLANE_WM_SAGV_TRANS(pipe, plane_id),
 				   &wm->sagv.trans_wm);
 	}
 
-	if (DISPLAY_VER(dev_priv) >= 11) {
+	skl_ddb_entry_write(dev_priv,
+			    PLANE_BUF_CFG(pipe, plane_id), ddb);
+
+	if (DISPLAY_VER(dev_priv) < 11)
 		skl_ddb_entry_write(dev_priv,
-				    PLANE_BUF_CFG(pipe, plane_id), ddb_y);
-		return;
-	}
-
-	if (wm->is_planar)
-		swap(ddb_y, ddb_uv);
-
-	skl_ddb_entry_write(dev_priv,
-			    PLANE_BUF_CFG(pipe, plane_id), ddb_y);
-	skl_ddb_entry_write(dev_priv,
-			    PLANE_NV12_BUF_CFG(pipe, plane_id), ddb_uv);
+				    PLANE_NV12_BUF_CFG(pipe, plane_id), ddb_y);
 }
 
 void skl_write_cursor_wm(struct intel_plane *plane,
@@ -5918,7 +5900,7 @@ void skl_write_cursor_wm(struct intel_plane *plane,
 	enum pipe pipe = plane->pipe;
 	const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
 	const struct skl_ddb_entry *ddb =
-		&crtc_state->wm.skl.plane_ddb_y[plane_id];
+		&crtc_state->wm.skl.plane_ddb[plane_id];
 
 	for (level = 0; level <= max_level; level++)
 		skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
@@ -6015,10 +5997,10 @@ skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state,
 		struct intel_plane_state *plane_state;
 		enum plane_id plane_id = plane->id;
 
-		if (skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_y[plane_id],
-					&new_crtc_state->wm.skl.plane_ddb_y[plane_id]) &&
-		    skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_uv[plane_id],
-					&new_crtc_state->wm.skl.plane_ddb_uv[plane_id]))
+		if (skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb[plane_id],
+					&new_crtc_state->wm.skl.plane_ddb[plane_id]) &&
+		    skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_y[plane_id],
+					&new_crtc_state->wm.skl.plane_ddb_y[plane_id]))
 			continue;
 
 		plane_state = intel_atomic_get_plane_state(state, plane);
@@ -6185,8 +6167,8 @@ skl_print_wm_changes(struct intel_atomic_state *state)
 			enum plane_id plane_id = plane->id;
 			const struct skl_ddb_entry *old, *new;
 
-			old = &old_crtc_state->wm.skl.plane_ddb_y[plane_id];
-			new = &new_crtc_state->wm.skl.plane_ddb_y[plane_id];
+			old = &old_crtc_state->wm.skl.plane_ddb[plane_id];
+			new = &new_crtc_state->wm.skl.plane_ddb[plane_id];
 
 			if (skl_ddb_entry_equal(old, new))
 				continue;
@@ -6587,16 +6569,16 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
 		memset(&dbuf_state->ddb[pipe], 0, sizeof(dbuf_state->ddb[pipe]));
 
 		for_each_plane_id_on_crtc(crtc, plane_id) {
+			struct skl_ddb_entry *ddb =
+				&crtc_state->wm.skl.plane_ddb[plane_id];
 			struct skl_ddb_entry *ddb_y =
 				&crtc_state->wm.skl.plane_ddb_y[plane_id];
-			struct skl_ddb_entry *ddb_uv =
-				&crtc_state->wm.skl.plane_ddb_uv[plane_id];
 
 			skl_ddb_get_hw_plane_state(dev_priv, crtc->pipe,
-						   plane_id, ddb_y, ddb_uv);
+						   plane_id, ddb, ddb_y);
 
+			skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb);
 			skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb_y);
-			skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb_uv);
 		}
 
 		dbuf_state->slices[pipe] =
-- 
2.32.0

[Intel-gfx] [PATCH 08/15] drm/i915: Split plane data_rate into data_rate+data_rate_y

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Split the currently combined plane data_rate into the proper
Y vs. CbCr components. This matches how we now track the
plane dbuf allocations, and thus will make the dbuf bandwidth
calculations actually produce the correct numbers for each
dbuf slice.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 .../gpu/drm/i915/display/intel_atomic_plane.c | 34 ++++++++----------
 .../gpu/drm/i915/display/intel_atomic_plane.h |  3 +-
 drivers/gpu/drm/i915/display/intel_bw.c       | 36 +++++++++----------
 drivers/gpu/drm/i915/display/intel_display.c  |  4 +++
 .../drm/i915/display/intel_display_types.h    |  3 ++
 5 files changed, 42 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 52239351931c..cd18155830d4 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -180,29 +180,16 @@ unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
 }
 
 unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
-				   const struct intel_plane_state *plane_state)
+				   const struct intel_plane_state *plane_state,
+				   int color_plane)
 {
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
-	unsigned int cpp;
-	unsigned int pixel_rate;
 
 	if (!plane_state->uapi.visible)
 		return 0;
 
-	pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);
-
-	cpp = fb->format->cpp[0];
-
-	/*
-	 * Based on HSD#:1408715493
-	 * NV12 cpp == 4, P010 cpp == 8
-	 *
-	 * FIXME what is the logic behind this?
-	 */
-	if (fb->format->is_yuv && fb->format->num_planes > 1)
-		cpp *= 4;
-
-	return pixel_rate * cpp;
+	return intel_plane_pixel_rate(crtc_state, plane_state) *
+		fb->format->cpp[color_plane];
 }
 
 int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
@@ -324,6 +311,7 @@ void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
 	crtc_state->nv12_planes &= ~BIT(plane->id);
 	crtc_state->c8_planes &= ~BIT(plane->id);
 	crtc_state->data_rate[plane->id] = 0;
+	crtc_state->data_rate_y[plane->id] = 0;
 	crtc_state->min_cdclk[plane->id] = 0;
 
 	plane_state->uapi.visible = false;
@@ -366,8 +354,16 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
 	if (new_plane_state->uapi.visible || old_plane_state->uapi.visible)
 		new_crtc_state->update_planes |= BIT(plane->id);
 
-	new_crtc_state->data_rate[plane->id] =
-		intel_plane_data_rate(new_crtc_state, new_plane_state);
+	if (new_plane_state->uapi.visible &&
+	    intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
+		new_crtc_state->data_rate_y[plane->id] =
+			intel_plane_data_rate(new_crtc_state, new_plane_state, 0);
+		new_crtc_state->data_rate[plane->id] =
+			intel_plane_data_rate(new_crtc_state, new_plane_state, 1);
+	} else if (new_plane_state->uapi.visible) {
+		new_crtc_state->data_rate[plane->id] =
+			intel_plane_data_rate(new_crtc_state, new_plane_state, 0);
+	}
 
 	return intel_plane_atomic_calc_changes(old_crtc_state, new_crtc_state,
 					       old_plane_state, new_plane_state);
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index 7907f601598e..aa26ce5fb654 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -24,7 +24,8 @@ unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
 				    const struct intel_plane_state *plane_state);
 
 unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
-				   const struct intel_plane_state *plane_state);
+				   const struct intel_plane_state *plane_state,
+				   int color_plane);
 void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
 				       const struct intel_plane_state *from_plane_state,
 				       struct intel_crtc *crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 82f0435bcb6d..93feab671c29 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -576,6 +576,7 @@ static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_stat
 static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	unsigned int data_rate = 0;
 	enum plane_id plane_id;
 
@@ -588,6 +589,9 @@ static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_
 			continue;
 
 		data_rate += crtc_state->data_rate[plane_id];
+
+		if (DISPLAY_VER(i915) < 11)
+			data_rate += crtc_state->data_rate_y[plane_id];
 	}
 
 	return data_rate;
@@ -688,28 +692,24 @@ static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state,
 	for_each_plane_id_on_crtc(crtc, plane_id) {
 		const struct skl_ddb_entry *ddb =
 			&crtc_state->wm.skl.plane_ddb[plane_id];
-		const struct skl_ddb_entry *ddb_y =
-			&crtc_state->wm.skl.plane_ddb_y[plane_id];
 		unsigned int data_rate = crtc_state->data_rate[plane_id];
-		unsigned int dbuf_mask = 0;
+		unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(i915, ddb);
 		enum dbuf_slice slice;
 
-		dbuf_mask |= skl_ddb_dbuf_slice_mask(i915, ddb);
-		dbuf_mask |= skl_ddb_dbuf_slice_mask(i915, ddb_y);
+		for_each_dbuf_slice_in_mask(i915, slice, dbuf_mask)
+			crtc_bw->used_bw[slice] += data_rate;
+	}
+
+	if (DISPLAY_VER(i915) >= 11)
+		return;
+
+	for_each_plane_id_on_crtc(crtc, plane_id) {
+		const struct skl_ddb_entry *ddb =
+			&crtc_state->wm.skl.plane_ddb_y[plane_id];
+		unsigned int data_rate = crtc_state->data_rate_y[plane_id];
+		unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(i915, ddb);
+		enum dbuf_slice slice;
 
-		/*
-		 * FIXME: To calculate that more properly we probably
-		 * need to split per plane data_rate into data_rate_y
-		 * and data_rate_uv for multiplanar formats in order not
-		 * to get accounted those twice if they happen to reside
-		 * on different slices.
-		 * However for pre-icl this would work anyway because
-		 * we have only single slice and for icl+ uv plane has
-		 * non-zero data rate.
-		 * So in worst case those calculation are a bit
-		 * pessimistic, which shouldn't pose any significant
-		 * problem anyway.
-		 */
 		for_each_dbuf_slice_in_mask(i915, slice, dbuf_mask)
 			crtc_bw->used_bw[slice] += data_rate;
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index af23153f6502..39dd2e7383e0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -761,6 +761,7 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
 	intel_set_plane_visible(crtc_state, plane_state, false);
 	fixup_plane_bitmasks(crtc_state);
 	crtc_state->data_rate[plane->id] = 0;
+	crtc_state->data_rate_y[plane->id] = 0;
 	crtc_state->min_cdclk[plane->id] = 0;
 
 	if (plane->id == PLANE_PRIMARY)
@@ -5110,6 +5111,7 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
 			crtc_state->enabled_planes &= ~BIT(plane->id);
 			crtc_state->active_planes &= ~BIT(plane->id);
 			crtc_state->update_planes |= BIT(plane->id);
+			crtc_state->data_rate[plane->id] = 0;
 		}
 
 		plane_state->planar_slave = false;
@@ -5154,6 +5156,8 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
 		crtc_state->enabled_planes |= BIT(linked->id);
 		crtc_state->active_planes |= BIT(linked->id);
 		crtc_state->update_planes |= BIT(linked->id);
+		crtc_state->data_rate[linked->id] =
+			crtc_state->data_rate_y[plane->id];
 		drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",
 			    linked->base.name, plane->base.name);
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 578c6069376b..7e147e110059 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1148,7 +1148,10 @@ struct intel_crtc_state {
 
 	int min_cdclk[I915_MAX_PLANES];
 
+	/* for packed/planar CbCr */
 	u32 data_rate[I915_MAX_PLANES];
+	/* for planar Y */
+	u32 data_rate_y[I915_MAX_PLANES];
 
 	/* FIXME unify with data_rate[] */
 	u64 plane_data_rate[I915_MAX_PLANES];
-- 
2.32.0

[Intel-gfx] [PATCH 09/15] drm/i915: Pre-calculate plane relative data rate

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Handle the plane relative data rate in exactly the same
way as we already handle the real data rate. Ie. pre-calculate
it during intel_plane_atomic_check_with_state(), and assign/clear
it for the Y plane as needed. This should guarantee that the
tracking is 100% consistent, and makes me have to think less
when the same apporach is used by both types of data rate.

We might even want to consider replacing the relative
data rate with the real data rate entirely, but it's not
clear if that will produce less optimal plane ddb
allocations. So for now lets keep using the current approach.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 .../gpu/drm/i915/display/intel_atomic_plane.c |  37 ++++
 drivers/gpu/drm/i915/display/intel_display.c  |   5 +
 .../drm/i915/display/intel_display_types.h    |   6 +-
 drivers/gpu/drm/i915/intel_pm.c               | 170 ++++--------------
 4 files changed, 80 insertions(+), 138 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index cd18155830d4..a61344dcfb94 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -192,6 +192,33 @@ unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
 		fb->format->cpp[color_plane];
 }
 
+static unsigned int
+intel_plane_relative_data_rate(const struct intel_plane_state *plane_state,
+			       int color_plane)
+{
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
+	int width, height;
+
+	if (!plane_state->uapi.visible)
+		return 0;
+
+	/*
+	 * Src coordinates are already rotated by 270 degrees for
+	 * the 90/270 degree plane rotation cases (to match the
+	 * GTT mapping), hence no need to account for rotation here.
+	 */
+	width = drm_rect_width(&plane_state->uapi.src) >> 16;
+	height = drm_rect_height(&plane_state->uapi.src) >> 16;
+
+	/* UV plane does 1/2 pixel sub-sampling */
+	if (color_plane == 1) {
+		width /= 2;
+		height /= 2;
+	}
+
+	return width * height * fb->format->cpp[color_plane];
+}
+
 int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
 			       struct intel_plane *plane,
 			       bool *need_cdclk_calc)
@@ -312,6 +339,8 @@ void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
 	crtc_state->c8_planes &= ~BIT(plane->id);
 	crtc_state->data_rate[plane->id] = 0;
 	crtc_state->data_rate_y[plane->id] = 0;
+	crtc_state->rel_data_rate[plane->id] = 0;
+	crtc_state->rel_data_rate_y[plane->id] = 0;
 	crtc_state->min_cdclk[plane->id] = 0;
 
 	plane_state->uapi.visible = false;
@@ -360,9 +389,17 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
 			intel_plane_data_rate(new_crtc_state, new_plane_state, 0);
 		new_crtc_state->data_rate[plane->id] =
 			intel_plane_data_rate(new_crtc_state, new_plane_state, 1);
+
+		new_crtc_state->rel_data_rate_y[plane->id] =
+			intel_plane_relative_data_rate(new_plane_state, 0);
+		new_crtc_state->rel_data_rate[plane->id] =
+			intel_plane_relative_data_rate(new_plane_state, 1);
 	} else if (new_plane_state->uapi.visible) {
 		new_crtc_state->data_rate[plane->id] =
 			intel_plane_data_rate(new_crtc_state, new_plane_state, 0);
+
+		new_crtc_state->rel_data_rate[plane->id] =
+			intel_plane_relative_data_rate(new_plane_state, 0);
 	}
 
 	return intel_plane_atomic_calc_changes(old_crtc_state, new_crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 39dd2e7383e0..8f3034713c56 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -762,6 +762,8 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
 	fixup_plane_bitmasks(crtc_state);
 	crtc_state->data_rate[plane->id] = 0;
 	crtc_state->data_rate_y[plane->id] = 0;
+	crtc_state->rel_data_rate[plane->id] = 0;
+	crtc_state->rel_data_rate_y[plane->id] = 0;
 	crtc_state->min_cdclk[plane->id] = 0;
 
 	if (plane->id == PLANE_PRIMARY)
@@ -5112,6 +5114,7 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
 			crtc_state->active_planes &= ~BIT(plane->id);
 			crtc_state->update_planes |= BIT(plane->id);
 			crtc_state->data_rate[plane->id] = 0;
+			crtc_state->rel_data_rate[plane->id] = 0;
 		}
 
 		plane_state->planar_slave = false;
@@ -5158,6 +5161,8 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
 		crtc_state->update_planes |= BIT(linked->id);
 		crtc_state->data_rate[linked->id] =
 			crtc_state->data_rate_y[plane->id];
+		crtc_state->rel_data_rate[linked->id] =
+			crtc_state->rel_data_rate_y[plane->id];
 		drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",
 			    linked->base.name, plane->base.name);
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 7e147e110059..871485af14d4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1153,9 +1153,9 @@ struct intel_crtc_state {
 	/* for planar Y */
 	u32 data_rate_y[I915_MAX_PLANES];
 
-	/* FIXME unify with data_rate[] */
-	u64 plane_data_rate[I915_MAX_PLANES];
-	u64 uv_plane_data_rate[I915_MAX_PLANES];
+	/* FIXME unify with data_rate[]? */
+	u64 rel_data_rate[I915_MAX_PLANES];
+	u64 rel_data_rate_y[I915_MAX_PLANES];
 
 	/* Gamma mode programmed on the pipe */
 	u32 gamma_mode;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8a115b4c9e71..134584c77697 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4862,126 +4862,24 @@ static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes)
 }
 
 static u64
-skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
-			     const struct intel_plane_state *plane_state,
-			     int color_plane)
+skl_total_relative_data_rate(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
-	const struct drm_framebuffer *fb = plane_state->hw.fb;
-	int width, height;
-
-	if (!plane_state->uapi.visible)
-		return 0;
-
-	if (plane->id == PLANE_CURSOR)
-		return 0;
-
-	if (color_plane == 1 &&
-	    !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
-		return 0;
-
-	/*
-	 * Src coordinates are already rotated by 270 degrees for
-	 * the 90/270 degree plane rotation cases (to match the
-	 * GTT mapping), hence no need to account for rotation here.
-	 */
-	width = drm_rect_width(&plane_state->uapi.src) >> 16;
-	height = drm_rect_height(&plane_state->uapi.src) >> 16;
-
-	/* UV plane does 1/2 pixel sub-sampling */
-	if (color_plane == 1) {
-		width /= 2;
-		height /= 2;
-	}
-
-	return width * height * fb->format->cpp[color_plane];
-}
-
-static u64
-skl_get_total_relative_data_rate(struct intel_atomic_state *state,
-				 struct intel_crtc *crtc)
-{
-	struct intel_crtc_state *crtc_state =
-		intel_atomic_get_new_crtc_state(state, crtc);
-	const struct intel_plane_state *plane_state;
-	struct intel_plane *plane;
-	u64 total_data_rate = 0;
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	enum plane_id plane_id;
-	int i;
-
-	/* Calculate and cache data rate for each plane */
-	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
-		if (plane->pipe != crtc->pipe)
-			continue;
-
-		plane_id = plane->id;
-
-		/* packed/y */
-		crtc_state->plane_data_rate[plane_id] =
-			skl_plane_relative_data_rate(crtc_state, plane_state, 0);
-
-		/* uv-plane */
-		crtc_state->uv_plane_data_rate[plane_id] =
-			skl_plane_relative_data_rate(crtc_state, plane_state, 1);
-	}
+	u64 data_rate = 0;
 
 	for_each_plane_id_on_crtc(crtc, plane_id) {
-		total_data_rate += crtc_state->plane_data_rate[plane_id];
-		total_data_rate += crtc_state->uv_plane_data_rate[plane_id];
-	}
-
-	return total_data_rate;
-}
-
-static u64
-icl_get_total_relative_data_rate(struct intel_atomic_state *state,
-				 struct intel_crtc *crtc)
-{
-	struct intel_crtc_state *crtc_state =
-		intel_atomic_get_new_crtc_state(state, crtc);
-	const struct intel_plane_state *plane_state;
-	struct intel_plane *plane;
-	u64 total_data_rate = 0;
-	enum plane_id plane_id;
-	int i;
-
-	/* Calculate and cache data rate for each plane */
-	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
-		if (plane->pipe != crtc->pipe)
+		if (plane_id == PLANE_CURSOR)
 			continue;
 
-		plane_id = plane->id;
+		data_rate += crtc_state->rel_data_rate[plane_id];
 
-		if (!plane_state->planar_linked_plane) {
-			crtc_state->plane_data_rate[plane_id] =
-				skl_plane_relative_data_rate(crtc_state, plane_state, 0);
-		} else {
-			enum plane_id y_plane_id;
-
-			/*
-			 * The slave plane might not iterate in
-			 * intel_atomic_crtc_state_for_each_plane_state(),
-			 * and needs the master plane state which may be
-			 * NULL if we try get_new_plane_state(), so we
-			 * always calculate from the master.
-			 */
-			if (plane_state->planar_slave)
-				continue;
-
-			/* Y plane rate is calculated on the slave */
-			y_plane_id = plane_state->planar_linked_plane->id;
-			crtc_state->plane_data_rate[y_plane_id] =
-				skl_plane_relative_data_rate(crtc_state, plane_state, 0);
-
-			crtc_state->plane_data_rate[plane_id] =
-				skl_plane_relative_data_rate(crtc_state, plane_state, 1);
-		}
+		if (DISPLAY_VER(i915) < 11)
+			data_rate += crtc_state->rel_data_rate_y[plane_id];
 	}
 
-	for_each_plane_id_on_crtc(crtc, plane_id)
-		total_data_rate += crtc_state->plane_data_rate[plane_id];
-
-	return total_data_rate;
+	return data_rate;
 }
 
 const struct skl_wm_level *
@@ -5096,11 +4994,6 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
 	if (!crtc_state->hw.active)
 		return 0;
 
-	if (DISPLAY_VER(dev_priv) >= 11)
-		iter.data_rate = icl_get_total_relative_data_rate(state, crtc);
-	else
-		iter.data_rate = skl_get_total_relative_data_rate(state, crtc);
-
 	iter.size = skl_ddb_entry_size(alloc);
 	if (iter.size == 0)
 		return 0;
@@ -5111,6 +5004,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
 	skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[PLANE_CURSOR],
 			   alloc->end - iter.total[PLANE_CURSOR], alloc->end);
 
+	iter.data_rate = skl_total_relative_data_rate(crtc_state);
 	if (iter.data_rate == 0)
 		return 0;
 
@@ -5171,16 +5065,19 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
 		if (iter.data_rate == 0)
 			break;
 
-		iter.total[plane_id] =
-			skl_allocate_plane_ddb(&iter, &wm->wm[level],
-					       crtc_state->plane_data_rate[plane_id]);
-
-		if (iter.data_rate == 0)
-			break;
-
-		iter.uv_total[plane_id] =
-			skl_allocate_plane_ddb(&iter, &wm->uv_wm[level],
-					       crtc_state->uv_plane_data_rate[plane_id]);
+		if (DISPLAY_VER(dev_priv) < 11 &&
+		    crtc_state->nv12_planes & BIT(plane_id)) {
+			iter.total[plane_id] =
+				skl_allocate_plane_ddb(&iter, &wm->wm[level],
+						       crtc_state->rel_data_rate_y[plane_id]);
+			iter.uv_total[plane_id] =
+				skl_allocate_plane_ddb(&iter, &wm->uv_wm[level],
+						       crtc_state->rel_data_rate[plane_id]);
+		} else {
+			iter.total[plane_id] =
+				skl_allocate_plane_ddb(&iter, &wm->wm[level],
+						       crtc_state->rel_data_rate[plane_id]);
+		}
 	}
 	drm_WARN_ON(&dev_priv->drm, iter.size != 0 || iter.data_rate != 0);
 
@@ -5200,15 +5097,18 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
 			    DISPLAY_VER(dev_priv) >= 11 && iter.uv_total[plane_id]);
 
 		/* Leave disabled planes at (0,0) */
-		if (iter.total[plane_id])
-			iter.start = skl_ddb_entry_init(ddb, iter.start,
-							iter.start + iter.total[plane_id]);
-
-		if (iter.uv_total[plane_id]) {
-			/* hardware wants these swapped */
-			*ddb_y = *ddb;
-			iter.start = skl_ddb_entry_init(ddb, iter.start,
-							iter.start + iter.uv_total[plane_id]);
+		if (DISPLAY_VER(dev_priv) < 11 &&
+		    crtc_state->nv12_planes & BIT(plane_id)) {
+			if (iter.total[plane_id])
+				iter.start = skl_ddb_entry_init(ddb_y, iter.start,
+								iter.start + iter.total[plane_id]);
+			if (iter.uv_total[plane_id])
+				iter.start = skl_ddb_entry_init(ddb, iter.start,
+								iter.start + iter.uv_total[plane_id]);
+		} else {
+			if (iter.total[plane_id])
+				iter.start = skl_ddb_entry_init(ddb, iter.start,
+								iter.start + iter.total[plane_id]);
 		}
 	}
 
-- 
2.32.0

[Intel-gfx] [PATCH 10/15] drm/i915: Remove total[] and uv_total[] from ddb allocation

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

There's really no need to maintain these total[] arrays to
track the size of each plane's ddb allocation. We just stick
the results straight into the crtc_state ddb tracking structures.

The main annoyance with all this is the mismatch between
wm_uv vs. ddb_y on pre-icl. If only the hw was consistent in
what it considers the primary source of information we could
avoid some of the uglyness. But since that is not the case
we need a bit of special casing for planar formats.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 115 +++++++++++++++-----------------
 1 file changed, 55 insertions(+), 60 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 134584c77697..6c30c57748e8 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4920,18 +4920,18 @@ skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm,
  * So this is actually safe to do.
  */
 static void
-skl_check_wm_level(struct skl_wm_level *wm, u64 total)
+skl_check_wm_level(struct skl_wm_level *wm, const struct skl_ddb_entry *ddb)
 {
-	if (wm->min_ddb_alloc > total)
+	if (wm->min_ddb_alloc > skl_ddb_entry_size(ddb))
 		memset(wm, 0, sizeof(*wm));
 }
 
 static void
 skl_check_nv12_wm_level(struct skl_wm_level *wm, struct skl_wm_level *uv_wm,
-			u64 total, u64 uv_total)
+			const struct skl_ddb_entry *ddb_y, const struct skl_ddb_entry *ddb)
 {
-	if (wm->min_ddb_alloc > total ||
-	    uv_wm->min_ddb_alloc > uv_total) {
+	if (wm->min_ddb_alloc > skl_ddb_entry_size(ddb_y) ||
+	    uv_wm->min_ddb_alloc > skl_ddb_entry_size(ddb)) {
 		memset(wm, 0, sizeof(*wm));
 		memset(uv_wm, 0, sizeof(*uv_wm));
 	}
@@ -4951,13 +4951,12 @@ static bool icl_need_wm1_wa(struct drm_i915_private *i915,
 
 struct skl_plane_ddb_iter {
 	u64 data_rate;
-	u16 total[I915_MAX_PLANES];
-	u16 uv_total[I915_MAX_PLANES];
 	u16 start, size;
 };
 
-static u16
+static void
 skl_allocate_plane_ddb(struct skl_plane_ddb_iter *iter,
+		       struct skl_ddb_entry *ddb,
 		       const struct skl_wm_level *wm,
 		       u64 data_rate)
 {
@@ -4968,7 +4967,8 @@ skl_allocate_plane_ddb(struct skl_plane_ddb_iter *iter,
 	iter->size -= extra;
 	iter->data_rate -= data_rate;
 
-	return wm->min_ddb_alloc + extra;
+	iter->start = skl_ddb_entry_init(ddb, iter->start,
+					 iter->start + wm->min_ddb_alloc + extra);
 }
 
 static int
@@ -4982,8 +4982,9 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
 		intel_atomic_get_new_dbuf_state(state);
 	const struct skl_ddb_entry *alloc = &dbuf_state->ddb[crtc->pipe];
 	int num_active = hweight8(dbuf_state->active_pipes);
-	struct skl_plane_ddb_iter iter = {};
+	struct skl_plane_ddb_iter iter;
 	enum plane_id plane_id;
+	u16 cursor_size;
 	u32 blocks;
 	int level;
 
@@ -4994,15 +4995,16 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
 	if (!crtc_state->hw.active)
 		return 0;
 
+	iter.start = alloc->start;
 	iter.size = skl_ddb_entry_size(alloc);
 	if (iter.size == 0)
 		return 0;
 
 	/* Allocate fixed number of blocks for cursor. */
-	iter.total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
-	iter.size -= iter.total[PLANE_CURSOR];
+	cursor_size = skl_cursor_allocation(crtc_state, num_active);
+	iter.size -= cursor_size;
 	skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[PLANE_CURSOR],
-			   alloc->end - iter.total[PLANE_CURSOR], alloc->end);
+			   alloc->end - cursor_size, alloc->end);
 
 	iter.data_rate = skl_total_relative_data_rate(crtc_state);
 	if (iter.data_rate == 0)
@@ -5019,7 +5021,10 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
 				&crtc_state->wm.skl.optimal.planes[plane_id];
 
 			if (plane_id == PLANE_CURSOR) {
-				if (wm->wm[level].min_ddb_alloc > iter.total[PLANE_CURSOR]) {
+				const struct skl_ddb_entry *ddb =
+					&crtc_state->wm.skl.plane_ddb[plane_id];
+
+				if (wm->wm[level].min_ddb_alloc > skl_ddb_entry_size(ddb)) {
 					drm_WARN_ON(&dev_priv->drm,
 						    wm->wm[level].min_ddb_alloc != U16_MAX);
 					blocks = U32_MAX;
@@ -5052,6 +5057,10 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
 	 * proportional to its relative data rate.
 	 */
 	for_each_plane_id_on_crtc(crtc, plane_id) {
+		struct skl_ddb_entry *ddb =
+			&crtc_state->wm.skl.plane_ddb[plane_id];
+		struct skl_ddb_entry *ddb_y =
+			&crtc_state->wm.skl.plane_ddb_y[plane_id];
 		const struct skl_plane_wm *wm =
 			&crtc_state->wm.skl.optimal.planes[plane_id];
 
@@ -5067,51 +5076,17 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
 
 		if (DISPLAY_VER(dev_priv) < 11 &&
 		    crtc_state->nv12_planes & BIT(plane_id)) {
-			iter.total[plane_id] =
-				skl_allocate_plane_ddb(&iter, &wm->wm[level],
-						       crtc_state->rel_data_rate_y[plane_id]);
-			iter.uv_total[plane_id] =
-				skl_allocate_plane_ddb(&iter, &wm->uv_wm[level],
-						       crtc_state->rel_data_rate[plane_id]);
+			skl_allocate_plane_ddb(&iter, ddb_y, &wm->wm[level],
+					       crtc_state->rel_data_rate_y[plane_id]);
+			skl_allocate_plane_ddb(&iter, ddb, &wm->uv_wm[level],
+					       crtc_state->rel_data_rate[plane_id]);
 		} else {
-			iter.total[plane_id] =
-				skl_allocate_plane_ddb(&iter, &wm->wm[level],
-						       crtc_state->rel_data_rate[plane_id]);
+			skl_allocate_plane_ddb(&iter, ddb, &wm->wm[level],
+					       crtc_state->rel_data_rate[plane_id]);
 		}
 	}
 	drm_WARN_ON(&dev_priv->drm, iter.size != 0 || iter.data_rate != 0);
 
-	/* Set the actual DDB start/end points for each plane */
-	iter.start = alloc->start;
-	for_each_plane_id_on_crtc(crtc, plane_id) {
-		struct skl_ddb_entry *ddb =
-			&crtc_state->wm.skl.plane_ddb[plane_id];
-		struct skl_ddb_entry *ddb_y =
-			&crtc_state->wm.skl.plane_ddb_y[plane_id];
-
-		if (plane_id == PLANE_CURSOR)
-			continue;
-
-		/* Gen11+ uses a separate plane for UV watermarks */
-		drm_WARN_ON(&dev_priv->drm,
-			    DISPLAY_VER(dev_priv) >= 11 && iter.uv_total[plane_id]);
-
-		/* Leave disabled planes at (0,0) */
-		if (DISPLAY_VER(dev_priv) < 11 &&
-		    crtc_state->nv12_planes & BIT(plane_id)) {
-			if (iter.total[plane_id])
-				iter.start = skl_ddb_entry_init(ddb_y, iter.start,
-								iter.start + iter.total[plane_id]);
-			if (iter.uv_total[plane_id])
-				iter.start = skl_ddb_entry_init(ddb, iter.start,
-								iter.start + iter.uv_total[plane_id]);
-		} else {
-			if (iter.total[plane_id])
-				iter.start = skl_ddb_entry_init(ddb, iter.start,
-								iter.start + iter.total[plane_id]);
-		}
-	}
-
 	/*
 	 * When we calculated watermark values we didn't know how high
 	 * of a level we'd actually be able to hit, so we just marked
@@ -5120,12 +5095,20 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
 	 */
 	for (level++; level <= ilk_wm_max_level(dev_priv); level++) {
 		for_each_plane_id_on_crtc(crtc, plane_id) {
+			const struct skl_ddb_entry *ddb =
+				&crtc_state->wm.skl.plane_ddb[plane_id];
+			const struct skl_ddb_entry *ddb_y =
+				&crtc_state->wm.skl.plane_ddb_y[plane_id];
 			struct skl_plane_wm *wm =
 				&crtc_state->wm.skl.optimal.planes[plane_id];
 
-			skl_check_nv12_wm_level(&wm->wm[level], &wm->uv_wm[level],
-						iter.total[plane_id],
-						iter.uv_total[plane_id]);
+			if (DISPLAY_VER(dev_priv) < 11 &&
+			    crtc_state->nv12_planes & BIT(plane_id))
+				skl_check_nv12_wm_level(&wm->wm[level],
+							&wm->uv_wm[level],
+							ddb_y, ddb);
+			else
+				skl_check_wm_level(&wm->wm[level], ddb);
 
 			if (icl_need_wm1_wa(dev_priv, plane_id) &&
 			    level == 1 && wm->wm[0].enable) {
@@ -5141,12 +5124,24 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
 	 * if it turns out we don't have enough DDB blocks for them.
 	 */
 	for_each_plane_id_on_crtc(crtc, plane_id) {
+		const struct skl_ddb_entry *ddb =
+			&crtc_state->wm.skl.plane_ddb[plane_id];
+		const struct skl_ddb_entry *ddb_y =
+			&crtc_state->wm.skl.plane_ddb_y[plane_id];
 		struct skl_plane_wm *wm =
 			&crtc_state->wm.skl.optimal.planes[plane_id];
 
-		skl_check_wm_level(&wm->trans_wm, iter.total[plane_id]);
-		skl_check_wm_level(&wm->sagv.wm0, iter.total[plane_id]);
-		skl_check_wm_level(&wm->sagv.trans_wm, iter.total[plane_id]);
+		if (DISPLAY_VER(dev_priv) < 11 &&
+		    crtc_state->nv12_planes & BIT(plane_id)) {
+			skl_check_wm_level(&wm->trans_wm, ddb_y);
+		} else {
+			WARN_ON(skl_ddb_entry_size(ddb_y));
+
+			skl_check_wm_level(&wm->trans_wm, ddb);
+		}
+
+		skl_check_wm_level(&wm->sagv.wm0, ddb);
+		skl_check_wm_level(&wm->sagv.trans_wm, ddb);
 	}
 
 	return 0;
-- 
2.32.0

[Intel-gfx] [PATCH 11/15] drm/i915: Nuke intel_bw_calc_min_cdclk()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

intel_bw_calc_min_cdclk() is entirely pointless. All it manages to do is
somehow conflate the per-pipe min cdclk with dbuf min cdclk. There is no
(at least documented) dbuf min cdclk limit on pre-skl so let's just get
rid of all this confusion.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c    | 49 ++--------------------
 drivers/gpu/drm/i915/display/intel_bw.h    |  1 -
 drivers/gpu/drm/i915/display/intel_cdclk.c | 31 +-------------
 3 files changed, 5 insertions(+), 76 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 93feab671c29..a3f169686f14 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -715,7 +715,7 @@ static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state,
 	}
 }
 
-int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
+int intel_bw_calc_min_cdclk(struct intel_atomic_state *state)
 {
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 	struct intel_bw_state *new_bw_state = NULL;
@@ -726,6 +726,9 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
 	enum pipe pipe;
 	int i;
 
+	if (DISPLAY_VER(dev_priv) < 9)
+		return 0;
+
 	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
 		new_bw_state = intel_atomic_get_bw_state(state);
 		if (IS_ERR(new_bw_state))
@@ -770,50 +773,6 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
 	return 0;
 }
 
-int intel_bw_calc_min_cdclk(struct intel_atomic_state *state)
-{
-	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-	struct intel_bw_state *new_bw_state = NULL;
-	struct intel_bw_state *old_bw_state = NULL;
-	const struct intel_crtc_state *crtc_state;
-	struct intel_crtc *crtc;
-	int min_cdclk = 0;
-	enum pipe pipe;
-	int i;
-
-	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
-		new_bw_state = intel_atomic_get_bw_state(state);
-		if (IS_ERR(new_bw_state))
-			return PTR_ERR(new_bw_state);
-
-		old_bw_state = intel_atomic_get_old_bw_state(state);
-	}
-
-	if (!old_bw_state)
-		return 0;
-
-	for_each_pipe(dev_priv, pipe) {
-		struct intel_cdclk_state *cdclk_state;
-
-		cdclk_state = intel_atomic_get_new_cdclk_state(state);
-		if (!cdclk_state)
-			return 0;
-
-		min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk);
-	}
-
-	new_bw_state->min_cdclk = min_cdclk;
-
-	if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) {
-		int ret = intel_atomic_lock_global_state(&new_bw_state->base);
-
-		if (ret)
-			return ret;
-	}
-
-	return 0;
-}
-
 int intel_bw_atomic_check(struct intel_atomic_state *state)
 {
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index 46c6eecbd917..57eb755d298a 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -65,6 +65,5 @@ void intel_bw_crtc_update(struct intel_bw_state *bw_state,
 int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
 				  u32 points_mask);
 int intel_bw_calc_min_cdclk(struct intel_atomic_state *state);
-int skl_bw_calc_min_cdclk(struct intel_atomic_state *state);
 
 #endif /* __INTEL_BW_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 7e20967307df..078dc6e1ee34 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -70,7 +70,6 @@ struct intel_cdclk_funcs {
 	void (*set_cdclk)(struct drm_i915_private *i915,
 			  const struct intel_cdclk_config *cdclk_config,
 			  enum pipe pipe);
-	int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
 	int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
 	u8 (*calc_voltage_level)(int cdclk);
 };
@@ -81,12 +80,6 @@ void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
 	dev_priv->cdclk_funcs->get_cdclk(dev_priv, cdclk_config);
 }
 
-static int intel_cdclk_bw_calc_min_cdclk(struct intel_atomic_state *state)
-{
-	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-	return dev_priv->cdclk_funcs->bw_calc_min_cdclk(state);
-}
-
 static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv,
 				  const struct intel_cdclk_config *cdclk_config,
 				  enum pipe pipe)
@@ -2680,7 +2673,7 @@ int intel_cdclk_atomic_check(struct intel_atomic_state *state,
 	    old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)
 		*need_cdclk_calc = true;
 
-	ret = intel_cdclk_bw_calc_min_cdclk(state);
+	ret = intel_bw_calc_min_cdclk(state);
 	if (ret)
 		return ret;
 
@@ -3069,7 +3062,6 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
 static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
 	.get_cdclk = bxt_get_cdclk,
 	.set_cdclk = bxt_set_cdclk,
-	.bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
 	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
 	.calc_voltage_level = tgl_calc_voltage_level,
 };
@@ -3077,7 +3069,6 @@ static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
 static const struct intel_cdclk_funcs ehl_cdclk_funcs = {
 	.get_cdclk = bxt_get_cdclk,
 	.set_cdclk = bxt_set_cdclk,
-	.bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
 	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
 	.calc_voltage_level = ehl_calc_voltage_level,
 };
@@ -3085,7 +3076,6 @@ static const struct intel_cdclk_funcs ehl_cdclk_funcs = {
 static const struct intel_cdclk_funcs icl_cdclk_funcs = {
 	.get_cdclk = bxt_get_cdclk,
 	.set_cdclk = bxt_set_cdclk,
-	.bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
 	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
 	.calc_voltage_level = icl_calc_voltage_level,
 };
@@ -3093,7 +3083,6 @@ static const struct intel_cdclk_funcs icl_cdclk_funcs = {
 static const struct intel_cdclk_funcs bxt_cdclk_funcs = {
 	.get_cdclk = bxt_get_cdclk,
 	.set_cdclk = bxt_set_cdclk,
-	.bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
 	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
 	.calc_voltage_level = bxt_calc_voltage_level,
 };
@@ -3101,53 +3090,45 @@ static const struct intel_cdclk_funcs bxt_cdclk_funcs = {
 static const struct intel_cdclk_funcs skl_cdclk_funcs = {
 	.get_cdclk = skl_get_cdclk,
 	.set_cdclk = skl_set_cdclk,
-	.bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
 	.modeset_calc_cdclk = skl_modeset_calc_cdclk,
 };
 
 static const struct intel_cdclk_funcs bdw_cdclk_funcs = {
 	.get_cdclk = bdw_get_cdclk,
 	.set_cdclk = bdw_set_cdclk,
-	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
 	.modeset_calc_cdclk = bdw_modeset_calc_cdclk,
 };
 
 static const struct intel_cdclk_funcs chv_cdclk_funcs = {
 	.get_cdclk = vlv_get_cdclk,
 	.set_cdclk = chv_set_cdclk,
-	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
 	.modeset_calc_cdclk = vlv_modeset_calc_cdclk,
 };
 
 static const struct intel_cdclk_funcs vlv_cdclk_funcs = {
 	.get_cdclk = vlv_get_cdclk,
 	.set_cdclk = vlv_set_cdclk,
-	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
 	.modeset_calc_cdclk = vlv_modeset_calc_cdclk,
 };
 
 static const struct intel_cdclk_funcs hsw_cdclk_funcs = {
 	.get_cdclk = hsw_get_cdclk,
-	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
 	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
 };
 
 /* SNB, IVB, 965G, 945G */
 static const struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = {
 	.get_cdclk = fixed_400mhz_get_cdclk,
-	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
 	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
 };
 
 static const struct intel_cdclk_funcs ilk_cdclk_funcs = {
 	.get_cdclk = fixed_450mhz_get_cdclk,
-	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
 	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
 };
 
 static const struct intel_cdclk_funcs gm45_cdclk_funcs = {
 	.get_cdclk = gm45_get_cdclk,
-	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
 	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
 };
 
@@ -3155,7 +3136,6 @@ static const struct intel_cdclk_funcs gm45_cdclk_funcs = {
 
 static const struct intel_cdclk_funcs i965gm_cdclk_funcs = {
 	.get_cdclk = i965gm_get_cdclk,
-	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
 	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
 };
 
@@ -3163,19 +3143,16 @@ static const struct intel_cdclk_funcs i965gm_cdclk_funcs = {
 
 static const struct intel_cdclk_funcs pnv_cdclk_funcs = {
 	.get_cdclk = pnv_get_cdclk,
-	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
 	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
 };
 
 static const struct intel_cdclk_funcs g33_cdclk_funcs = {
 	.get_cdclk = g33_get_cdclk,
-	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
 	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
 };
 
 static const struct intel_cdclk_funcs i945gm_cdclk_funcs = {
 	.get_cdclk = i945gm_get_cdclk,
-	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
 	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
 };
 
@@ -3183,37 +3160,31 @@ static const struct intel_cdclk_funcs i945gm_cdclk_funcs = {
 
 static const struct intel_cdclk_funcs i915gm_cdclk_funcs = {
 	.get_cdclk = i915gm_get_cdclk,
-	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
 	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
 };
 
 static const struct intel_cdclk_funcs i915g_cdclk_funcs = {
 	.get_cdclk = fixed_333mhz_get_cdclk,
-	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
 	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
 };
 
 static const struct intel_cdclk_funcs i865g_cdclk_funcs = {
 	.get_cdclk = fixed_266mhz_get_cdclk,
-	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
 	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
 };
 
 static const struct intel_cdclk_funcs i85x_cdclk_funcs = {
 	.get_cdclk = i85x_get_cdclk,
-	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
 	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
 };
 
 static const struct intel_cdclk_funcs i845g_cdclk_funcs = {
 	.get_cdclk = fixed_200mhz_get_cdclk,
-	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
 	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
 };
 
 static const struct intel_cdclk_funcs i830_cdclk_funcs = {
 	.get_cdclk = fixed_133mhz_get_cdclk,
-	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
 	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
 };
 
-- 
2.32.0

[Intel-gfx] [PATCH 12/15] drm/i915: Round up when calculating display bandwidth requirements

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We should round up when doing bandwidth calculations to make sure
our estimates don't fall short of the actual number.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index a3f169686f14..b0cdad89c1ba 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -636,7 +636,7 @@ static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
 		data_rate += bw_state->data_rate[pipe];
 
 	if (DISPLAY_VER(dev_priv) >= 13 && intel_vtd_active(dev_priv))
-		data_rate = data_rate * 105 / 100;
+		data_rate = DIV_ROUND_UP(data_rate * 105, 100);
 
 	return data_rate;
 }
@@ -761,7 +761,7 @@ int intel_bw_calc_min_cdclk(struct intel_atomic_state *state)
 		}
 	}
 
-	new_bw_state->min_cdclk = max_bw / 64;
+	new_bw_state->min_cdclk = DIV_ROUND_UP(max_bw, 64);
 
 	if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) {
 		int ret = intel_atomic_lock_global_state(&new_bw_state->base);
-- 
2.32.0

[Intel-gfx] [PATCH 13/15] drm/i915: Properly write lock bw_state when it changes

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The current code also forgets to call intel_atomic_lock_global_state()
when other stuff besides the final min_cdlck changes in the state.
That means we may throw away data which actually has changed, and
thus we can't be at all sure what the code ends up doing during
subsequent commits. Do the write lock properly.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 24 +++++++++++++++++++++++-
 1 file changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index b0cdad89c1ba..b1f6cf178678 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -676,6 +676,28 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state)
 	return to_intel_bw_state(bw_state);
 }
 
+static bool intel_bw_state_changed(struct drm_i915_private *i915,
+				   const struct intel_bw_state *old_bw_state,
+				   const struct intel_bw_state *new_bw_state)
+{
+	enum pipe pipe;
+
+	for_each_pipe(i915, pipe) {
+		const struct intel_dbuf_bw *old_crtc_bw =
+			&old_bw_state->dbuf_bw[pipe];
+		const struct intel_dbuf_bw *new_crtc_bw =
+			&new_bw_state->dbuf_bw[pipe];
+		enum dbuf_slice slice;
+
+		for_each_dbuf_slice(i915, slice) {
+			if (old_crtc_bw->used_bw[slice] != new_crtc_bw->used_bw[slice])
+				return true;
+		}
+	}
+
+	return old_bw_state->min_cdclk != new_bw_state->min_cdclk;
+}
+
 static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state,
 				  const struct intel_crtc_state *crtc_state)
 {
@@ -763,7 +785,7 @@ int intel_bw_calc_min_cdclk(struct intel_atomic_state *state)
 
 	new_bw_state->min_cdclk = DIV_ROUND_UP(max_bw, 64);
 
-	if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) {
+	if (intel_bw_state_changed(dev_priv, old_bw_state, new_bw_state)) {
 		int ret = intel_atomic_lock_global_state(&new_bw_state->base);
 
 		if (ret)
-- 
2.32.0

[Intel-gfx] [PATCH 14/15] drm/i915: Fix DBUF bandwidth vs. cdclk handling

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Make the dbuf bandwidth min cdclk calculations match the spec
more closely. Supposedly the arbiter can only guarantee an equal
share of the total bandwidth of the slice to each active plane
on that slice. So we take the max bandwidth of any of the planes
on each slice and multiply that by the number of active planes
on the slice to get a worst case estimate on how much bandwidth
we require.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c    | 159 +++++++++++++++------
 drivers/gpu/drm/i915/display/intel_bw.h    |  10 +-
 drivers/gpu/drm/i915/display/intel_cdclk.c |  67 ++++-----
 drivers/gpu/drm/i915/display/intel_cdclk.h |   2 +
 4 files changed, 148 insertions(+), 90 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index b1f6cf178678..072e5fcedc54 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -690,12 +690,34 @@ static bool intel_bw_state_changed(struct drm_i915_private *i915,
 		enum dbuf_slice slice;
 
 		for_each_dbuf_slice(i915, slice) {
-			if (old_crtc_bw->used_bw[slice] != new_crtc_bw->used_bw[slice])
+			if (old_crtc_bw->max_bw[slice] != new_crtc_bw->max_bw[slice] ||
+			    old_crtc_bw->active_planes[slice] != new_crtc_bw->active_planes[slice])
 				return true;
 		}
 	}
 
-	return old_bw_state->min_cdclk != new_bw_state->min_cdclk;
+	return false;
+}
+
+static void skl_plane_calc_dbuf_bw(struct intel_bw_state *bw_state,
+				   struct intel_crtc *crtc,
+				   enum plane_id plane_id,
+				   const struct skl_ddb_entry *ddb,
+				   unsigned int data_rate)
+{
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+	struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe];
+	unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(i915, ddb);
+	enum dbuf_slice slice;
+
+	/*
+	 * The arbiter can only really guarantee an
+	 * equal share of the total bw to each plane.
+	 */
+	for_each_dbuf_slice_in_mask(i915, slice, dbuf_mask) {
+		crtc_bw->max_bw[slice] = max(crtc_bw->max_bw[slice], data_rate);
+		crtc_bw->active_planes[slice] |= BIT(plane_id);
+	}
 }
 
 static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state,
@@ -706,46 +728,77 @@ static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state,
 	struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe];
 	enum plane_id plane_id;
 
-	memset(&crtc_bw->used_bw, 0, sizeof(crtc_bw->used_bw));
+	memset(crtc_bw, 0, sizeof(*crtc_bw));
 
 	if (!crtc_state->hw.active)
 		return;
 
 	for_each_plane_id_on_crtc(crtc, plane_id) {
-		const struct skl_ddb_entry *ddb =
-			&crtc_state->wm.skl.plane_ddb[plane_id];
-		unsigned int data_rate = crtc_state->data_rate[plane_id];
-		unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(i915, ddb);
-		enum dbuf_slice slice;
-
-		for_each_dbuf_slice_in_mask(i915, slice, dbuf_mask)
-			crtc_bw->used_bw[slice] += data_rate;
+		/*
+		 * We assume cursors are small enough
+		 * to not cause bandwidth problems.
+		 */
+		if (plane_id == PLANE_CURSOR)
+			continue;
+
+		skl_plane_calc_dbuf_bw(bw_state, crtc, plane_id,
+				       &crtc_state->wm.skl.plane_ddb[plane_id],
+				       crtc_state->data_rate[plane_id]);
+
+		if (DISPLAY_VER(i915) < 11)
+			skl_plane_calc_dbuf_bw(bw_state, crtc, plane_id,
+					       &crtc_state->wm.skl.plane_ddb_y[plane_id],
+					       crtc_state->data_rate[plane_id]);
 	}
+}
+
+/* "Maximum Data Buffer Bandwidth" */
+static int
+intel_bw_dbuf_min_cdclk(struct drm_i915_private *i915,
+			const struct intel_bw_state *bw_state)
+{
+	unsigned int total_max_bw = 0;
+	enum dbuf_slice slice;
 
-	if (DISPLAY_VER(i915) >= 11)
-		return;
+	for_each_dbuf_slice(i915, slice) {
+		int num_active_planes = 0;
+		unsigned int max_bw = 0;
+		enum pipe pipe;
 
-	for_each_plane_id_on_crtc(crtc, plane_id) {
-		const struct skl_ddb_entry *ddb =
-			&crtc_state->wm.skl.plane_ddb_y[plane_id];
-		unsigned int data_rate = crtc_state->data_rate_y[plane_id];
-		unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(i915, ddb);
-		enum dbuf_slice slice;
+		/*
+		 * The arbiter can only really guarantee an
+		 * equal share of the total bw to each plane.
+		 */
+		for_each_pipe(i915, pipe) {
+			const struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[pipe];
 
-		for_each_dbuf_slice_in_mask(i915, slice, dbuf_mask)
-			crtc_bw->used_bw[slice] += data_rate;
+			max_bw = max(crtc_bw->max_bw[slice], max_bw);
+			num_active_planes += hweight8(crtc_bw->active_planes[slice]);
+		}
+		max_bw *= num_active_planes;
+
+		total_max_bw = max(total_max_bw, max_bw);
 	}
+
+	return DIV_ROUND_UP(total_max_bw, 64);
+}
+
+int intel_bw_min_cdclk(struct drm_i915_private *i915,
+		       const struct intel_bw_state *bw_state)
+{
+	return intel_bw_dbuf_min_cdclk(i915, bw_state);
 }
 
-int intel_bw_calc_min_cdclk(struct intel_atomic_state *state)
+int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
+			    bool *need_cdclk_calc)
 {
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 	struct intel_bw_state *new_bw_state = NULL;
-	struct intel_bw_state *old_bw_state = NULL;
+	const struct intel_bw_state *old_bw_state = NULL;
+	const struct intel_cdclk_state *cdclk_state;
 	const struct intel_crtc_state *crtc_state;
+	int old_min_cdclk, new_min_cdclk;
 	struct intel_crtc *crtc;
-	int max_bw = 0;
-	enum pipe pipe;
 	int i;
 
 	if (DISPLAY_VER(dev_priv) < 9)
@@ -764,34 +817,46 @@ int intel_bw_calc_min_cdclk(struct intel_atomic_state *state)
 	if (!old_bw_state)
 		return 0;
 
-	for_each_pipe(dev_priv, pipe) {
-		struct intel_dbuf_bw *crtc_bw;
-		enum dbuf_slice slice;
-
-		crtc_bw = &new_bw_state->dbuf_bw[pipe];
-
-		for_each_dbuf_slice(dev_priv, slice) {
-			/*
-			 * Current experimental observations show that contrary
-			 * to BSpec we get underruns once we exceed 64 * CDCLK
-			 * for slices in total.
-			 * As a temporary measure in order not to keep CDCLK
-			 * bumped up all the time we calculate CDCLK according
-			 * to this formula for  overall bw consumed by slices.
-			 */
-			max_bw += crtc_bw->used_bw[slice];
-		}
-	}
-
-	new_bw_state->min_cdclk = DIV_ROUND_UP(max_bw, 64);
-
 	if (intel_bw_state_changed(dev_priv, old_bw_state, new_bw_state)) {
 		int ret = intel_atomic_lock_global_state(&new_bw_state->base);
-
 		if (ret)
 			return ret;
 	}
 
+	old_min_cdclk = intel_bw_min_cdclk(dev_priv, old_bw_state);
+	new_min_cdclk = intel_bw_min_cdclk(dev_priv, new_bw_state);
+
+	/*
+	 * No need to check against the cdclk state if
+	 * the min cdclk for the dbuf doesn't increase.
+	 *
+	 * Ie. we only ever increase the cdclk due to dbuf
+	 * requirements. This can reduce back and forth
+	 * display blinking due to constant cdclk changes.
+	 */
+	if (new_min_cdclk <= old_min_cdclk)
+		return 0;
+
+	cdclk_state = intel_atomic_get_cdclk_state(state);
+	if (IS_ERR(cdclk_state))
+		return PTR_ERR(cdclk_state);
+
+	/*
+	 * No need to recalculate the cdclk state if
+	 * the min cdclk for the dbuf doesn't increase.
+	 *
+	 * Ie. we only ever increase the cdclk due to dbuf
+	 * requirements. This can reduce back and forth
+	 * display blinking due to constant cdclk changes.
+	 */
+	if (new_min_cdclk <= cdclk_state->bw_min_cdclk)
+		return 0;
+
+	drm_dbg_kms(&dev_priv->drm,
+		    "new bandwidth min cdclk (%d kHz) > old min cdclk (%d kHz)\n",
+		    new_min_cdclk, cdclk_state->bw_min_cdclk);
+	*need_cdclk_calc = true;
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index 57eb755d298a..1edab79d120c 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -17,7 +17,8 @@ struct intel_atomic_state;
 struct intel_crtc_state;
 
 struct intel_dbuf_bw {
-	int used_bw[I915_MAX_DBUF_SLICES];
+	unsigned int max_bw[I915_MAX_DBUF_SLICES];
+	u8 active_planes[I915_MAX_DBUF_SLICES];
 };
 
 struct intel_bw_state {
@@ -42,8 +43,6 @@ struct intel_bw_state {
 
 	/* bitmask of active pipes */
 	u8 active_pipes;
-
-	int min_cdclk;
 };
 
 #define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
@@ -64,6 +63,9 @@ void intel_bw_crtc_update(struct intel_bw_state *bw_state,
 			  const struct intel_crtc_state *crtc_state);
 int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
 				  u32 points_mask);
-int intel_bw_calc_min_cdclk(struct intel_atomic_state *state);
+int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
+			    bool *need_cdclk_calc);
+int intel_bw_min_cdclk(struct drm_i915_private *i915,
+		       const struct intel_bw_state *bw_state);
 
 #endif /* __INTEL_BW_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 078dc6e1ee34..a2446802ded5 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2315,13 +2315,6 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
 					dev_priv->max_cdclk_freq));
 	}
 
-	if (min_cdclk > dev_priv->max_cdclk_freq) {
-		drm_dbg_kms(&dev_priv->drm,
-			    "required cdclk (%d kHz) exceeds max (%d kHz)\n",
-			    min_cdclk, dev_priv->max_cdclk_freq);
-		return -EINVAL;
-	}
-
 	return min_cdclk;
 }
 
@@ -2329,7 +2322,7 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
 {
 	struct intel_atomic_state *state = cdclk_state->base.state;
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-	struct intel_bw_state *bw_state = NULL;
+	const struct intel_bw_state *bw_state;
 	struct intel_crtc *crtc;
 	struct intel_crtc_state *crtc_state;
 	int min_cdclk, i;
@@ -2342,10 +2335,6 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
 		if (min_cdclk < 0)
 			return min_cdclk;
 
-		bw_state = intel_atomic_get_bw_state(state);
-		if (IS_ERR(bw_state))
-			return PTR_ERR(bw_state);
-
 		if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk)
 			continue;
 
@@ -2356,14 +2345,31 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
 			return ret;
 	}
 
-	min_cdclk = cdclk_state->force_min_cdclk;
-	for_each_pipe(dev_priv, pipe) {
+	bw_state = intel_atomic_get_new_bw_state(state);
+	if (bw_state) {
+		min_cdclk = intel_bw_min_cdclk(dev_priv, bw_state);
+
+		if (cdclk_state->bw_min_cdclk != min_cdclk) {
+			int ret;
+
+			cdclk_state->bw_min_cdclk = min_cdclk;
+
+			ret = intel_atomic_lock_global_state(&cdclk_state->base);
+			if (ret)
+				return ret;
+		}
+	}
+
+	min_cdclk = max(cdclk_state->force_min_cdclk,
+			cdclk_state->bw_min_cdclk);
+	for_each_pipe(dev_priv, pipe)
 		min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk);
 
-		if (!bw_state)
-			continue;
-
-		min_cdclk = max(bw_state->min_cdclk, min_cdclk);
+	if (min_cdclk > dev_priv->max_cdclk_freq) {
+		drm_dbg_kms(&dev_priv->drm,
+			    "required cdclk (%d kHz) exceeds max (%d kHz)\n",
+			    min_cdclk, dev_priv->max_cdclk_freq);
+		return -EINVAL;
 	}
 
 	return min_cdclk;
@@ -2644,14 +2650,10 @@ intel_atomic_get_cdclk_state(struct intel_atomic_state *state)
 int intel_cdclk_atomic_check(struct intel_atomic_state *state,
 			     bool *need_cdclk_calc)
 {
-	struct drm_i915_private *i915 = to_i915(state->base.dev);
 	const struct intel_cdclk_state *old_cdclk_state;
 	const struct intel_cdclk_state *new_cdclk_state;
 	struct intel_plane_state *plane_state;
-	struct intel_bw_state *new_bw_state;
 	struct intel_plane *plane;
-	int min_cdclk = 0;
-	enum pipe pipe;
 	int ret;
 	int i;
 
@@ -2666,6 +2668,10 @@ int intel_cdclk_atomic_check(struct intel_atomic_state *state,
 			return ret;
 	}
 
+	ret = intel_bw_calc_min_cdclk(state, need_cdclk_calc);
+	if (ret)
+		return ret;
+
 	old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
 	new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
 
@@ -2673,23 +2679,6 @@ int intel_cdclk_atomic_check(struct intel_atomic_state *state,
 	    old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)
 		*need_cdclk_calc = true;
 
-	ret = intel_bw_calc_min_cdclk(state);
-	if (ret)
-		return ret;
-
-	new_bw_state = intel_atomic_get_new_bw_state(state);
-
-	if (!new_cdclk_state || !new_bw_state)
-		return 0;
-
-	for_each_pipe(i915, pipe) {
-		min_cdclk = max(new_cdclk_state->min_cdclk[pipe], min_cdclk);
-
-		/* Currently do this change only if we need to increase */
-		if (new_bw_state->min_cdclk > min_cdclk)
-			*need_cdclk_calc = true;
-	}
-
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index 71dd84740ae3..ace24de746a4 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -36,6 +36,8 @@ struct intel_cdclk_state {
 	 */
 	struct intel_cdclk_config actual;
 
+	/* minimum acceptable cdclk to satisfy bandwidth requirements */
+	int bw_min_cdclk;
 	/* minimum acceptable cdclk for each pipe */
 	int min_cdclk[I915_MAX_PIPES];
 	/* minimum acceptable voltage level for each pipe */
-- 
2.32.0

[Intel-gfx] [PATCH 15/15] drm/i915: Add "maximum pipe read bandwidth" checks

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Make sure the CDCLK is high enough to support the so called
"maximum pipe read bandwidth" limitation. Specified as
51.2 x CDCLK.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 36 +++++++++++++++++++++----
 drivers/gpu/drm/i915/display/intel_bw.h |  1 +
 2 files changed, 32 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 072e5fcedc54..4b3e903c5d67 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -597,6 +597,18 @@ static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_
 	return data_rate;
 }
 
+/* "Maximum Pipe Read Bandwidth" */
+static int intel_bw_crtc_min_cdclk(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+
+	if (DISPLAY_VER(i915) < 12)
+		return 0;
+
+	return DIV_ROUND_UP_ULL(mul_u32_u32(intel_bw_crtc_data_rate(crtc_state), 10), 512);
+}
+
 void intel_bw_crtc_update(struct intel_bw_state *bw_state,
 			  const struct intel_crtc_state *crtc_state)
 {
@@ -694,6 +706,9 @@ static bool intel_bw_state_changed(struct drm_i915_private *i915,
 			    old_crtc_bw->active_planes[slice] != new_crtc_bw->active_planes[slice])
 				return true;
 		}
+
+		if (old_bw_state->min_cdclk[pipe] != new_bw_state->min_cdclk[pipe])
+			return true;
 	}
 
 	return false;
@@ -786,7 +801,15 @@ intel_bw_dbuf_min_cdclk(struct drm_i915_private *i915,
 int intel_bw_min_cdclk(struct drm_i915_private *i915,
 		       const struct intel_bw_state *bw_state)
 {
-	return intel_bw_dbuf_min_cdclk(i915, bw_state);
+	enum pipe pipe;
+	int min_cdclk;
+
+	min_cdclk = intel_bw_dbuf_min_cdclk(i915, bw_state);
+
+	for_each_pipe(i915, pipe)
+		min_cdclk = max(bw_state->min_cdclk[pipe], min_cdclk);
+
+	return min_cdclk;
 }
 
 int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
@@ -812,6 +835,9 @@ int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
 		old_bw_state = intel_atomic_get_old_bw_state(state);
 
 		skl_crtc_calc_dbuf_bw(new_bw_state, crtc_state);
+
+		new_bw_state->min_cdclk[crtc->pipe] =
+			intel_bw_crtc_min_cdclk(crtc_state);
 	}
 
 	if (!old_bw_state)
@@ -828,9 +854,9 @@ int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
 
 	/*
 	 * No need to check against the cdclk state if
-	 * the min cdclk for the dbuf doesn't increase.
+	 * the min cdclk doesn't increase.
 	 *
-	 * Ie. we only ever increase the cdclk due to dbuf
+	 * Ie. we only ever increase the cdclk due to bandwidth
 	 * requirements. This can reduce back and forth
 	 * display blinking due to constant cdclk changes.
 	 */
@@ -843,9 +869,9 @@ int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
 
 	/*
 	 * No need to recalculate the cdclk state if
-	 * the min cdclk for the dbuf doesn't increase.
+	 * the min cdclk doesn't increase.
 	 *
-	 * Ie. we only ever increase the cdclk due to dbuf
+	 * Ie. we only ever increase the cdclk due to bandwidth
 	 * requirements. This can reduce back and forth
 	 * display blinking due to constant cdclk changes.
 	 */
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index 1edab79d120c..aaaf10f04d96 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -38,6 +38,7 @@ struct intel_bw_state {
 	 */
 	u8 qgv_points_mask;
 
+	int min_cdclk[I915_MAX_PIPES];
 	unsigned int data_rate[I915_MAX_PIPES];
 	u8 num_active_planes[I915_MAX_PIPES];
 
-- 
2.32.0

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Fix bandwith related cdclk calculations

[Patchwork]

== Series Details ==

Series: drm/i915: Fix bandwith related cdclk calculations
URL   : https://patchwork.freedesktop.org/series/98975/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
f65f6b681b85 drm/i915: Drop pointless dev_priv argument
9668fabd85a5 drm/i915: Extract skl_ddb_entry_init()
dee30e2a1ae4 drm/i915: Fix plane relative_data_rate calculation
73d19f52835a drm/i915: Introduce skl_plane_ddb_iter
fbf2a65a754f drm/i915: Extract skl_allocate_plane_ddb()
8eb5c0bb1655 drm/i915: Extract skl_crtc_calc_dbuf_bw()
e7ec581a03b3 drm/i915: Tweak plane ddb allocation tracking
988a18fdccaa drm/i915: Split plane data_rate into data_rate+data_rate_y
f3dc6a126906 drm/i915: Pre-calculate plane relative data rate
-:345: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#345: FILE: drivers/gpu/drm/i915/intel_pm.c:5107:
+								iter.start + iter.uv_total[plane_id]);

total: 0 errors, 1 warnings, 0 checks, 302 lines checked
3d9ea614fc38 drm/i915: Remove total[] and uv_total[] from ddb allocation
2eca9b239d7d drm/i915: Nuke intel_bw_calc_min_cdclk()
28a02ba19afc drm/i915: Round up when calculating display bandwidth requirements
08b2d8e87205 drm/i915: Properly write lock bw_state when it changes
e3a2fec61118 drm/i915: Fix DBUF bandwidth vs. cdclk handling
7d55ec242dd3 drm/i915: Add "maximum pipe read bandwidth" checks

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Fix bandwith related cdclk calculations

[Patchwork]

== Series Details ==

Series: drm/i915: Fix bandwith related cdclk calculations
URL   : https://patchwork.freedesktop.org/series/98975/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix bandwith related cdclk calculations

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 9532 bytes --]

== Series Details ==

Series: drm/i915: Fix bandwith related cdclk calculations
URL   : https://patchwork.freedesktop.org/series/98975/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11094 -> Patchwork_22010
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/index.html

Participating hosts (46 -> 40)
------------------------------

  Additional (1): fi-icl-u2 
  Missing    (7): shard-tglu fi-bsw-cyan fi-kbl-7500u shard-rkl shard-dg1 bat-jsl-2 fi-bdw-samus 

Known issues
------------

  Here are the changes found in Patchwork_22010 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@semaphore:
    - fi-bdw-5557u:       NOTRUN -> [SKIP][1] ([fdo#109271]) +31 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/fi-bdw-5557u/igt@amdgpu/amd_basic@semaphore.html

  * igt@amdgpu/amd_cs_nop@fork-gfx0:
    - fi-icl-u2:          NOTRUN -> [SKIP][2] ([fdo#109315]) +17 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/fi-icl-u2/igt@amdgpu/amd_cs_nop@fork-gfx0.html

  * igt@amdgpu/amd_cs_nop@sync-fork-compute0:
    - fi-snb-2600:        NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/fi-snb-2600/igt@amdgpu/amd_cs_nop@sync-fork-compute0.html

  * igt@gem_flink_basic@bad-flink:
    - fi-skl-6600u:       [PASS][4] -> [INCOMPLETE][5] ([i915#4547])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html

  * igt@gem_huc_copy@huc-copy:
    - fi-icl-u2:          NOTRUN -> [SKIP][6] ([i915#2190])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/fi-icl-u2/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - fi-icl-u2:          NOTRUN -> [SKIP][7] ([i915#4613]) +3 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/fi-icl-u2/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-icl-u2:          NOTRUN -> [SKIP][8] ([fdo#111827]) +8 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html

  * igt@kms_chamelium@vga-edid-read:
    - fi-bdw-5557u:       NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/fi-bdw-5557u/igt@kms_chamelium@vga-edid-read.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - fi-icl-u2:          NOTRUN -> [SKIP][10] ([fdo#109278]) +2 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_force_connector_basic@force-load-detect:
    - fi-icl-u2:          NOTRUN -> [SKIP][11] ([fdo#109285])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/fi-icl-u2/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-cfl-8109u:       [PASS][12] -> [DMESG-FAIL][13] ([i915#295])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-b:
    - fi-cfl-8109u:       [PASS][14] -> [DMESG-WARN][15] ([i915#295]) +10 similar issues
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/fi-cfl-8109u/igt@kms_pipe_crc_basic@read-crc-pipe-b.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/fi-cfl-8109u/igt@kms_pipe_crc_basic@read-crc-pipe-b.html

  * igt@prime_vgem@basic-userptr:
    - fi-icl-u2:          NOTRUN -> [SKIP][16] ([i915#3301])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/fi-icl-u2/igt@prime_vgem@basic-userptr.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s3@smem:
    - fi-bdw-5557u:       [INCOMPLETE][17] ([i915#146]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3@smem.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3@smem.html

  * igt@i915_selftest@live@gt_heartbeat:
    - {fi-tgl-dsi}:       [INCOMPLETE][19] -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@hangcheck:
    - bat-dg1-6:          [DMESG-FAIL][21] ([i915#4494]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
    - fi-snb-2600:        [INCOMPLETE][23] ([i915#3921]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/fi-snb-2600/igt@i915_selftest@live@hangcheck.html

  
#### Warnings ####

  * igt@runner@aborted:
    - fi-skl-6600u:       [FAIL][25] ([i915#4312]) -> [FAIL][26] ([i915#2722] / [i915#4312])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/fi-skl-6600u/igt@runner@aborted.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/fi-skl-6600u/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
  [i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
  [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
  [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
  [i915#4897]: https://gitlab.freedesktop.org/drm/intel/issues/4897


Build changes
-------------

  * Linux: CI_DRM_11094 -> Patchwork_22010

  CI-20190529: 20190529
  CI_DRM_11094: 6ce31c986ee8beaa0f98fd4e200b7a421fd4adf9 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6327: 0d559158c2d3b5723abbfc2cb4b04532e28663b2 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_22010: 7d55ec242dd368a9a7d0a32d4572f81addbb684d @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

7d55ec242dd3 drm/i915: Add "maximum pipe read bandwidth" checks
e3a2fec61118 drm/i915: Fix DBUF bandwidth vs. cdclk handling
08b2d8e87205 drm/i915: Properly write lock bw_state when it changes
28a02ba19afc drm/i915: Round up when calculating display bandwidth requirements
2eca9b239d7d drm/i915: Nuke intel_bw_calc_min_cdclk()
3d9ea614fc38 drm/i915: Remove total[] and uv_total[] from ddb allocation
f3dc6a126906 drm/i915: Pre-calculate plane relative data rate
988a18fdccaa drm/i915: Split plane data_rate into data_rate+data_rate_y
e7ec581a03b3 drm/i915: Tweak plane ddb allocation tracking
8eb5c0bb1655 drm/i915: Extract skl_crtc_calc_dbuf_bw()
fbf2a65a754f drm/i915: Extract skl_allocate_plane_ddb()
73d19f52835a drm/i915: Introduce skl_plane_ddb_iter
dee30e2a1ae4 drm/i915: Fix plane relative_data_rate calculation
9668fabd85a5 drm/i915: Extract skl_ddb_entry_init()
f65f6b681b85 drm/i915: Drop pointless dev_priv argument

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/index.html

[-- Attachment #2: Type: text/html, Size: 9987 bytes --]

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Fix bandwith related cdclk calculations

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 30272 bytes --]

== Series Details ==

Series: drm/i915: Fix bandwith related cdclk calculations
URL   : https://patchwork.freedesktop.org/series/98975/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11094_full -> Patchwork_22010_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_22010_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22010_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (13 -> 13)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_22010_full:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_pm_rpm@system-suspend-devices:
    - shard-iclb:         [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-iclb7/igt@i915_pm_rpm@system-suspend-devices.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-iclb7/igt@i915_pm_rpm@system-suspend-devices.html

  * igt@i915_selftest@live@hangcheck:
    - shard-tglb:         [PASS][3] -> [DMESG-FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-tglb8/igt@i915_selftest@live@hangcheck.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-tglb5/igt@i915_selftest@live@hangcheck.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_ctx_persistence@smoketest:
    - {shard-tglu}:       [PASS][5] -> [INCOMPLETE][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-tglu-1/igt@gem_ctx_persistence@smoketest.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-tglu-7/igt@gem_ctx_persistence@smoketest.html

  * igt@gem_exec_schedule@smoketest@rcs0:
    - {shard-rkl}:        [PASS][7] -> [INCOMPLETE][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-rkl-1/igt@gem_exec_schedule@smoketest@rcs0.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-rkl-5/igt@gem_exec_schedule@smoketest@rcs0.html

  * igt@i915_hangman@engine-hang@vcs0:
    - {shard-rkl}:        [PASS][9] -> [FAIL][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-rkl-2/igt@i915_hangman@engine-hang@vcs0.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-rkl-5/igt@i915_hangman@engine-hang@vcs0.html

  * igt@kms_cursor_legacy@all-pipes-forked-move:
    - {shard-rkl}:        NOTRUN -> [INCOMPLETE][11]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-rkl-5/igt@kms_cursor_legacy@all-pipes-forked-move.html

  * igt@runner@aborted:
    - {shard-tglu}:       ([FAIL][12], [FAIL][13], [FAIL][14]) ([i915#3002] / [i915#4312]) -> ([FAIL][15], [FAIL][16], [FAIL][17], [FAIL][18]) ([i915#2722] / [i915#3002] / [i915#4312])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-tglu-6/igt@runner@aborted.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-tglu-7/igt@runner@aborted.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-tglu-1/igt@runner@aborted.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-tglu-1/igt@runner@aborted.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-tglu-4/igt@runner@aborted.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-tglu-2/igt@runner@aborted.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-tglu-7/igt@runner@aborted.html

  
Known issues
------------

  Here are the changes found in Patchwork_22010_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@preservation-s3@bcs0:
    - shard-kbl:          [PASS][19] -> [DMESG-WARN][20] ([i915#180]) +1 similar issue
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-kbl1/igt@gem_ctx_isolation@preservation-s3@bcs0.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-kbl1/igt@gem_ctx_isolation@preservation-s3@bcs0.html

  * igt@gem_exec_balancer@parallel-out-fence:
    - shard-iclb:         [PASS][21] -> [SKIP][22] ([i915#4525]) +2 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-iclb2/igt@gem_exec_balancer@parallel-out-fence.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-iclb6/igt@gem_exec_balancer@parallel-out-fence.html

  * igt@gem_exec_capture@pi@vcs0:
    - shard-skl:          NOTRUN -> [INCOMPLETE][23] ([i915#4547])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-skl8/igt@gem_exec_capture@pi@vcs0.html

  * igt@gem_exec_endless@dispatch@vecs0:
    - shard-tglb:         [PASS][24] -> [INCOMPLETE][25] ([i915#3778])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-tglb8/igt@gem_exec_endless@dispatch@vecs0.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-tglb3/igt@gem_exec_endless@dispatch@vecs0.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-skl:          NOTRUN -> [FAIL][26] ([i915#2846])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-skl2/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-none@vecs0:
    - shard-kbl:          NOTRUN -> [FAIL][27] ([i915#2842])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-kbl4/igt@gem_exec_fair@basic-none@vecs0.html

  * igt@gem_exec_fair@basic-pace@vecs0:
    - shard-kbl:          [PASS][28] -> [FAIL][29] ([i915#2842]) +2 similar issues
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-kbl1/igt@gem_exec_fair@basic-pace@vecs0.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-kbl1/igt@gem_exec_fair@basic-pace@vecs0.html

  * igt@gem_exec_whisper@basic-queues-forked-all:
    - shard-glk:          [PASS][30] -> [DMESG-WARN][31] ([i915#118])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-glk8/igt@gem_exec_whisper@basic-queues-forked-all.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-glk8/igt@gem_exec_whisper@basic-queues-forked-all.html

  * igt@gem_huc_copy@huc-copy:
    - shard-kbl:          NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#2190])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-kbl7/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@heavy-random:
    - shard-skl:          NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#4613]) +2 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-skl10/igt@gem_lmem_swapping@heavy-random.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-skl:          NOTRUN -> [WARN][34] ([i915#2658])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-skl10/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-kbl:          NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#3323])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-kbl1/igt@gem_userptr_blits@dmabuf-sync.html
    - shard-skl:          NOTRUN -> [SKIP][36] ([fdo#109271] / [i915#3323])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-skl9/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@vma-merge:
    - shard-skl:          NOTRUN -> [FAIL][37] ([i915#3318])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-skl8/igt@gem_userptr_blits@vma-merge.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-skl:          NOTRUN -> [FAIL][38] ([i915#454])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-skl7/igt@i915_pm_dc@dc6-psr.html

  * igt@i915_pm_dc@dc9-dpms:
    - shard-iclb:         [PASS][39] -> [SKIP][40] ([i915#4281])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-iclb4/igt@i915_pm_dc@dc9-dpms.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
    - shard-skl:          NOTRUN -> [FAIL][41] ([i915#3743]) +2 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-skl10/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-skl:          NOTRUN -> [SKIP][42] ([fdo#109271] / [i915#3777]) +3 similar issues
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-skl10/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-kbl:          NOTRUN -> [SKIP][43] ([fdo#109271] / [i915#3777])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-kbl7/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs:
    - shard-apl:          NOTRUN -> [SKIP][44] ([fdo#109271]) +18 similar issues
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-apl7/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs.html

  * igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
    - shard-kbl:          NOTRUN -> [SKIP][45] ([fdo#109271] / [i915#3886]) +4 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-kbl7/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
    - shard-skl:          NOTRUN -> [SKIP][46] ([fdo#109271] / [i915#3886]) +13 similar issues
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-skl4/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html

  * igt@kms_color_chamelium@pipe-b-ctm-limited-range:
    - shard-apl:          NOTRUN -> [SKIP][47] ([fdo#109271] / [fdo#111827]) +1 similar issue
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-apl2/igt@kms_color_chamelium@pipe-b-ctm-limited-range.html

  * igt@kms_color_chamelium@pipe-b-ctm-max:
    - shard-skl:          NOTRUN -> [SKIP][48] ([fdo#109271] / [fdo#111827]) +28 similar issues
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-skl8/igt@kms_color_chamelium@pipe-b-ctm-max.html

  * igt@kms_color_chamelium@pipe-c-ctm-max:
    - shard-kbl:          NOTRUN -> [SKIP][49] ([fdo#109271] / [fdo#111827]) +4 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-kbl4/igt@kms_color_chamelium@pipe-c-ctm-max.html

  * igt@kms_color_chamelium@pipe-d-ctm-blue-to-red:
    - shard-snb:          NOTRUN -> [SKIP][50] ([fdo#109271] / [fdo#111827])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-snb7/igt@kms_color_chamelium@pipe-d-ctm-blue-to-red.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-iclb:         [PASS][51] -> [FAIL][52] ([i915#2346])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
    - shard-glk:          [PASS][53] -> [FAIL][54] ([i915#2346] / [i915#533])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-glk5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2:
    - shard-glk:          [PASS][55] -> [FAIL][56] ([i915#79])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-glk5/igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
    - shard-skl:          [PASS][57] -> [FAIL][58] ([i915#79])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
    - shard-apl:          [PASS][59] -> [DMESG-WARN][60] ([i915#180]) +3 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html

  * igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1:
    - shard-skl:          NOTRUN -> [FAIL][61] ([i915#2122])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-skl2/igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling:
    - shard-glk:          [PASS][62] -> [FAIL][63] ([i915#4911])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-glk9/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling:
    - shard-iclb:         [PASS][64] -> [SKIP][65] ([i915#3701])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-iclb8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html

  * igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack-mmap-gtt:
    - shard-skl:          NOTRUN -> [SKIP][66] ([fdo#109271]) +364 similar issues
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-skl10/igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt:
    - shard-kbl:          NOTRUN -> [SKIP][67] ([fdo#109271]) +72 similar issues
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-kbl4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt:
    - shard-snb:          NOTRUN -> [SKIP][68] ([fdo#109271]) +35 similar issues
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-snb7/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-skl:          [PASS][69] -> [FAIL][70] ([i915#1188])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-skl8/igt@kms_hdr@bpc-switch-suspend.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-skl10/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
    - shard-skl:          NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#533])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-skl2/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
    - shard-skl:          [PASS][72] -> [INCOMPLETE][73] ([i915#2828])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-skl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-skl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
    - shard-kbl:          NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#533]) +1 similar issue
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-kbl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
    - shard-skl:          NOTRUN -> [FAIL][75] ([fdo#108145] / [i915#265]) +7 similar issues
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
    - shard-skl:          NOTRUN -> [FAIL][76] ([i915#265]) +1 similar issue
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html

  * igt@kms_psr2_sf@cursor-plane-update-sf:
    - shard-skl:          NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#658]) +4 similar issues
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-skl3/igt@kms_psr2_sf@cursor-plane-update-sf.html

  * igt@kms_psr@psr2_cursor_plane_onoff:
    - shard-iclb:         [PASS][78] -> [SKIP][79] ([fdo#109441])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-iclb6/igt@kms_psr@psr2_cursor_plane_onoff.html

  * igt@kms_writeback@writeback-check-output:
    - shard-skl:          NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#2437])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-skl10/igt@kms_writeback@writeback-check-output.html

  * igt@sysfs_clients@fair-0:
    - shard-skl:          NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#2994]) +5 similar issues
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-skl3/igt@sysfs_clients@fair-0.html

  
#### Possible fixes ####

  * igt@gem_ctx_shared@q-smoketest-all:
    - {shard-rkl}:        ([INCOMPLETE][82], [PASS][83]) -> [PASS][84]
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-rkl-5/igt@gem_ctx_shared@q-smoketest-all.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-rkl-4/igt@gem_ctx_shared@q-smoketest-all.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-rkl-4/igt@gem_ctx_shared@q-smoketest-all.html

  * igt@gem_eio@in-flight-contexts-1us:
    - shard-tglb:         [TIMEOUT][85] ([i915#3063]) -> [PASS][86]
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-tglb8/igt@gem_eio@in-flight-contexts-1us.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-tglb3/igt@gem_eio@in-flight-contexts-1us.html

  * igt@gem_exec_balancer@parallel:
    - shard-iclb:         [SKIP][87] ([i915#4525]) -> [PASS][88] +1 similar issue
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-iclb8/igt@gem_exec_balancer@parallel.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-iclb2/igt@gem_exec_balancer@parallel.html

  * igt@gem_exec_create@forked@smem:
    - {shard-tglu}:       [INCOMPLETE][89] -> [PASS][90]
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-tglu-7/igt@gem_exec_create@forked@smem.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-tglu-4/igt@gem_exec_create@forked@smem.html

  * igt@gem_exec_create@legacy@smem:
    - {shard-rkl}:        [DMESG-WARN][91] -> ([PASS][92], [PASS][93])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-rkl-5/igt@gem_exec_create@legacy@smem.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-rkl-5/igt@gem_exec_create@legacy@smem.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-rkl-4/igt@gem_exec_create@legacy@smem.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-glk:          [FAIL][94] ([i915#2846]) -> [PASS][95]
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-glk8/igt@gem_exec_fair@basic-deadline.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-glk2/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-kbl:          [FAIL][96] ([i915#2842]) -> [PASS][97] +2 similar issues
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-kbl3/igt@gem_exec_fair@basic-none-solo@rcs0.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-kbl4/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-iclb:         [FAIL][98] ([i915#2842]) -> [PASS][99]
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-iclb6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-iclb5/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_exec_reloc@basic-scanout@vecs0:
    - {shard-rkl}:        [SKIP][100] ([i915#3639]) -> [PASS][101] +3 similar issues
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-rkl-2/igt@gem_exec_reloc@basic-scanout@vecs0.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-rkl-6/igt@gem_exec_reloc@basic-scanout@vecs0.html

  * igt@gem_exec_suspend@basic-s3@smem:
    - shard-apl:          [DMESG-WARN][102] ([i915#180]) -> [PASS][103] +2 similar issues
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-apl1/igt@gem_exec_suspend@basic-s3@smem.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-apl2/igt@gem_exec_suspend@basic-s3@smem.html

  * igt@gem_exec_whisper@basic-contexts-all:
    - shard-glk:          [DMESG-WARN][104] ([i915#118]) -> [PASS][105]
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-glk3/igt@gem_exec_whisper@basic-contexts-all.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-glk2/igt@gem_exec_whisper@basic-contexts-all.html

  * igt@gem_huc_copy@huc-copy:
    - shard-tglb:         [SKIP][106] ([i915#2190]) -> [PASS][107]
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-tglb7/igt@gem_huc_copy@huc-copy.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-tglb1/igt@gem_huc_copy@huc-copy.html

  * igt@gem_linear_blits@interruptible:
    - {shard-tglu}:       [FAIL][108] -> [PASS][109]
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-tglu-7/igt@gem_linear_blits@interruptible.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-tglu-8/igt@gem_linear_blits@interruptible.html

  * igt@gem_mmap_offset@close-race:
    - {shard-rkl}:        [INCOMPLETE][110] -> [PASS][111]
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-rkl-5/igt@gem_mmap_offset@close-race.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-rkl-2/igt@gem_mmap_offset@close-race.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-iclb:         [FAIL][112] ([i915#454]) -> [PASS][113]
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-iclb1/igt@i915_pm_dc@dc6-dpms.html

  * igt@i915_pm_rpm@gem-execbuf:
    - {shard-rkl}:        [SKIP][114] ([fdo#109308]) -> [PASS][115]
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-rkl-2/igt@i915_pm_rpm@gem-execbuf.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-rkl-6/igt@i915_pm_rpm@gem-execbuf.html

  * igt@i915_pm_rps@min-max-config-idle:
    - {shard-rkl}:        ([FAIL][116], [PASS][117]) ([i915#4016]) -> [PASS][118]
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-rkl-2/igt@i915_pm_rps@min-max-config-idle.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-rkl-4/igt@i915_pm_rps@min-max-config-idle.html
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-rkl-6/igt@i915_pm_rps@min-max-config-idle.html

  * igt@i915_pm_rps@reset:
    - {shard-dg1}:        [FAIL][119] ([i915#3719]) -> [PASS][120]
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-dg1-16/igt@i915_pm_rps@reset.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-dg1-15/igt@i915_pm_rps@reset.html

  * igt@i915_selftest@live@hangcheck:
    - shard-snb:          [INCOMPLETE][121] ([i915#3921]) -> [PASS][122]
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-snb6/igt@i915_selftest@live@hangcheck.html
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-snb7/igt@i915_selftest@live@hangcheck.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180:
    - {shard-rkl}:        ([SKIP][123], [SKIP][124]) ([i915#1845]) -> [PASS][125]
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-rkl-2/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-rkl-4/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-rkl-6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - {shard-rkl}:        [SKIP][126] ([i915#1845]) -> [PASS][127] +18 similar issues
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-rkl-2/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-rkl-6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_rc_ccs:
    - {shard-rkl}:        [SKIP][128] ([i915#1845] / [i915#4098]) -> [PASS][129] +1 similar issue
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-rkl-2/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_rc_ccs.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-rkl-6/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_rc_ccs.html

  * igt@kms_color@pipe-a-ctm-blue-to-red:
    - {shard-rkl}:        [SKIP][130] ([i915#1149] / [i915#1849] / [i915#4070]) -> [PASS][131] +2 similar issues
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-rkl-2/igt@kms_color@pipe-a-ctm-blue-to-red.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-rkl-6/igt@kms_color@pipe-a-ctm-blue-to-red.html

  * igt@kms_cursor_crc@pipe-b-cursor-256x85-random:
    - {shard-rkl}:        [SKIP][132] ([fdo#112022] / [i915#4070]) -> [PASS][133] +2 similar issues
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-rkl-2/igt@kms_cursor_crc@pipe-b-cursor-256x85-random.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-rkl-6/igt@kms_cursor_crc@pipe-b-cursor-256x85-random.html

  * igt@kms_cursor_edge_walk@pipe-a-256x256-right-edge:
    - {shard-rkl}:        [SKIP][134] ([i915#1849] / [i915#4070]) -> [PASS][135]
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-rkl-2/igt@kms_cursor_edge_walk@pipe-a-256x256-right-edge.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-rkl-6/igt@kms_cursor_edge_walk@pipe-a-256x256-right-edge.html

  * igt@kms_cursor_edge_walk@pipe-a-64x64-bottom-edge:
    - {shard-rkl}:        ([SKIP][136], [SKIP][137]) ([i915#1849] / [i915#4070] / [i915#4098]) -> [PASS][138]
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-rkl-2/igt@kms_cursor_edge_walk@pipe-a-64x64-bottom-edge.html
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-rkl-4/igt@kms_cursor_edge_walk@pipe-a-64x64-bottom-edge.html
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-rkl-6/igt@kms_cursor_edge_walk@pipe-a-64x64-bottom-edge.html

  * igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size:
    - {shard-rkl}:        [SKIP][139] ([fdo#111825] / [i915#4070]) -> [PASS][140] +1 similar issue
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-rkl-2/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-rkl-6/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html

  * igt@kms_cursor_legacy@cursora-vs-flipa-varying-size:
    - shard-tglb:         [DMESG-WARN][141] ([i915#1982]) -> [PASS][142]
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-tglb2/igt@kms_cursor_legacy@cursora-vs-flipa-varying-size.html
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-tglb2/igt@kms_cursor_legacy@cursora-vs-flipa-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-iclb:         [FAIL][143] ([i915#2346]) -> [PASS][144]
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - {shard-rkl}:        ([SKIP][145], [SKIP][146]) ([fdo#111825] / [i915#4070]) -> [PASS][147]
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-rkl-2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-rkl-4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/shard-rkl-6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@pipe-c-single-bo:
    - {shard-rkl}:        [SKIP][148] ([i915#4070]) -> [PASS][149]
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22010/index.html

[-- Attachment #2: Type: text/html, Size: 33147 bytes --]

Re: [Intel-gfx] [PATCH 01/15] drm/i915: Drop pointless dev_priv argument

[Lisovskiy, Stanislav]

On Tue, Jan 18, 2022 at 11:23:40AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> skl_ddb_entry_init_from_hw() has no need for dev_priv.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 11 +++++------
>  1 file changed, 5 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 62fde21fac39..7185af0ff205 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4289,8 +4289,7 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
>  	return max(num_active == 1 ? 32 : 8, min_ddb_alloc);
>  }
>  
> -static void skl_ddb_entry_init_from_hw(struct drm_i915_private *dev_priv,
> -				       struct skl_ddb_entry *entry, u32 reg)
> +static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
>  {
>  	entry->start = REG_FIELD_GET(PLANE_BUF_START_MASK, reg);
>  	entry->end = REG_FIELD_GET(PLANE_BUF_END_MASK, reg);
> @@ -4311,7 +4310,7 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
>  	/* Cursor doesn't support NV12/planar, so no extra calculation needed */
>  	if (plane_id == PLANE_CURSOR) {
>  		val = intel_uncore_read(&dev_priv->uncore, CUR_BUF_CFG(pipe));
> -		skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
> +		skl_ddb_entry_init_from_hw(ddb_y, val);
>  		return;
>  	}
>  
> @@ -4325,7 +4324,7 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
>  
>  	if (DISPLAY_VER(dev_priv) >= 11) {
>  		val = intel_uncore_read(&dev_priv->uncore, PLANE_BUF_CFG(pipe, plane_id));
> -		skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
> +		skl_ddb_entry_init_from_hw(ddb_y, val);
>  	} else {
>  		val = intel_uncore_read(&dev_priv->uncore, PLANE_BUF_CFG(pipe, plane_id));
>  		val2 = intel_uncore_read(&dev_priv->uncore, PLANE_NV12_BUF_CFG(pipe, plane_id));
> @@ -4334,8 +4333,8 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
>  		    drm_format_info_is_yuv_semiplanar(drm_format_info(fourcc)))
>  			swap(val, val2);
>  
> -		skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
> -		skl_ddb_entry_init_from_hw(dev_priv, ddb_uv, val2);
> +		skl_ddb_entry_init_from_hw(ddb_y, val);
> +		skl_ddb_entry_init_from_hw(ddb_uv, val2);
>  	}
>  }
>  
> -- 
> 2.32.0
> 

Re: [Intel-gfx] [PATCH 02/15] drm/i915: Extract skl_ddb_entry_init()

[Lisovskiy, Stanislav]

On Tue, Jan 18, 2022 at 11:23:41AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Extract a small helper to populate a ddb entry.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 44 +++++++++++++++++++--------------
>  1 file changed, 25 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 7185af0ff205..9a9d4acb2988 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4058,6 +4058,15 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
>  	return 0;
>  }
>  
> +static u16 skl_ddb_entry_init(struct skl_ddb_entry *entry,
> +			      u16 start, u16 end)
> +{
> +	entry->start = start;
> +	entry->end = end;
> +
> +	return end;
> +}
> +
>  static int intel_dbuf_slice_size(struct drm_i915_private *dev_priv)
>  {
>  	return INTEL_INFO(dev_priv)->dbuf.size /
> @@ -4196,8 +4205,7 @@ skl_crtc_allocate_ddb(struct intel_atomic_state *state, struct intel_crtc *crtc)
>  	int ret;
>  
>  	if (new_dbuf_state->weight[pipe] == 0) {
> -		new_dbuf_state->ddb[pipe].start = 0;
> -		new_dbuf_state->ddb[pipe].end = 0;
> +		skl_ddb_entry_init(&new_dbuf_state->ddb[pipe], 0, 0);
>  		goto out;
>  	}
>  
> @@ -4213,8 +4221,10 @@ skl_crtc_allocate_ddb(struct intel_atomic_state *state, struct intel_crtc *crtc)
>  	start = ddb_range_size * weight_start / weight_total;
>  	end = ddb_range_size * weight_end / weight_total;
>  
> -	new_dbuf_state->ddb[pipe].start = ddb_slices.start - mbus_offset + start;
> -	new_dbuf_state->ddb[pipe].end = ddb_slices.start - mbus_offset + end;
> +	skl_ddb_entry_init(&new_dbuf_state->ddb[pipe],
> +			   ddb_slices.start - mbus_offset + start,
> +			   ddb_slices.start - mbus_offset + end);
> +
>  out:
>  	if (old_dbuf_state->slices[pipe] == new_dbuf_state->slices[pipe] &&
>  	    skl_ddb_entry_equal(&old_dbuf_state->ddb[pipe],
> @@ -4291,8 +4301,9 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
>  
>  static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
>  {
> -	entry->start = REG_FIELD_GET(PLANE_BUF_START_MASK, reg);
> -	entry->end = REG_FIELD_GET(PLANE_BUF_END_MASK, reg);
> +	skl_ddb_entry_init(entry,
> +			   REG_FIELD_GET(PLANE_BUF_START_MASK, reg),
> +			   REG_FIELD_GET(PLANE_BUF_END_MASK, reg));
>  	if (entry->end)
>  		entry->end++;
>  }
> @@ -5154,9 +5165,8 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
>  	/* Allocate fixed number of blocks for cursor. */
>  	total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
>  	alloc_size -= total[PLANE_CURSOR];
> -	crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].start =
> -		alloc->end - total[PLANE_CURSOR];
> -	crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;
> +	skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR],
> +			   alloc->end - total[PLANE_CURSOR], alloc->end);
>  
>  	if (total_data_rate == 0)
>  		return 0;
> @@ -5257,17 +5267,13 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
>  			    DISPLAY_VER(dev_priv) >= 11 && uv_total[plane_id]);
>  
>  		/* Leave disabled planes at (0,0) */
> -		if (total[plane_id]) {
> -			plane_alloc->start = start;
> -			start += total[plane_id];
> -			plane_alloc->end = start;
> -		}
> +		if (total[plane_id])
> +			start = skl_ddb_entry_init(plane_alloc, start,
> +						   start + total[plane_id]);
>  
> -		if (uv_total[plane_id]) {
> -			uv_plane_alloc->start = start;
> -			start += uv_total[plane_id];
> -			uv_plane_alloc->end = start;
> -		}
> +		if (uv_total[plane_id])
> +			start = skl_ddb_entry_init(uv_plane_alloc, start,
> +						   start + uv_total[plane_id]);
>  	}
>  
>  	/*
> -- 
> 2.32.0
> 

Re: [Intel-gfx] [PATCH 03/15] drm/i915: Fix plane relative_data_rate calculation

[Lisovskiy, Stanislav]

On Tue, Jan 18, 2022 at 11:23:42AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> We are currently computing the relative data rates as
> src_size * scale_factor where scale_factor is src_size / dst_size.
> Thus relative data rate is src_size * src_size / dst_size,
> which is just utter nonsense. What we really seem to want is
> just a reasonable estimate on how much data will be fetched
> which is just src_size. So let's do that instead.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Omg, how could it stay like this all the time?

I actually had similar question, but thought that there just might
be again some magical/empirical heuristics behind this.
Need to challenge more anything, which can't be explained with
BSpec formulas or by common sense...

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 63 ++-------------------------------
>  1 file changed, 2 insertions(+), 61 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 9a9d4acb2988..e8fb56f288b4 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4373,55 +4373,6 @@ void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
>  	intel_display_power_put(dev_priv, power_domain, wakeref);
>  }
>  
> -/*
> - * Determines the downscale amount of a plane for the purposes of watermark calculations.
> - * The bspec defines downscale amount as:
> - *
> - * """
> - * Horizontal down scale amount = maximum[1, Horizontal source size /
> - *                                           Horizontal destination size]
> - * Vertical down scale amount = maximum[1, Vertical source size /
> - *                                         Vertical destination size]
> - * Total down scale amount = Horizontal down scale amount *
> - *                           Vertical down scale amount
> - * """
> - *
> - * Return value is provided in 16.16 fixed point form to retain fractional part.
> - * Caller should take care of dividing & rounding off the value.
> - */
> -static uint_fixed_16_16_t
> -skl_plane_downscale_amount(const struct intel_crtc_state *crtc_state,
> -			   const struct intel_plane_state *plane_state)
> -{
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> -	u32 src_w, src_h, dst_w, dst_h;
> -	uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
> -	uint_fixed_16_16_t downscale_h, downscale_w;
> -
> -	if (drm_WARN_ON(&dev_priv->drm,
> -			!intel_wm_plane_visible(crtc_state, plane_state)))
> -		return u32_to_fixed16(0);
> -
> -	/*
> -	 * Src coordinates are already rotated by 270 degrees for
> -	 * the 90/270 degree plane rotation cases (to match the
> -	 * GTT mapping), hence no need to account for rotation here.
> -	 *
> -	 * n.b., src is 16.16 fixed point, dst is whole integer.
> -	 */
> -	src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
> -	src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
> -	dst_w = drm_rect_width(&plane_state->uapi.dst);
> -	dst_h = drm_rect_height(&plane_state->uapi.dst);
> -
> -	fp_w_ratio = div_fixed16(src_w, dst_w);
> -	fp_h_ratio = div_fixed16(src_h, dst_h);
> -	downscale_w = max_fixed16(fp_w_ratio, u32_to_fixed16(1));
> -	downscale_h = max_fixed16(fp_h_ratio, u32_to_fixed16(1));
> -
> -	return mul_fixed16(downscale_w, downscale_h);
> -}
> -
>  struct dbuf_slice_conf_entry {
>  	u8 active_pipes;
>  	u8 dbuf_mask[I915_MAX_PIPES];
> @@ -4932,10 +4883,7 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
>  {
>  	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
>  	const struct drm_framebuffer *fb = plane_state->hw.fb;
> -	u32 data_rate;
> -	u32 width = 0, height = 0;
> -	uint_fixed_16_16_t down_scale_amount;
> -	u64 rate;
> +	int width, height;
>  
>  	if (!plane_state->uapi.visible)
>  		return 0;
> @@ -4961,14 +4909,7 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
>  		height /= 2;
>  	}
>  
> -	data_rate = width * height;
> -
> -	down_scale_amount = skl_plane_downscale_amount(crtc_state, plane_state);
> -
> -	rate = mul_round_up_u32_fixed16(data_rate, down_scale_amount);
> -
> -	rate *= fb->format->cpp[color_plane];
> -	return rate;
> +	return width * height * fb->format->cpp[color_plane];
>  }
>  
>  static u64
> -- 
> 2.32.0
> 

Re: [Intel-gfx] [PATCH 04/15] drm/i915: Introduce skl_plane_ddb_iter

[Lisovskiy, Stanislav]

On Tue, Jan 18, 2022 at 11:23:43AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Collect a bit of the stuff used during the plane ddb
> allocation into a struct we can pass around.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 97 +++++++++++++++++----------------
>  1 file changed, 49 insertions(+), 48 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index e8fb56f288b4..cd1b5f09f241 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5066,6 +5066,13 @@ static bool icl_need_wm1_wa(struct drm_i915_private *i915,
>  	       (IS_DISPLAY_VER(i915, 12, 13) && plane_id == PLANE_CURSOR);
>  }
>  
> +struct skl_plane_ddb_iter {
> +	u64 data_rate;
> +	u16 total[I915_MAX_PLANES];
> +	u16 uv_total[I915_MAX_PLANES];
> +	u16 start, size;
> +};
> +
>  static int
>  skl_allocate_plane_ddb(struct intel_atomic_state *state,
>  		       struct intel_crtc *crtc)
> @@ -5077,10 +5084,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
>  		intel_atomic_get_new_dbuf_state(state);
>  	const struct skl_ddb_entry *alloc = &dbuf_state->ddb[crtc->pipe];
>  	int num_active = hweight8(dbuf_state->active_pipes);
> -	u16 alloc_size, start = 0;
> -	u16 total[I915_MAX_PLANES] = {};
> -	u16 uv_total[I915_MAX_PLANES] = {};
> -	u64 total_data_rate;
> +	struct skl_plane_ddb_iter iter = {};
>  	enum plane_id plane_id;
>  	u32 blocks;
>  	int level;
> @@ -5093,23 +5097,21 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
>  		return 0;
>  
>  	if (DISPLAY_VER(dev_priv) >= 11)
> -		total_data_rate =
> -			icl_get_total_relative_data_rate(state, crtc);
> +		iter.data_rate = icl_get_total_relative_data_rate(state, crtc);
>  	else
> -		total_data_rate =
> -			skl_get_total_relative_data_rate(state, crtc);
> +		iter.data_rate = skl_get_total_relative_data_rate(state, crtc);
>  
> -	alloc_size = skl_ddb_entry_size(alloc);
> -	if (alloc_size == 0)
> +	iter.size = skl_ddb_entry_size(alloc);
> +	if (iter.size == 0)
>  		return 0;
>  
>  	/* Allocate fixed number of blocks for cursor. */
> -	total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
> -	alloc_size -= total[PLANE_CURSOR];
> +	iter.total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
> +	iter.size -= iter.total[PLANE_CURSOR];
>  	skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR],
> -			   alloc->end - total[PLANE_CURSOR], alloc->end);
> +			   alloc->end - iter.total[PLANE_CURSOR], alloc->end);
>  
> -	if (total_data_rate == 0)
> +	if (iter.data_rate == 0)
>  		return 0;
>  
>  	/*
> @@ -5123,7 +5125,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
>  				&crtc_state->wm.skl.optimal.planes[plane_id];
>  
>  			if (plane_id == PLANE_CURSOR) {
> -				if (wm->wm[level].min_ddb_alloc > total[PLANE_CURSOR]) {
> +				if (wm->wm[level].min_ddb_alloc > iter.total[PLANE_CURSOR]) {
>  					drm_WARN_ON(&dev_priv->drm,
>  						    wm->wm[level].min_ddb_alloc != U16_MAX);
>  					blocks = U32_MAX;
> @@ -5136,8 +5138,8 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
>  			blocks += wm->uv_wm[level].min_ddb_alloc;
>  		}
>  
> -		if (blocks <= alloc_size) {
> -			alloc_size -= blocks;
> +		if (blocks <= iter.size) {
> +			iter.size -= blocks;
>  			break;
>  		}
>  	}
> @@ -5146,7 +5148,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
>  		drm_dbg_kms(&dev_priv->drm,
>  			    "Requested display configuration exceeds system DDB limitations");
>  		drm_dbg_kms(&dev_priv->drm, "minimum required %d/%d\n",
> -			    blocks, alloc_size);
> +			    blocks, iter.size);
>  		return -EINVAL;
>  	}
>  
> @@ -5158,7 +5160,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
>  	for_each_plane_id_on_crtc(crtc, plane_id) {
>  		const struct skl_plane_wm *wm =
>  			&crtc_state->wm.skl.optimal.planes[plane_id];
> -		u64 rate;
> +		u64 data_rate;
>  		u16 extra;
>  
>  		if (plane_id == PLANE_CURSOR)
> @@ -5168,32 +5170,30 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
>  		 * We've accounted for all active planes; remaining planes are
>  		 * all disabled.
>  		 */
> -		if (total_data_rate == 0)
> +		if (iter.data_rate == 0)
>  			break;
>  
> -		rate = crtc_state->plane_data_rate[plane_id];
> -		extra = min_t(u16, alloc_size,
> -			      DIV64_U64_ROUND_UP(alloc_size * rate,
> -						 total_data_rate));
> -		total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
> -		alloc_size -= extra;
> -		total_data_rate -= rate;
> +		data_rate = crtc_state->plane_data_rate[plane_id];
> +		extra = min_t(u16, iter.size,
> +			      DIV64_U64_ROUND_UP(iter.size * data_rate, iter.data_rate));
> +		iter.total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
> +		iter.size -= extra;
> +		iter.data_rate -= data_rate;
>  
> -		if (total_data_rate == 0)
> +		if (iter.data_rate == 0)
>  			break;
>  
> -		rate = crtc_state->uv_plane_data_rate[plane_id];
> -		extra = min_t(u16, alloc_size,
> -			      DIV64_U64_ROUND_UP(alloc_size * rate,
> -						 total_data_rate));
> -		uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
> -		alloc_size -= extra;
> -		total_data_rate -= rate;
> +		data_rate = crtc_state->uv_plane_data_rate[plane_id];
> +		extra = min_t(u16, iter.size,
> +			      DIV64_U64_ROUND_UP(iter.size * data_rate, iter.data_rate));
> +		iter.uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
> +		iter.size -= extra;
> +		iter.data_rate -= data_rate;
>  	}
> -	drm_WARN_ON(&dev_priv->drm, alloc_size != 0 || total_data_rate != 0);
> +	drm_WARN_ON(&dev_priv->drm, iter.size != 0 || iter.data_rate != 0);
>  
>  	/* Set the actual DDB start/end points for each plane */
> -	start = alloc->start;
> +	iter.start = alloc->start;
>  	for_each_plane_id_on_crtc(crtc, plane_id) {
>  		struct skl_ddb_entry *plane_alloc =
>  			&crtc_state->wm.skl.plane_ddb_y[plane_id];
> @@ -5205,16 +5205,16 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
>  
>  		/* Gen11+ uses a separate plane for UV watermarks */
>  		drm_WARN_ON(&dev_priv->drm,
> -			    DISPLAY_VER(dev_priv) >= 11 && uv_total[plane_id]);
> +			    DISPLAY_VER(dev_priv) >= 11 && iter.uv_total[plane_id]);
>  
>  		/* Leave disabled planes at (0,0) */
> -		if (total[plane_id])
> -			start = skl_ddb_entry_init(plane_alloc, start,
> -						   start + total[plane_id]);
> +		if (iter.total[plane_id])
> +			iter.start = skl_ddb_entry_init(plane_alloc, iter.start,
> +							iter.start + iter.total[plane_id]);
>  
> -		if (uv_total[plane_id])
> -			start = skl_ddb_entry_init(uv_plane_alloc, start,
> -						   start + uv_total[plane_id]);
> +		if (iter.uv_total[plane_id])
> +			iter.start = skl_ddb_entry_init(uv_plane_alloc, iter.start,
> +							iter.start + iter.uv_total[plane_id]);
>  	}
>  
>  	/*
> @@ -5229,7 +5229,8 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
>  				&crtc_state->wm.skl.optimal.planes[plane_id];
>  
>  			skl_check_nv12_wm_level(&wm->wm[level], &wm->uv_wm[level],
> -						total[plane_id], uv_total[plane_id]);
> +						iter.total[plane_id],
> +						iter.uv_total[plane_id]);
>  
>  			if (icl_need_wm1_wa(dev_priv, plane_id) &&
>  			    level == 1 && wm->wm[0].enable) {
> @@ -5248,9 +5249,9 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
>  		struct skl_plane_wm *wm =
>  			&crtc_state->wm.skl.optimal.planes[plane_id];
>  
> -		skl_check_wm_level(&wm->trans_wm, total[plane_id]);
> -		skl_check_wm_level(&wm->sagv.wm0, total[plane_id]);
> -		skl_check_wm_level(&wm->sagv.trans_wm, total[plane_id]);
> +		skl_check_wm_level(&wm->trans_wm, iter.total[plane_id]);
> +		skl_check_wm_level(&wm->sagv.wm0, iter.total[plane_id]);
> +		skl_check_wm_level(&wm->sagv.trans_wm, iter.total[plane_id]);
>  	}
>  
>  	return 0;
> -- 
> 2.32.0
> 

Re: [Intel-gfx] [PATCH 05/15] drm/i915: Extract skl_allocate_plane_ddb()

[Lisovskiy, Stanislav]

On Tue, Jan 18, 2022 at 11:23:44AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Replace some copy-pasta with a function.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 41 +++++++++++++++++++--------------
>  1 file changed, 24 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index cd1b5f09f241..93ff07f6ef26 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5073,9 +5073,24 @@ struct skl_plane_ddb_iter {
>  	u16 start, size;
>  };
>  
> +static u16
> +skl_allocate_plane_ddb(struct skl_plane_ddb_iter *iter,
> +		       const struct skl_wm_level *wm,
> +		       u64 data_rate)
> +{
> +	u16 extra;
> +
> +	extra = min_t(u16, iter->size,
> +		      DIV64_U64_ROUND_UP(iter->size * data_rate, iter->data_rate));
> +	iter->size -= extra;
> +	iter->data_rate -= data_rate;
> +
> +	return wm->min_ddb_alloc + extra;
> +}
> +
>  static int
> -skl_allocate_plane_ddb(struct intel_atomic_state *state,
> -		       struct intel_crtc *crtc)
> +skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
> +			    struct intel_crtc *crtc)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	struct intel_crtc_state *crtc_state =
> @@ -5160,8 +5175,6 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
>  	for_each_plane_id_on_crtc(crtc, plane_id) {
>  		const struct skl_plane_wm *wm =
>  			&crtc_state->wm.skl.optimal.planes[plane_id];
> -		u64 data_rate;
> -		u16 extra;
>  
>  		if (plane_id == PLANE_CURSOR)
>  			continue;
> @@ -5173,22 +5186,16 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
>  		if (iter.data_rate == 0)
>  			break;
>  
> -		data_rate = crtc_state->plane_data_rate[plane_id];
> -		extra = min_t(u16, iter.size,
> -			      DIV64_U64_ROUND_UP(iter.size * data_rate, iter.data_rate));
> -		iter.total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
> -		iter.size -= extra;
> -		iter.data_rate -= data_rate;
> +		iter.total[plane_id] =
> +			skl_allocate_plane_ddb(&iter, &wm->wm[level],
> +					       crtc_state->plane_data_rate[plane_id]);
>  
>  		if (iter.data_rate == 0)
>  			break;
>  
> -		data_rate = crtc_state->uv_plane_data_rate[plane_id];
> -		extra = min_t(u16, iter.size,
> -			      DIV64_U64_ROUND_UP(iter.size * data_rate, iter.data_rate));
> -		iter.uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
> -		iter.size -= extra;
> -		iter.data_rate -= data_rate;
> +		iter.uv_total[plane_id] =
> +			skl_allocate_plane_ddb(&iter, &wm->uv_wm[level],
> +					       crtc_state->uv_plane_data_rate[plane_id]);
>  	}
>  	drm_WARN_ON(&dev_priv->drm, iter.size != 0 || iter.data_rate != 0);
>  
> @@ -6136,7 +6143,7 @@ skl_compute_ddb(struct intel_atomic_state *state)
>  
>  	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
>  					    new_crtc_state, i) {
> -		ret = skl_allocate_plane_ddb(state, crtc);
> +		ret = skl_crtc_allocate_plane_ddb(state, crtc);
>  		if (ret)
>  			return ret;
>  
> -- 
> 2.32.0
> 

Re: [Intel-gfx] [PATCH 06/15] drm/i915: Extract skl_crtc_calc_dbuf_bw()

[Lisovskiy, Stanislav]

On Tue, Jan 18, 2022 at 11:23:45AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Extract the dbuf slice data_rate calculation into a small
> helper. Should make it a bit easier to handle the different
> color planes of planar formats correctly.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>


> ---
>  drivers/gpu/drm/i915/display/intel_bw.c | 82 +++++++++++++------------
>  1 file changed, 44 insertions(+), 38 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index c35bad21b657..f0d6fad048c7 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -672,6 +672,49 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state)
>  	return to_intel_bw_state(bw_state);
>  }
>  
> +static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state,
> +				  const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> +	struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe];
> +	enum plane_id plane_id;
> +
> +	memset(&crtc_bw->used_bw, 0, sizeof(crtc_bw->used_bw));
> +
> +	if (!crtc_state->hw.active)
> +		return;
> +
> +	for_each_plane_id_on_crtc(crtc, plane_id) {
> +		const struct skl_ddb_entry *ddb_y =
> +			&crtc_state->wm.skl.plane_ddb_y[plane_id];
> +		const struct skl_ddb_entry *ddb_uv =
> +			&crtc_state->wm.skl.plane_ddb_uv[plane_id];
> +		unsigned int data_rate = crtc_state->data_rate[plane_id];
> +		unsigned int dbuf_mask = 0;
> +		enum dbuf_slice slice;
> +
> +		dbuf_mask |= skl_ddb_dbuf_slice_mask(i915, ddb_y);
> +		dbuf_mask |= skl_ddb_dbuf_slice_mask(i915, ddb_uv);
> +
> +		/*
> +		 * FIXME: To calculate that more properly we probably
> +		 * need to split per plane data_rate into data_rate_y
> +		 * and data_rate_uv for multiplanar formats in order not
> +		 * to get accounted those twice if they happen to reside
> +		 * on different slices.
> +		 * However for pre-icl this would work anyway because
> +		 * we have only single slice and for icl+ uv plane has
> +		 * non-zero data rate.
> +		 * So in worst case those calculation are a bit
> +		 * pessimistic, which shouldn't pose any significant
> +		 * problem anyway.
> +		 */
> +		for_each_dbuf_slice_in_mask(i915, slice, dbuf_mask)
> +			crtc_bw->used_bw[slice] += data_rate;
> +	}
> +}
> +
>  int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> @@ -684,50 +727,13 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
>  	int i;
>  
>  	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> -		enum plane_id plane_id;
> -		struct intel_dbuf_bw *crtc_bw;
> -
>  		new_bw_state = intel_atomic_get_bw_state(state);
>  		if (IS_ERR(new_bw_state))
>  			return PTR_ERR(new_bw_state);
>  
>  		old_bw_state = intel_atomic_get_old_bw_state(state);
>  
> -		crtc_bw = &new_bw_state->dbuf_bw[crtc->pipe];
> -
> -		memset(&crtc_bw->used_bw, 0, sizeof(crtc_bw->used_bw));
> -
> -		if (!crtc_state->hw.active)
> -			continue;
> -
> -		for_each_plane_id_on_crtc(crtc, plane_id) {
> -			const struct skl_ddb_entry *plane_alloc =
> -				&crtc_state->wm.skl.plane_ddb_y[plane_id];
> -			const struct skl_ddb_entry *uv_plane_alloc =
> -				&crtc_state->wm.skl.plane_ddb_uv[plane_id];
> -			unsigned int data_rate = crtc_state->data_rate[plane_id];
> -			unsigned int dbuf_mask = 0;
> -			enum dbuf_slice slice;
> -
> -			dbuf_mask |= skl_ddb_dbuf_slice_mask(dev_priv, plane_alloc);
> -			dbuf_mask |= skl_ddb_dbuf_slice_mask(dev_priv, uv_plane_alloc);
> -
> -			/*
> -			 * FIXME: To calculate that more properly we probably
> -			 * need to to split per plane data_rate into data_rate_y
> -			 * and data_rate_uv for multiplanar formats in order not
> -			 * to get accounted those twice if they happen to reside
> -			 * on different slices.
> -			 * However for pre-icl this would work anyway because
> -			 * we have only single slice and for icl+ uv plane has
> -			 * non-zero data rate.
> -			 * So in worst case those calculation are a bit
> -			 * pessimistic, which shouldn't pose any significant
> -			 * problem anyway.
> -			 */
> -			for_each_dbuf_slice_in_mask(dev_priv, slice, dbuf_mask)
> -				crtc_bw->used_bw[slice] += data_rate;
> -		}
> +		skl_crtc_calc_dbuf_bw(new_bw_state, crtc_state);
>  	}
>  
>  	if (!old_bw_state)
> -- 
> 2.32.0
> 

Re: [Intel-gfx] [PATCH 03/15] drm/i915: Fix plane relative_data_rate calculation

[Ville Syrjälä]

On Thu, Jan 27, 2022 at 10:21:06AM +0200, Lisovskiy, Stanislav wrote:
> On Tue, Jan 18, 2022 at 11:23:42AM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > We are currently computing the relative data rates as
> > src_size * scale_factor where scale_factor is src_size / dst_size.
> > Thus relative data rate is src_size * src_size / dst_size,
> > which is just utter nonsense. What we really seem to want is
> > just a reasonable estimate on how much data will be fetched
> > which is just src_size. So let's do that instead.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Omg, how could it stay like this all the time?
> 
> I actually had similar question, but thought that there just might
> be again some magical/empirical heuristics behind this.
> Need to challenge more anything, which can't be explained with
> BSpec formulas or by common sense...

Yeah, I suspect it's just some kind of brain fart when writing the
spec. I think I filed an issues for it but nothing really happened
IIRC.

> 
> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> 
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 63 ++-------------------------------
> >  1 file changed, 2 insertions(+), 61 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 9a9d4acb2988..e8fb56f288b4 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4373,55 +4373,6 @@ void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
> >  	intel_display_power_put(dev_priv, power_domain, wakeref);
> >  }
> >  
> > -/*
> > - * Determines the downscale amount of a plane for the purposes of watermark calculations.
> > - * The bspec defines downscale amount as:
> > - *
> > - * """
> > - * Horizontal down scale amount = maximum[1, Horizontal source size /
> > - *                                           Horizontal destination size]
> > - * Vertical down scale amount = maximum[1, Vertical source size /
> > - *                                         Vertical destination size]
> > - * Total down scale amount = Horizontal down scale amount *
> > - *                           Vertical down scale amount
> > - * """
> > - *
> > - * Return value is provided in 16.16 fixed point form to retain fractional part.
> > - * Caller should take care of dividing & rounding off the value.
> > - */
> > -static uint_fixed_16_16_t
> > -skl_plane_downscale_amount(const struct intel_crtc_state *crtc_state,
> > -			   const struct intel_plane_state *plane_state)
> > -{
> > -	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> > -	u32 src_w, src_h, dst_w, dst_h;
> > -	uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
> > -	uint_fixed_16_16_t downscale_h, downscale_w;
> > -
> > -	if (drm_WARN_ON(&dev_priv->drm,
> > -			!intel_wm_plane_visible(crtc_state, plane_state)))
> > -		return u32_to_fixed16(0);
> > -
> > -	/*
> > -	 * Src coordinates are already rotated by 270 degrees for
> > -	 * the 90/270 degree plane rotation cases (to match the
> > -	 * GTT mapping), hence no need to account for rotation here.
> > -	 *
> > -	 * n.b., src is 16.16 fixed point, dst is whole integer.
> > -	 */
> > -	src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
> > -	src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
> > -	dst_w = drm_rect_width(&plane_state->uapi.dst);
> > -	dst_h = drm_rect_height(&plane_state->uapi.dst);
> > -
> > -	fp_w_ratio = div_fixed16(src_w, dst_w);
> > -	fp_h_ratio = div_fixed16(src_h, dst_h);
> > -	downscale_w = max_fixed16(fp_w_ratio, u32_to_fixed16(1));
> > -	downscale_h = max_fixed16(fp_h_ratio, u32_to_fixed16(1));
> > -
> > -	return mul_fixed16(downscale_w, downscale_h);
> > -}
> > -
> >  struct dbuf_slice_conf_entry {
> >  	u8 active_pipes;
> >  	u8 dbuf_mask[I915_MAX_PIPES];
> > @@ -4932,10 +4883,7 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
> >  {
> >  	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> >  	const struct drm_framebuffer *fb = plane_state->hw.fb;
> > -	u32 data_rate;
> > -	u32 width = 0, height = 0;
> > -	uint_fixed_16_16_t down_scale_amount;
> > -	u64 rate;
> > +	int width, height;
> >  
> >  	if (!plane_state->uapi.visible)
> >  		return 0;
> > @@ -4961,14 +4909,7 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
> >  		height /= 2;
> >  	}
> >  
> > -	data_rate = width * height;
> > -
> > -	down_scale_amount = skl_plane_downscale_amount(crtc_state, plane_state);
> > -
> > -	rate = mul_round_up_u32_fixed16(data_rate, down_scale_amount);
> > -
> > -	rate *= fb->format->cpp[color_plane];
> > -	return rate;
> > +	return width * height * fb->format->cpp[color_plane];
> >  }
> >  
> >  static u64
> > -- 
> > 2.32.0
> > 

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH 07/15] drm/i915: Tweak plane ddb allocation tracking

[Lisovskiy, Stanislav]

On Tue, Jan 18, 2022 at 11:23:46AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Let's store the plane allocation in a manner which more closely
> matches how the hw operates. That is, we store the packed/CbCr
> ddb in one struct, and the Y ddb in another. Currently we're
> storing packed/Y in one struct, CbCr in the other.
> 
> This also works pretty well for icl+ where the UV plane is
> the main plane and the Y plane is subservient to it. Although
> in this case we do not even use ddb_y as we do the ddb allocation
> in terms of hw planes.

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  .../gpu/drm/i915/display/intel_atomic_plane.c |  32 +++---
>  drivers/gpu/drm/i915/display/intel_bw.c       |   6 +-
>  drivers/gpu/drm/i915/display/intel_display.c  |   8 +-
>  .../drm/i915/display/intel_display_debugfs.c  |   4 +-
>  .../drm/i915/display/intel_display_types.h    |   7 +-
>  drivers/gpu/drm/i915/intel_pm.c               | 108 ++++++++----------
>  6 files changed, 74 insertions(+), 91 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index c2c512cd8ec0..52239351931c 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -430,8 +430,8 @@ int intel_plane_atomic_check(struct intel_atomic_state *state,
>  static struct intel_plane *
>  skl_next_plane_to_commit(struct intel_atomic_state *state,
>  			 struct intel_crtc *crtc,
> -			 struct skl_ddb_entry entries_y[I915_MAX_PLANES],
> -			 struct skl_ddb_entry entries_uv[I915_MAX_PLANES],
> +			 struct skl_ddb_entry ddb[I915_MAX_PLANES],
> +			 struct skl_ddb_entry ddb_y[I915_MAX_PLANES],
>  			 unsigned int *update_mask)
>  {
>  	struct intel_crtc_state *crtc_state =
> @@ -450,17 +450,15 @@ skl_next_plane_to_commit(struct intel_atomic_state *state,
>  		    !(*update_mask & BIT(plane_id)))
>  			continue;
>  
> -		if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id],
> -						entries_y,
> -						I915_MAX_PLANES, plane_id) ||
> -		    skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_uv[plane_id],
> -						entries_uv,
> -						I915_MAX_PLANES, plane_id))
> +		if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb[plane_id],
> +						ddb, I915_MAX_PLANES, plane_id) ||
> +		    skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id],
> +						ddb_y, I915_MAX_PLANES, plane_id))
>  			continue;
>  
>  		*update_mask &= ~BIT(plane_id);
> -		entries_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id];
> -		entries_uv[plane_id] = crtc_state->wm.skl.plane_ddb_uv[plane_id];
> +		ddb[plane_id] = crtc_state->wm.skl.plane_ddb[plane_id];
> +		ddb_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id];
>  
>  		return plane;
>  	}
> @@ -542,19 +540,17 @@ void skl_arm_planes_on_crtc(struct intel_atomic_state *state,
>  		intel_atomic_get_old_crtc_state(state, crtc);
>  	struct intel_crtc_state *new_crtc_state =
>  		intel_atomic_get_new_crtc_state(state, crtc);
> -	struct skl_ddb_entry entries_y[I915_MAX_PLANES];
> -	struct skl_ddb_entry entries_uv[I915_MAX_PLANES];
> +	struct skl_ddb_entry ddb[I915_MAX_PLANES];
> +	struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
>  	u32 update_mask = new_crtc_state->update_planes;
>  	struct intel_plane *plane;
>  
> -	memcpy(entries_y, old_crtc_state->wm.skl.plane_ddb_y,
> +	memcpy(ddb, old_crtc_state->wm.skl.plane_ddb,
> +	       sizeof(old_crtc_state->wm.skl.plane_ddb));
> +	memcpy(ddb_y, old_crtc_state->wm.skl.plane_ddb_y,
>  	       sizeof(old_crtc_state->wm.skl.plane_ddb_y));
> -	memcpy(entries_uv, old_crtc_state->wm.skl.plane_ddb_uv,
> -	       sizeof(old_crtc_state->wm.skl.plane_ddb_uv));
>  
> -	while ((plane = skl_next_plane_to_commit(state, crtc,
> -						 entries_y, entries_uv,
> -						 &update_mask))) {
> +	while ((plane = skl_next_plane_to_commit(state, crtc, ddb, ddb_y, &update_mask))) {
>  		struct intel_plane_state *new_plane_state =
>  			intel_atomic_get_new_plane_state(state, plane);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index f0d6fad048c7..82f0435bcb6d 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -686,16 +686,16 @@ static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state,
>  		return;
>  
>  	for_each_plane_id_on_crtc(crtc, plane_id) {
> +		const struct skl_ddb_entry *ddb =
> +			&crtc_state->wm.skl.plane_ddb[plane_id];
>  		const struct skl_ddb_entry *ddb_y =
>  			&crtc_state->wm.skl.plane_ddb_y[plane_id];
> -		const struct skl_ddb_entry *ddb_uv =
> -			&crtc_state->wm.skl.plane_ddb_uv[plane_id];
>  		unsigned int data_rate = crtc_state->data_rate[plane_id];
>  		unsigned int dbuf_mask = 0;
>  		enum dbuf_slice slice;
>  
> +		dbuf_mask |= skl_ddb_dbuf_slice_mask(i915, ddb);
>  		dbuf_mask |= skl_ddb_dbuf_slice_mask(i915, ddb_y);
> -		dbuf_mask |= skl_ddb_dbuf_slice_mask(i915, ddb_uv);
>  
>  		/*
>  		 * FIXME: To calculate that more properly we probably
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 0964b2403e2d..af23153f6502 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6750,8 +6750,8 @@ static void verify_wm_state(struct intel_crtc *crtc,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	struct skl_hw_state {
> +		struct skl_ddb_entry ddb[I915_MAX_PLANES];
>  		struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
> -		struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
>  		struct skl_pipe_wm wm;
>  	} *hw;
>  	const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal;
> @@ -6768,7 +6768,7 @@ static void verify_wm_state(struct intel_crtc *crtc,
>  
>  	skl_pipe_wm_get_hw_state(crtc, &hw->wm);
>  
> -	skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
> +	skl_pipe_ddb_get_hw_state(crtc, hw->ddb, hw->ddb_y);
>  
>  	hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
>  
> @@ -6850,8 +6850,8 @@ static void verify_wm_state(struct intel_crtc *crtc,
>  		}
>  
>  		/* DDB */
> -		hw_ddb_entry = &hw->ddb_y[plane->id];
> -		sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane->id];
> +		hw_ddb_entry = &hw->ddb[PLANE_CURSOR];
> +		sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb[PLANE_CURSOR];
>  
>  		if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
>  			drm_err(&dev_priv->drm,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index f4de004d470f..5ef4a86ccf66 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -1116,13 +1116,13 @@ static int i915_ddb_info(struct seq_file *m, void *unused)
>  		seq_printf(m, "Pipe %c\n", pipe_name(pipe));
>  
>  		for_each_plane_id_on_crtc(crtc, plane_id) {
> -			entry = &crtc_state->wm.skl.plane_ddb_y[plane_id];
> +			entry = &crtc_state->wm.skl.plane_ddb[plane_id];
>  			seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane_id + 1,
>  				   entry->start, entry->end,
>  				   skl_ddb_entry_size(entry));
>  		}
>  
> -		entry = &crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
> +		entry = &crtc_state->wm.skl.plane_ddb[PLANE_CURSOR];
>  		seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
>  			   entry->end, skl_ddb_entry_size(entry));
>  	}
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 41e3dd25a78f..578c6069376b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -868,8 +868,13 @@ struct intel_crtc_wm_state {
>  			/* gen9+ only needs 1-step wm programming */
>  			struct skl_pipe_wm optimal;
>  			struct skl_ddb_entry ddb;
> +			/*
> +			 * pre-icl: for packed/planar CbCr
> +			 * icl+: for everything
> +			 */
> +			struct skl_ddb_entry plane_ddb[I915_MAX_PLANES];
> +			/* pre-icl: for planar Y */
>  			struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
> -			struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
>  		} skl;
>  
>  		struct {
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 93ff07f6ef26..8a115b4c9e71 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4312,46 +4312,31 @@ static void
>  skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
>  			   const enum pipe pipe,
>  			   const enum plane_id plane_id,
> -			   struct skl_ddb_entry *ddb_y,
> -			   struct skl_ddb_entry *ddb_uv)
> +			   struct skl_ddb_entry *ddb,
> +			   struct skl_ddb_entry *ddb_y)
>  {
> -	u32 val, val2;
> -	u32 fourcc = 0;
> +	u32 val;
>  
>  	/* Cursor doesn't support NV12/planar, so no extra calculation needed */
>  	if (plane_id == PLANE_CURSOR) {
>  		val = intel_uncore_read(&dev_priv->uncore, CUR_BUF_CFG(pipe));
> -		skl_ddb_entry_init_from_hw(ddb_y, val);
> +		skl_ddb_entry_init_from_hw(ddb, val);
>  		return;
>  	}
>  
> -	val = intel_uncore_read(&dev_priv->uncore, PLANE_CTL(pipe, plane_id));
> +	val = intel_uncore_read(&dev_priv->uncore, PLANE_BUF_CFG(pipe, plane_id));
> +	skl_ddb_entry_init_from_hw(ddb, val);
>  
> -	/* No DDB allocated for disabled planes */
> -	if (val & PLANE_CTL_ENABLE)
> -		fourcc = skl_format_to_fourcc(val & PLANE_CTL_FORMAT_MASK_SKL,
> -					      val & PLANE_CTL_ORDER_RGBX,
> -					      val & PLANE_CTL_ALPHA_MASK);
> -
> -	if (DISPLAY_VER(dev_priv) >= 11) {
> -		val = intel_uncore_read(&dev_priv->uncore, PLANE_BUF_CFG(pipe, plane_id));
> -		skl_ddb_entry_init_from_hw(ddb_y, val);
> -	} else {
> -		val = intel_uncore_read(&dev_priv->uncore, PLANE_BUF_CFG(pipe, plane_id));
> -		val2 = intel_uncore_read(&dev_priv->uncore, PLANE_NV12_BUF_CFG(pipe, plane_id));
> -
> -		if (fourcc &&
> -		    drm_format_info_is_yuv_semiplanar(drm_format_info(fourcc)))
> -			swap(val, val2);
> +	if (DISPLAY_VER(dev_priv) >= 11)
> +		return;
>  
> -		skl_ddb_entry_init_from_hw(ddb_y, val);
> -		skl_ddb_entry_init_from_hw(ddb_uv, val2);
> -	}
> +	val = intel_uncore_read(&dev_priv->uncore, PLANE_NV12_BUF_CFG(pipe, plane_id));
> +	skl_ddb_entry_init_from_hw(ddb_y, val);
>  }
>  
>  void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
> -			       struct skl_ddb_entry *ddb_y,
> -			       struct skl_ddb_entry *ddb_uv)
> +			       struct skl_ddb_entry *ddb,
> +			       struct skl_ddb_entry *ddb_y)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum intel_display_power_domain power_domain;
> @@ -4367,8 +4352,8 @@ void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
>  	for_each_plane_id_on_crtc(crtc, plane_id)
>  		skl_ddb_get_hw_plane_state(dev_priv, pipe,
>  					   plane_id,
> -					   &ddb_y[plane_id],
> -					   &ddb_uv[plane_id]);
> +					   &ddb[plane_id],
> +					   &ddb_y[plane_id]);
>  
>  	intel_display_power_put(dev_priv, power_domain, wakeref);
>  }
> @@ -5105,8 +5090,8 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
>  	int level;
>  
>  	/* Clear the partitioning for disabled planes. */
> +	memset(crtc_state->wm.skl.plane_ddb, 0, sizeof(crtc_state->wm.skl.plane_ddb));
>  	memset(crtc_state->wm.skl.plane_ddb_y, 0, sizeof(crtc_state->wm.skl.plane_ddb_y));
> -	memset(crtc_state->wm.skl.plane_ddb_uv, 0, sizeof(crtc_state->wm.skl.plane_ddb_uv));
>  
>  	if (!crtc_state->hw.active)
>  		return 0;
> @@ -5123,7 +5108,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
>  	/* Allocate fixed number of blocks for cursor. */
>  	iter.total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
>  	iter.size -= iter.total[PLANE_CURSOR];
> -	skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR],
> +	skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[PLANE_CURSOR],
>  			   alloc->end - iter.total[PLANE_CURSOR], alloc->end);
>  
>  	if (iter.data_rate == 0)
> @@ -5202,10 +5187,10 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
>  	/* Set the actual DDB start/end points for each plane */
>  	iter.start = alloc->start;
>  	for_each_plane_id_on_crtc(crtc, plane_id) {
> -		struct skl_ddb_entry *plane_alloc =
> +		struct skl_ddb_entry *ddb =
> +			&crtc_state->wm.skl.plane_ddb[plane_id];
> +		struct skl_ddb_entry *ddb_y =
>  			&crtc_state->wm.skl.plane_ddb_y[plane_id];
> -		struct skl_ddb_entry *uv_plane_alloc =
> -			&crtc_state->wm.skl.plane_ddb_uv[plane_id];
>  
>  		if (plane_id == PLANE_CURSOR)
>  			continue;
> @@ -5216,12 +5201,15 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
>  
>  		/* Leave disabled planes at (0,0) */
>  		if (iter.total[plane_id])
> -			iter.start = skl_ddb_entry_init(plane_alloc, iter.start,
> +			iter.start = skl_ddb_entry_init(ddb, iter.start,
>  							iter.start + iter.total[plane_id]);
>  
> -		if (iter.uv_total[plane_id])
> -			iter.start = skl_ddb_entry_init(uv_plane_alloc, iter.start,
> +		if (iter.uv_total[plane_id]) {
> +			/* hardware wants these swapped */
> +			*ddb_y = *ddb;
> +			iter.start = skl_ddb_entry_init(ddb, iter.start,
>  							iter.start + iter.uv_total[plane_id]);
> +		}
>  	}
>  
>  	/*
> @@ -5874,11 +5862,10 @@ void skl_write_plane_wm(struct intel_plane *plane,
>  	enum plane_id plane_id = plane->id;
>  	enum pipe pipe = plane->pipe;
>  	const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> -	const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
> +	const struct skl_ddb_entry *ddb =
> +		&crtc_state->wm.skl.plane_ddb[plane_id];
>  	const struct skl_ddb_entry *ddb_y =
>  		&crtc_state->wm.skl.plane_ddb_y[plane_id];
> -	const struct skl_ddb_entry *ddb_uv =
> -		&crtc_state->wm.skl.plane_ddb_uv[plane_id];
>  
>  	for (level = 0; level <= max_level; level++)
>  		skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
> @@ -5888,25 +5875,20 @@ void skl_write_plane_wm(struct intel_plane *plane,
>  			   skl_plane_trans_wm(pipe_wm, plane_id));
>  
>  	if (HAS_HW_SAGV_WM(dev_priv)) {
> +		const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
> +
>  		skl_write_wm_level(dev_priv, PLANE_WM_SAGV(pipe, plane_id),
>  				   &wm->sagv.wm0);
>  		skl_write_wm_level(dev_priv, PLANE_WM_SAGV_TRANS(pipe, plane_id),
>  				   &wm->sagv.trans_wm);
>  	}
>  
> -	if (DISPLAY_VER(dev_priv) >= 11) {
> +	skl_ddb_entry_write(dev_priv,
> +			    PLANE_BUF_CFG(pipe, plane_id), ddb);
> +
> +	if (DISPLAY_VER(dev_priv) < 11)
>  		skl_ddb_entry_write(dev_priv,
> -				    PLANE_BUF_CFG(pipe, plane_id), ddb_y);
> -		return;
> -	}
> -
> -	if (wm->is_planar)
> -		swap(ddb_y, ddb_uv);
> -
> -	skl_ddb_entry_write(dev_priv,
> -			    PLANE_BUF_CFG(pipe, plane_id), ddb_y);
> -	skl_ddb_entry_write(dev_priv,
> -			    PLANE_NV12_BUF_CFG(pipe, plane_id), ddb_uv);
> +				    PLANE_NV12_BUF_CFG(pipe, plane_id), ddb_y);
>  }
>  
>  void skl_write_cursor_wm(struct intel_plane *plane,
> @@ -5918,7 +5900,7 @@ void skl_write_cursor_wm(struct intel_plane *plane,
>  	enum pipe pipe = plane->pipe;
>  	const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
>  	const struct skl_ddb_entry *ddb =
> -		&crtc_state->wm.skl.plane_ddb_y[plane_id];
> +		&crtc_state->wm.skl.plane_ddb[plane_id];
>  
>  	for (level = 0; level <= max_level; level++)
>  		skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
> @@ -6015,10 +5997,10 @@ skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state,
>  		struct intel_plane_state *plane_state;
>  		enum plane_id plane_id = plane->id;
>  
> -		if (skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_y[plane_id],
> -					&new_crtc_state->wm.skl.plane_ddb_y[plane_id]) &&
> -		    skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_uv[plane_id],
> -					&new_crtc_state->wm.skl.plane_ddb_uv[plane_id]))
> +		if (skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb[plane_id],
> +					&new_crtc_state->wm.skl.plane_ddb[plane_id]) &&
> +		    skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_y[plane_id],
> +					&new_crtc_state->wm.skl.plane_ddb_y[plane_id]))
>  			continue;
>  
>  		plane_state = intel_atomic_get_plane_state(state, plane);
> @@ -6185,8 +6167,8 @@ skl_print_wm_changes(struct intel_atomic_state *state)
>  			enum plane_id plane_id = plane->id;
>  			const struct skl_ddb_entry *old, *new;
>  
> -			old = &old_crtc_state->wm.skl.plane_ddb_y[plane_id];
> -			new = &new_crtc_state->wm.skl.plane_ddb_y[plane_id];
> +			old = &old_crtc_state->wm.skl.plane_ddb[plane_id];
> +			new = &new_crtc_state->wm.skl.plane_ddb[plane_id];
>  
>  			if (skl_ddb_entry_equal(old, new))
>  				continue;
> @@ -6587,16 +6569,16 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
>  		memset(&dbuf_state->ddb[pipe], 0, sizeof(dbuf_state->ddb[pipe]));
>  
>  		for_each_plane_id_on_crtc(crtc, plane_id) {
> +			struct skl_ddb_entry *ddb =
> +				&crtc_state->wm.skl.plane_ddb[plane_id];
>  			struct skl_ddb_entry *ddb_y =
>  				&crtc_state->wm.skl.plane_ddb_y[plane_id];
> -			struct skl_ddb_entry *ddb_uv =
> -				&crtc_state->wm.skl.plane_ddb_uv[plane_id];
>  
>  			skl_ddb_get_hw_plane_state(dev_priv, crtc->pipe,
> -						   plane_id, ddb_y, ddb_uv);
> +						   plane_id, ddb, ddb_y);
>  
> +			skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb);
>  			skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb_y);
> -			skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb_uv);
>  		}
>  
>  		dbuf_state->slices[pipe] =
> -- 
> 2.32.0
> 

Re: [Intel-gfx] [PATCH 08/15] drm/i915: Split plane data_rate into data_rate+data_rate_y

[Lisovskiy, Stanislav]

On Tue, Jan 18, 2022 at 11:23:47AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Split the currently combined plane data_rate into the proper
> Y vs. CbCr components. This matches how we now track the
> plane dbuf allocations, and thus will make the dbuf bandwidth
> calculations actually produce the correct numbers for each
> dbuf slice.

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  .../gpu/drm/i915/display/intel_atomic_plane.c | 34 ++++++++----------
>  .../gpu/drm/i915/display/intel_atomic_plane.h |  3 +-
>  drivers/gpu/drm/i915/display/intel_bw.c       | 36 +++++++++----------
>  drivers/gpu/drm/i915/display/intel_display.c  |  4 +++
>  .../drm/i915/display/intel_display_types.h    |  3 ++
>  5 files changed, 42 insertions(+), 38 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index 52239351931c..cd18155830d4 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -180,29 +180,16 @@ unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
>  }
>  
>  unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
> -				   const struct intel_plane_state *plane_state)
> +				   const struct intel_plane_state *plane_state,
> +				   int color_plane)
>  {
>  	const struct drm_framebuffer *fb = plane_state->hw.fb;
> -	unsigned int cpp;
> -	unsigned int pixel_rate;
>  
>  	if (!plane_state->uapi.visible)
>  		return 0;
>  
> -	pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);
> -
> -	cpp = fb->format->cpp[0];
> -
> -	/*
> -	 * Based on HSD#:1408715493
> -	 * NV12 cpp == 4, P010 cpp == 8
> -	 *
> -	 * FIXME what is the logic behind this?
> -	 */
> -	if (fb->format->is_yuv && fb->format->num_planes > 1)
> -		cpp *= 4;
> -
> -	return pixel_rate * cpp;
> +	return intel_plane_pixel_rate(crtc_state, plane_state) *
> +		fb->format->cpp[color_plane];
>  }
>  
>  int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
> @@ -324,6 +311,7 @@ void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
>  	crtc_state->nv12_planes &= ~BIT(plane->id);
>  	crtc_state->c8_planes &= ~BIT(plane->id);
>  	crtc_state->data_rate[plane->id] = 0;
> +	crtc_state->data_rate_y[plane->id] = 0;
>  	crtc_state->min_cdclk[plane->id] = 0;
>  
>  	plane_state->uapi.visible = false;
> @@ -366,8 +354,16 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
>  	if (new_plane_state->uapi.visible || old_plane_state->uapi.visible)
>  		new_crtc_state->update_planes |= BIT(plane->id);
>  
> -	new_crtc_state->data_rate[plane->id] =
> -		intel_plane_data_rate(new_crtc_state, new_plane_state);
> +	if (new_plane_state->uapi.visible &&
> +	    intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
> +		new_crtc_state->data_rate_y[plane->id] =
> +			intel_plane_data_rate(new_crtc_state, new_plane_state, 0);
> +		new_crtc_state->data_rate[plane->id] =
> +			intel_plane_data_rate(new_crtc_state, new_plane_state, 1);
> +	} else if (new_plane_state->uapi.visible) {
> +		new_crtc_state->data_rate[plane->id] =
> +			intel_plane_data_rate(new_crtc_state, new_plane_state, 0);
> +	}
>  
>  	return intel_plane_atomic_calc_changes(old_crtc_state, new_crtc_state,
>  					       old_plane_state, new_plane_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> index 7907f601598e..aa26ce5fb654 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> @@ -24,7 +24,8 @@ unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
>  				    const struct intel_plane_state *plane_state);
>  
>  unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
> -				   const struct intel_plane_state *plane_state);
> +				   const struct intel_plane_state *plane_state,
> +				   int color_plane);
>  void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
>  				       const struct intel_plane_state *from_plane_state,
>  				       struct intel_crtc *crtc);
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 82f0435bcb6d..93feab671c29 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -576,6 +576,7 @@ static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_stat
>  static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>  	unsigned int data_rate = 0;
>  	enum plane_id plane_id;
>  
> @@ -588,6 +589,9 @@ static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_
>  			continue;
>  
>  		data_rate += crtc_state->data_rate[plane_id];
> +
> +		if (DISPLAY_VER(i915) < 11)
> +			data_rate += crtc_state->data_rate_y[plane_id];
>  	}
>  
>  	return data_rate;
> @@ -688,28 +692,24 @@ static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state,
>  	for_each_plane_id_on_crtc(crtc, plane_id) {
>  		const struct skl_ddb_entry *ddb =
>  			&crtc_state->wm.skl.plane_ddb[plane_id];
> -		const struct skl_ddb_entry *ddb_y =
> -			&crtc_state->wm.skl.plane_ddb_y[plane_id];
>  		unsigned int data_rate = crtc_state->data_rate[plane_id];
> -		unsigned int dbuf_mask = 0;
> +		unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(i915, ddb);
>  		enum dbuf_slice slice;
>  
> -		dbuf_mask |= skl_ddb_dbuf_slice_mask(i915, ddb);
> -		dbuf_mask |= skl_ddb_dbuf_slice_mask(i915, ddb_y);
> +		for_each_dbuf_slice_in_mask(i915, slice, dbuf_mask)
> +			crtc_bw->used_bw[slice] += data_rate;
> +	}
> +
> +	if (DISPLAY_VER(i915) >= 11)
> +		return;
> +
> +	for_each_plane_id_on_crtc(crtc, plane_id) {
> +		const struct skl_ddb_entry *ddb =
> +			&crtc_state->wm.skl.plane_ddb_y[plane_id];
> +		unsigned int data_rate = crtc_state->data_rate_y[plane_id];
> +		unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(i915, ddb);
> +		enum dbuf_slice slice;
>  
> -		/*
> -		 * FIXME: To calculate that more properly we probably
> -		 * need to split per plane data_rate into data_rate_y
> -		 * and data_rate_uv for multiplanar formats in order not
> -		 * to get accounted those twice if they happen to reside
> -		 * on different slices.
> -		 * However for pre-icl this would work anyway because
> -		 * we have only single slice and for icl+ uv plane has
> -		 * non-zero data rate.
> -		 * So in worst case those calculation are a bit
> -		 * pessimistic, which shouldn't pose any significant
> -		 * problem anyway.
> -		 */
>  		for_each_dbuf_slice_in_mask(i915, slice, dbuf_mask)
>  			crtc_bw->used_bw[slice] += data_rate;
>  	}
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index af23153f6502..39dd2e7383e0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -761,6 +761,7 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
>  	intel_set_plane_visible(crtc_state, plane_state, false);
>  	fixup_plane_bitmasks(crtc_state);
>  	crtc_state->data_rate[plane->id] = 0;
> +	crtc_state->data_rate_y[plane->id] = 0;
>  	crtc_state->min_cdclk[plane->id] = 0;
>  
>  	if (plane->id == PLANE_PRIMARY)
> @@ -5110,6 +5111,7 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
>  			crtc_state->enabled_planes &= ~BIT(plane->id);
>  			crtc_state->active_planes &= ~BIT(plane->id);
>  			crtc_state->update_planes |= BIT(plane->id);
> +			crtc_state->data_rate[plane->id] = 0;
>  		}
>  
>  		plane_state->planar_slave = false;
> @@ -5154,6 +5156,8 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
>  		crtc_state->enabled_planes |= BIT(linked->id);
>  		crtc_state->active_planes |= BIT(linked->id);
>  		crtc_state->update_planes |= BIT(linked->id);
> +		crtc_state->data_rate[linked->id] =
> +			crtc_state->data_rate_y[plane->id];
>  		drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",
>  			    linked->base.name, plane->base.name);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 578c6069376b..7e147e110059 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1148,7 +1148,10 @@ struct intel_crtc_state {
>  
>  	int min_cdclk[I915_MAX_PLANES];
>  
> +	/* for packed/planar CbCr */
>  	u32 data_rate[I915_MAX_PLANES];
> +	/* for planar Y */
> +	u32 data_rate_y[I915_MAX_PLANES];
>  
>  	/* FIXME unify with data_rate[] */
>  	u64 plane_data_rate[I915_MAX_PLANES];
> -- 
> 2.32.0
> 

Re: [Intel-gfx] [PATCH 09/15] drm/i915: Pre-calculate plane relative data rate

[Lisovskiy, Stanislav]

On Tue, Jan 18, 2022 at 11:23:48AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Handle the plane relative data rate in exactly the same
> way as we already handle the real data rate. Ie. pre-calculate
> it during intel_plane_atomic_check_with_state(), and assign/clear
> it for the Y plane as needed. This should guarantee that the
> tracking is 100% consistent, and makes me have to think less
> when the same apporach is used by both types of data rate.
> 
> We might even want to consider replacing the relative
> data rate with the real data rate entirely, but it's not
> clear if that will produce less optimal plane ddb
> allocations. So for now lets keep using the current approach.

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  .../gpu/drm/i915/display/intel_atomic_plane.c |  37 ++++
>  drivers/gpu/drm/i915/display/intel_display.c  |   5 +
>  .../drm/i915/display/intel_display_types.h    |   6 +-
>  drivers/gpu/drm/i915/intel_pm.c               | 170 ++++--------------
>  4 files changed, 80 insertions(+), 138 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index cd18155830d4..a61344dcfb94 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -192,6 +192,33 @@ unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
>  		fb->format->cpp[color_plane];
>  }
>  
> +static unsigned int
> +intel_plane_relative_data_rate(const struct intel_plane_state *plane_state,
> +			       int color_plane)
> +{
> +	const struct drm_framebuffer *fb = plane_state->hw.fb;
> +	int width, height;
> +
> +	if (!plane_state->uapi.visible)
> +		return 0;
> +
> +	/*
> +	 * Src coordinates are already rotated by 270 degrees for
> +	 * the 90/270 degree plane rotation cases (to match the
> +	 * GTT mapping), hence no need to account for rotation here.
> +	 */
> +	width = drm_rect_width(&plane_state->uapi.src) >> 16;
> +	height = drm_rect_height(&plane_state->uapi.src) >> 16;
> +
> +	/* UV plane does 1/2 pixel sub-sampling */
> +	if (color_plane == 1) {
> +		width /= 2;
> +		height /= 2;
> +	}
> +
> +	return width * height * fb->format->cpp[color_plane];
> +}
> +
>  int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
>  			       struct intel_plane *plane,
>  			       bool *need_cdclk_calc)
> @@ -312,6 +339,8 @@ void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
>  	crtc_state->c8_planes &= ~BIT(plane->id);
>  	crtc_state->data_rate[plane->id] = 0;
>  	crtc_state->data_rate_y[plane->id] = 0;
> +	crtc_state->rel_data_rate[plane->id] = 0;
> +	crtc_state->rel_data_rate_y[plane->id] = 0;
>  	crtc_state->min_cdclk[plane->id] = 0;
>  
>  	plane_state->uapi.visible = false;
> @@ -360,9 +389,17 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
>  			intel_plane_data_rate(new_crtc_state, new_plane_state, 0);
>  		new_crtc_state->data_rate[plane->id] =
>  			intel_plane_data_rate(new_crtc_state, new_plane_state, 1);
> +
> +		new_crtc_state->rel_data_rate_y[plane->id] =
> +			intel_plane_relative_data_rate(new_plane_state, 0);
> +		new_crtc_state->rel_data_rate[plane->id] =
> +			intel_plane_relative_data_rate(new_plane_state, 1);
>  	} else if (new_plane_state->uapi.visible) {
>  		new_crtc_state->data_rate[plane->id] =
>  			intel_plane_data_rate(new_crtc_state, new_plane_state, 0);
> +
> +		new_crtc_state->rel_data_rate[plane->id] =
> +			intel_plane_relative_data_rate(new_plane_state, 0);
>  	}
>  
>  	return intel_plane_atomic_calc_changes(old_crtc_state, new_crtc_state,
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 39dd2e7383e0..8f3034713c56 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -762,6 +762,8 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
>  	fixup_plane_bitmasks(crtc_state);
>  	crtc_state->data_rate[plane->id] = 0;
>  	crtc_state->data_rate_y[plane->id] = 0;
> +	crtc_state->rel_data_rate[plane->id] = 0;
> +	crtc_state->rel_data_rate_y[plane->id] = 0;
>  	crtc_state->min_cdclk[plane->id] = 0;
>  
>  	if (plane->id == PLANE_PRIMARY)
> @@ -5112,6 +5114,7 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
>  			crtc_state->active_planes &= ~BIT(plane->id);
>  			crtc_state->update_planes |= BIT(plane->id);
>  			crtc_state->data_rate[plane->id] = 0;
> +			crtc_state->rel_data_rate[plane->id] = 0;
>  		}
>  
>  		plane_state->planar_slave = false;
> @@ -5158,6 +5161,8 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
>  		crtc_state->update_planes |= BIT(linked->id);
>  		crtc_state->data_rate[linked->id] =
>  			crtc_state->data_rate_y[plane->id];
> +		crtc_state->rel_data_rate[linked->id] =
> +			crtc_state->rel_data_rate_y[plane->id];
>  		drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",
>  			    linked->base.name, plane->base.name);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 7e147e110059..871485af14d4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1153,9 +1153,9 @@ struct intel_crtc_state {
>  	/* for planar Y */
>  	u32 data_rate_y[I915_MAX_PLANES];
>  
> -	/* FIXME unify with data_rate[] */
> -	u64 plane_data_rate[I915_MAX_PLANES];
> -	u64 uv_plane_data_rate[I915_MAX_PLANES];
> +	/* FIXME unify with data_rate[]? */
> +	u64 rel_data_rate[I915_MAX_PLANES];
> +	u64 rel_data_rate_y[I915_MAX_PLANES];
>  
>  	/* Gamma mode programmed on the pipe */
>  	u32 gamma_mode;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 8a115b4c9e71..134584c77697 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4862,126 +4862,24 @@ static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes)
>  }
>  
>  static u64
> -skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
> -			     const struct intel_plane_state *plane_state,
> -			     int color_plane)
> +skl_total_relative_data_rate(const struct intel_crtc_state *crtc_state)
>  {
> -	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> -	const struct drm_framebuffer *fb = plane_state->hw.fb;
> -	int width, height;
> -
> -	if (!plane_state->uapi.visible)
> -		return 0;
> -
> -	if (plane->id == PLANE_CURSOR)
> -		return 0;
> -
> -	if (color_plane == 1 &&
> -	    !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
> -		return 0;
> -
> -	/*
> -	 * Src coordinates are already rotated by 270 degrees for
> -	 * the 90/270 degree plane rotation cases (to match the
> -	 * GTT mapping), hence no need to account for rotation here.
> -	 */
> -	width = drm_rect_width(&plane_state->uapi.src) >> 16;
> -	height = drm_rect_height(&plane_state->uapi.src) >> 16;
> -
> -	/* UV plane does 1/2 pixel sub-sampling */
> -	if (color_plane == 1) {
> -		width /= 2;
> -		height /= 2;
> -	}
> -
> -	return width * height * fb->format->cpp[color_plane];
> -}
> -
> -static u64
> -skl_get_total_relative_data_rate(struct intel_atomic_state *state,
> -				 struct intel_crtc *crtc)
> -{
> -	struct intel_crtc_state *crtc_state =
> -		intel_atomic_get_new_crtc_state(state, crtc);
> -	const struct intel_plane_state *plane_state;
> -	struct intel_plane *plane;
> -	u64 total_data_rate = 0;
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>  	enum plane_id plane_id;
> -	int i;
> -
> -	/* Calculate and cache data rate for each plane */
> -	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
> -		if (plane->pipe != crtc->pipe)
> -			continue;
> -
> -		plane_id = plane->id;
> -
> -		/* packed/y */
> -		crtc_state->plane_data_rate[plane_id] =
> -			skl_plane_relative_data_rate(crtc_state, plane_state, 0);
> -
> -		/* uv-plane */
> -		crtc_state->uv_plane_data_rate[plane_id] =
> -			skl_plane_relative_data_rate(crtc_state, plane_state, 1);
> -	}
> +	u64 data_rate = 0;
>  
>  	for_each_plane_id_on_crtc(crtc, plane_id) {
> -		total_data_rate += crtc_state->plane_data_rate[plane_id];
> -		total_data_rate += crtc_state->uv_plane_data_rate[plane_id];
> -	}
> -
> -	return total_data_rate;
> -}
> -
> -static u64
> -icl_get_total_relative_data_rate(struct intel_atomic_state *state,
> -				 struct intel_crtc *crtc)
> -{
> -	struct intel_crtc_state *crtc_state =
> -		intel_atomic_get_new_crtc_state(state, crtc);
> -	const struct intel_plane_state *plane_state;
> -	struct intel_plane *plane;
> -	u64 total_data_rate = 0;
> -	enum plane_id plane_id;
> -	int i;
> -
> -	/* Calculate and cache data rate for each plane */
> -	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
> -		if (plane->pipe != crtc->pipe)
> +		if (plane_id == PLANE_CURSOR)
>  			continue;
>  
> -		plane_id = plane->id;
> +		data_rate += crtc_state->rel_data_rate[plane_id];
>  
> -		if (!plane_state->planar_linked_plane) {
> -			crtc_state->plane_data_rate[plane_id] =
> -				skl_plane_relative_data_rate(crtc_state, plane_state, 0);
> -		} else {
> -			enum plane_id y_plane_id;
> -
> -			/*
> -			 * The slave plane might not iterate in
> -			 * intel_atomic_crtc_state_for_each_plane_state(),
> -			 * and needs the master plane state which may be
> -			 * NULL if we try get_new_plane_state(), so we
> -			 * always calculate from the master.
> -			 */
> -			if (plane_state->planar_slave)
> -				continue;
> -
> -			/* Y plane rate is calculated on the slave */
> -			y_plane_id = plane_state->planar_linked_plane->id;
> -			crtc_state->plane_data_rate[y_plane_id] =
> -				skl_plane_relative_data_rate(crtc_state, plane_state, 0);
> -
> -			crtc_state->plane_data_rate[plane_id] =
> -				skl_plane_relative_data_rate(crtc_state, plane_state, 1);
> -		}
> +		if (DISPLAY_VER(i915) < 11)
> +			data_rate += crtc_state->rel_data_rate_y[plane_id];
>  	}
>  
> -	for_each_plane_id_on_crtc(crtc, plane_id)
> -		total_data_rate += crtc_state->plane_data_rate[plane_id];
> -
> -	return total_data_rate;
> +	return data_rate;
>  }
>  
>  const struct skl_wm_level *
> @@ -5096,11 +4994,6 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
>  	if (!crtc_state->hw.active)
>  		return 0;
>  
> -	if (DISPLAY_VER(dev_priv) >= 11)
> -		iter.data_rate = icl_get_total_relative_data_rate(state, crtc);
> -	else
> -		iter.data_rate = skl_get_total_relative_data_rate(state, crtc);
> -
>  	iter.size = skl_ddb_entry_size(alloc);
>  	if (iter.size == 0)
>  		return 0;
> @@ -5111,6 +5004,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
>  	skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[PLANE_CURSOR],
>  			   alloc->end - iter.total[PLANE_CURSOR], alloc->end);
>  
> +	iter.data_rate = skl_total_relative_data_rate(crtc_state);
>  	if (iter.data_rate == 0)
>  		return 0;
>  
> @@ -5171,16 +5065,19 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
>  		if (iter.data_rate == 0)
>  			break;
>  
> -		iter.total[plane_id] =
> -			skl_allocate_plane_ddb(&iter, &wm->wm[level],
> -					       crtc_state->plane_data_rate[plane_id]);
> -
> -		if (iter.data_rate == 0)
> -			break;
> -
> -		iter.uv_total[plane_id] =
> -			skl_allocate_plane_ddb(&iter, &wm->uv_wm[level],
> -					       crtc_state->uv_plane_data_rate[plane_id]);
> +		if (DISPLAY_VER(dev_priv) < 11 &&
> +		    crtc_state->nv12_planes & BIT(plane_id)) {
> +			iter.total[plane_id] =
> +				skl_allocate_plane_ddb(&iter, &wm->wm[level],
> +						       crtc_state->rel_data_rate_y[plane_id]);
> +			iter.uv_total[plane_id] =
> +				skl_allocate_plane_ddb(&iter, &wm->uv_wm[level],
> +						       crtc_state->rel_data_rate[plane_id]);
> +		} else {
> +			iter.total[plane_id] =
> +				skl_allocate_plane_ddb(&iter, &wm->wm[level],
> +						       crtc_state->rel_data_rate[plane_id]);
> +		}
>  	}
>  	drm_WARN_ON(&dev_priv->drm, iter.size != 0 || iter.data_rate != 0);
>  
> @@ -5200,15 +5097,18 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
>  			    DISPLAY_VER(dev_priv) >= 11 && iter.uv_total[plane_id]);
>  
>  		/* Leave disabled planes at (0,0) */
> -		if (iter.total[plane_id])
> -			iter.start = skl_ddb_entry_init(ddb, iter.start,
> -							iter.start + iter.total[plane_id]);
> -
> -		if (iter.uv_total[plane_id]) {
> -			/* hardware wants these swapped */
> -			*ddb_y = *ddb;
> -			iter.start = skl_ddb_entry_init(ddb, iter.start,
> -							iter.start + iter.uv_total[plane_id]);
> +		if (DISPLAY_VER(dev_priv) < 11 &&
> +		    crtc_state->nv12_planes & BIT(plane_id)) {
> +			if (iter.total[plane_id])
> +				iter.start = skl_ddb_entry_init(ddb_y, iter.start,
> +								iter.start + iter.total[plane_id]);
> +			if (iter.uv_total[plane_id])
> +				iter.start = skl_ddb_entry_init(ddb, iter.start,
> +								iter.start + iter.uv_total[plane_id]);
> +		} else {
> +			if (iter.total[plane_id])
> +				iter.start = skl_ddb_entry_init(ddb, iter.start,
> +								iter.start + iter.total[plane_id]);
>  		}
>  	}
>  
> -- 
> 2.32.0
> 

Re: [Intel-gfx] [PATCH 10/15] drm/i915: Remove total[] and uv_total[] from ddb allocation

[Lisovskiy, Stanislav]

On Tue, Jan 18, 2022 at 11:23:49AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> There's really no need to maintain these total[] arrays to
> track the size of each plane's ddb allocation. We just stick
> the results straight into the crtc_state ddb tracking structures.
> 
> The main annoyance with all this is the mismatch between
> wm_uv vs. ddb_y on pre-icl. If only the hw was consistent in
> what it considers the primary source of information we could
> avoid some of the uglyness. But since that is not the case
> we need a bit of special casing for planar formats.

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 115 +++++++++++++++-----------------
>  1 file changed, 55 insertions(+), 60 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 134584c77697..6c30c57748e8 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4920,18 +4920,18 @@ skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm,
>   * So this is actually safe to do.
>   */
>  static void
> -skl_check_wm_level(struct skl_wm_level *wm, u64 total)
> +skl_check_wm_level(struct skl_wm_level *wm, const struct skl_ddb_entry *ddb)
>  {
> -	if (wm->min_ddb_alloc > total)
> +	if (wm->min_ddb_alloc > skl_ddb_entry_size(ddb))
>  		memset(wm, 0, sizeof(*wm));
>  }
>  
>  static void
>  skl_check_nv12_wm_level(struct skl_wm_level *wm, struct skl_wm_level *uv_wm,
> -			u64 total, u64 uv_total)
> +			const struct skl_ddb_entry *ddb_y, const struct skl_ddb_entry *ddb)
>  {
> -	if (wm->min_ddb_alloc > total ||
> -	    uv_wm->min_ddb_alloc > uv_total) {
> +	if (wm->min_ddb_alloc > skl_ddb_entry_size(ddb_y) ||
> +	    uv_wm->min_ddb_alloc > skl_ddb_entry_size(ddb)) {
>  		memset(wm, 0, sizeof(*wm));
>  		memset(uv_wm, 0, sizeof(*uv_wm));
>  	}
> @@ -4951,13 +4951,12 @@ static bool icl_need_wm1_wa(struct drm_i915_private *i915,
>  
>  struct skl_plane_ddb_iter {
>  	u64 data_rate;
> -	u16 total[I915_MAX_PLANES];
> -	u16 uv_total[I915_MAX_PLANES];
>  	u16 start, size;
>  };
>  
> -static u16
> +static void
>  skl_allocate_plane_ddb(struct skl_plane_ddb_iter *iter,
> +		       struct skl_ddb_entry *ddb,
>  		       const struct skl_wm_level *wm,
>  		       u64 data_rate)
>  {
> @@ -4968,7 +4967,8 @@ skl_allocate_plane_ddb(struct skl_plane_ddb_iter *iter,
>  	iter->size -= extra;
>  	iter->data_rate -= data_rate;
>  
> -	return wm->min_ddb_alloc + extra;
> +	iter->start = skl_ddb_entry_init(ddb, iter->start,
> +					 iter->start + wm->min_ddb_alloc + extra);
>  }
>  
>  static int
> @@ -4982,8 +4982,9 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
>  		intel_atomic_get_new_dbuf_state(state);
>  	const struct skl_ddb_entry *alloc = &dbuf_state->ddb[crtc->pipe];
>  	int num_active = hweight8(dbuf_state->active_pipes);
> -	struct skl_plane_ddb_iter iter = {};
> +	struct skl_plane_ddb_iter iter;
>  	enum plane_id plane_id;
> +	u16 cursor_size;
>  	u32 blocks;
>  	int level;
>  
> @@ -4994,15 +4995,16 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
>  	if (!crtc_state->hw.active)
>  		return 0;
>  
> +	iter.start = alloc->start;
>  	iter.size = skl_ddb_entry_size(alloc);
>  	if (iter.size == 0)
>  		return 0;
>  
>  	/* Allocate fixed number of blocks for cursor. */
> -	iter.total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
> -	iter.size -= iter.total[PLANE_CURSOR];
> +	cursor_size = skl_cursor_allocation(crtc_state, num_active);
> +	iter.size -= cursor_size;
>  	skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[PLANE_CURSOR],
> -			   alloc->end - iter.total[PLANE_CURSOR], alloc->end);
> +			   alloc->end - cursor_size, alloc->end);
>  
>  	iter.data_rate = skl_total_relative_data_rate(crtc_state);
>  	if (iter.data_rate == 0)
> @@ -5019,7 +5021,10 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
>  				&crtc_state->wm.skl.optimal.planes[plane_id];
>  
>  			if (plane_id == PLANE_CURSOR) {
> -				if (wm->wm[level].min_ddb_alloc > iter.total[PLANE_CURSOR]) {
> +				const struct skl_ddb_entry *ddb =
> +					&crtc_state->wm.skl.plane_ddb[plane_id];
> +
> +				if (wm->wm[level].min_ddb_alloc > skl_ddb_entry_size(ddb)) {
>  					drm_WARN_ON(&dev_priv->drm,
>  						    wm->wm[level].min_ddb_alloc != U16_MAX);
>  					blocks = U32_MAX;
> @@ -5052,6 +5057,10 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
>  	 * proportional to its relative data rate.
>  	 */
>  	for_each_plane_id_on_crtc(crtc, plane_id) {
> +		struct skl_ddb_entry *ddb =
> +			&crtc_state->wm.skl.plane_ddb[plane_id];
> +		struct skl_ddb_entry *ddb_y =
> +			&crtc_state->wm.skl.plane_ddb_y[plane_id];
>  		const struct skl_plane_wm *wm =
>  			&crtc_state->wm.skl.optimal.planes[plane_id];
>  
> @@ -5067,51 +5076,17 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
>  
>  		if (DISPLAY_VER(dev_priv) < 11 &&
>  		    crtc_state->nv12_planes & BIT(plane_id)) {
> -			iter.total[plane_id] =
> -				skl_allocate_plane_ddb(&iter, &wm->wm[level],
> -						       crtc_state->rel_data_rate_y[plane_id]);
> -			iter.uv_total[plane_id] =
> -				skl_allocate_plane_ddb(&iter, &wm->uv_wm[level],
> -						       crtc_state->rel_data_rate[plane_id]);
> +			skl_allocate_plane_ddb(&iter, ddb_y, &wm->wm[level],
> +					       crtc_state->rel_data_rate_y[plane_id]);
> +			skl_allocate_plane_ddb(&iter, ddb, &wm->uv_wm[level],
> +					       crtc_state->rel_data_rate[plane_id]);
>  		} else {
> -			iter.total[plane_id] =
> -				skl_allocate_plane_ddb(&iter, &wm->wm[level],
> -						       crtc_state->rel_data_rate[plane_id]);
> +			skl_allocate_plane_ddb(&iter, ddb, &wm->wm[level],
> +					       crtc_state->rel_data_rate[plane_id]);
>  		}
>  	}
>  	drm_WARN_ON(&dev_priv->drm, iter.size != 0 || iter.data_rate != 0);
>  
> -	/* Set the actual DDB start/end points for each plane */
> -	iter.start = alloc->start;
> -	for_each_plane_id_on_crtc(crtc, plane_id) {
> -		struct skl_ddb_entry *ddb =
> -			&crtc_state->wm.skl.plane_ddb[plane_id];
> -		struct skl_ddb_entry *ddb_y =
> -			&crtc_state->wm.skl.plane_ddb_y[plane_id];
> -
> -		if (plane_id == PLANE_CURSOR)
> -			continue;
> -
> -		/* Gen11+ uses a separate plane for UV watermarks */
> -		drm_WARN_ON(&dev_priv->drm,
> -			    DISPLAY_VER(dev_priv) >= 11 && iter.uv_total[plane_id]);
> -
> -		/* Leave disabled planes at (0,0) */
> -		if (DISPLAY_VER(dev_priv) < 11 &&
> -		    crtc_state->nv12_planes & BIT(plane_id)) {
> -			if (iter.total[plane_id])
> -				iter.start = skl_ddb_entry_init(ddb_y, iter.start,
> -								iter.start + iter.total[plane_id]);
> -			if (iter.uv_total[plane_id])
> -				iter.start = skl_ddb_entry_init(ddb, iter.start,
> -								iter.start + iter.uv_total[plane_id]);
> -		} else {
> -			if (iter.total[plane_id])
> -				iter.start = skl_ddb_entry_init(ddb, iter.start,
> -								iter.start + iter.total[plane_id]);
> -		}
> -	}
> -
>  	/*
>  	 * When we calculated watermark values we didn't know how high
>  	 * of a level we'd actually be able to hit, so we just marked
> @@ -5120,12 +5095,20 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
>  	 */
>  	for (level++; level <= ilk_wm_max_level(dev_priv); level++) {
>  		for_each_plane_id_on_crtc(crtc, plane_id) {
> +			const struct skl_ddb_entry *ddb =
> +				&crtc_state->wm.skl.plane_ddb[plane_id];
> +			const struct skl_ddb_entry *ddb_y =
> +				&crtc_state->wm.skl.plane_ddb_y[plane_id];
>  			struct skl_plane_wm *wm =
>  				&crtc_state->wm.skl.optimal.planes[plane_id];
>  
> -			skl_check_nv12_wm_level(&wm->wm[level], &wm->uv_wm[level],
> -						iter.total[plane_id],
> -						iter.uv_total[plane_id]);
> +			if (DISPLAY_VER(dev_priv) < 11 &&
> +			    crtc_state->nv12_planes & BIT(plane_id))
> +				skl_check_nv12_wm_level(&wm->wm[level],
> +							&wm->uv_wm[level],
> +							ddb_y, ddb);
> +			else
> +				skl_check_wm_level(&wm->wm[level], ddb);
>  
>  			if (icl_need_wm1_wa(dev_priv, plane_id) &&
>  			    level == 1 && wm->wm[0].enable) {
> @@ -5141,12 +5124,24 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
>  	 * if it turns out we don't have enough DDB blocks for them.
>  	 */
>  	for_each_plane_id_on_crtc(crtc, plane_id) {
> +		const struct skl_ddb_entry *ddb =
> +			&crtc_state->wm.skl.plane_ddb[plane_id];
> +		const struct skl_ddb_entry *ddb_y =
> +			&crtc_state->wm.skl.plane_ddb_y[plane_id];
>  		struct skl_plane_wm *wm =
>  			&crtc_state->wm.skl.optimal.planes[plane_id];
>  
> -		skl_check_wm_level(&wm->trans_wm, iter.total[plane_id]);
> -		skl_check_wm_level(&wm->sagv.wm0, iter.total[plane_id]);
> -		skl_check_wm_level(&wm->sagv.trans_wm, iter.total[plane_id]);
> +		if (DISPLAY_VER(dev_priv) < 11 &&
> +		    crtc_state->nv12_planes & BIT(plane_id)) {
> +			skl_check_wm_level(&wm->trans_wm, ddb_y);
> +		} else {
> +			WARN_ON(skl_ddb_entry_size(ddb_y));
> +
> +			skl_check_wm_level(&wm->trans_wm, ddb);
> +		}
> +
> +		skl_check_wm_level(&wm->sagv.wm0, ddb);
> +		skl_check_wm_level(&wm->sagv.trans_wm, ddb);
>  	}
>  
>  	return 0;
> -- 
> 2.32.0
> 

Re: [Intel-gfx] [PATCH 11/15] drm/i915: Nuke intel_bw_calc_min_cdclk()

[Lisovskiy, Stanislav]

On Tue, Jan 18, 2022 at 11:23:50AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> intel_bw_calc_min_cdclk() is entirely pointless. All it manages to do is
> somehow conflate the per-pipe min cdclk with dbuf min cdclk. There is no
> (at least documented) dbuf min cdclk limit on pre-skl so let's just get
> rid of all this confusion.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

I think we constantly have a bit contradictional attitude towards such situation.
From one perspective you can say, that those kind of "leagcy" callbacks are
pointless, from the other hand one might say. that we need to have a unified
approach for all platforms and I think we got, some legacy handlers for old
platforms for similar purpose as well.
I'm fine with both approaches, however for example when I was submitting
that patch, I was asked by reviewer to add this kind of legacy callback, so that we have
a "uniform" approach.
We just then need to have some standard agreement on those, which doesn't
depend on today's cosmic radiation levels :)

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>


> ---
>  drivers/gpu/drm/i915/display/intel_bw.c    | 49 ++--------------------
>  drivers/gpu/drm/i915/display/intel_bw.h    |  1 -
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 31 +-------------
>  3 files changed, 5 insertions(+), 76 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 93feab671c29..a3f169686f14 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -715,7 +715,7 @@ static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state,
>  	}
>  }
>  
> -int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
> +int intel_bw_calc_min_cdclk(struct intel_atomic_state *state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>  	struct intel_bw_state *new_bw_state = NULL;
> @@ -726,6 +726,9 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
>  	enum pipe pipe;
>  	int i;
>  
> +	if (DISPLAY_VER(dev_priv) < 9)
> +		return 0;
> +
>  	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
>  		new_bw_state = intel_atomic_get_bw_state(state);
>  		if (IS_ERR(new_bw_state))
> @@ -770,50 +773,6 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
>  	return 0;
>  }
>  
> -int intel_bw_calc_min_cdclk(struct intel_atomic_state *state)
> -{
> -	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> -	struct intel_bw_state *new_bw_state = NULL;
> -	struct intel_bw_state *old_bw_state = NULL;
> -	const struct intel_crtc_state *crtc_state;
> -	struct intel_crtc *crtc;
> -	int min_cdclk = 0;
> -	enum pipe pipe;
> -	int i;
> -
> -	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> -		new_bw_state = intel_atomic_get_bw_state(state);
> -		if (IS_ERR(new_bw_state))
> -			return PTR_ERR(new_bw_state);
> -
> -		old_bw_state = intel_atomic_get_old_bw_state(state);
> -	}
> -
> -	if (!old_bw_state)
> -		return 0;
> -
> -	for_each_pipe(dev_priv, pipe) {
> -		struct intel_cdclk_state *cdclk_state;
> -
> -		cdclk_state = intel_atomic_get_new_cdclk_state(state);
> -		if (!cdclk_state)
> -			return 0;
> -
> -		min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk);
> -	}
> -
> -	new_bw_state->min_cdclk = min_cdclk;
> -
> -	if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) {
> -		int ret = intel_atomic_lock_global_state(&new_bw_state->base);
> -
> -		if (ret)
> -			return ret;
> -	}
> -
> -	return 0;
> -}
> -
>  int intel_bw_atomic_check(struct intel_atomic_state *state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> index 46c6eecbd917..57eb755d298a 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.h
> +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> @@ -65,6 +65,5 @@ void intel_bw_crtc_update(struct intel_bw_state *bw_state,
>  int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
>  				  u32 points_mask);
>  int intel_bw_calc_min_cdclk(struct intel_atomic_state *state);
> -int skl_bw_calc_min_cdclk(struct intel_atomic_state *state);
>  
>  #endif /* __INTEL_BW_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 7e20967307df..078dc6e1ee34 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -70,7 +70,6 @@ struct intel_cdclk_funcs {
>  	void (*set_cdclk)(struct drm_i915_private *i915,
>  			  const struct intel_cdclk_config *cdclk_config,
>  			  enum pipe pipe);
> -	int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
>  	int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
>  	u8 (*calc_voltage_level)(int cdclk);
>  };
> @@ -81,12 +80,6 @@ void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
>  	dev_priv->cdclk_funcs->get_cdclk(dev_priv, cdclk_config);
>  }
>  
> -static int intel_cdclk_bw_calc_min_cdclk(struct intel_atomic_state *state)
> -{
> -	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> -	return dev_priv->cdclk_funcs->bw_calc_min_cdclk(state);
> -}
> -
>  static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv,
>  				  const struct intel_cdclk_config *cdclk_config,
>  				  enum pipe pipe)
> @@ -2680,7 +2673,7 @@ int intel_cdclk_atomic_check(struct intel_atomic_state *state,
>  	    old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)
>  		*need_cdclk_calc = true;
>  
> -	ret = intel_cdclk_bw_calc_min_cdclk(state);
> +	ret = intel_bw_calc_min_cdclk(state);
>  	if (ret)
>  		return ret;
>  
> @@ -3069,7 +3062,6 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
>  static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
>  	.get_cdclk = bxt_get_cdclk,
>  	.set_cdclk = bxt_set_cdclk,
> -	.bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
>  	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
>  	.calc_voltage_level = tgl_calc_voltage_level,
>  };
> @@ -3077,7 +3069,6 @@ static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
>  static const struct intel_cdclk_funcs ehl_cdclk_funcs = {
>  	.get_cdclk = bxt_get_cdclk,
>  	.set_cdclk = bxt_set_cdclk,
> -	.bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
>  	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
>  	.calc_voltage_level = ehl_calc_voltage_level,
>  };
> @@ -3085,7 +3076,6 @@ static const struct intel_cdclk_funcs ehl_cdclk_funcs = {
>  static const struct intel_cdclk_funcs icl_cdclk_funcs = {
>  	.get_cdclk = bxt_get_cdclk,
>  	.set_cdclk = bxt_set_cdclk,
> -	.bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
>  	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
>  	.calc_voltage_level = icl_calc_voltage_level,
>  };
> @@ -3093,7 +3083,6 @@ static const struct intel_cdclk_funcs icl_cdclk_funcs = {
>  static const struct intel_cdclk_funcs bxt_cdclk_funcs = {
>  	.get_cdclk = bxt_get_cdclk,
>  	.set_cdclk = bxt_set_cdclk,
> -	.bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
>  	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
>  	.calc_voltage_level = bxt_calc_voltage_level,
>  };
> @@ -3101,53 +3090,45 @@ static const struct intel_cdclk_funcs bxt_cdclk_funcs = {
>  static const struct intel_cdclk_funcs skl_cdclk_funcs = {
>  	.get_cdclk = skl_get_cdclk,
>  	.set_cdclk = skl_set_cdclk,
> -	.bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
>  	.modeset_calc_cdclk = skl_modeset_calc_cdclk,
>  };
>  
>  static const struct intel_cdclk_funcs bdw_cdclk_funcs = {
>  	.get_cdclk = bdw_get_cdclk,
>  	.set_cdclk = bdw_set_cdclk,
> -	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
>  	.modeset_calc_cdclk = bdw_modeset_calc_cdclk,
>  };
>  
>  static const struct intel_cdclk_funcs chv_cdclk_funcs = {
>  	.get_cdclk = vlv_get_cdclk,
>  	.set_cdclk = chv_set_cdclk,
> -	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
>  	.modeset_calc_cdclk = vlv_modeset_calc_cdclk,
>  };
>  
>  static const struct intel_cdclk_funcs vlv_cdclk_funcs = {
>  	.get_cdclk = vlv_get_cdclk,
>  	.set_cdclk = vlv_set_cdclk,
> -	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
>  	.modeset_calc_cdclk = vlv_modeset_calc_cdclk,
>  };
>  
>  static const struct intel_cdclk_funcs hsw_cdclk_funcs = {
>  	.get_cdclk = hsw_get_cdclk,
> -	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
>  	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
>  };
>  
>  /* SNB, IVB, 965G, 945G */
>  static const struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = {
>  	.get_cdclk = fixed_400mhz_get_cdclk,
> -	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
>  	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
>  };
>  
>  static const struct intel_cdclk_funcs ilk_cdclk_funcs = {
>  	.get_cdclk = fixed_450mhz_get_cdclk,
> -	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
>  	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
>  };
>  
>  static const struct intel_cdclk_funcs gm45_cdclk_funcs = {
>  	.get_cdclk = gm45_get_cdclk,
> -	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
>  	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
>  };
>  
> @@ -3155,7 +3136,6 @@ static const struct intel_cdclk_funcs gm45_cdclk_funcs = {
>  
>  static const struct intel_cdclk_funcs i965gm_cdclk_funcs = {
>  	.get_cdclk = i965gm_get_cdclk,
> -	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
>  	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
>  };
>  
> @@ -3163,19 +3143,16 @@ static const struct intel_cdclk_funcs i965gm_cdclk_funcs = {
>  
>  static const struct intel_cdclk_funcs pnv_cdclk_funcs = {
>  	.get_cdclk = pnv_get_cdclk,
> -	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
>  	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
>  };
>  
>  static const struct intel_cdclk_funcs g33_cdclk_funcs = {
>  	.get_cdclk = g33_get_cdclk,
> -	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
>  	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
>  };
>  
>  static const struct intel_cdclk_funcs i945gm_cdclk_funcs = {
>  	.get_cdclk = i945gm_get_cdclk,
> -	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
>  	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
>  };
>  
> @@ -3183,37 +3160,31 @@ static const struct intel_cdclk_funcs i945gm_cdclk_funcs = {
>  
>  static const struct intel_cdclk_funcs i915gm_cdclk_funcs = {
>  	.get_cdclk = i915gm_get_cdclk,
> -	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
>  	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
>  };
>  
>  static const struct intel_cdclk_funcs i915g_cdclk_funcs = {
>  	.get_cdclk = fixed_333mhz_get_cdclk,
> -	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
>  	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
>  };
>  
>  static const struct intel_cdclk_funcs i865g_cdclk_funcs = {
>  	.get_cdclk = fixed_266mhz_get_cdclk,
> -	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
>  	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
>  };
>  
>  static const struct intel_cdclk_funcs i85x_cdclk_funcs = {
>  	.get_cdclk = i85x_get_cdclk,
> -	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
>  	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
>  };
>  
>  static const struct intel_cdclk_funcs i845g_cdclk_funcs = {
>  	.get_cdclk = fixed_200mhz_get_cdclk,
> -	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
>  	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
>  };
>  
>  static const struct intel_cdclk_funcs i830_cdclk_funcs = {
>  	.get_cdclk = fixed_133mhz_get_cdclk,
> -	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
>  	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
>  };
>  
> -- 
> 2.32.0
> 

Re: [Intel-gfx] [PATCH 11/15] drm/i915: Nuke intel_bw_calc_min_cdclk()

[Ville Syrjälä]

On Tue, Feb 01, 2022 at 10:52:39AM +0200, Lisovskiy, Stanislav wrote:
> On Tue, Jan 18, 2022 at 11:23:50AM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > intel_bw_calc_min_cdclk() is entirely pointless. All it manages to do is
> > somehow conflate the per-pipe min cdclk with dbuf min cdclk. There is no
> > (at least documented) dbuf min cdclk limit on pre-skl so let's just get
> > rid of all this confusion.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> I think we constantly have a bit contradictional attitude towards such situation.
> >From one perspective you can say, that those kind of "leagcy" callbacks are
> pointless, from the other hand one might say. that we need to have a unified
> approach for all platforms and I think we got, some legacy handlers for old
> platforms for similar purpose as well.
> I'm fine with both approaches, however for example when I was submitting
> that patch, I was asked by reviewer to add this kind of legacy callback, so that we have
> a "uniform" approach.
> We just then need to have some standard agreement on those, which doesn't
> depend on today's cosmic radiation levels :)

Yes in general I prefer a unified approach across all platforms.
But in this case there is nothing to do for the old platforms as they
don't have any kind of dbuf cdclk limit, or if there is one we don't
know what it is since it's not documented.

So the only thing the code was really doing was conflating the
per-pipe cdclk limit (which is handled elsewhere for all platforms
in a  unified fashion) with something that doesn't even exist.

Also I don't think it was even correct anyway since it was
using the per-pipe cdclk_state->min_cdclk[] already during
intel_cdclk_atomic_check(), but cdclk_state->min_cdclk[]
isn't even computed until intel_modeset_calc_cdclk() which 
is called later. So I guess it was basically just computing 
the max of the min_cdclk[] for all the pipes for the _old_
state, not the new state.

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH 11/15] drm/i915: Nuke intel_bw_calc_min_cdclk()

[Lisovskiy, Stanislav]

On Tue, Feb 01, 2022 at 12:05:13PM +0200, Ville Syrjälä wrote:
> On Tue, Feb 01, 2022 at 10:52:39AM +0200, Lisovskiy, Stanislav wrote:
> > On Tue, Jan 18, 2022 at 11:23:50AM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > intel_bw_calc_min_cdclk() is entirely pointless. All it manages to do is
> > > somehow conflate the per-pipe min cdclk with dbuf min cdclk. There is no
> > > (at least documented) dbuf min cdclk limit on pre-skl so let's just get
> > > rid of all this confusion.
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > I think we constantly have a bit contradictional attitude towards such situation.
> > >From one perspective you can say, that those kind of "leagcy" callbacks are
> > pointless, from the other hand one might say. that we need to have a unified
> > approach for all platforms and I think we got, some legacy handlers for old
> > platforms for similar purpose as well.
> > I'm fine with both approaches, however for example when I was submitting
> > that patch, I was asked by reviewer to add this kind of legacy callback, so that we have
> > a "uniform" approach.
> > We just then need to have some standard agreement on those, which doesn't
> > depend on today's cosmic radiation levels :)
> 
> Yes in general I prefer a unified approach across all platforms.
> But in this case there is nothing to do for the old platforms as they
> don't have any kind of dbuf cdclk limit, or if there is one we don't
> know what it is since it's not documented.
> 
> So the only thing the code was really doing was conflating the
> per-pipe cdclk limit (which is handled elsewhere for all platforms
> in a  unified fashion) with something that doesn't even exist.
> 
> Also I don't think it was even correct anyway since it was
> using the per-pipe cdclk_state->min_cdclk[] already during
> intel_cdclk_atomic_check(), but cdclk_state->min_cdclk[]
> isn't even computed until intel_modeset_calc_cdclk() which 
> is called later. So I guess it was basically just computing 
> the max of the min_cdclk[] for all the pipes for the _old_
> state, not the new state.

No, I think actually the idea was that it was first calculating
new_bw_state->min_cdclk, based on plane and dbuf bandwidth requirements
in intel_atomic_check_cdclk, however then the final decision which
cdclk to choose was is done in intel_cdclk.c, which calculated new_cdclk_state->min_cdclk
and then we just choose maximum of those.
And intel_compute_min_cdclk is the final arbiter:

static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
{
        struct intel_atomic_state *state = cdclk_state->base.state;
        struct drm_i915_private *dev_priv = to_i915(state->base.dev);
        struct intel_bw_state *bw_state = NULL;
        struct intel_crtc *crtc;
        struct intel_crtc_state *crtc_state;
        int min_cdclk, i;
        enum pipe pipe;

        for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
                int ret;

                min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
                if (min_cdclk < 0)
                        return min_cdclk;

                bw_state = intel_atomic_get_bw_state(state);
                if (IS_ERR(bw_state))
                        return PTR_ERR(bw_state);

                if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk)
                        continue;

                cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;

                ret = intel_atomic_lock_global_state(&cdclk_state->base);
                if (ret)
                        return ret;
        }

        min_cdclk = cdclk_state->force_min_cdclk;
        for_each_pipe(dev_priv, pipe) {
                min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk);

                if (!bw_state)
                        continue;

                min_cdclk = max(bw_state->min_cdclk, min_cdclk);
        }

        return min_cdclk;
}

Stan

> 
> -- 
> Ville Syrjälä
> Intel

Re: [Intel-gfx] [PATCH 11/15] drm/i915: Nuke intel_bw_calc_min_cdclk()

[Ville Syrjälä]

On Tue, Feb 01, 2022 at 01:18:18PM +0200, Lisovskiy, Stanislav wrote:
> On Tue, Feb 01, 2022 at 12:05:13PM +0200, Ville Syrjälä wrote:
> > On Tue, Feb 01, 2022 at 10:52:39AM +0200, Lisovskiy, Stanislav wrote:
> > > On Tue, Jan 18, 2022 at 11:23:50AM +0200, Ville Syrjala wrote:
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > 
> > > > intel_bw_calc_min_cdclk() is entirely pointless. All it manages to do is
> > > > somehow conflate the per-pipe min cdclk with dbuf min cdclk. There is no
> > > > (at least documented) dbuf min cdclk limit on pre-skl so let's just get
> > > > rid of all this confusion.
> > > > 
> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > I think we constantly have a bit contradictional attitude towards such situation.
> > > >From one perspective you can say, that those kind of "leagcy" callbacks are
> > > pointless, from the other hand one might say. that we need to have a unified
> > > approach for all platforms and I think we got, some legacy handlers for old
> > > platforms for similar purpose as well.
> > > I'm fine with both approaches, however for example when I was submitting
> > > that patch, I was asked by reviewer to add this kind of legacy callback, so that we have
> > > a "uniform" approach.
> > > We just then need to have some standard agreement on those, which doesn't
> > > depend on today's cosmic radiation levels :)
> > 
> > Yes in general I prefer a unified approach across all platforms.
> > But in this case there is nothing to do for the old platforms as they
> > don't have any kind of dbuf cdclk limit, or if there is one we don't
> > know what it is since it's not documented.
> > 
> > So the only thing the code was really doing was conflating the
> > per-pipe cdclk limit (which is handled elsewhere for all platforms
> > in a  unified fashion) with something that doesn't even exist.
> > 
> > Also I don't think it was even correct anyway since it was
> > using the per-pipe cdclk_state->min_cdclk[] already during
> > intel_cdclk_atomic_check(), but cdclk_state->min_cdclk[]
> > isn't even computed until intel_modeset_calc_cdclk() which 
> > is called later. So I guess it was basically just computing 
> > the max of the min_cdclk[] for all the pipes for the _old_
> > state, not the new state.
> 
> No, I think actually the idea was that it was first calculating
> new_bw_state->min_cdclk, based on plane and dbuf bandwidth requirements
> in intel_atomic_check_cdclk,

Well intel_bw_calc_min_cdclk() did none of that. Like I said it
just took the max of the _old_ per-pipe cdclk_state->min_cdclk[]
values and stored that as the *new* bw min cdclk, which later
would get consulted by intel_compute_min_cdclk().

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH 11/15] drm/i915: Nuke intel_bw_calc_min_cdclk()

[Lisovskiy, Stanislav]

On Tue, Feb 01, 2022 at 03:45:35PM +0200, Ville Syrjälä wrote:
> On Tue, Feb 01, 2022 at 01:18:18PM +0200, Lisovskiy, Stanislav wrote:
> > On Tue, Feb 01, 2022 at 12:05:13PM +0200, Ville Syrjälä wrote:
> > > On Tue, Feb 01, 2022 at 10:52:39AM +0200, Lisovskiy, Stanislav wrote:
> > > > On Tue, Jan 18, 2022 at 11:23:50AM +0200, Ville Syrjala wrote:
> > > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > > 
> > > > > intel_bw_calc_min_cdclk() is entirely pointless. All it manages to do is
> > > > > somehow conflate the per-pipe min cdclk with dbuf min cdclk. There is no
> > > > > (at least documented) dbuf min cdclk limit on pre-skl so let's just get
> > > > > rid of all this confusion.
> > > > > 
> > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > 
> > > > I think we constantly have a bit contradictional attitude towards such situation.
> > > > >From one perspective you can say, that those kind of "leagcy" callbacks are
> > > > pointless, from the other hand one might say. that we need to have a unified
> > > > approach for all platforms and I think we got, some legacy handlers for old
> > > > platforms for similar purpose as well.
> > > > I'm fine with both approaches, however for example when I was submitting
> > > > that patch, I was asked by reviewer to add this kind of legacy callback, so that we have
> > > > a "uniform" approach.
> > > > We just then need to have some standard agreement on those, which doesn't
> > > > depend on today's cosmic radiation levels :)
> > > 
> > > Yes in general I prefer a unified approach across all platforms.
> > > But in this case there is nothing to do for the old platforms as they
> > > don't have any kind of dbuf cdclk limit, or if there is one we don't
> > > know what it is since it's not documented.
> > > 
> > > So the only thing the code was really doing was conflating the
> > > per-pipe cdclk limit (which is handled elsewhere for all platforms
> > > in a  unified fashion) with something that doesn't even exist.
> > > 
> > > Also I don't think it was even correct anyway since it was
> > > using the per-pipe cdclk_state->min_cdclk[] already during
> > > intel_cdclk_atomic_check(), but cdclk_state->min_cdclk[]
> > > isn't even computed until intel_modeset_calc_cdclk() which 
> > > is called later. So I guess it was basically just computing 
> > > the max of the min_cdclk[] for all the pipes for the _old_
> > > state, not the new state.
> > 
> > No, I think actually the idea was that it was first calculating
> > new_bw_state->min_cdclk, based on plane and dbuf bandwidth requirements
> > in intel_atomic_check_cdclk,
> 
> Well intel_bw_calc_min_cdclk() did none of that. Like I said it
> just took the max of the _old_ per-pipe cdclk_state->min_cdclk[]
> values and stored that as the *new* bw min cdclk, which later
> would get consulted by intel_compute_min_cdclk().

Yeah, because it was a stub basically just for "uniformity".

Stan


> 
> -- 
> Ville Syrjälä
> Intel