* [Intel-gfx] [PATCH 0/4] Async flip optimization for DG2
@ 2022-01-18 10:48 Stanislav Lisovskiy
2022-01-18 10:48 ` [Intel-gfx] [PATCH 1/4] drm/i915: Pass plane to watermark calculation functions Stanislav Lisovskiy
` (10 more replies)
0 siblings, 11 replies; 32+ messages in thread
From: Stanislav Lisovskiy @ 2022-01-18 10:48 UTC (permalink / raw)
To: intel-gfx
Limitting the WM levels to 0 for DG2 during async flips,
allows to slightly increase the perfomance, as recommended
by HW team.
Stanislav Lisovskiy (4):
drm/i915: Pass plane to watermark calculation functions
drm/i915: Introduce do_async_flip flag to intel_plane_state
drm/i915: Use wm0 only during async flips for DG2
drm/i915: Don't allocate extra ddb during async flip for DG2
.../gpu/drm/i915/display/intel_atomic_plane.c | 4 +-
.../gpu/drm/i915/display/intel_atomic_plane.h | 3 +
drivers/gpu/drm/i915/display/intel_display.c | 15 ++++
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/intel_pm.c | 69 +++++++++++++++----
5 files changed, 77 insertions(+), 17 deletions(-)
--
2.24.1.485.gad05a3d8e5
^ permalink raw reply [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 1/4] drm/i915: Pass plane to watermark calculation functions
2022-01-18 10:48 [Intel-gfx] [PATCH 0/4] Async flip optimization for DG2 Stanislav Lisovskiy
@ 2022-01-18 10:48 ` Stanislav Lisovskiy
2022-01-19 11:26 ` Ville Syrjälä
2022-01-18 10:48 ` [Intel-gfx] [PATCH 2/4] drm/i915: Introduce do_async_flip flag to intel_plane_state Stanislav Lisovskiy
` (9 subsequent siblings)
10 siblings, 1 reply; 32+ messages in thread
From: Stanislav Lisovskiy @ 2022-01-18 10:48 UTC (permalink / raw)
To: intel-gfx
Sometimes we might need to change the way we calculate
watermarks, based on which particular plane it is calculated
for. Thus it would be convenient to pass plane struct to those
functions.
v2: Pass plane instead of plane_id
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 2 +-
.../gpu/drm/i915/display/intel_atomic_plane.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 23 +++++++++++++------
3 files changed, 20 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index c2c512cd8ec0..d1344e9c06de 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -373,7 +373,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
old_plane_state, new_plane_state);
}
-static struct intel_plane *
+struct intel_plane *
intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id)
{
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index 7907f601598e..c1499bb7370e 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -16,10 +16,13 @@ struct intel_crtc;
struct intel_crtc_state;
struct intel_plane;
struct intel_plane_state;
+enum plane_id;
unsigned int intel_adjusted_rate(const struct drm_rect *src,
const struct drm_rect *dst,
unsigned int rate);
+struct intel_plane *intel_crtc_get_plane(struct intel_crtc *crtc,
+ enum plane_id plane_id);
unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 62fde21fac39..dc1203d21c46 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4252,7 +4252,9 @@ static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
u64 modifier, unsigned int rotation,
u32 plane_pixel_rate, struct skl_wm_params *wp,
int color_plane);
+
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
+ const struct intel_plane *plane,
int level,
unsigned int latency,
const struct skl_wm_params *wp,
@@ -4261,6 +4263,7 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
static unsigned int
skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
+ const struct intel_plane *plane,
int num_active)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
@@ -4279,7 +4282,7 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
for (level = 0; level <= max_level; level++) {
unsigned int latency = dev_priv->wm.skl_latency[level];
- skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
+ skl_compute_plane_wm(crtc_state, plane, level, latency, &wp, &wm, &wm);
if (wm.min_ddb_alloc == U16_MAX)
break;
@@ -5124,6 +5127,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
intel_atomic_get_new_crtc_state(state, crtc);
const struct intel_dbuf_state *dbuf_state =
intel_atomic_get_new_dbuf_state(state);
+ const struct intel_plane *cursor_plane = intel_crtc_get_plane(crtc, PLANE_CURSOR);
const struct skl_ddb_entry *alloc = &dbuf_state->ddb[crtc->pipe];
int num_active = hweight8(dbuf_state->active_pipes);
u16 alloc_size, start = 0;
@@ -5153,7 +5157,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
return 0;
/* Allocate fixed number of blocks for cursor. */
- total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
+ total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, cursor_plane, num_active);
alloc_size -= total[PLANE_CURSOR];
crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].start =
alloc->end - total[PLANE_CURSOR];
@@ -5507,6 +5511,7 @@ static int skl_wm_max_lines(struct drm_i915_private *dev_priv)
}
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
+ const struct intel_plane *plane,
int level,
unsigned int latency,
const struct skl_wm_params *wp,
@@ -5634,6 +5639,7 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
static void
skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
+ const struct intel_plane *plane,
const struct skl_wm_params *wm_params,
struct skl_wm_level *levels)
{
@@ -5645,7 +5651,7 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
struct skl_wm_level *result = &levels[level];
unsigned int latency = dev_priv->wm.skl_latency[level];
- skl_compute_plane_wm(crtc_state, level, latency,
+ skl_compute_plane_wm(crtc_state, plane, level, latency,
wm_params, result_prev, result);
result_prev = result;
@@ -5653,6 +5659,7 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
}
static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
+ const struct intel_plane *plane,
const struct skl_wm_params *wm_params,
struct skl_plane_wm *plane_wm)
{
@@ -5661,7 +5668,7 @@ static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
struct skl_wm_level *levels = plane_wm->wm;
unsigned int latency = dev_priv->wm.skl_latency[0] + dev_priv->sagv_block_time_us;
- skl_compute_plane_wm(crtc_state, 0, latency,
+ skl_compute_plane_wm(crtc_state, plane, 0, latency,
wm_params, &levels[0],
sagv_wm);
}
@@ -5736,6 +5743,7 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct skl_wm_params wm_params;
int ret;
@@ -5744,13 +5752,13 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
+ skl_compute_wm_levels(crtc_state, plane, &wm_params, wm->wm);
skl_compute_transition_wm(dev_priv, &wm->trans_wm,
&wm->wm[0], &wm_params);
if (DISPLAY_VER(dev_priv) >= 12) {
- tgl_compute_sagv_wm(crtc_state, &wm_params, wm);
+ tgl_compute_sagv_wm(crtc_state, plane, &wm_params, wm);
skl_compute_transition_wm(dev_priv, &wm->sagv.trans_wm,
&wm->sagv.wm0, &wm_params);
@@ -5764,6 +5772,7 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
enum plane_id plane_id)
{
struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct skl_wm_params wm_params;
int ret;
@@ -5775,7 +5784,7 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
+ skl_compute_wm_levels(crtc_state, plane, &wm_params, wm->uv_wm);
return 0;
}
--
2.24.1.485.gad05a3d8e5
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 2/4] drm/i915: Introduce do_async_flip flag to intel_plane_state
2022-01-18 10:48 [Intel-gfx] [PATCH 0/4] Async flip optimization for DG2 Stanislav Lisovskiy
2022-01-18 10:48 ` [Intel-gfx] [PATCH 1/4] drm/i915: Pass plane to watermark calculation functions Stanislav Lisovskiy
@ 2022-01-18 10:48 ` Stanislav Lisovskiy
2022-01-19 11:35 ` Ville Syrjälä
2022-01-18 10:48 ` [Intel-gfx] [PATCH 3/4] drm/i915: Use wm0 only during async flips for DG2 Stanislav Lisovskiy
` (8 subsequent siblings)
10 siblings, 1 reply; 32+ messages in thread
From: Stanislav Lisovskiy @ 2022-01-18 10:48 UTC (permalink / raw)
To: intel-gfx
There might be various logical contructs when we might want
to enable async flip, so lets calculate those and set this
flag, so that there is no need in long conditions in other
places.
v2: - Set do_async_flip flag to False, if no async flip needed.
Lets not rely that it will be 0-initialized, but set
explicitly, so that the logic is clear as well.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 5 +++++
drivers/gpu/drm/i915/display/intel_display_types.h | 3 +++
3 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index d1344e9c06de..87bad665a2c8 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -491,7 +491,7 @@ void intel_plane_update_arm(struct intel_plane *plane,
trace_intel_plane_update_arm(&plane->base, crtc);
- if (crtc_state->uapi.async_flip && plane->async_flip)
+ if (plane_state->do_async_flip)
plane->async_flip(plane, crtc_state, plane_state, true);
else
plane->update_arm(plane, crtc_state, plane_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0964b2403e2d..f3ce29c42bc3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5027,6 +5027,11 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
needs_scaling(new_plane_state))))
new_crtc_state->disable_lp_wm = true;
+ if (new_crtc_state->uapi.async_flip && plane->async_flip)
+ new_plane_state->do_async_flip = true;
+ else
+ new_plane_state->do_async_flip = false;
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 41e3dd25a78f..6b107872ad39 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -634,6 +634,9 @@ struct intel_plane_state {
struct intel_fb_view view;
+ /* Indicates if async flip is required */
+ bool do_async_flip;
+
/* Plane pxp decryption state */
bool decrypt;
--
2.24.1.485.gad05a3d8e5
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 3/4] drm/i915: Use wm0 only during async flips for DG2
2022-01-18 10:48 [Intel-gfx] [PATCH 0/4] Async flip optimization for DG2 Stanislav Lisovskiy
2022-01-18 10:48 ` [Intel-gfx] [PATCH 1/4] drm/i915: Pass plane to watermark calculation functions Stanislav Lisovskiy
2022-01-18 10:48 ` [Intel-gfx] [PATCH 2/4] drm/i915: Introduce do_async_flip flag to intel_plane_state Stanislav Lisovskiy
@ 2022-01-18 10:48 ` Stanislav Lisovskiy
2022-01-19 11:51 ` Ville Syrjälä
2022-01-18 10:48 ` [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip " Stanislav Lisovskiy
` (7 subsequent siblings)
10 siblings, 1 reply; 32+ messages in thread
From: Stanislav Lisovskiy @ 2022-01-18 10:48 UTC (permalink / raw)
To: intel-gfx
This optimization allows to achieve higher perfomance
during async flips.
For the first async flip we have to still temporarily
switch to sync flip, in order to reprogram plane
watermarks, so this requires taking into account
old plane state's do_async_flip flag.
v2: - Removed redundant new_plane_state->do_async_flip
check from needs_async_flip_wm_override condition
(Ville Syrjälä)
- Extract dg2_async_flip_optimization to separate
function(Ville Syrjälä)
- Check for plane->async_flip instead of plane_id
(Ville Syrjälä)
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 12 +++++++++++-
drivers/gpu/drm/i915/intel_pm.c | 12 +++++++++++-
2 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f3ce29c42bc3..9a5126310014 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4908,6 +4908,15 @@ static bool needs_scaling(const struct intel_plane_state *state)
return (src_w != dst_w || src_h != dst_h);
}
+static bool needs_async_flip_wm_override(struct intel_plane *plane,
+ const struct intel_plane_state *new_plane_state,
+ const struct intel_plane_state *old_plane_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+
+ return DISPLAY_VER(dev_priv) >= 13 && !old_plane_state->do_async_flip;
+}
+
int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
struct intel_crtc_state *new_crtc_state,
const struct intel_plane_state *old_plane_state,
@@ -5027,7 +5036,8 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
needs_scaling(new_plane_state))))
new_crtc_state->disable_lp_wm = true;
- if (new_crtc_state->uapi.async_flip && plane->async_flip)
+ if (new_crtc_state->uapi.async_flip &&
+ !needs_async_flip_wm_override(plane, new_plane_state, old_plane_state))
new_plane_state->do_async_flip = true;
else
new_plane_state->do_async_flip = false;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index dc1203d21c46..5d350ddc447f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5510,6 +5510,15 @@ static int skl_wm_max_lines(struct drm_i915_private *dev_priv)
return 31;
}
+bool dg2_async_flip_optimization(struct drm_i915_private *i915,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane *plane)
+{
+ return DISPLAY_VER(i915) >= 13 &&
+ crtc_state->uapi.async_flip &&
+ plane->async_flip;
+}
+
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
const struct intel_plane *plane,
int level,
@@ -5523,7 +5532,8 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
uint_fixed_16_16_t selected_result;
u32 blocks, lines, min_ddb_alloc = 0;
- if (latency == 0) {
+ if (latency == 0 ||
+ (dg2_async_flip_optimization(dev_priv, crtc_state, plane) && level > 0)) {
/* reject it */
result->min_ddb_alloc = U16_MAX;
return;
--
2.24.1.485.gad05a3d8e5
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip for DG2
2022-01-18 10:48 [Intel-gfx] [PATCH 0/4] Async flip optimization for DG2 Stanislav Lisovskiy
` (2 preceding siblings ...)
2022-01-18 10:48 ` [Intel-gfx] [PATCH 3/4] drm/i915: Use wm0 only during async flips for DG2 Stanislav Lisovskiy
@ 2022-01-18 10:48 ` Stanislav Lisovskiy
2022-01-19 11:59 ` Ville Syrjälä
2022-01-18 12:28 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Async flip optimization " Patchwork
` (6 subsequent siblings)
10 siblings, 1 reply; 32+ messages in thread
From: Stanislav Lisovskiy @ 2022-01-18 10:48 UTC (permalink / raw)
To: intel-gfx
In terms of async flip optimization we don't to allocate
extra ddb space, so lets skip it.
v2: - Extracted min ddb async flip check to separate function
(Ville Syrjälä)
- Used this function to prevent false positive WARN
to be triggered(Ville Syrjälä)
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 34 ++++++++++++++++++++++++++-------
1 file changed, 27 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5d350ddc447f..4922c9108f08 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5118,6 +5118,12 @@ static bool icl_need_wm1_wa(struct drm_i915_private *i915,
(IS_DISPLAY_VER(i915, 12, 13) && plane_id == PLANE_CURSOR);
}
+static bool dg2_need_min_ddb(struct drm_i915_private *i915,
+ struct intel_crtc_state *crtc_state)
+{
+ return IS_DG2(i915) && crtc_state->uapi.async_flip;
+}
+
static int
skl_allocate_plane_ddb(struct intel_atomic_state *state,
struct intel_crtc *crtc)
@@ -5226,9 +5232,15 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
break;
rate = crtc_state->plane_data_rate[plane_id];
- extra = min_t(u16, alloc_size,
- DIV64_U64_ROUND_UP(alloc_size * rate,
- total_data_rate));
+
+ if (dg2_need_min_ddb(dev_priv, crtc_state)) {
+ extra = 0;
+ } else {
+ extra = min_t(u16, alloc_size,
+ DIV64_U64_ROUND_UP(alloc_size * rate,
+ total_data_rate));
+ }
+
total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
alloc_size -= extra;
total_data_rate -= rate;
@@ -5237,14 +5249,22 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
break;
rate = crtc_state->uv_plane_data_rate[plane_id];
- extra = min_t(u16, alloc_size,
- DIV64_U64_ROUND_UP(alloc_size * rate,
- total_data_rate));
+
+ if (dg2_need_min_ddb(dev_priv, crtc_state)) {
+ extra = 0;
+ } else {
+ extra = min_t(u16, alloc_size,
+ DIV64_U64_ROUND_UP(alloc_size * rate,
+ total_data_rate));
+ }
+
uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
alloc_size -= extra;
total_data_rate -= rate;
}
- drm_WARN_ON(&dev_priv->drm, alloc_size != 0 || total_data_rate != 0);
+
+ if (!dg2_need_min_ddb(dev_priv, crtc_state))
+ drm_WARN_ON(&dev_priv->drm, alloc_size != 0 || total_data_rate != 0);
/* Set the actual DDB start/end points for each plane */
start = alloc->start;
--
2.24.1.485.gad05a3d8e5
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Async flip optimization for DG2
2022-01-18 10:48 [Intel-gfx] [PATCH 0/4] Async flip optimization for DG2 Stanislav Lisovskiy
` (3 preceding siblings ...)
2022-01-18 10:48 ` [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip " Stanislav Lisovskiy
@ 2022-01-18 12:28 ` Patchwork
2022-01-18 12:28 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (5 subsequent siblings)
10 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2022-01-18 12:28 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Async flip optimization for DG2
URL : https://patchwork.freedesktop.org/series/98981/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b3d8c1a22c8c drm/i915: Pass plane to watermark calculation functions
16735b01eebb drm/i915: Introduce do_async_flip flag to intel_plane_state
44bbf14d7cbb drm/i915: Use wm0 only during async flips for DG2
-:9: WARNING:TYPO_SPELLING: 'perfomance' may be misspelled - perhaps 'performance'?
#9:
This optimization allows to achieve higher perfomance
^^^^^^^^^^
total: 0 errors, 1 warnings, 0 checks, 48 lines checked
3602601138fc drm/i915: Don't allocate extra ddb during async flip for DG2
^ permalink raw reply [flat|nested] 32+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Async flip optimization for DG2
2022-01-18 10:48 [Intel-gfx] [PATCH 0/4] Async flip optimization for DG2 Stanislav Lisovskiy
` (4 preceding siblings ...)
2022-01-18 12:28 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Async flip optimization " Patchwork
@ 2022-01-18 12:28 ` Patchwork
2022-01-18 13:03 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
` (4 subsequent siblings)
10 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2022-01-18 12:28 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Async flip optimization for DG2
URL : https://patchwork.freedesktop.org/series/98981/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/intel_pm.c:5533:6: warning: symbol 'dg2_async_flip_optimization' was not declared. Should it be static?
^ permalink raw reply [flat|nested] 32+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for Async flip optimization for DG2
2022-01-18 10:48 [Intel-gfx] [PATCH 0/4] Async flip optimization for DG2 Stanislav Lisovskiy
` (5 preceding siblings ...)
2022-01-18 12:28 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2022-01-18 13:03 ` Patchwork
2022-01-18 14:00 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Async flip optimization for DG2 (rev2) Patchwork
` (3 subsequent siblings)
10 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2022-01-18 13:03 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 9792 bytes --]
== Series Details ==
Series: Async flip optimization for DG2
URL : https://patchwork.freedesktop.org/series/98981/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11094 -> Patchwork_22013
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_22013 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22013, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22013/index.html
Participating hosts (46 -> 42)
------------------------------
Additional (2): fi-kbl-soraka fi-icl-u2
Missing (6): shard-tglu fi-tgl-dsi fi-bsw-cyan shard-rkl shard-dg1 fi-bdw-samus
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22013:
### IGT changes ###
#### Possible regressions ####
* igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size:
- fi-kbl-soraka: NOTRUN -> [INCOMPLETE][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22013/fi-kbl-soraka/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html
Known issues
------------
Here are the changes found in Patchwork_22013 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@semaphore:
- fi-bdw-5557u: NOTRUN -> [SKIP][2] ([fdo#109271]) +31 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22013/fi-bdw-5557u/igt@amdgpu/amd_basic@semaphore.html
* igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2: NOTRUN -> [SKIP][3] ([fdo#109315]) +17 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22013/fi-icl-u2/igt@amdgpu/amd_cs_nop@fork-gfx0.html
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600: NOTRUN -> [SKIP][4] ([fdo#109271]) +17 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22013/fi-snb-2600/igt@amdgpu/amd_cs_nop@sync-fork-compute0.html
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271]) +8 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22013/fi-kbl-soraka/igt@gem_exec_fence@basic-busy@bcs0.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#2190])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22013/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html
- fi-icl-u2: NOTRUN -> [SKIP][7] ([i915#2190])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22013/fi-icl-u2/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2: NOTRUN -> [SKIP][8] ([i915#4613]) +3 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22013/fi-icl-u2/igt@gem_lmem_swapping@parallel-random-engines.html
- fi-kbl-soraka: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613]) +3 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22013/fi-kbl-soraka/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][10] ([i915#1886] / [i915#2291])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22013/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770: [PASS][11] -> [INCOMPLETE][12] ([i915#3303])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22013/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
* igt@kms_chamelium@dp-edid-read:
- fi-kbl-soraka: NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +8 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22013/fi-kbl-soraka/igt@kms_chamelium@dp-edid-read.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: NOTRUN -> [SKIP][14] ([fdo#111827]) +8 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22013/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_chamelium@vga-edid-read:
- fi-bdw-5557u: NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) +8 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22013/fi-bdw-5557u/igt@kms_chamelium@vga-edid-read.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-icl-u2: NOTRUN -> [SKIP][16] ([fdo#109278]) +2 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22013/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2: NOTRUN -> [SKIP][17] ([fdo#109285])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22013/fi-icl-u2/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [PASS][18] -> [DMESG-WARN][19] ([i915#4269])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22013/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#533])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22013/fi-kbl-soraka/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@prime_vgem@basic-userptr:
- fi-skl-6600u: NOTRUN -> [SKIP][21] ([fdo#109271]) +18 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22013/fi-skl-6600u/igt@prime_vgem@basic-userptr.html
- fi-icl-u2: NOTRUN -> [SKIP][22] ([i915#3301])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22013/fi-icl-u2/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-hsw-4770: NOTRUN -> [FAIL][23] ([fdo#109271] / [i915#1436] / [i915#4312])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22013/fi-hsw-4770/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3@smem:
- fi-bdw-5557u: [INCOMPLETE][24] ([i915#146]) -> [PASS][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3@smem.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22013/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3@smem.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [INCOMPLETE][26] ([i915#3921]) -> [PASS][27]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22013/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
* igt@kms_psr@primary_page_flip:
- fi-skl-6600u: [FAIL][28] ([i915#4547]) -> [PASS][29]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/fi-skl-6600u/igt@kms_psr@primary_page_flip.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22013/fi-skl-6600u/igt@kms_psr@primary_page_flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4898]: https://gitlab.freedesktop.org/drm/intel/issues/4898
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Build changes
-------------
* Linux: CI_DRM_11094 -> Patchwork_22013
CI-20190529: 20190529
CI_DRM_11094: 6ce31c986ee8beaa0f98fd4e200b7a421fd4adf9 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6327: 0d559158c2d3b5723abbfc2cb4b04532e28663b2 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22013: 3602601138fc8f8fab22e342827cf62cf85c0793 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
3602601138fc drm/i915: Don't allocate extra ddb during async flip for DG2
44bbf14d7cbb drm/i915: Use wm0 only during async flips for DG2
16735b01eebb drm/i915: Introduce do_async_flip flag to intel_plane_state
b3d8c1a22c8c drm/i915: Pass plane to watermark calculation functions
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22013/index.html
[-- Attachment #2: Type: text/html, Size: 11678 bytes --]
^ permalink raw reply [flat|nested] 32+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Async flip optimization for DG2 (rev2)
2022-01-18 10:48 [Intel-gfx] [PATCH 0/4] Async flip optimization for DG2 Stanislav Lisovskiy
` (6 preceding siblings ...)
2022-01-18 13:03 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2022-01-18 14:00 ` Patchwork
2022-01-18 14:01 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
10 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2022-01-18 14:00 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Async flip optimization for DG2 (rev2)
URL : https://patchwork.freedesktop.org/series/98981/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
af673ae37d0c drm/i915: Pass plane to watermark calculation functions
69a7c958433d drm/i915: Introduce do_async_flip flag to intel_plane_state
288d6ef2c274 drm/i915: Use wm0 only during async flips for DG2
-:9: WARNING:TYPO_SPELLING: 'perfomance' may be misspelled - perhaps 'performance'?
#9:
This optimization allows to achieve higher perfomance
^^^^^^^^^^
total: 0 errors, 1 warnings, 0 checks, 48 lines checked
52ba575ac8c7 drm/i915: Don't allocate extra ddb during async flip for DG2
^ permalink raw reply [flat|nested] 32+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Async flip optimization for DG2 (rev2)
2022-01-18 10:48 [Intel-gfx] [PATCH 0/4] Async flip optimization for DG2 Stanislav Lisovskiy
` (7 preceding siblings ...)
2022-01-18 14:00 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Async flip optimization for DG2 (rev2) Patchwork
@ 2022-01-18 14:01 ` Patchwork
2022-01-18 14:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-01-18 16:55 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
10 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2022-01-18 14:01 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Async flip optimization for DG2 (rev2)
URL : https://patchwork.freedesktop.org/series/98981/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/intel_pm.c:5533:6: warning: symbol 'dg2_async_flip_optimization' was not declared. Should it be static?
^ permalink raw reply [flat|nested] 32+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Async flip optimization for DG2 (rev2)
2022-01-18 10:48 [Intel-gfx] [PATCH 0/4] Async flip optimization for DG2 Stanislav Lisovskiy
` (8 preceding siblings ...)
2022-01-18 14:01 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2022-01-18 14:27 ` Patchwork
2022-01-18 16:55 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
10 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2022-01-18 14:27 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 6235 bytes --]
== Series Details ==
Series: Async flip optimization for DG2 (rev2)
URL : https://patchwork.freedesktop.org/series/98981/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11094 -> Patchwork_22015
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/index.html
Participating hosts (46 -> 41)
------------------------------
Missing (5): shard-tglu fi-bsw-cyan shard-rkl shard-dg1 fi-bdw-samus
Known issues
------------
Here are the changes found in Patchwork_22015 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@semaphore:
- fi-bdw-5557u: NOTRUN -> [SKIP][1] ([fdo#109271]) +31 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/fi-bdw-5557u/igt@amdgpu/amd_basic@semaphore.html
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600: NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/fi-snb-2600/igt@amdgpu/amd_cs_nop@sync-fork-compute0.html
* igt@gem_exec_suspend@basic-s3:
- fi-skl-6600u: NOTRUN -> [FAIL][3] ([i915#4547])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/fi-skl-6600u/igt@gem_exec_suspend@basic-s3.html
* igt@i915_selftest@live@execlists:
- fi-bsw-n3050: [PASS][4] -> [INCOMPLETE][5] ([i915#2940])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
* igt@kms_chamelium@vga-edid-read:
- fi-bdw-5557u: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/fi-bdw-5557u/igt@kms_chamelium@vga-edid-read.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#4269])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
* igt@runner@aborted:
- fi-bsw-n3050: NOTRUN -> [FAIL][9] ([fdo#109271] / [i915#1436] / [i915#3428] / [i915#4312])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/fi-bsw-n3050/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3@smem:
- fi-bdw-5557u: [INCOMPLETE][10] ([i915#146]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3@smem.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3@smem.html
* igt@i915_selftest@live@gt_heartbeat:
- {fi-tgl-dsi}: [INCOMPLETE][12] -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [DMESG-FAIL][14] ([i915#4494]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
- bat-dg1-5: [DMESG-FAIL][16] ([i915#4494]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
- fi-snb-2600: [INCOMPLETE][18] ([i915#3921]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4898]: https://gitlab.freedesktop.org/drm/intel/issues/4898
Build changes
-------------
* Linux: CI_DRM_11094 -> Patchwork_22015
CI-20190529: 20190529
CI_DRM_11094: 6ce31c986ee8beaa0f98fd4e200b7a421fd4adf9 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6327: 0d559158c2d3b5723abbfc2cb4b04532e28663b2 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22015: 52ba575ac8c774a47867e57a16c9f7cd08a969b2 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
52ba575ac8c7 drm/i915: Don't allocate extra ddb during async flip for DG2
288d6ef2c274 drm/i915: Use wm0 only during async flips for DG2
69a7c958433d drm/i915: Introduce do_async_flip flag to intel_plane_state
af673ae37d0c drm/i915: Pass plane to watermark calculation functions
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/index.html
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^ permalink raw reply [flat|nested] 32+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for Async flip optimization for DG2 (rev2)
2022-01-18 10:48 [Intel-gfx] [PATCH 0/4] Async flip optimization for DG2 Stanislav Lisovskiy
` (9 preceding siblings ...)
2022-01-18 14:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-01-18 16:55 ` Patchwork
10 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2022-01-18 16:55 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
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== Series Details ==
Series: Async flip optimization for DG2 (rev2)
URL : https://patchwork.freedesktop.org/series/98981/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11094_full -> Patchwork_22015_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (13 -> 13)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22015_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_schedule@wide@vecs0:
- {shard-rkl}: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-rkl-5/igt@gem_exec_schedule@wide@vecs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-rkl-5/igt@gem_exec_schedule@wide@vecs0.html
* igt@gem_exec_whisper@basic-contexts-forked-all:
- {shard-tglu}: [PASS][3] -> [FAIL][4] +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-tglu-6/igt@gem_exec_whisper@basic-contexts-forked-all.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-tglu-7/igt@gem_exec_whisper@basic-contexts-forked-all.html
* igt@gem_flink_race@flink_name:
- {shard-rkl}: [PASS][5] -> [INCOMPLETE][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-rkl-2/igt@gem_flink_race@flink_name.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-rkl-5/igt@gem_flink_race@flink_name.html
Known issues
------------
Here are the changes found in Patchwork_22015_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_eio@unwedge-stress:
- shard-skl: [PASS][7] -> [TIMEOUT][8] ([i915#3063])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-skl6/igt@gem_eio@unwedge-stress.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-skl8/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_capture@pi@rcs0:
- shard-skl: NOTRUN -> [INCOMPLETE][9] ([i915#4547])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-skl7/igt@gem_exec_capture@pi@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: NOTRUN -> [FAIL][10] ([i915#2842])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-kbl4/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-apl: NOTRUN -> [FAIL][11] ([i915#2842])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-apl7/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-kbl: [PASS][12] -> [FAIL][13] ([i915#2842])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs0.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-kbl6/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-kbl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#2190])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-kbl3/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@heavy-verify-random:
- shard-skl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613]) +5 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-skl9/igt@gem_lmem_swapping@heavy-verify-random.html
* igt@gem_lmem_swapping@parallel-random-verify:
- shard-kbl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-kbl1/igt@gem_lmem_swapping@parallel-random-verify.html
* igt@gem_pwrite@basic-exhaustion:
- shard-skl: NOTRUN -> [WARN][17] ([i915#2658])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-skl10/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-kbl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#3323])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-kbl3/igt@gem_userptr_blits@dmabuf-sync.html
- shard-skl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#3323])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-skl6/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@vma-merge:
- shard-skl: NOTRUN -> [FAIL][20] ([i915#3318])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-skl4/igt@gem_userptr_blits@vma-merge.html
* igt@gen9_exec_parse@basic-rejected-ctx-param:
- shard-tglb: NOTRUN -> [SKIP][21] ([i915#2527] / [i915#2856])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-tglb1/igt@gen9_exec_parse@basic-rejected-ctx-param.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][22] -> [FAIL][23] ([i915#454])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-iclb7/igt@i915_pm_dc@dc6-psr.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-iclb4/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rpm@pm-caching:
- shard-glk: [PASS][24] -> [DMESG-WARN][25] ([i915#118])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-glk6/igt@i915_pm_rpm@pm-caching.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-glk6/igt@i915_pm_rpm@pm-caching.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-skl: NOTRUN -> [FAIL][26] ([i915#3743]) +2 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-skl10/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-skl: NOTRUN -> [SKIP][27] ([fdo#109271] / [i915#3777]) +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-skl10/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][28] ([fdo#111614])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-tglb1/igt@kms_big_fb@y-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-kbl: NOTRUN -> [SKIP][29] ([fdo#109271] / [i915#3777])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-kbl3/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-90:
- shard-tglb: NOTRUN -> [SKIP][30] ([fdo#111615])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-tglb1/igt@kms_big_fb@yf-tiled-32bpp-rotate-90.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs:
- shard-apl: NOTRUN -> [SKIP][31] ([fdo#109271]) +18 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-apl7/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
- shard-kbl: NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#3886]) +4 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-kbl3/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#3886]) +12 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-skl4/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_cdclk@mode-transition:
- shard-tglb: NOTRUN -> [SKIP][34] ([i915#3742])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-tglb1/igt@kms_cdclk@mode-transition.html
* igt@kms_color@pipe-c-ctm-0-5:
- shard-skl: [PASS][35] -> [DMESG-WARN][36] ([i915#1982]) +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-skl10/igt@kms_color@pipe-c-ctm-0-5.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-skl10/igt@kms_color@pipe-c-ctm-0-5.html
* igt@kms_color_chamelium@pipe-a-ctm-0-75:
- shard-kbl: NOTRUN -> [SKIP][37] ([fdo#109271] / [fdo#111827]) +8 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-kbl1/igt@kms_color_chamelium@pipe-a-ctm-0-75.html
* igt@kms_color_chamelium@pipe-b-ctm-limited-range:
- shard-apl: NOTRUN -> [SKIP][38] ([fdo#109271] / [fdo#111827]) +1 similar issue
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-apl3/igt@kms_color_chamelium@pipe-b-ctm-limited-range.html
* igt@kms_color_chamelium@pipe-b-ctm-max:
- shard-skl: NOTRUN -> [SKIP][39] ([fdo#109271] / [fdo#111827]) +31 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-skl4/igt@kms_color_chamelium@pipe-b-ctm-max.html
* igt@kms_cursor_crc@pipe-b-cursor-32x32-sliding:
- shard-tglb: NOTRUN -> [SKIP][40] ([i915#3319])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-tglb1/igt@kms_cursor_crc@pipe-b-cursor-32x32-sliding.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [PASS][41] -> [DMESG-WARN][42] ([i915#180]) +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
- shard-apl: [PASS][43] -> [DMESG-WARN][44] ([i915#180])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-apl2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-apl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
- shard-skl: NOTRUN -> [FAIL][45] ([i915#2122]) +2 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-skl2/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
* igt@kms_flip@plain-flip-fb-recreate@a-edp1:
- shard-skl: [PASS][46] -> [FAIL][47] ([i915#2122])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-skl2/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-skl7/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling:
- shard-skl: NOTRUN -> [INCOMPLETE][48] ([i915#3701])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-skl9/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling:
- shard-glk: [PASS][49] -> [FAIL][50] ([i915#4911])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-glk9/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
- shard-iclb: [PASS][51] -> [SKIP][52] ([i915#3701])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-iclb5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html
* igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack-mmap-gtt:
- shard-skl: NOTRUN -> [SKIP][53] ([fdo#109271]) +423 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-skl10/igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt:
- shard-kbl: NOTRUN -> [SKIP][54] ([fdo#109271]) +114 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-kbl4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
- shard-tglb: NOTRUN -> [SKIP][55] ([fdo#109280] / [fdo#111825]) +2 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-tglb1/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
* igt@kms_pipe_b_c_ivb@pipe-b-dpms-off-modeset-pipe-c:
- shard-tglb: NOTRUN -> [SKIP][56] ([fdo#109289])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-tglb1/igt@kms_pipe_b_c_ivb@pipe-b-dpms-off-modeset-pipe-c.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- shard-skl: NOTRUN -> [SKIP][57] ([fdo#109271] / [i915#533]) +2 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-skl9/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-kbl: [PASS][58] -> [INCOMPLETE][59] ([i915#794])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-kbl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-kbl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
- shard-kbl: NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#533]) +1 similar issue
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-kbl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-skl: NOTRUN -> [FAIL][61] ([fdo#108145] / [i915#265]) +8 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
- shard-skl: NOTRUN -> [FAIL][62] ([i915#265]) +1 similar issue
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html
* igt@kms_psr2_sf@cursor-plane-update-sf:
- shard-kbl: NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#658])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-kbl1/igt@kms_psr2_sf@cursor-plane-update-sf.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-skl: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#658]) +6 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-skl4/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
* igt@kms_psr@psr2_cursor_mmap_gtt:
- shard-tglb: NOTRUN -> [FAIL][65] ([i915#132] / [i915#3467])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-tglb1/igt@kms_psr@psr2_cursor_mmap_gtt.html
* igt@kms_psr@psr2_cursor_plane_onoff:
- shard-iclb: [PASS][66] -> [SKIP][67] ([fdo#109441])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-iclb4/igt@kms_psr@psr2_cursor_plane_onoff.html
* igt@kms_writeback@writeback-check-output:
- shard-skl: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#2437])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-skl10/igt@kms_writeback@writeback-check-output.html
* igt@sysfs_clients@create:
- shard-kbl: NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#2994]) +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-kbl1/igt@sysfs_clients@create.html
* igt@sysfs_clients@fair-0:
- shard-skl: NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#2994]) +5 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-skl2/igt@sysfs_clients@fair-0.html
#### Possible fixes ####
* igt@gem_ctx_persistence@smoketest:
- {shard-dg1}: [DMESG-WARN][71] ([i915#4892]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-dg1-19/igt@gem_ctx_persistence@smoketest.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-dg1-12/igt@gem_ctx_persistence@smoketest.html
* igt@gem_ctx_shared@q-smoketest-all:
- {shard-rkl}: ([INCOMPLETE][73], [PASS][74]) -> ([PASS][75], [PASS][76])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-rkl-5/igt@gem_ctx_shared@q-smoketest-all.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-rkl-4/igt@gem_ctx_shared@q-smoketest-all.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-rkl-1/igt@gem_ctx_shared@q-smoketest-all.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-rkl-4/igt@gem_ctx_shared@q-smoketest-all.html
* igt@gem_eio@in-flight-contexts-1us:
- shard-tglb: [TIMEOUT][77] ([i915#3063]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-tglb8/igt@gem_eio@in-flight-contexts-1us.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-tglb8/igt@gem_eio@in-flight-contexts-1us.html
* igt@gem_exec_balancer@parallel:
- shard-iclb: [SKIP][79] ([i915#4525]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-iclb8/igt@gem_exec_balancer@parallel.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-iclb4/igt@gem_exec_balancer@parallel.html
* igt@gem_exec_create@forked@smem:
- {shard-tglu}: [INCOMPLETE][81] -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-tglu-7/igt@gem_exec_create@forked@smem.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-tglu-2/igt@gem_exec_create@forked@smem.html
* igt@gem_exec_create@legacy@smem:
- {shard-rkl}: [DMESG-WARN][83] -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-rkl-5/igt@gem_exec_create@legacy@smem.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-rkl-1/igt@gem_exec_create@legacy@smem.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [FAIL][85] ([i915#2842]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-tglb2/igt@gem_exec_fair@basic-flow@rcs0.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-tglb3/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-kbl: [FAIL][87] ([i915#2842]) -> [PASS][88] +1 similar issue
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-kbl4/igt@gem_exec_fair@basic-none-vip@rcs0.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-kbl7/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-iclb: [FAIL][89] ([i915#2842]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-iclb4/igt@gem_exec_fair@basic-pace@bcs0.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-iclb5/igt@gem_exec_fair@basic-pace@bcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][91] ([i915#2849]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-iclb2/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_suspend@basic-s3@smem:
- shard-apl: [DMESG-WARN][93] ([i915#180]) -> [PASS][94] +2 similar issues
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-apl1/igt@gem_exec_suspend@basic-s3@smem.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-apl3/igt@gem_exec_suspend@basic-s3@smem.html
* igt@gem_exec_whisper@basic-contexts-all:
- shard-glk: [DMESG-WARN][95] ([i915#118]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-glk3/igt@gem_exec_whisper@basic-contexts-all.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-glk4/igt@gem_exec_whisper@basic-contexts-all.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [SKIP][97] ([i915#2190]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-tglb7/igt@gem_huc_copy@huc-copy.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-tglb5/igt@gem_huc_copy@huc-copy.html
* igt@gem_linear_blits@interruptible:
- {shard-tglu}: [FAIL][99] -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-tglu-7/igt@gem_linear_blits@interruptible.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-tglu-4/igt@gem_linear_blits@interruptible.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- {shard-dg1}: [DMESG-WARN][101] ([i915#4936]) -> [PASS][102]
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-dg1-15/igt@gem_lmem_swapping@smem-oom@lmem0.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-dg1-16/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@gen9_exec_parse@allowed-all:
- shard-skl: [DMESG-WARN][103] ([i915#1436] / [i915#716]) -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-skl7/igt@gen9_exec_parse@allowed-all.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-skl9/igt@gen9_exec_parse@allowed-all.html
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [FAIL][105] ([i915#454]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-iclb8/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
- {shard-dg1}: [SKIP][107] ([i915#1397]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-dg1-18/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-dg1-13/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
* igt@i915_selftest@live@execlists:
- shard-skl: [INCOMPLETE][109] -> [PASS][110]
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-skl9/igt@i915_selftest@live@execlists.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-skl6/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@hangcheck:
- {shard-dg1}: [DMESG-FAIL][111] ([i915#4494]) -> [PASS][112]
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-dg1-15/igt@i915_selftest@live@hangcheck.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-dg1-18/igt@i915_selftest@live@hangcheck.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-180:
- {shard-tglu}: [DMESG-WARN][113] ([i915#402]) -> [PASS][114]
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-tglu-5/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-tglu-1/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
* igt@kms_color@pipe-b-ctm-0-25:
- {shard-rkl}: ([SKIP][115], [PASS][116]) ([i915#1149] / [i915#4098]) -> [PASS][117] +1 similar issue
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-rkl-4/igt@kms_color@pipe-b-ctm-0-25.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-rkl-6/igt@kms_color@pipe-b-ctm-0-25.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-rkl-6/igt@kms_color@pipe-b-ctm-0-25.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- {shard-rkl}: ([SKIP][118], [PASS][119]) ([fdo#112022]) -> [PASS][120] +1 similar issue
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-rkl-4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_legacy@cursora-vs-flipa-varying-size:
- shard-tglb: [DMESG-WARN][121] ([i915#1982]) -> [PASS][122]
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-tglb2/igt@kms_cursor_legacy@cursora-vs-flipa-varying-size.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-tglb5/igt@kms_cursor_legacy@cursora-vs-flipa-varying-size.html
* igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size:
- shard-skl: [FAIL][123] ([i915#2346]) -> [PASS][124]
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-skl2/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-skl7/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [INCOMPLETE][125] ([i915#180]) -> [PASS][126]
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-apl3/igt@kms_fbcon_fbt@fbc-suspend.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-apl8/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@plain-flip-fb-recreate@b-edp1:
- shard-skl: [FAIL][127] ([i915#2122]) -> [PASS][128] +1 similar issue
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-skl2/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-skl7/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl: [DMESG-WARN][129] ([i915#180]) -> [PASS][130] +5 similar issues
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-kbl3/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render:
- {shard-rkl}: ([SKIP][131], [PASS][132]) ([i915#4098]) -> [PASS][133] +3 similar issues
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html
* igt@kms_invalid_mode@zero-clock:
- {shard-rkl}: ([SKIP][134], [PASS][135]) ([i915#4278]) -> [PASS][136]
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-rkl-4/igt@kms_invalid_mode@zero-clock.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-rkl-6/igt@kms_invalid_mode@zero-clock.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-rkl-6/igt@kms_invalid_mode@zero-clock.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [FAIL][137] ([fdo#108145] / [i915#265]) -> [PASS][138]
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_psr@psr2_primary_blt:
- shard-iclb: [SKIP][139] ([fdo#109441]) -> [PASS][140]
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-iclb5/igt@kms_psr@psr2_primary_blt.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-iclb2/igt@kms_psr@psr2_primary_blt.html
* igt@kms_rotation_crc@sprite-rotation-270:
- {shard-rkl}: ([PASS][141], [SKIP][142]) ([i915#1845]) -> [PASS][143] +2 similar issues
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-rkl-6/igt@kms_rotation_crc@sprite-rotation-270.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-rkl-4/igt@kms_rotation_crc@sprite-rotation-270.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-rkl-6/igt@kms_rotation_crc@sprite-rotation-270.html
* igt@kms_setmode@basic:
- shard-glk: [FAIL][144] ([i915#31]) -> [PASS][145]
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-glk4/igt@kms_setmode@basic.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-glk2/igt@kms_setmode@basic.html
* igt@perf@blocking:
- shard-skl: [FAIL][146] ([i915#1542]) -> [PASS][147] +1 similar issue
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-skl10/igt@perf@blocking.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-skl10/igt@perf@blocking.html
#### Warnings ####
* igt@gem_eio@unwedge-stress:
- shard-tglb: [TIMEOUT][148] ([i915#3063] / [i915#3648]) -> [FAIL][149] ([i915#232])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11094/shard-tglb6/igt@gem_eio@unwedge-stress.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/shard-tglb1/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22015/index.html
[-- Attachment #2: Type: text/html, Size: 33306 bytes --]
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 1/4] drm/i915: Pass plane to watermark calculation functions
2022-01-18 10:48 ` [Intel-gfx] [PATCH 1/4] drm/i915: Pass plane to watermark calculation functions Stanislav Lisovskiy
@ 2022-01-19 11:26 ` Ville Syrjälä
0 siblings, 0 replies; 32+ messages in thread
From: Ville Syrjälä @ 2022-01-19 11:26 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
On Tue, Jan 18, 2022 at 12:48:36PM +0200, Stanislav Lisovskiy wrote:
> Sometimes we might need to change the way we calculate
> watermarks, based on which particular plane it is calculated
> for. Thus it would be convenient to pass plane struct to those
> functions.
>
> v2: Pass plane instead of plane_id
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> .../gpu/drm/i915/display/intel_atomic_plane.c | 2 +-
> .../gpu/drm/i915/display/intel_atomic_plane.h | 3 +++
> drivers/gpu/drm/i915/intel_pm.c | 23 +++++++++++++------
> 3 files changed, 20 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index c2c512cd8ec0..d1344e9c06de 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -373,7 +373,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
> old_plane_state, new_plane_state);
> }
>
> -static struct intel_plane *
> +struct intel_plane *
> intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id)
> {
> struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> index 7907f601598e..c1499bb7370e 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> @@ -16,10 +16,13 @@ struct intel_crtc;
> struct intel_crtc_state;
> struct intel_plane;
> struct intel_plane_state;
> +enum plane_id;
>
> unsigned int intel_adjusted_rate(const struct drm_rect *src,
> const struct drm_rect *dst,
> unsigned int rate);
> +struct intel_plane *intel_crtc_get_plane(struct intel_crtc *crtc,
> + enum plane_id plane_id);
> unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state);
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 62fde21fac39..dc1203d21c46 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4252,7 +4252,9 @@ static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
> u64 modifier, unsigned int rotation,
> u32 plane_pixel_rate, struct skl_wm_params *wp,
> int color_plane);
> +
> static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> + const struct intel_plane *plane,
> int level,
> unsigned int latency,
> const struct skl_wm_params *wp,
> @@ -4261,6 +4263,7 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
>
> static unsigned int
> skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
> + const struct intel_plane *plane,
I don't see a reason for having the caller pass this in. We can just
keep it local to this function.
Also we don't usually const these things.
> int num_active)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> @@ -4279,7 +4282,7 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
> for (level = 0; level <= max_level; level++) {
> unsigned int latency = dev_priv->wm.skl_latency[level];
>
> - skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
> + skl_compute_plane_wm(crtc_state, plane, level, latency, &wp, &wm, &wm);
> if (wm.min_ddb_alloc == U16_MAX)
> break;
>
> @@ -5124,6 +5127,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
> intel_atomic_get_new_crtc_state(state, crtc);
> const struct intel_dbuf_state *dbuf_state =
> intel_atomic_get_new_dbuf_state(state);
> + const struct intel_plane *cursor_plane = intel_crtc_get_plane(crtc, PLANE_CURSOR);
Could be just to_intel_plane(crtc->base.cursor)
Apart from that looks OK.
> const struct skl_ddb_entry *alloc = &dbuf_state->ddb[crtc->pipe];
> int num_active = hweight8(dbuf_state->active_pipes);
> u16 alloc_size, start = 0;
> @@ -5153,7 +5157,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
> return 0;
>
> /* Allocate fixed number of blocks for cursor. */
> - total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
> + total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, cursor_plane, num_active);
> alloc_size -= total[PLANE_CURSOR];
> crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].start =
> alloc->end - total[PLANE_CURSOR];
> @@ -5507,6 +5511,7 @@ static int skl_wm_max_lines(struct drm_i915_private *dev_priv)
> }
>
> static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> + const struct intel_plane *plane,
> int level,
> unsigned int latency,
> const struct skl_wm_params *wp,
> @@ -5634,6 +5639,7 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
>
> static void
> skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
> + const struct intel_plane *plane,
> const struct skl_wm_params *wm_params,
> struct skl_wm_level *levels)
> {
> @@ -5645,7 +5651,7 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
> struct skl_wm_level *result = &levels[level];
> unsigned int latency = dev_priv->wm.skl_latency[level];
>
> - skl_compute_plane_wm(crtc_state, level, latency,
> + skl_compute_plane_wm(crtc_state, plane, level, latency,
> wm_params, result_prev, result);
>
> result_prev = result;
> @@ -5653,6 +5659,7 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
> }
>
> static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
> + const struct intel_plane *plane,
> const struct skl_wm_params *wm_params,
> struct skl_plane_wm *plane_wm)
> {
> @@ -5661,7 +5668,7 @@ static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
> struct skl_wm_level *levels = plane_wm->wm;
> unsigned int latency = dev_priv->wm.skl_latency[0] + dev_priv->sagv_block_time_us;
>
> - skl_compute_plane_wm(crtc_state, 0, latency,
> + skl_compute_plane_wm(crtc_state, plane, 0, latency,
> wm_params, &levels[0],
> sagv_wm);
> }
> @@ -5736,6 +5743,7 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
> + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> struct skl_wm_params wm_params;
> int ret;
>
> @@ -5744,13 +5752,13 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
> if (ret)
> return ret;
>
> - skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
> + skl_compute_wm_levels(crtc_state, plane, &wm_params, wm->wm);
>
> skl_compute_transition_wm(dev_priv, &wm->trans_wm,
> &wm->wm[0], &wm_params);
>
> if (DISPLAY_VER(dev_priv) >= 12) {
> - tgl_compute_sagv_wm(crtc_state, &wm_params, wm);
> + tgl_compute_sagv_wm(crtc_state, plane, &wm_params, wm);
>
> skl_compute_transition_wm(dev_priv, &wm->sagv.trans_wm,
> &wm->sagv.wm0, &wm_params);
> @@ -5764,6 +5772,7 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
> enum plane_id plane_id)
> {
> struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
> + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> struct skl_wm_params wm_params;
> int ret;
>
> @@ -5775,7 +5784,7 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
> if (ret)
> return ret;
>
> - skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
> + skl_compute_wm_levels(crtc_state, plane, &wm_params, wm->uv_wm);
>
> return 0;
> }
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 2/4] drm/i915: Introduce do_async_flip flag to intel_plane_state
2022-01-18 10:48 ` [Intel-gfx] [PATCH 2/4] drm/i915: Introduce do_async_flip flag to intel_plane_state Stanislav Lisovskiy
@ 2022-01-19 11:35 ` Ville Syrjälä
0 siblings, 0 replies; 32+ messages in thread
From: Ville Syrjälä @ 2022-01-19 11:35 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
On Tue, Jan 18, 2022 at 12:48:37PM +0200, Stanislav Lisovskiy wrote:
> There might be various logical contructs when we might want
> to enable async flip, so lets calculate those and set this
> flag, so that there is no need in long conditions in other
> places.
>
> v2: - Set do_async_flip flag to False, if no async flip needed.
> Lets not rely that it will be 0-initialized, but set
> explicitly, so that the logic is clear as well.
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_atomic_plane.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display.c | 5 +++++
> drivers/gpu/drm/i915/display/intel_display_types.h | 3 +++
> 3 files changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index d1344e9c06de..87bad665a2c8 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -491,7 +491,7 @@ void intel_plane_update_arm(struct intel_plane *plane,
>
> trace_intel_plane_update_arm(&plane->base, crtc);
>
> - if (crtc_state->uapi.async_flip && plane->async_flip)
> + if (plane_state->do_async_flip)
> plane->async_flip(plane, crtc_state, plane_state, true);
> else
> plane->update_arm(plane, crtc_state, plane_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 0964b2403e2d..f3ce29c42bc3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5027,6 +5027,11 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
> needs_scaling(new_plane_state))))
> new_crtc_state->disable_lp_wm = true;
>
> + if (new_crtc_state->uapi.async_flip && plane->async_flip)
> + new_plane_state->do_async_flip = true;
> + else
> + new_plane_state->do_async_flip = false;
Clearing the flag should probably be in intel_plane_duplicate_state().
The decision to call intel_crtc_{enable,disable}_flip_done() should
also be based on do_async_flip, otherwise we're going to try to complete
the flip using two different mechanisms when we decide to do a sync flip
instead of an async flip.
Otherwise lgtm.
> +
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 41e3dd25a78f..6b107872ad39 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -634,6 +634,9 @@ struct intel_plane_state {
>
> struct intel_fb_view view;
>
> + /* Indicates if async flip is required */
> + bool do_async_flip;
> +
> /* Plane pxp decryption state */
> bool decrypt;
>
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 3/4] drm/i915: Use wm0 only during async flips for DG2
2022-01-18 10:48 ` [Intel-gfx] [PATCH 3/4] drm/i915: Use wm0 only during async flips for DG2 Stanislav Lisovskiy
@ 2022-01-19 11:51 ` Ville Syrjälä
0 siblings, 0 replies; 32+ messages in thread
From: Ville Syrjälä @ 2022-01-19 11:51 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
On Tue, Jan 18, 2022 at 12:48:38PM +0200, Stanislav Lisovskiy wrote:
> This optimization allows to achieve higher perfomance
> during async flips.
> For the first async flip we have to still temporarily
> switch to sync flip, in order to reprogram plane
> watermarks, so this requires taking into account
> old plane state's do_async_flip flag.
>
> v2: - Removed redundant new_plane_state->do_async_flip
> check from needs_async_flip_wm_override condition
> (Ville Syrjälä)
> - Extract dg2_async_flip_optimization to separate
> function(Ville Syrjälä)
> - Check for plane->async_flip instead of plane_id
> (Ville Syrjälä)
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 12 +++++++++++-
> drivers/gpu/drm/i915/intel_pm.c | 12 +++++++++++-
> 2 files changed, 22 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index f3ce29c42bc3..9a5126310014 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4908,6 +4908,15 @@ static bool needs_scaling(const struct intel_plane_state *state)
> return (src_w != dst_w || src_h != dst_h);
> }
>
> +static bool needs_async_flip_wm_override(struct intel_plane *plane,
> + const struct intel_plane_state *new_plane_state,
> + const struct intel_plane_state *old_plane_state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
I'd probably put all the require logic into this one function.
Perhaps somehting like?
intel_plane_do_async_flip()
{
if (!plane->async_flip)
return false;
if (!new_crtc_state->uapi.async_flip)
return false;
/* some explanation what's going on here */
return DISPLAY_VER < 13 || old_crtc_state->uapi.async_flip;
}
>+
> + return DISPLAY_VER(dev_priv) >= 13 && !old_plane_state->do_async_flip;
> +}
> +
> int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
> struct intel_crtc_state *new_crtc_state,
> const struct intel_plane_state *old_plane_state,
> @@ -5027,7 +5036,8 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
> needs_scaling(new_plane_state))))
> new_crtc_state->disable_lp_wm = true;
>
> - if (new_crtc_state->uapi.async_flip && plane->async_flip)
> + if (new_crtc_state->uapi.async_flip &&
> + !needs_async_flip_wm_override(plane, new_plane_state, old_plane_state))
> new_plane_state->do_async_flip = true;
> else
> new_plane_state->do_async_flip = false;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index dc1203d21c46..5d350ddc447f 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5510,6 +5510,15 @@ static int skl_wm_max_lines(struct drm_i915_private *dev_priv)
> return 31;
> }
>
> +bool dg2_async_flip_optimization(struct drm_i915_private *i915,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane *plane)
I'd drop the platform specific suffix from this since it's more of
a policy quesion rather than really a platform specific question.
We may or may not want to extend this to other platforms too if we
figure out that it can actually help (although my initial quick
tests did show a potentially negative impact for some unknown reason).
In fact maybe it should be just called use_minimal_wm0_only()
or something since the callers don't really need to know why it's
being done, only that we want to limit to just wm0 with minimal ddb
allocation?
> +{
> + return DISPLAY_VER(i915) >= 13 &&
> + crtc_state->uapi.async_flip &&
> + plane->async_flip;
> +}
> +
> static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> const struct intel_plane *plane,
> int level,
> @@ -5523,7 +5532,8 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> uint_fixed_16_16_t selected_result;
> u32 blocks, lines, min_ddb_alloc = 0;
>
> - if (latency == 0) {
> + if (latency == 0 ||
> + (dg2_async_flip_optimization(dev_priv, crtc_state, plane) && level > 0)) {
> /* reject it */
> result->min_ddb_alloc = U16_MAX;
> return;
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip for DG2
2022-01-18 10:48 ` [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip " Stanislav Lisovskiy
@ 2022-01-19 11:59 ` Ville Syrjälä
0 siblings, 0 replies; 32+ messages in thread
From: Ville Syrjälä @ 2022-01-19 11:59 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
On Tue, Jan 18, 2022 at 12:48:39PM +0200, Stanislav Lisovskiy wrote:
> In terms of async flip optimization we don't to allocate
> extra ddb space, so lets skip it.
>
> v2: - Extracted min ddb async flip check to separate function
> (Ville Syrjälä)
> - Used this function to prevent false positive WARN
> to be triggered(Ville Syrjälä)
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 34 ++++++++++++++++++++++++++-------
> 1 file changed, 27 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 5d350ddc447f..4922c9108f08 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5118,6 +5118,12 @@ static bool icl_need_wm1_wa(struct drm_i915_private *i915,
> (IS_DISPLAY_VER(i915, 12, 13) && plane_id == PLANE_CURSOR);
> }
>
> +static bool dg2_need_min_ddb(struct drm_i915_private *i915,
> + struct intel_crtc_state *crtc_state)
> +{
> + return IS_DG2(i915) && crtc_state->uapi.async_flip;
Why are we using IS_DG2 here vs. DISPLAY>=13 for the wm0 only decision?
> +}
> +
> static int
> skl_allocate_plane_ddb(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> @@ -5226,9 +5232,15 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
> break;
>
> rate = crtc_state->plane_data_rate[plane_id];
> - extra = min_t(u16, alloc_size,
> - DIV64_U64_ROUND_UP(alloc_size * rate,
> - total_data_rate));
> +
> + if (dg2_need_min_ddb(dev_priv, crtc_state)) {
> + extra = 0;
> + } else {
> + extra = min_t(u16, alloc_size,
> + DIV64_U64_ROUND_UP(alloc_size * rate,
> + total_data_rate));
> + }
Hmm. I wonder if we should just set rate=0 instead. That would
let the other planes pick up the now unused extra ddb space. Would
also avoid having to skip the WARN since we'd still allocate the
full ddb.
> +
> total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
> alloc_size -= extra;
> total_data_rate -= rate;
> @@ -5237,14 +5249,22 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
> break;
>
> rate = crtc_state->uv_plane_data_rate[plane_id];
> - extra = min_t(u16, alloc_size,
> - DIV64_U64_ROUND_UP(alloc_size * rate,
> - total_data_rate));
> +
> + if (dg2_need_min_ddb(dev_priv, crtc_state)) {
> + extra = 0;
> + } else {
> + extra = min_t(u16, alloc_size,
> + DIV64_U64_ROUND_UP(alloc_size * rate,
> + total_data_rate));
> + }
> +
> uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
> alloc_size -= extra;
> total_data_rate -= rate;
> }
> - drm_WARN_ON(&dev_priv->drm, alloc_size != 0 || total_data_rate != 0);
> +
> + if (!dg2_need_min_ddb(dev_priv, crtc_state))
> + drm_WARN_ON(&dev_priv->drm, alloc_size != 0 || total_data_rate != 0);
>
> /* Set the actual DDB start/end points for each plane */
> start = alloc->start;
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip for DG2
2022-01-24 18:55 ` Ville Syrjälä
@ 2022-01-25 11:36 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 32+ messages in thread
From: Lisovskiy, Stanislav @ 2022-01-25 11:36 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Mon, Jan 24, 2022 at 08:55:57PM +0200, Ville Syrjälä wrote:
> On Mon, Jan 24, 2022 at 03:52:34PM +0200, Stanislav Lisovskiy wrote:
> > In terms of async flip optimization we don't to allocate
> > extra ddb space, so lets skip it.
> >
> > v2: - Extracted min ddb async flip check to separate function
> > (Ville Syrjälä)
> > - Used this function to prevent false positive WARN
> > to be triggered(Ville Syrjälä)
> >
> > v3: - Renamed dg2_need_min_ddb to need_min_ddb thus making
> > it more universal.
> > - Also used DISPLAY_VER instead of IS_DG2(Ville Syrjälä)
> > - Use rate = 0 instead of just setting extra = 0, thus
> > letting other planes to use extra ddb and avoiding WARN
> > (Ville Syrjälä)
> >
> > v4: - Renamed needs_min_ddb as s/needs/use/ to match
> > the wm0 counterpart(Ville Syrjälä)
> > - Added plane->async_flip check to use_min_ddb(now
> > passing plane as a parameter to do that)(Ville Syrjälä)
> > - Account for use_min_ddb also when calculating total data rate
> > (Ville Syrjälä)
> >
> > v5:
> > - Use for_each_intel_plane_on_crtc instead of for_each_intel_plane_id
> > to get plane->async_flip check and account for all planes(Ville Syrjälä)
> > - Fix line wrapping(Ville Syrjälä)
> > - Set plane data rate conditionally, avoiding on redundant assignment
> > (Ville Syrjälä)
> > - Removed redundant whitespace(Ville Syrjälä)
> > - Handle use_min_ddb case in skl_plane_relative_data_rate instead of
> > icl_get_total_relative_data_rate(Ville Syrjälä)
> >
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++
> > 1 file changed, 18 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 0bb4c941f950..bb147e5a77b6 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4906,6 +4906,16 @@ static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes)
> > return active_pipes & BIT(pipe) ? BIT(DBUF_S1) : 0;
> > }
> >
> > +static bool use_min_ddb(const struct intel_crtc_state *crtc_state,
> > + struct intel_plane *plane)
> > +{
> > + struct drm_i915_private *i915 = to_i915(plane->base.dev);
> > +
> > + return DISPLAY_VER(i915) >= 13 &&
> > + crtc_state->uapi.async_flip &&
> > + plane->async_flip;
> > +}
> > +
> > static bool use_minimal_wm0_only(const struct intel_crtc_state *crtc_state,
> > struct intel_plane *plane)
> > {
> > @@ -4934,6 +4944,14 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
> > if (plane->id == PLANE_CURSOR)
> > return 0;
> >
> > + /*
> > + * We calculate extra ddb based on ratio plane rate/total data rate
> > + * in case, in some cases we should not allocate extra ddb for the plane,
> > + * so do not count its data rate, if this is the case.
> > + */
> > + if (use_min_ddb(crtc_state, plane))
> > + return 0;
> > +
> > if (color_plane == 1 &&
> > !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
> > return 0;
>
> Yeah this looks nice and simple. Only minor nit is that I'd probably
> have put it after this ccs vs. planar related thing which is a more
> static decision than the async flip optimization.
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
I guess the first patch in this series is also ok?
Just wondering, if I can push it now.
Stan
>
> > --
> > 2.24.1.485.gad05a3d8e5
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip for DG2
2022-01-24 13:52 ` Stanislav Lisovskiy
@ 2022-01-24 18:55 ` Ville Syrjälä
2022-01-25 11:36 ` Lisovskiy, Stanislav
0 siblings, 1 reply; 32+ messages in thread
From: Ville Syrjälä @ 2022-01-24 18:55 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
On Mon, Jan 24, 2022 at 03:52:34PM +0200, Stanislav Lisovskiy wrote:
> In terms of async flip optimization we don't to allocate
> extra ddb space, so lets skip it.
>
> v2: - Extracted min ddb async flip check to separate function
> (Ville Syrjälä)
> - Used this function to prevent false positive WARN
> to be triggered(Ville Syrjälä)
>
> v3: - Renamed dg2_need_min_ddb to need_min_ddb thus making
> it more universal.
> - Also used DISPLAY_VER instead of IS_DG2(Ville Syrjälä)
> - Use rate = 0 instead of just setting extra = 0, thus
> letting other planes to use extra ddb and avoiding WARN
> (Ville Syrjälä)
>
> v4: - Renamed needs_min_ddb as s/needs/use/ to match
> the wm0 counterpart(Ville Syrjälä)
> - Added plane->async_flip check to use_min_ddb(now
> passing plane as a parameter to do that)(Ville Syrjälä)
> - Account for use_min_ddb also when calculating total data rate
> (Ville Syrjälä)
>
> v5:
> - Use for_each_intel_plane_on_crtc instead of for_each_intel_plane_id
> to get plane->async_flip check and account for all planes(Ville Syrjälä)
> - Fix line wrapping(Ville Syrjälä)
> - Set plane data rate conditionally, avoiding on redundant assignment
> (Ville Syrjälä)
> - Removed redundant whitespace(Ville Syrjälä)
> - Handle use_min_ddb case in skl_plane_relative_data_rate instead of
> icl_get_total_relative_data_rate(Ville Syrjälä)
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 0bb4c941f950..bb147e5a77b6 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4906,6 +4906,16 @@ static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes)
> return active_pipes & BIT(pipe) ? BIT(DBUF_S1) : 0;
> }
>
> +static bool use_min_ddb(const struct intel_crtc_state *crtc_state,
> + struct intel_plane *plane)
> +{
> + struct drm_i915_private *i915 = to_i915(plane->base.dev);
> +
> + return DISPLAY_VER(i915) >= 13 &&
> + crtc_state->uapi.async_flip &&
> + plane->async_flip;
> +}
> +
> static bool use_minimal_wm0_only(const struct intel_crtc_state *crtc_state,
> struct intel_plane *plane)
> {
> @@ -4934,6 +4944,14 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
> if (plane->id == PLANE_CURSOR)
> return 0;
>
> + /*
> + * We calculate extra ddb based on ratio plane rate/total data rate
> + * in case, in some cases we should not allocate extra ddb for the plane,
> + * so do not count its data rate, if this is the case.
> + */
> + if (use_min_ddb(crtc_state, plane))
> + return 0;
> +
> if (color_plane == 1 &&
> !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
> return 0;
Yeah this looks nice and simple. Only minor nit is that I'd probably
have put it after this ccs vs. planar related thing which is a more
static decision than the async flip optimization.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip for DG2
2022-01-24 9:06 ` [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip " Stanislav Lisovskiy
2022-01-24 9:16 ` Ville Syrjälä
2022-01-24 9:51 ` Stanislav Lisovskiy
@ 2022-01-24 13:52 ` Stanislav Lisovskiy
2022-01-24 18:55 ` Ville Syrjälä
2 siblings, 1 reply; 32+ messages in thread
From: Stanislav Lisovskiy @ 2022-01-24 13:52 UTC (permalink / raw)
To: intel-gfx
In terms of async flip optimization we don't to allocate
extra ddb space, so lets skip it.
v2: - Extracted min ddb async flip check to separate function
(Ville Syrjälä)
- Used this function to prevent false positive WARN
to be triggered(Ville Syrjälä)
v3: - Renamed dg2_need_min_ddb to need_min_ddb thus making
it more universal.
- Also used DISPLAY_VER instead of IS_DG2(Ville Syrjälä)
- Use rate = 0 instead of just setting extra = 0, thus
letting other planes to use extra ddb and avoiding WARN
(Ville Syrjälä)
v4: - Renamed needs_min_ddb as s/needs/use/ to match
the wm0 counterpart(Ville Syrjälä)
- Added plane->async_flip check to use_min_ddb(now
passing plane as a parameter to do that)(Ville Syrjälä)
- Account for use_min_ddb also when calculating total data rate
(Ville Syrjälä)
v5:
- Use for_each_intel_plane_on_crtc instead of for_each_intel_plane_id
to get plane->async_flip check and account for all planes(Ville Syrjälä)
- Fix line wrapping(Ville Syrjälä)
- Set plane data rate conditionally, avoiding on redundant assignment
(Ville Syrjälä)
- Removed redundant whitespace(Ville Syrjälä)
- Handle use_min_ddb case in skl_plane_relative_data_rate instead of
icl_get_total_relative_data_rate(Ville Syrjälä)
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0bb4c941f950..bb147e5a77b6 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4906,6 +4906,16 @@ static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes)
return active_pipes & BIT(pipe) ? BIT(DBUF_S1) : 0;
}
+static bool use_min_ddb(const struct intel_crtc_state *crtc_state,
+ struct intel_plane *plane)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+
+ return DISPLAY_VER(i915) >= 13 &&
+ crtc_state->uapi.async_flip &&
+ plane->async_flip;
+}
+
static bool use_minimal_wm0_only(const struct intel_crtc_state *crtc_state,
struct intel_plane *plane)
{
@@ -4934,6 +4944,14 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
if (plane->id == PLANE_CURSOR)
return 0;
+ /*
+ * We calculate extra ddb based on ratio plane rate/total data rate
+ * in case, in some cases we should not allocate extra ddb for the plane,
+ * so do not count its data rate, if this is the case.
+ */
+ if (use_min_ddb(crtc_state, plane))
+ return 0;
+
if (color_plane == 1 &&
!intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
return 0;
--
2.24.1.485.gad05a3d8e5
^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip for DG2
2022-01-24 9:51 ` Stanislav Lisovskiy
@ 2022-01-24 10:32 ` Ville Syrjälä
0 siblings, 0 replies; 32+ messages in thread
From: Ville Syrjälä @ 2022-01-24 10:32 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
On Mon, Jan 24, 2022 at 11:51:23AM +0200, Stanislav Lisovskiy wrote:
> In terms of async flip optimization we don't to allocate
> extra ddb space, so lets skip it.
>
> v2: - Extracted min ddb async flip check to separate function
> (Ville Syrjälä)
> - Used this function to prevent false positive WARN
> to be triggered(Ville Syrjälä)
>
> v3: - Renamed dg2_need_min_ddb to need_min_ddb thus making
> it more universal.
> - Also used DISPLAY_VER instead of IS_DG2(Ville Syrjälä)
> - Use rate = 0 instead of just setting extra = 0, thus
> letting other planes to use extra ddb and avoiding WARN
> (Ville Syrjälä)
>
> v4: - Renamed needs_min_ddb as s/needs/use/ to match
> the wm0 counterpart(Ville Syrjälä)
> - Added plane->async_flip check to use_min_ddb(now
> passing plane as a parameter to do that)(Ville Syrjälä)
> - Account for use_min_ddb also when calculating total data rate
> (Ville Syrjälä)
>
> v5:
> - Use for_each_intel_plane_on_crtc instead of for_each_intel_plane_id
> to get plane->async_flip check and account for all planes(Ville Syrjälä)
> - Fix line wrapping(Ville Syrjälä)
> - Set plane data rate conditionally, avoiding on redundant assignment
> (Ville Syrjälä)
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> .../gpu/drm/i915/display/intel_atomic_plane.h | 1 -
> drivers/gpu/drm/i915/intel_pm.c | 40 ++++++++++++++++---
> 2 files changed, 35 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> index ead789709477..c238177e5563 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> @@ -23,7 +23,6 @@ unsigned int intel_adjusted_rate(const struct drm_rect *src,
> unsigned int rate);
> unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state);
> -
supurious whitespace changes
> unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state);
> void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index f6c742b583c1..7ce26f22e10e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4988,6 +4988,16 @@ skl_get_total_relative_data_rate(struct intel_atomic_state *state,
> return total_data_rate;
> }
>
> +static bool use_min_ddb(struct intel_crtc_state *crtc_state,
> + struct intel_plane *plane)
> +{
> + struct drm_i915_private *i915 = to_i915(plane->base.dev);
> +
> + return DISPLAY_VER(i915) >= 13 &&
> + crtc_state->uapi.async_flip &&
> + plane->async_flip;
> +}
> +
> static bool use_minimal_wm0_only(const struct intel_crtc_state *crtc_state,
> struct intel_plane *plane)
> {
> @@ -5002,6 +5012,7 @@ static u64
> icl_get_total_relative_data_rate(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> const struct intel_plane_state *plane_state;
> @@ -5043,8 +5054,15 @@ icl_get_total_relative_data_rate(struct intel_atomic_state *state,
> }
> }
>
> - for_each_plane_id_on_crtc(crtc, plane_id)
> - total_data_rate += crtc_state->plane_data_rate[plane_id];
Hmm. I was going to say we should remove plane_id now, but looks like
the other loop still uses it. I would move the declaration into that
loop now to make it less likely we mess up and use the wrong thing.
> + for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
> + /*
> + * We calculate extra ddb based on ratio plane rate/total data rate
> + * in case, in some cases we should not allocate extra ddb for the plane,
> + * so do not count its data rate, if this is the case.
> + */
> + if (!use_min_ddb(crtc_state, plane))
> + total_data_rate += crtc_state->plane_data_rate[plane->id];
> + }
>
> return total_data_rate;
> }
> @@ -5130,6 +5148,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
> u16 alloc_size, start = 0;
> u16 total[I915_MAX_PLANES] = {};
> u16 uv_total[I915_MAX_PLANES] = {};
> + struct intel_plane *plane;
> u64 total_data_rate;
> enum plane_id plane_id;
> u32 blocks;
> @@ -5206,7 +5225,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
> * watermark level, plus an extra share of the leftover blocks
> * proportional to its relative data rate.
> */
> - for_each_plane_id_on_crtc(crtc, plane_id) {
> + for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
> const struct skl_plane_wm *wm =
> &crtc_state->wm.skl.optimal.planes[plane_id];
And here we do use the wrong thing. Should be plane->id.
Apparently some other loops still use plane_id, so can't remove it
fully :(
It's looking a bit messy overall. Might just be much cleaner to
calculate the plane_data_rate[] stuff as zero to start with so we
wouldn't have to deal with any of this here. Looks like you could
just handle it in skl_plane_relative_data_rate() in fact.
> u64 rate;
> @@ -5222,10 +5241,15 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
> if (total_data_rate == 0)
> break;
>
> - rate = crtc_state->plane_data_rate[plane_id];
> + if (use_min_ddb(crtc_state, plane))
> + rate = 0;
> + else
> + rate = crtc_state->plane_data_rate[plane_id];
> +
> extra = min_t(u16, alloc_size,
> DIV64_U64_ROUND_UP(alloc_size * rate,
> total_data_rate));
> +
> total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
> alloc_size -= extra;
> total_data_rate -= rate;
> @@ -5233,14 +5257,20 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
> if (total_data_rate == 0)
> break;
>
> - rate = crtc_state->uv_plane_data_rate[plane_id];
> + if (use_min_ddb(crtc_state, plane))
> + rate = 0;
> + else
> + rate = crtc_state->uv_plane_data_rate[plane_id];
> +
> extra = min_t(u16, alloc_size,
> DIV64_U64_ROUND_UP(alloc_size * rate,
> total_data_rate));
> +
> uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
> alloc_size -= extra;
> total_data_rate -= rate;
> }
> +
> drm_WARN_ON(&dev_priv->drm, alloc_size != 0 || total_data_rate != 0);
>
> /* Set the actual DDB start/end points for each plane */
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip for DG2
2022-01-24 9:06 ` [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip " Stanislav Lisovskiy
2022-01-24 9:16 ` Ville Syrjälä
@ 2022-01-24 9:51 ` Stanislav Lisovskiy
2022-01-24 10:32 ` Ville Syrjälä
2022-01-24 13:52 ` Stanislav Lisovskiy
2 siblings, 1 reply; 32+ messages in thread
From: Stanislav Lisovskiy @ 2022-01-24 9:51 UTC (permalink / raw)
To: intel-gfx
In terms of async flip optimization we don't to allocate
extra ddb space, so lets skip it.
v2: - Extracted min ddb async flip check to separate function
(Ville Syrjälä)
- Used this function to prevent false positive WARN
to be triggered(Ville Syrjälä)
v3: - Renamed dg2_need_min_ddb to need_min_ddb thus making
it more universal.
- Also used DISPLAY_VER instead of IS_DG2(Ville Syrjälä)
- Use rate = 0 instead of just setting extra = 0, thus
letting other planes to use extra ddb and avoiding WARN
(Ville Syrjälä)
v4: - Renamed needs_min_ddb as s/needs/use/ to match
the wm0 counterpart(Ville Syrjälä)
- Added plane->async_flip check to use_min_ddb(now
passing plane as a parameter to do that)(Ville Syrjälä)
- Account for use_min_ddb also when calculating total data rate
(Ville Syrjälä)
v5:
- Use for_each_intel_plane_on_crtc instead of for_each_intel_plane_id
to get plane->async_flip check and account for all planes(Ville Syrjälä)
- Fix line wrapping(Ville Syrjälä)
- Set plane data rate conditionally, avoiding on redundant assignment
(Ville Syrjälä)
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
.../gpu/drm/i915/display/intel_atomic_plane.h | 1 -
drivers/gpu/drm/i915/intel_pm.c | 40 ++++++++++++++++---
2 files changed, 35 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index ead789709477..c238177e5563 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -23,7 +23,6 @@ unsigned int intel_adjusted_rate(const struct drm_rect *src,
unsigned int rate);
unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
-
unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f6c742b583c1..7ce26f22e10e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4988,6 +4988,16 @@ skl_get_total_relative_data_rate(struct intel_atomic_state *state,
return total_data_rate;
}
+static bool use_min_ddb(struct intel_crtc_state *crtc_state,
+ struct intel_plane *plane)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+
+ return DISPLAY_VER(i915) >= 13 &&
+ crtc_state->uapi.async_flip &&
+ plane->async_flip;
+}
+
static bool use_minimal_wm0_only(const struct intel_crtc_state *crtc_state,
struct intel_plane *plane)
{
@@ -5002,6 +5012,7 @@ static u64
icl_get_total_relative_data_rate(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
const struct intel_plane_state *plane_state;
@@ -5043,8 +5054,15 @@ icl_get_total_relative_data_rate(struct intel_atomic_state *state,
}
}
- for_each_plane_id_on_crtc(crtc, plane_id)
- total_data_rate += crtc_state->plane_data_rate[plane_id];
+ for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
+ /*
+ * We calculate extra ddb based on ratio plane rate/total data rate
+ * in case, in some cases we should not allocate extra ddb for the plane,
+ * so do not count its data rate, if this is the case.
+ */
+ if (!use_min_ddb(crtc_state, plane))
+ total_data_rate += crtc_state->plane_data_rate[plane->id];
+ }
return total_data_rate;
}
@@ -5130,6 +5148,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
u16 alloc_size, start = 0;
u16 total[I915_MAX_PLANES] = {};
u16 uv_total[I915_MAX_PLANES] = {};
+ struct intel_plane *plane;
u64 total_data_rate;
enum plane_id plane_id;
u32 blocks;
@@ -5206,7 +5225,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
* watermark level, plus an extra share of the leftover blocks
* proportional to its relative data rate.
*/
- for_each_plane_id_on_crtc(crtc, plane_id) {
+ for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
const struct skl_plane_wm *wm =
&crtc_state->wm.skl.optimal.planes[plane_id];
u64 rate;
@@ -5222,10 +5241,15 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
if (total_data_rate == 0)
break;
- rate = crtc_state->plane_data_rate[plane_id];
+ if (use_min_ddb(crtc_state, plane))
+ rate = 0;
+ else
+ rate = crtc_state->plane_data_rate[plane_id];
+
extra = min_t(u16, alloc_size,
DIV64_U64_ROUND_UP(alloc_size * rate,
total_data_rate));
+
total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
alloc_size -= extra;
total_data_rate -= rate;
@@ -5233,14 +5257,20 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
if (total_data_rate == 0)
break;
- rate = crtc_state->uv_plane_data_rate[plane_id];
+ if (use_min_ddb(crtc_state, plane))
+ rate = 0;
+ else
+ rate = crtc_state->uv_plane_data_rate[plane_id];
+
extra = min_t(u16, alloc_size,
DIV64_U64_ROUND_UP(alloc_size * rate,
total_data_rate));
+
uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
alloc_size -= extra;
total_data_rate -= rate;
}
+
drm_WARN_ON(&dev_priv->drm, alloc_size != 0 || total_data_rate != 0);
/* Set the actual DDB start/end points for each plane */
--
2.24.1.485.gad05a3d8e5
^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip for DG2
2022-01-24 9:16 ` Ville Syrjälä
@ 2022-01-24 9:29 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 32+ messages in thread
From: Lisovskiy, Stanislav @ 2022-01-24 9:29 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Mon, Jan 24, 2022 at 11:16:36AM +0200, Ville Syrjälä wrote:
> On Mon, Jan 24, 2022 at 11:06:53AM +0200, Stanislav Lisovskiy wrote:
> > In terms of async flip optimization we don't to allocate
> > extra ddb space, so lets skip it.
> >
> > v2: - Extracted min ddb async flip check to separate function
> > (Ville Syrjälä)
> > - Used this function to prevent false positive WARN
> > to be triggered(Ville Syrjälä)
> >
> > v3: - Renamed dg2_need_min_ddb to need_min_ddb thus making
> > it more universal.
> > - Also used DISPLAY_VER instead of IS_DG2(Ville Syrjälä)
> > - Use rate = 0 instead of just setting extra = 0, thus
> > letting other planes to use extra ddb and avoiding WARN
> > (Ville Syrjälä)
> >
> > v4: - Renamed needs_min_ddb as s/needs/use/ to match
> > the wm0 counterpart(Ville Syrjälä)
> > - Added plane->async_flip check to use_min_ddb(now
> > passing plane as a parameter to do that)(Ville Syrjälä)
> > - Account for use_min_ddb also when calculating total data rate
> > (Ville Syrjälä)
> >
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > ---
> > .../gpu/drm/i915/display/intel_atomic_plane.c | 2 +-
> > .../gpu/drm/i915/display/intel_atomic_plane.h | 3 +-
> > drivers/gpu/drm/i915/intel_pm.c | 53 ++++++++++++++-----
> > 3 files changed, 44 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > index b20cf2c16691..9d79ab987b2e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > @@ -374,7 +374,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
> > old_plane_state, new_plane_state);
> > }
> >
> > -static struct intel_plane *
> > +struct intel_plane *
> > intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id)
> > {
> > struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> > index ead789709477..aaddcc636f98 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> > @@ -23,7 +23,8 @@ unsigned int intel_adjusted_rate(const struct drm_rect *src,
> > unsigned int rate);
> > unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
> > const struct intel_plane_state *plane_state);
> > -
> > +struct intel_plane *intel_crtc_get_plane(struct intel_crtc *crtc,
> > + enum plane_id plane_id);
> > unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
> > const struct intel_plane_state *plane_state);
> > void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 8269f1e9c784..fbe6a45801bc 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4988,6 +4988,25 @@ skl_get_total_relative_data_rate(struct intel_atomic_state *state,
> > return total_data_rate;
> > }
> >
> > +static bool use_min_ddb(struct intel_crtc_state *crtc_state,
> > + struct intel_plane *plane)
> > +{
> > + struct drm_i915_private *i915 = to_i915(plane->base.dev);
> > +
> > + return DISPLAY_VER(i915) >= 13 && crtc_state->uapi.async_flip &&
> > + plane->async_flip;
> > +}
> > +
> > +static bool use_minimal_wm0_only(const struct intel_crtc_state *crtc_state,
> > + struct intel_plane *plane)
>
> Please put this function into the right spot to begin with.
> Avoids polluting this patch with unrelated code movement.
It happened this way, because initially use_minimal_wm0_only which
is needed only by skl_compute_plane_wm was much lower, however as
you recommended to group it with use_min_ddb, so had to move it higher,
because use_min_ddb is required way higher in the file.
However I will then change the patch where it was introduced, so that
its already there.
>
> > +{
> > + struct drm_i915_private *i915 = to_i915(plane->base.dev);
> > +
> > + return DISPLAY_VER(i915) >= 13 &&
> > + crtc_state->uapi.async_flip &&
> > + plane->async_flip;
>
> Line wrapping is different between the two functions despite the
> identical contents, which looks a bit weird.
>
> > +}
> > +
> > static u64
> > icl_get_total_relative_data_rate(struct intel_atomic_state *state,
> > struct intel_crtc *crtc)
> > @@ -5033,8 +5052,15 @@ icl_get_total_relative_data_rate(struct intel_atomic_state *state,
> > }
> > }
> >
> > - for_each_plane_id_on_crtc(crtc, plane_id)
> > - total_data_rate += crtc_state->plane_data_rate[plane_id];
> > + for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
>
> for_each_intel_plane_on_crtc() otherwise we miss all
> the planes not in the state.
Right, we recalculate those which changed first, then get total data rate.
For some reason I was looking at first cycle so just took same macro.
>
> > + /*
> > + * We calculate extra ddb based on ratio plane rate/total data rate
> > + * in case, in some cases we should not allocate extra ddb for the plane,
> > + * so do not count its data rate, if this is the case.
> > + */
> > + if (!use_min_ddb(crtc_state, plane))
> > + total_data_rate += crtc_state->plane_data_rate[plane->id];
> > + }
> >
> > return total_data_rate;
> > }
> > @@ -5199,6 +5225,8 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
> > for_each_plane_id_on_crtc(crtc, plane_id) {
>
> for_each_intel_plane_on_crtc()...
>
> > const struct skl_plane_wm *wm =
> > &crtc_state->wm.skl.optimal.planes[plane_id];
> > + struct intel_plane *plane =
> > + intel_crtc_get_plane(crtc, plane_id);
>
> ... avoids needing that function.
>
> > u64 rate;
> > u16 extra;
> >
> > @@ -5213,9 +5241,14 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
> > break;
> >
> > rate = crtc_state->plane_data_rate[plane_id];
> > +
> > + if (use_min_ddb(crtc_state, plane))
> > + rate = 0;
>
> else
> rate = crtc_state->plane_data_rate[plane_id];
>
> is how I'd write that probably.
>
> > +
> > extra = min_t(u16, alloc_size,
> > DIV64_U64_ROUND_UP(alloc_size * rate,
> > total_data_rate));
> > +
> > total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
> > alloc_size -= extra;
> > total_data_rate -= rate;
> > @@ -5224,13 +5257,19 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
> > break;
> >
> > rate = crtc_state->uv_plane_data_rate[plane_id];
> > +
> > + if (use_min_ddb(crtc_state, plane))
> > + rate = 0;
> > +
> > extra = min_t(u16, alloc_size,
> > DIV64_U64_ROUND_UP(alloc_size * rate,
> > total_data_rate));
> > +
> > uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
> > alloc_size -= extra;
> > total_data_rate -= rate;
> > }
> > +
> > drm_WARN_ON(&dev_priv->drm, alloc_size != 0 || total_data_rate != 0);
> >
> > /* Set the actual DDB start/end points for each plane */
> > @@ -5497,16 +5536,6 @@ static int skl_wm_max_lines(struct drm_i915_private *dev_priv)
> > return 31;
> > }
> >
> > -static bool use_minimal_wm0_only(const struct intel_crtc_state *crtc_state,
> > - struct intel_plane *plane)
> > -{
> > - struct drm_i915_private *i915 = to_i915(plane->base.dev);
> > -
> > - return DISPLAY_VER(i915) >= 13 &&
> > - crtc_state->uapi.async_flip &&
> > - plane->async_flip;
> > -}
> > -
> > static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> > struct intel_plane *plane,
> > int level,
> > --
> > 2.24.1.485.gad05a3d8e5
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip for DG2
2022-01-24 9:06 ` [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip " Stanislav Lisovskiy
@ 2022-01-24 9:16 ` Ville Syrjälä
2022-01-24 9:29 ` Lisovskiy, Stanislav
2022-01-24 9:51 ` Stanislav Lisovskiy
2022-01-24 13:52 ` Stanislav Lisovskiy
2 siblings, 1 reply; 32+ messages in thread
From: Ville Syrjälä @ 2022-01-24 9:16 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
On Mon, Jan 24, 2022 at 11:06:53AM +0200, Stanislav Lisovskiy wrote:
> In terms of async flip optimization we don't to allocate
> extra ddb space, so lets skip it.
>
> v2: - Extracted min ddb async flip check to separate function
> (Ville Syrjälä)
> - Used this function to prevent false positive WARN
> to be triggered(Ville Syrjälä)
>
> v3: - Renamed dg2_need_min_ddb to need_min_ddb thus making
> it more universal.
> - Also used DISPLAY_VER instead of IS_DG2(Ville Syrjälä)
> - Use rate = 0 instead of just setting extra = 0, thus
> letting other planes to use extra ddb and avoiding WARN
> (Ville Syrjälä)
>
> v4: - Renamed needs_min_ddb as s/needs/use/ to match
> the wm0 counterpart(Ville Syrjälä)
> - Added plane->async_flip check to use_min_ddb(now
> passing plane as a parameter to do that)(Ville Syrjälä)
> - Account for use_min_ddb also when calculating total data rate
> (Ville Syrjälä)
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> .../gpu/drm/i915/display/intel_atomic_plane.c | 2 +-
> .../gpu/drm/i915/display/intel_atomic_plane.h | 3 +-
> drivers/gpu/drm/i915/intel_pm.c | 53 ++++++++++++++-----
> 3 files changed, 44 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index b20cf2c16691..9d79ab987b2e 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -374,7 +374,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
> old_plane_state, new_plane_state);
> }
>
> -static struct intel_plane *
> +struct intel_plane *
> intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id)
> {
> struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> index ead789709477..aaddcc636f98 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> @@ -23,7 +23,8 @@ unsigned int intel_adjusted_rate(const struct drm_rect *src,
> unsigned int rate);
> unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state);
> -
> +struct intel_plane *intel_crtc_get_plane(struct intel_crtc *crtc,
> + enum plane_id plane_id);
> unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state);
> void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 8269f1e9c784..fbe6a45801bc 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4988,6 +4988,25 @@ skl_get_total_relative_data_rate(struct intel_atomic_state *state,
> return total_data_rate;
> }
>
> +static bool use_min_ddb(struct intel_crtc_state *crtc_state,
> + struct intel_plane *plane)
> +{
> + struct drm_i915_private *i915 = to_i915(plane->base.dev);
> +
> + return DISPLAY_VER(i915) >= 13 && crtc_state->uapi.async_flip &&
> + plane->async_flip;
> +}
> +
> +static bool use_minimal_wm0_only(const struct intel_crtc_state *crtc_state,
> + struct intel_plane *plane)
Please put this function into the right spot to begin with.
Avoids polluting this patch with unrelated code movement.
> +{
> + struct drm_i915_private *i915 = to_i915(plane->base.dev);
> +
> + return DISPLAY_VER(i915) >= 13 &&
> + crtc_state->uapi.async_flip &&
> + plane->async_flip;
Line wrapping is different between the two functions despite the
identical contents, which looks a bit weird.
> +}
> +
> static u64
> icl_get_total_relative_data_rate(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> @@ -5033,8 +5052,15 @@ icl_get_total_relative_data_rate(struct intel_atomic_state *state,
> }
> }
>
> - for_each_plane_id_on_crtc(crtc, plane_id)
> - total_data_rate += crtc_state->plane_data_rate[plane_id];
> + for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
for_each_intel_plane_on_crtc() otherwise we miss all
the planes not in the state.
> + /*
> + * We calculate extra ddb based on ratio plane rate/total data rate
> + * in case, in some cases we should not allocate extra ddb for the plane,
> + * so do not count its data rate, if this is the case.
> + */
> + if (!use_min_ddb(crtc_state, plane))
> + total_data_rate += crtc_state->plane_data_rate[plane->id];
> + }
>
> return total_data_rate;
> }
> @@ -5199,6 +5225,8 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
> for_each_plane_id_on_crtc(crtc, plane_id) {
for_each_intel_plane_on_crtc()...
> const struct skl_plane_wm *wm =
> &crtc_state->wm.skl.optimal.planes[plane_id];
> + struct intel_plane *plane =
> + intel_crtc_get_plane(crtc, plane_id);
... avoids needing that function.
> u64 rate;
> u16 extra;
>
> @@ -5213,9 +5241,14 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
> break;
>
> rate = crtc_state->plane_data_rate[plane_id];
> +
> + if (use_min_ddb(crtc_state, plane))
> + rate = 0;
else
rate = crtc_state->plane_data_rate[plane_id];
is how I'd write that probably.
> +
> extra = min_t(u16, alloc_size,
> DIV64_U64_ROUND_UP(alloc_size * rate,
> total_data_rate));
> +
> total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
> alloc_size -= extra;
> total_data_rate -= rate;
> @@ -5224,13 +5257,19 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
> break;
>
> rate = crtc_state->uv_plane_data_rate[plane_id];
> +
> + if (use_min_ddb(crtc_state, plane))
> + rate = 0;
> +
> extra = min_t(u16, alloc_size,
> DIV64_U64_ROUND_UP(alloc_size * rate,
> total_data_rate));
> +
> uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
> alloc_size -= extra;
> total_data_rate -= rate;
> }
> +
> drm_WARN_ON(&dev_priv->drm, alloc_size != 0 || total_data_rate != 0);
>
> /* Set the actual DDB start/end points for each plane */
> @@ -5497,16 +5536,6 @@ static int skl_wm_max_lines(struct drm_i915_private *dev_priv)
> return 31;
> }
>
> -static bool use_minimal_wm0_only(const struct intel_crtc_state *crtc_state,
> - struct intel_plane *plane)
> -{
> - struct drm_i915_private *i915 = to_i915(plane->base.dev);
> -
> - return DISPLAY_VER(i915) >= 13 &&
> - crtc_state->uapi.async_flip &&
> - plane->async_flip;
> -}
> -
> static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> struct intel_plane *plane,
> int level,
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip for DG2
2022-01-24 9:06 [Intel-gfx] [PATCH 0/4] Async flip optimization for DG2 Stanislav Lisovskiy
@ 2022-01-24 9:06 ` Stanislav Lisovskiy
2022-01-24 9:16 ` Ville Syrjälä
` (2 more replies)
0 siblings, 3 replies; 32+ messages in thread
From: Stanislav Lisovskiy @ 2022-01-24 9:06 UTC (permalink / raw)
To: intel-gfx
In terms of async flip optimization we don't to allocate
extra ddb space, so lets skip it.
v2: - Extracted min ddb async flip check to separate function
(Ville Syrjälä)
- Used this function to prevent false positive WARN
to be triggered(Ville Syrjälä)
v3: - Renamed dg2_need_min_ddb to need_min_ddb thus making
it more universal.
- Also used DISPLAY_VER instead of IS_DG2(Ville Syrjälä)
- Use rate = 0 instead of just setting extra = 0, thus
letting other planes to use extra ddb and avoiding WARN
(Ville Syrjälä)
v4: - Renamed needs_min_ddb as s/needs/use/ to match
the wm0 counterpart(Ville Syrjälä)
- Added plane->async_flip check to use_min_ddb(now
passing plane as a parameter to do that)(Ville Syrjälä)
- Account for use_min_ddb also when calculating total data rate
(Ville Syrjälä)
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 2 +-
.../gpu/drm/i915/display/intel_atomic_plane.h | 3 +-
drivers/gpu/drm/i915/intel_pm.c | 53 ++++++++++++++-----
3 files changed, 44 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index b20cf2c16691..9d79ab987b2e 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -374,7 +374,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
old_plane_state, new_plane_state);
}
-static struct intel_plane *
+struct intel_plane *
intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id)
{
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index ead789709477..aaddcc636f98 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -23,7 +23,8 @@ unsigned int intel_adjusted_rate(const struct drm_rect *src,
unsigned int rate);
unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
-
+struct intel_plane *intel_crtc_get_plane(struct intel_crtc *crtc,
+ enum plane_id plane_id);
unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8269f1e9c784..fbe6a45801bc 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4988,6 +4988,25 @@ skl_get_total_relative_data_rate(struct intel_atomic_state *state,
return total_data_rate;
}
+static bool use_min_ddb(struct intel_crtc_state *crtc_state,
+ struct intel_plane *plane)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+
+ return DISPLAY_VER(i915) >= 13 && crtc_state->uapi.async_flip &&
+ plane->async_flip;
+}
+
+static bool use_minimal_wm0_only(const struct intel_crtc_state *crtc_state,
+ struct intel_plane *plane)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+
+ return DISPLAY_VER(i915) >= 13 &&
+ crtc_state->uapi.async_flip &&
+ plane->async_flip;
+}
+
static u64
icl_get_total_relative_data_rate(struct intel_atomic_state *state,
struct intel_crtc *crtc)
@@ -5033,8 +5052,15 @@ icl_get_total_relative_data_rate(struct intel_atomic_state *state,
}
}
- for_each_plane_id_on_crtc(crtc, plane_id)
- total_data_rate += crtc_state->plane_data_rate[plane_id];
+ for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
+ /*
+ * We calculate extra ddb based on ratio plane rate/total data rate
+ * in case, in some cases we should not allocate extra ddb for the plane,
+ * so do not count its data rate, if this is the case.
+ */
+ if (!use_min_ddb(crtc_state, plane))
+ total_data_rate += crtc_state->plane_data_rate[plane->id];
+ }
return total_data_rate;
}
@@ -5199,6 +5225,8 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
for_each_plane_id_on_crtc(crtc, plane_id) {
const struct skl_plane_wm *wm =
&crtc_state->wm.skl.optimal.planes[plane_id];
+ struct intel_plane *plane =
+ intel_crtc_get_plane(crtc, plane_id);
u64 rate;
u16 extra;
@@ -5213,9 +5241,14 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
break;
rate = crtc_state->plane_data_rate[plane_id];
+
+ if (use_min_ddb(crtc_state, plane))
+ rate = 0;
+
extra = min_t(u16, alloc_size,
DIV64_U64_ROUND_UP(alloc_size * rate,
total_data_rate));
+
total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
alloc_size -= extra;
total_data_rate -= rate;
@@ -5224,13 +5257,19 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
break;
rate = crtc_state->uv_plane_data_rate[plane_id];
+
+ if (use_min_ddb(crtc_state, plane))
+ rate = 0;
+
extra = min_t(u16, alloc_size,
DIV64_U64_ROUND_UP(alloc_size * rate,
total_data_rate));
+
uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
alloc_size -= extra;
total_data_rate -= rate;
}
+
drm_WARN_ON(&dev_priv->drm, alloc_size != 0 || total_data_rate != 0);
/* Set the actual DDB start/end points for each plane */
@@ -5497,16 +5536,6 @@ static int skl_wm_max_lines(struct drm_i915_private *dev_priv)
return 31;
}
-static bool use_minimal_wm0_only(const struct intel_crtc_state *crtc_state,
- struct intel_plane *plane)
-{
- struct drm_i915_private *i915 = to_i915(plane->base.dev);
-
- return DISPLAY_VER(i915) >= 13 &&
- crtc_state->uapi.async_flip &&
- plane->async_flip;
-}
-
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
struct intel_plane *plane,
int level,
--
2.24.1.485.gad05a3d8e5
^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip for DG2
2022-01-23 20:34 ` Lisovskiy, Stanislav
@ 2022-01-24 7:42 ` Ville Syrjälä
0 siblings, 0 replies; 32+ messages in thread
From: Ville Syrjälä @ 2022-01-24 7:42 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
On Sun, Jan 23, 2022 at 10:34:17PM +0200, Lisovskiy, Stanislav wrote:
> On Fri, Jan 21, 2022 at 02:06:12PM +0200, Ville Syrjälä wrote:
> > On Fri, Jan 21, 2022 at 10:06:15AM +0200, Stanislav Lisovskiy wrote:
> > > In terms of async flip optimization we don't to allocate
> > > extra ddb space, so lets skip it.
> > >
> > > v2: - Extracted min ddb async flip check to separate function
> > > (Ville Syrjälä)
> > > - Used this function to prevent false positive WARN
> > > to be triggered(Ville Syrjälä)
> > >
> > > v3: - Renamed dg2_need_min_ddb to need_min_ddb thus making
> > > it more universal.
> > > - Also used DISPLAY_VER instead of IS_DG2(Ville Syrjälä)
> > > - Use rate = 0 instead of just setting extra = 0, thus
> > > letting other planes to use extra ddb and avoiding WARN
> > > (Ville Syrjälä)
> > >
> > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/intel_pm.c | 17 +++++++++++++++++
> > > 1 file changed, 17 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > index 5fb022a2a4d7..18fb35c480ef 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -5118,6 +5118,12 @@ static bool icl_need_wm1_wa(struct drm_i915_private *i915,
> > > (IS_DISPLAY_VER(i915, 12, 13) && plane_id == PLANE_CURSOR);
> > > }
> > >
> > > +static bool needs_min_ddb(struct drm_i915_private *i915,
> > > + struct intel_crtc_state *crtc_state)
> >
> > s/needs/use/ to match the wm0 counterpart?
> >
> > Could use a comment as well perhaps, or maybe just put this right
> > next to the wm0 counterpart so the reader can see both together and
> > make the connection.
> >
> > Hmm. Actually I think this would also need the plane->async_flip
> > check here too or else we'll drop all the planes to min ddb
> > instead of just the plane doing async flips.
> >
> > Oh, and I think we need this same thing when calculating the
> > total_data_rate or else the numbers won't match.
>
> Yes, there seems to be a problem with that approach, we use ratio
> from data plane_data_rate/total_data_rate to determine how we split
> extra ddb blocks, however if plane data rate can be just set as 0
> here localle, total_data_rate is obtained from crtc_state->plane_data_rate,
> which is being calculated first.
> So if we trick icl_get_total_relative_data_rate function to calculate
> total_data_rate corresponding to rate = 0, we will then have
> crtc_state->plane_data_rate[plane_id] set to 0, which is probably
> not what we want.
These are just the relative data rates so they're not actually used for
anything else. So I guess we could even set them to 0. Though I don't
even recall if the current code really works or not. I think there
might have been some problem with calculating these that I perhaps fixed
with my latest ddb series (or maybe I already fixed it with some earlier
series, can't remember anymore).
>
> Or should I just edit icl_get_total_relative_data_rate so that it
> still calculates crtc_state->plane_data_rate properly however, the
> doesn't add those to total_data_rate, if use_min_ddb(plane) is set?
This should work too. Can't immediately think why one approach would
be strictly better than the other.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip for DG2
2022-01-21 12:06 ` Ville Syrjälä
@ 2022-01-23 20:34 ` Lisovskiy, Stanislav
2022-01-24 7:42 ` Ville Syrjälä
0 siblings, 1 reply; 32+ messages in thread
From: Lisovskiy, Stanislav @ 2022-01-23 20:34 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Fri, Jan 21, 2022 at 02:06:12PM +0200, Ville Syrjälä wrote:
> On Fri, Jan 21, 2022 at 10:06:15AM +0200, Stanislav Lisovskiy wrote:
> > In terms of async flip optimization we don't to allocate
> > extra ddb space, so lets skip it.
> >
> > v2: - Extracted min ddb async flip check to separate function
> > (Ville Syrjälä)
> > - Used this function to prevent false positive WARN
> > to be triggered(Ville Syrjälä)
> >
> > v3: - Renamed dg2_need_min_ddb to need_min_ddb thus making
> > it more universal.
> > - Also used DISPLAY_VER instead of IS_DG2(Ville Syrjälä)
> > - Use rate = 0 instead of just setting extra = 0, thus
> > letting other planes to use extra ddb and avoiding WARN
> > (Ville Syrjälä)
> >
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 17 +++++++++++++++++
> > 1 file changed, 17 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 5fb022a2a4d7..18fb35c480ef 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -5118,6 +5118,12 @@ static bool icl_need_wm1_wa(struct drm_i915_private *i915,
> > (IS_DISPLAY_VER(i915, 12, 13) && plane_id == PLANE_CURSOR);
> > }
> >
> > +static bool needs_min_ddb(struct drm_i915_private *i915,
> > + struct intel_crtc_state *crtc_state)
>
> s/needs/use/ to match the wm0 counterpart?
>
> Could use a comment as well perhaps, or maybe just put this right
> next to the wm0 counterpart so the reader can see both together and
> make the connection.
>
> Hmm. Actually I think this would also need the plane->async_flip
> check here too or else we'll drop all the planes to min ddb
> instead of just the plane doing async flips.
>
> Oh, and I think we need this same thing when calculating the
> total_data_rate or else the numbers won't match.
Yes, there seems to be a problem with that approach, we use ratio
from data plane_data_rate/total_data_rate to determine how we split
extra ddb blocks, however if plane data rate can be just set as 0
here localle, total_data_rate is obtained from crtc_state->plane_data_rate,
which is being calculated first.
So if we trick icl_get_total_relative_data_rate function to calculate
total_data_rate corresponding to rate = 0, we will then have
crtc_state->plane_data_rate[plane_id] set to 0, which is probably
not what we want.
Or should I just edit icl_get_total_relative_data_rate so that it
still calculates crtc_state->plane_data_rate properly however, the
doesn't add those to total_data_rate, if use_min_ddb(plane) is set?
Stan
>
> > +{
> > + return DISPLAY_VER(i915) >= 13 && crtc_state->uapi.async_flip;
> > +}
> > +
> > static int
> > skl_allocate_plane_ddb(struct intel_atomic_state *state,
> > struct intel_crtc *crtc)
> > @@ -5225,9 +5231,14 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
> > break;
> >
> > rate = crtc_state->plane_data_rate[plane_id];
> > +
> > + if (needs_min_ddb(dev_priv, crtc_state))
> > + rate = 0;
> > +
> > extra = min_t(u16, alloc_size,
> > DIV64_U64_ROUND_UP(alloc_size * rate,
> > total_data_rate));
> > +
> > total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
> > alloc_size -= extra;
> > total_data_rate -= rate;
> > @@ -5236,13 +5247,19 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
> > break;
> >
> > rate = crtc_state->uv_plane_data_rate[plane_id];
> > +
> > + if (needs_min_ddb(dev_priv, crtc_state))
> > + rate = 0;
> > +
> > extra = min_t(u16, alloc_size,
> > DIV64_U64_ROUND_UP(alloc_size * rate,
> > total_data_rate));
> > +
> > uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
> > alloc_size -= extra;
> > total_data_rate -= rate;
> > }
> > +
> > drm_WARN_ON(&dev_priv->drm, alloc_size != 0 || total_data_rate != 0);
> >
> > /* Set the actual DDB start/end points for each plane */
> > --
> > 2.24.1.485.gad05a3d8e5
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip for DG2
2022-01-21 8:06 ` [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip " Stanislav Lisovskiy
@ 2022-01-21 12:06 ` Ville Syrjälä
2022-01-23 20:34 ` Lisovskiy, Stanislav
0 siblings, 1 reply; 32+ messages in thread
From: Ville Syrjälä @ 2022-01-21 12:06 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
On Fri, Jan 21, 2022 at 10:06:15AM +0200, Stanislav Lisovskiy wrote:
> In terms of async flip optimization we don't to allocate
> extra ddb space, so lets skip it.
>
> v2: - Extracted min ddb async flip check to separate function
> (Ville Syrjälä)
> - Used this function to prevent false positive WARN
> to be triggered(Ville Syrjälä)
>
> v3: - Renamed dg2_need_min_ddb to need_min_ddb thus making
> it more universal.
> - Also used DISPLAY_VER instead of IS_DG2(Ville Syrjälä)
> - Use rate = 0 instead of just setting extra = 0, thus
> letting other planes to use extra ddb and avoiding WARN
> (Ville Syrjälä)
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 5fb022a2a4d7..18fb35c480ef 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5118,6 +5118,12 @@ static bool icl_need_wm1_wa(struct drm_i915_private *i915,
> (IS_DISPLAY_VER(i915, 12, 13) && plane_id == PLANE_CURSOR);
> }
>
> +static bool needs_min_ddb(struct drm_i915_private *i915,
> + struct intel_crtc_state *crtc_state)
s/needs/use/ to match the wm0 counterpart?
Could use a comment as well perhaps, or maybe just put this right
next to the wm0 counterpart so the reader can see both together and
make the connection.
Hmm. Actually I think this would also need the plane->async_flip
check here too or else we'll drop all the planes to min ddb
instead of just the plane doing async flips.
Oh, and I think we need this same thing when calculating the
total_data_rate or else the numbers won't match.
> +{
> + return DISPLAY_VER(i915) >= 13 && crtc_state->uapi.async_flip;
> +}
> +
> static int
> skl_allocate_plane_ddb(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> @@ -5225,9 +5231,14 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
> break;
>
> rate = crtc_state->plane_data_rate[plane_id];
> +
> + if (needs_min_ddb(dev_priv, crtc_state))
> + rate = 0;
> +
> extra = min_t(u16, alloc_size,
> DIV64_U64_ROUND_UP(alloc_size * rate,
> total_data_rate));
> +
> total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
> alloc_size -= extra;
> total_data_rate -= rate;
> @@ -5236,13 +5247,19 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
> break;
>
> rate = crtc_state->uv_plane_data_rate[plane_id];
> +
> + if (needs_min_ddb(dev_priv, crtc_state))
> + rate = 0;
> +
> extra = min_t(u16, alloc_size,
> DIV64_U64_ROUND_UP(alloc_size * rate,
> total_data_rate));
> +
> uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
> alloc_size -= extra;
> total_data_rate -= rate;
> }
> +
> drm_WARN_ON(&dev_priv->drm, alloc_size != 0 || total_data_rate != 0);
>
> /* Set the actual DDB start/end points for each plane */
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip for DG2
2022-01-21 8:06 [Intel-gfx] [PATCH 0/4] Async flip optimization " Stanislav Lisovskiy
@ 2022-01-21 8:06 ` Stanislav Lisovskiy
2022-01-21 12:06 ` Ville Syrjälä
0 siblings, 1 reply; 32+ messages in thread
From: Stanislav Lisovskiy @ 2022-01-21 8:06 UTC (permalink / raw)
To: intel-gfx
In terms of async flip optimization we don't to allocate
extra ddb space, so lets skip it.
v2: - Extracted min ddb async flip check to separate function
(Ville Syrjälä)
- Used this function to prevent false positive WARN
to be triggered(Ville Syrjälä)
v3: - Renamed dg2_need_min_ddb to need_min_ddb thus making
it more universal.
- Also used DISPLAY_VER instead of IS_DG2(Ville Syrjälä)
- Use rate = 0 instead of just setting extra = 0, thus
letting other planes to use extra ddb and avoiding WARN
(Ville Syrjälä)
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5fb022a2a4d7..18fb35c480ef 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5118,6 +5118,12 @@ static bool icl_need_wm1_wa(struct drm_i915_private *i915,
(IS_DISPLAY_VER(i915, 12, 13) && plane_id == PLANE_CURSOR);
}
+static bool needs_min_ddb(struct drm_i915_private *i915,
+ struct intel_crtc_state *crtc_state)
+{
+ return DISPLAY_VER(i915) >= 13 && crtc_state->uapi.async_flip;
+}
+
static int
skl_allocate_plane_ddb(struct intel_atomic_state *state,
struct intel_crtc *crtc)
@@ -5225,9 +5231,14 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
break;
rate = crtc_state->plane_data_rate[plane_id];
+
+ if (needs_min_ddb(dev_priv, crtc_state))
+ rate = 0;
+
extra = min_t(u16, alloc_size,
DIV64_U64_ROUND_UP(alloc_size * rate,
total_data_rate));
+
total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
alloc_size -= extra;
total_data_rate -= rate;
@@ -5236,13 +5247,19 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
break;
rate = crtc_state->uv_plane_data_rate[plane_id];
+
+ if (needs_min_ddb(dev_priv, crtc_state))
+ rate = 0;
+
extra = min_t(u16, alloc_size,
DIV64_U64_ROUND_UP(alloc_size * rate,
total_data_rate));
+
uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
alloc_size -= extra;
total_data_rate -= rate;
}
+
drm_WARN_ON(&dev_priv->drm, alloc_size != 0 || total_data_rate != 0);
/* Set the actual DDB start/end points for each plane */
--
2.24.1.485.gad05a3d8e5
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip for DG2
2021-12-07 11:07 [Intel-gfx] [PATCH 1/4] drm/i915: Pass plane to watermark calculation functions Stanislav Lisovskiy
@ 2021-12-07 11:07 ` Stanislav Lisovskiy
0 siblings, 0 replies; 32+ messages in thread
From: Stanislav Lisovskiy @ 2021-12-07 11:07 UTC (permalink / raw)
To: intel-gfx
In terms of async flip optimization we don't to allocate
extra ddb space, so lets skip it.
v2: - Extracted min ddb async flip check to separate function
(Ville Syrjälä)
- Used this function to prevent false positive WARN
to be triggered(Ville Syrjälä)
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 34 ++++++++++++++++++++++++++-------
1 file changed, 27 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a529a116164e..619131de5d93 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5105,6 +5105,12 @@ static bool icl_need_wm1_wa(struct drm_i915_private *i915,
(IS_DISPLAY_VER(i915, 12, 13) && plane_id == PLANE_CURSOR);
}
+static bool dg2_need_min_ddb(struct drm_i915_private *i915,
+ struct intel_crtc_state *crtc_state)
+{
+ return IS_DG2(i915) && crtc_state->uapi.async_flip;
+}
+
static int
skl_allocate_plane_ddb(struct intel_atomic_state *state,
struct intel_crtc *crtc)
@@ -5213,9 +5219,15 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
break;
rate = crtc_state->plane_data_rate[plane_id];
- extra = min_t(u16, alloc_size,
- DIV64_U64_ROUND_UP(alloc_size * rate,
- total_data_rate));
+
+ if (dg2_need_min_ddb(dev_priv, crtc_state)) {
+ extra = 0;
+ } else {
+ extra = min_t(u16, alloc_size,
+ DIV64_U64_ROUND_UP(alloc_size * rate,
+ total_data_rate));
+ }
+
total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
alloc_size -= extra;
total_data_rate -= rate;
@@ -5224,14 +5236,22 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
break;
rate = crtc_state->uv_plane_data_rate[plane_id];
- extra = min_t(u16, alloc_size,
- DIV64_U64_ROUND_UP(alloc_size * rate,
- total_data_rate));
+
+ if (dg2_need_min_ddb(dev_priv, crtc_state)) {
+ extra = 0;
+ } else {
+ extra = min_t(u16, alloc_size,
+ DIV64_U64_ROUND_UP(alloc_size * rate,
+ total_data_rate));
+ }
+
uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
alloc_size -= extra;
total_data_rate -= rate;
}
- drm_WARN_ON(&dev_priv->drm, alloc_size != 0 || total_data_rate != 0);
+
+ if (!dg2_need_min_ddb(dev_priv, crtc_state))
+ drm_WARN_ON(&dev_priv->drm, alloc_size != 0 || total_data_rate != 0);
/* Set the actual DDB start/end points for each plane */
start = alloc->start;
--
2.24.1.485.gad05a3d8e5
^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip for DG2
2021-12-03 10:03 ` Ville Syrjälä
@ 2021-12-03 10:17 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 32+ messages in thread
From: Lisovskiy, Stanislav @ 2021-12-03 10:17 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, jani.saarinen
On Fri, Dec 03, 2021 at 12:03:41PM +0200, Ville Syrjälä wrote:
> On Fri, Dec 03, 2021 at 11:40:41AM +0200, Stanislav Lisovskiy wrote:
> > In terms of async flip optimization we don't to allocate
> > extra ddb space, so lets skip it.
> >
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 24 ++++++++++++++++++------
> > 1 file changed, 18 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 0b45d1d61d0f..e1594f43bb1b 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -5245,9 +5245,15 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
> > break;
> >
> > rate = crtc_state->plane_data_rate[plane_id];
> > - extra = min_t(u16, alloc_size,
> > - DIV64_U64_ROUND_UP(alloc_size * rate,
> > - total_data_rate));
> > +
> > + if (IS_DG2(dev_priv) && crtc_state->uapi.async_flip) {
>
> We should have a sensible function for this.
Agree, tbh was thinking about this as well.
>
> > + extra = 0;
>
> Aren't we going to get the WARN(alloc_size != 0) if this
> is the only enabled plane?
Actually true as well, I remember I did get this warn when
I was testing it.
I guess we shouldn't trigger WARN for that case then?
>
> > + } else {
> > + extra = min_t(u16, alloc_size,
> > + DIV64_U64_ROUND_UP(alloc_size * rate,
> > + total_data_rate));
> > + }
> > +
> > total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
> > alloc_size -= extra;
> > total_data_rate -= rate;
> > @@ -5256,9 +5262,15 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
> > break;
> >
> > rate = crtc_state->uv_plane_data_rate[plane_id];
> > - extra = min_t(u16, alloc_size,
> > - DIV64_U64_ROUND_UP(alloc_size * rate,
> > - total_data_rate));
> > +
> > + if (IS_DG2(dev_priv) && crtc_state->uapi.async_flip) {
> > + extra = 0;
> > + } else {
> > + extra = min_t(u16, alloc_size,
> > + DIV64_U64_ROUND_UP(alloc_size * rate,
> > + total_data_rate));
> > + }
> > +
> > uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
> > alloc_size -= extra;
> > total_data_rate -= rate;
> > --
> > 2.24.1.485.gad05a3d8e5
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip for DG2
2021-12-03 9:40 ` [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip for DG2 Stanislav Lisovskiy
@ 2021-12-03 10:03 ` Ville Syrjälä
2021-12-03 10:17 ` Lisovskiy, Stanislav
0 siblings, 1 reply; 32+ messages in thread
From: Ville Syrjälä @ 2021-12-03 10:03 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx, jani.saarinen
On Fri, Dec 03, 2021 at 11:40:41AM +0200, Stanislav Lisovskiy wrote:
> In terms of async flip optimization we don't to allocate
> extra ddb space, so lets skip it.
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 24 ++++++++++++++++++------
> 1 file changed, 18 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 0b45d1d61d0f..e1594f43bb1b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5245,9 +5245,15 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
> break;
>
> rate = crtc_state->plane_data_rate[plane_id];
> - extra = min_t(u16, alloc_size,
> - DIV64_U64_ROUND_UP(alloc_size * rate,
> - total_data_rate));
> +
> + if (IS_DG2(dev_priv) && crtc_state->uapi.async_flip) {
We should have a sensible function for this.
> + extra = 0;
Aren't we going to get the WARN(alloc_size != 0) if this
is the only enabled plane?
> + } else {
> + extra = min_t(u16, alloc_size,
> + DIV64_U64_ROUND_UP(alloc_size * rate,
> + total_data_rate));
> + }
> +
> total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
> alloc_size -= extra;
> total_data_rate -= rate;
> @@ -5256,9 +5262,15 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
> break;
>
> rate = crtc_state->uv_plane_data_rate[plane_id];
> - extra = min_t(u16, alloc_size,
> - DIV64_U64_ROUND_UP(alloc_size * rate,
> - total_data_rate));
> +
> + if (IS_DG2(dev_priv) && crtc_state->uapi.async_flip) {
> + extra = 0;
> + } else {
> + extra = min_t(u16, alloc_size,
> + DIV64_U64_ROUND_UP(alloc_size * rate,
> + total_data_rate));
> + }
> +
> uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
> alloc_size -= extra;
> total_data_rate -= rate;
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip for DG2
2021-12-03 9:40 [Intel-gfx] [PATCH 1/4] drm/i915: Pass plane id to watermark calculation functions Stanislav Lisovskiy
@ 2021-12-03 9:40 ` Stanislav Lisovskiy
2021-12-03 10:03 ` Ville Syrjälä
0 siblings, 1 reply; 32+ messages in thread
From: Stanislav Lisovskiy @ 2021-12-03 9:40 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.saarinen
In terms of async flip optimization we don't to allocate
extra ddb space, so lets skip it.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 24 ++++++++++++++++++------
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0b45d1d61d0f..e1594f43bb1b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5245,9 +5245,15 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
break;
rate = crtc_state->plane_data_rate[plane_id];
- extra = min_t(u16, alloc_size,
- DIV64_U64_ROUND_UP(alloc_size * rate,
- total_data_rate));
+
+ if (IS_DG2(dev_priv) && crtc_state->uapi.async_flip) {
+ extra = 0;
+ } else {
+ extra = min_t(u16, alloc_size,
+ DIV64_U64_ROUND_UP(alloc_size * rate,
+ total_data_rate));
+ }
+
total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
alloc_size -= extra;
total_data_rate -= rate;
@@ -5256,9 +5262,15 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
break;
rate = crtc_state->uv_plane_data_rate[plane_id];
- extra = min_t(u16, alloc_size,
- DIV64_U64_ROUND_UP(alloc_size * rate,
- total_data_rate));
+
+ if (IS_DG2(dev_priv) && crtc_state->uapi.async_flip) {
+ extra = 0;
+ } else {
+ extra = min_t(u16, alloc_size,
+ DIV64_U64_ROUND_UP(alloc_size * rate,
+ total_data_rate));
+ }
+
uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
alloc_size -= extra;
total_data_rate -= rate;
--
2.24.1.485.gad05a3d8e5
^ permalink raw reply related [flat|nested] 32+ messages in thread
end of thread, other threads:[~2022-01-25 11:36 UTC | newest]
Thread overview: 32+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-01-18 10:48 [Intel-gfx] [PATCH 0/4] Async flip optimization for DG2 Stanislav Lisovskiy
2022-01-18 10:48 ` [Intel-gfx] [PATCH 1/4] drm/i915: Pass plane to watermark calculation functions Stanislav Lisovskiy
2022-01-19 11:26 ` Ville Syrjälä
2022-01-18 10:48 ` [Intel-gfx] [PATCH 2/4] drm/i915: Introduce do_async_flip flag to intel_plane_state Stanislav Lisovskiy
2022-01-19 11:35 ` Ville Syrjälä
2022-01-18 10:48 ` [Intel-gfx] [PATCH 3/4] drm/i915: Use wm0 only during async flips for DG2 Stanislav Lisovskiy
2022-01-19 11:51 ` Ville Syrjälä
2022-01-18 10:48 ` [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip " Stanislav Lisovskiy
2022-01-19 11:59 ` Ville Syrjälä
2022-01-18 12:28 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Async flip optimization " Patchwork
2022-01-18 12:28 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-01-18 13:03 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-01-18 14:00 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Async flip optimization for DG2 (rev2) Patchwork
2022-01-18 14:01 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-01-18 14:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-01-18 16:55 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2022-01-24 9:06 [Intel-gfx] [PATCH 0/4] Async flip optimization for DG2 Stanislav Lisovskiy
2022-01-24 9:06 ` [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip " Stanislav Lisovskiy
2022-01-24 9:16 ` Ville Syrjälä
2022-01-24 9:29 ` Lisovskiy, Stanislav
2022-01-24 9:51 ` Stanislav Lisovskiy
2022-01-24 10:32 ` Ville Syrjälä
2022-01-24 13:52 ` Stanislav Lisovskiy
2022-01-24 18:55 ` Ville Syrjälä
2022-01-25 11:36 ` Lisovskiy, Stanislav
2022-01-21 8:06 [Intel-gfx] [PATCH 0/4] Async flip optimization " Stanislav Lisovskiy
2022-01-21 8:06 ` [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip " Stanislav Lisovskiy
2022-01-21 12:06 ` Ville Syrjälä
2022-01-23 20:34 ` Lisovskiy, Stanislav
2022-01-24 7:42 ` Ville Syrjälä
2021-12-07 11:07 [Intel-gfx] [PATCH 1/4] drm/i915: Pass plane to watermark calculation functions Stanislav Lisovskiy
2021-12-07 11:07 ` [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip for DG2 Stanislav Lisovskiy
2021-12-03 9:40 [Intel-gfx] [PATCH 1/4] drm/i915: Pass plane id to watermark calculation functions Stanislav Lisovskiy
2021-12-03 9:40 ` [Intel-gfx] [PATCH 4/4] drm/i915: Don't allocate extra ddb during async flip for DG2 Stanislav Lisovskiy
2021-12-03 10:03 ` Ville Syrjälä
2021-12-03 10:17 ` Lisovskiy, Stanislav
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