* [PATCH 0/2] net: stmmac: dwmac-visconti: Fix bit definitions and clock configuration for RMII mode
@ 2022-01-18 5:39 ` Yuji Ishikawa
0 siblings, 0 replies; 10+ messages in thread
From: Yuji Ishikawa @ 2022-01-18 5:39 UTC (permalink / raw)
To: David S . Miller, Jakub Kicinski
Cc: Giuseppe Cavallaro, Alexandre Torgue, Jose Abreu, netdev,
linux-arm-kernel, linux-kernel, nobuhiro1.iwamatsu,
yuji2.ishikawa
Hi,
This series is a fix for RMII/MII operation mode of the dwmac-visconti driver.
It is composed of two parts:
* 1/2: fix constant definitions for cleared bits in ETHER_CLK_SEL register
* 2/2: fix configuration of ETHER_CLK_SEL register for running in RMII operation mode.
Best regards,
Yuji
Yuji Ishikawa (2):
net: stmmac: dwmac-visconti: Fix bit definitions for ETHER_CLK_SEL
net: stmmac: dwmac-visconti: Fix clock configuration for RMII mode
.../ethernet/stmicro/stmmac/dwmac-visconti.c | 42 ++++++++++++-------
1 file changed, 26 insertions(+), 16 deletions(-)
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 0/2] net: stmmac: dwmac-visconti: Fix bit definitions and clock configuration for RMII mode
@ 2022-01-18 5:39 ` Yuji Ishikawa
0 siblings, 0 replies; 10+ messages in thread
From: Yuji Ishikawa @ 2022-01-18 5:39 UTC (permalink / raw)
To: David S . Miller, Jakub Kicinski
Cc: Giuseppe Cavallaro, Alexandre Torgue, Jose Abreu, netdev,
linux-arm-kernel, linux-kernel, nobuhiro1.iwamatsu,
yuji2.ishikawa
Hi,
This series is a fix for RMII/MII operation mode of the dwmac-visconti driver.
It is composed of two parts:
* 1/2: fix constant definitions for cleared bits in ETHER_CLK_SEL register
* 2/2: fix configuration of ETHER_CLK_SEL register for running in RMII operation mode.
Best regards,
Yuji
Yuji Ishikawa (2):
net: stmmac: dwmac-visconti: Fix bit definitions for ETHER_CLK_SEL
net: stmmac: dwmac-visconti: Fix clock configuration for RMII mode
.../ethernet/stmicro/stmmac/dwmac-visconti.c | 42 ++++++++++++-------
1 file changed, 26 insertions(+), 16 deletions(-)
--
2.17.1
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 1/2] net: stmmac: dwmac-visconti: Fix bit definitions for ETHER_CLK_SEL
2022-01-18 5:39 ` Yuji Ishikawa
@ 2022-01-18 5:39 ` Yuji Ishikawa
-1 siblings, 0 replies; 10+ messages in thread
From: Yuji Ishikawa @ 2022-01-18 5:39 UTC (permalink / raw)
To: David S . Miller, Jakub Kicinski
Cc: Giuseppe Cavallaro, Alexandre Torgue, Jose Abreu, netdev,
linux-arm-kernel, linux-kernel, nobuhiro1.iwamatsu,
yuji2.ishikawa
just 0 should be used to represent cleared bits
* ETHER_CLK_SEL_DIV_SEL_20
* ETHER_CLK_SEL_TX_CLK_EXT_SEL_IN
* ETHER_CLK_SEL_RX_CLK_EXT_SEL_IN
* ETHER_CLK_SEL_TX_CLK_O_TX_I
* ETHER_CLK_SEL_RMII_CLK_SEL_IN
Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
index e2e0f9778..43a446cea 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
@@ -22,21 +22,21 @@
#define ETHER_CLK_SEL_RMII_CLK_EN BIT(2)
#define ETHER_CLK_SEL_RMII_CLK_RST BIT(3)
#define ETHER_CLK_SEL_DIV_SEL_2 BIT(4)
-#define ETHER_CLK_SEL_DIV_SEL_20 BIT(0)
+#define ETHER_CLK_SEL_DIV_SEL_20 0
#define ETHER_CLK_SEL_FREQ_SEL_125M (BIT(9) | BIT(8))
#define ETHER_CLK_SEL_FREQ_SEL_50M BIT(9)
#define ETHER_CLK_SEL_FREQ_SEL_25M BIT(8)
#define ETHER_CLK_SEL_FREQ_SEL_2P5M 0
-#define ETHER_CLK_SEL_TX_CLK_EXT_SEL_IN BIT(0)
+#define ETHER_CLK_SEL_TX_CLK_EXT_SEL_IN 0
#define ETHER_CLK_SEL_TX_CLK_EXT_SEL_TXC BIT(10)
#define ETHER_CLK_SEL_TX_CLK_EXT_SEL_DIV BIT(11)
-#define ETHER_CLK_SEL_RX_CLK_EXT_SEL_IN BIT(0)
+#define ETHER_CLK_SEL_RX_CLK_EXT_SEL_IN 0
#define ETHER_CLK_SEL_RX_CLK_EXT_SEL_RXC BIT(12)
#define ETHER_CLK_SEL_RX_CLK_EXT_SEL_DIV BIT(13)
-#define ETHER_CLK_SEL_TX_CLK_O_TX_I BIT(0)
+#define ETHER_CLK_SEL_TX_CLK_O_TX_I 0
#define ETHER_CLK_SEL_TX_CLK_O_RMII_I BIT(14)
#define ETHER_CLK_SEL_TX_O_E_N_IN BIT(15)
-#define ETHER_CLK_SEL_RMII_CLK_SEL_IN BIT(0)
+#define ETHER_CLK_SEL_RMII_CLK_SEL_IN 0
#define ETHER_CLK_SEL_RMII_CLK_SEL_RX_C BIT(16)
#define ETHER_CLK_SEL_RX_TX_CLK_EN (ETHER_CLK_SEL_RX_CLK_EN | ETHER_CLK_SEL_TX_CLK_EN)
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 1/2] net: stmmac: dwmac-visconti: Fix bit definitions for ETHER_CLK_SEL
@ 2022-01-18 5:39 ` Yuji Ishikawa
0 siblings, 0 replies; 10+ messages in thread
From: Yuji Ishikawa @ 2022-01-18 5:39 UTC (permalink / raw)
To: David S . Miller, Jakub Kicinski
Cc: Giuseppe Cavallaro, Alexandre Torgue, Jose Abreu, netdev,
linux-arm-kernel, linux-kernel, nobuhiro1.iwamatsu,
yuji2.ishikawa
just 0 should be used to represent cleared bits
* ETHER_CLK_SEL_DIV_SEL_20
* ETHER_CLK_SEL_TX_CLK_EXT_SEL_IN
* ETHER_CLK_SEL_RX_CLK_EXT_SEL_IN
* ETHER_CLK_SEL_TX_CLK_O_TX_I
* ETHER_CLK_SEL_RMII_CLK_SEL_IN
Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
index e2e0f9778..43a446cea 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
@@ -22,21 +22,21 @@
#define ETHER_CLK_SEL_RMII_CLK_EN BIT(2)
#define ETHER_CLK_SEL_RMII_CLK_RST BIT(3)
#define ETHER_CLK_SEL_DIV_SEL_2 BIT(4)
-#define ETHER_CLK_SEL_DIV_SEL_20 BIT(0)
+#define ETHER_CLK_SEL_DIV_SEL_20 0
#define ETHER_CLK_SEL_FREQ_SEL_125M (BIT(9) | BIT(8))
#define ETHER_CLK_SEL_FREQ_SEL_50M BIT(9)
#define ETHER_CLK_SEL_FREQ_SEL_25M BIT(8)
#define ETHER_CLK_SEL_FREQ_SEL_2P5M 0
-#define ETHER_CLK_SEL_TX_CLK_EXT_SEL_IN BIT(0)
+#define ETHER_CLK_SEL_TX_CLK_EXT_SEL_IN 0
#define ETHER_CLK_SEL_TX_CLK_EXT_SEL_TXC BIT(10)
#define ETHER_CLK_SEL_TX_CLK_EXT_SEL_DIV BIT(11)
-#define ETHER_CLK_SEL_RX_CLK_EXT_SEL_IN BIT(0)
+#define ETHER_CLK_SEL_RX_CLK_EXT_SEL_IN 0
#define ETHER_CLK_SEL_RX_CLK_EXT_SEL_RXC BIT(12)
#define ETHER_CLK_SEL_RX_CLK_EXT_SEL_DIV BIT(13)
-#define ETHER_CLK_SEL_TX_CLK_O_TX_I BIT(0)
+#define ETHER_CLK_SEL_TX_CLK_O_TX_I 0
#define ETHER_CLK_SEL_TX_CLK_O_RMII_I BIT(14)
#define ETHER_CLK_SEL_TX_O_E_N_IN BIT(15)
-#define ETHER_CLK_SEL_RMII_CLK_SEL_IN BIT(0)
+#define ETHER_CLK_SEL_RMII_CLK_SEL_IN 0
#define ETHER_CLK_SEL_RMII_CLK_SEL_RX_C BIT(16)
#define ETHER_CLK_SEL_RX_TX_CLK_EN (ETHER_CLK_SEL_RX_CLK_EN | ETHER_CLK_SEL_TX_CLK_EN)
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/2] net: stmmac: dwmac-visconti: Fix clock configuration for RMII mode
2022-01-18 5:39 ` Yuji Ishikawa
@ 2022-01-18 5:39 ` Yuji Ishikawa
-1 siblings, 0 replies; 10+ messages in thread
From: Yuji Ishikawa @ 2022-01-18 5:39 UTC (permalink / raw)
To: David S . Miller, Jakub Kicinski
Cc: Giuseppe Cavallaro, Alexandre Torgue, Jose Abreu, netdev,
linux-arm-kernel, linux-kernel, nobuhiro1.iwamatsu,
yuji2.ishikawa
Bit pattern of the ETHER_CLOCK_SEL register for RMII/MII mode should be fixed.
Also, some control bits should be modified with a specific sequence.
Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
---
.../ethernet/stmicro/stmmac/dwmac-visconti.c | 32 ++++++++++++-------
1 file changed, 21 insertions(+), 11 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
index 43a446cea..dde5b772a 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
@@ -96,31 +96,41 @@ static void visconti_eth_fix_mac_speed(void *priv, unsigned int speed)
val |= ETHER_CLK_SEL_TX_O_E_N_IN;
writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
+ /* Set Clock-Mux, Start clock, Set TX_O direction */
switch (dwmac->phy_intf_sel) {
case ETHER_CONFIG_INTF_RGMII:
val = clk_sel_val | ETHER_CLK_SEL_RX_CLK_EXT_SEL_RXC;
+ writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
+
+ val |= ETHER_CLK_SEL_RX_TX_CLK_EN;
+ writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
+
+ val &= ~ETHER_CLK_SEL_TX_O_E_N_IN;
+ writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
break;
case ETHER_CONFIG_INTF_RMII:
val = clk_sel_val | ETHER_CLK_SEL_RX_CLK_EXT_SEL_DIV |
- ETHER_CLK_SEL_TX_CLK_EXT_SEL_TXC | ETHER_CLK_SEL_TX_O_E_N_IN |
+ ETHER_CLK_SEL_TX_CLK_EXT_SEL_DIV | ETHER_CLK_SEL_TX_O_E_N_IN |
ETHER_CLK_SEL_RMII_CLK_SEL_RX_C;
+ writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
+
+ val |= ETHER_CLK_SEL_RMII_CLK_RST;
+ writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
+
+ val |= ETHER_CLK_SEL_RMII_CLK_EN | ETHER_CLK_SEL_RX_TX_CLK_EN;
+ writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
break;
case ETHER_CONFIG_INTF_MII:
default:
val = clk_sel_val | ETHER_CLK_SEL_RX_CLK_EXT_SEL_RXC |
- ETHER_CLK_SEL_TX_CLK_EXT_SEL_DIV | ETHER_CLK_SEL_TX_O_E_N_IN |
- ETHER_CLK_SEL_RMII_CLK_EN;
+ ETHER_CLK_SEL_TX_CLK_EXT_SEL_TXC | ETHER_CLK_SEL_TX_O_E_N_IN;
+ writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
+
+ val |= ETHER_CLK_SEL_RX_TX_CLK_EN;
+ writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
break;
}
- /* Start clock */
- writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
- val |= ETHER_CLK_SEL_RX_TX_CLK_EN;
- writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
-
- val &= ~ETHER_CLK_SEL_TX_O_E_N_IN;
- writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
-
spin_unlock_irqrestore(&dwmac->lock, flags);
}
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/2] net: stmmac: dwmac-visconti: Fix clock configuration for RMII mode
@ 2022-01-18 5:39 ` Yuji Ishikawa
0 siblings, 0 replies; 10+ messages in thread
From: Yuji Ishikawa @ 2022-01-18 5:39 UTC (permalink / raw)
To: David S . Miller, Jakub Kicinski
Cc: Giuseppe Cavallaro, Alexandre Torgue, Jose Abreu, netdev,
linux-arm-kernel, linux-kernel, nobuhiro1.iwamatsu,
yuji2.ishikawa
Bit pattern of the ETHER_CLOCK_SEL register for RMII/MII mode should be fixed.
Also, some control bits should be modified with a specific sequence.
Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
---
.../ethernet/stmicro/stmmac/dwmac-visconti.c | 32 ++++++++++++-------
1 file changed, 21 insertions(+), 11 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
index 43a446cea..dde5b772a 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
@@ -96,31 +96,41 @@ static void visconti_eth_fix_mac_speed(void *priv, unsigned int speed)
val |= ETHER_CLK_SEL_TX_O_E_N_IN;
writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
+ /* Set Clock-Mux, Start clock, Set TX_O direction */
switch (dwmac->phy_intf_sel) {
case ETHER_CONFIG_INTF_RGMII:
val = clk_sel_val | ETHER_CLK_SEL_RX_CLK_EXT_SEL_RXC;
+ writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
+
+ val |= ETHER_CLK_SEL_RX_TX_CLK_EN;
+ writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
+
+ val &= ~ETHER_CLK_SEL_TX_O_E_N_IN;
+ writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
break;
case ETHER_CONFIG_INTF_RMII:
val = clk_sel_val | ETHER_CLK_SEL_RX_CLK_EXT_SEL_DIV |
- ETHER_CLK_SEL_TX_CLK_EXT_SEL_TXC | ETHER_CLK_SEL_TX_O_E_N_IN |
+ ETHER_CLK_SEL_TX_CLK_EXT_SEL_DIV | ETHER_CLK_SEL_TX_O_E_N_IN |
ETHER_CLK_SEL_RMII_CLK_SEL_RX_C;
+ writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
+
+ val |= ETHER_CLK_SEL_RMII_CLK_RST;
+ writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
+
+ val |= ETHER_CLK_SEL_RMII_CLK_EN | ETHER_CLK_SEL_RX_TX_CLK_EN;
+ writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
break;
case ETHER_CONFIG_INTF_MII:
default:
val = clk_sel_val | ETHER_CLK_SEL_RX_CLK_EXT_SEL_RXC |
- ETHER_CLK_SEL_TX_CLK_EXT_SEL_DIV | ETHER_CLK_SEL_TX_O_E_N_IN |
- ETHER_CLK_SEL_RMII_CLK_EN;
+ ETHER_CLK_SEL_TX_CLK_EXT_SEL_TXC | ETHER_CLK_SEL_TX_O_E_N_IN;
+ writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
+
+ val |= ETHER_CLK_SEL_RX_TX_CLK_EN;
+ writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
break;
}
- /* Start clock */
- writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
- val |= ETHER_CLK_SEL_RX_TX_CLK_EN;
- writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
-
- val &= ~ETHER_CLK_SEL_TX_O_E_N_IN;
- writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
-
spin_unlock_irqrestore(&dwmac->lock, flags);
}
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 0/2] net: stmmac: dwmac-visconti: Fix bit definitions and clock configuration for RMII mode
2022-01-18 5:39 ` Yuji Ishikawa
@ 2022-01-19 0:50 ` Jakub Kicinski
-1 siblings, 0 replies; 10+ messages in thread
From: Jakub Kicinski @ 2022-01-19 0:50 UTC (permalink / raw)
To: Yuji Ishikawa
Cc: David S . Miller, Giuseppe Cavallaro, Alexandre Torgue,
Jose Abreu, netdev, linux-arm-kernel, linux-kernel,
nobuhiro1.iwamatsu
On Tue, 18 Jan 2022 14:39:48 +0900 Yuji Ishikawa wrote:
> This series is a fix for RMII/MII operation mode of the dwmac-visconti driver.
> It is composed of two parts:
>
> * 1/2: fix constant definitions for cleared bits in ETHER_CLK_SEL register
> * 2/2: fix configuration of ETHER_CLK_SEL register for running in RMII operation mode.
Please add appropriate Fixes tag pointing to the commits where the
buggy code was introduced, even if it's the initial commit adding
the driver.
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 0/2] net: stmmac: dwmac-visconti: Fix bit definitions and clock configuration for RMII mode
@ 2022-01-19 0:50 ` Jakub Kicinski
0 siblings, 0 replies; 10+ messages in thread
From: Jakub Kicinski @ 2022-01-19 0:50 UTC (permalink / raw)
To: Yuji Ishikawa
Cc: David S . Miller, Giuseppe Cavallaro, Alexandre Torgue,
Jose Abreu, netdev, linux-arm-kernel, linux-kernel,
nobuhiro1.iwamatsu
On Tue, 18 Jan 2022 14:39:48 +0900 Yuji Ishikawa wrote:
> This series is a fix for RMII/MII operation mode of the dwmac-visconti driver.
> It is composed of two parts:
>
> * 1/2: fix constant definitions for cleared bits in ETHER_CLK_SEL register
> * 2/2: fix configuration of ETHER_CLK_SEL register for running in RMII operation mode.
Please add appropriate Fixes tag pointing to the commits where the
buggy code was introduced, even if it's the initial commit adding
the driver.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread
* RE: [PATCH 0/2] net: stmmac: dwmac-visconti: Fix bit definitions and clock configuration for RMII mode
2022-01-19 0:50 ` Jakub Kicinski
@ 2022-01-19 2:49 ` yuji2.ishikawa
-1 siblings, 0 replies; 10+ messages in thread
From: yuji2.ishikawa @ 2022-01-19 2:49 UTC (permalink / raw)
To: kuba
Cc: davem, peppe.cavallaro, alexandre.torgue, joabreu, netdev,
linux-arm-kernel, linux-kernel, nobuhiro1.iwamatsu
Hi Jakub,
Thank you for your comment. I will add Fixed tags to commit messages.
-----Original Message-----
From: Jakub Kicinski <kuba@kernel.org>
Sent: Wednesday, January 19, 2022 9:50 AM
To: ishikawa yuji(石川 悠司 ○ＲＤＣ□ＡＩＴＣ○ＥＡ開) <yuji2.ishikawa@toshiba.co.jp>
Cc: David S . Miller <davem@davemloft.net>; Giuseppe Cavallaro <peppe.cavallaro@st.com>; Alexandre Torgue <alexandre.torgue@st.com>; Jose Abreu <joabreu@synopsys.com>; netdev@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ) <nobuhiro1.iwamatsu@toshiba.co.jp>
Subject: Re: [PATCH 0/2] net: stmmac: dwmac-visconti: Fix bit definitions and clock configuration for RMII mode
> On Tue, 18 Jan 2022 14:39:48 +0900 Yuji Ishikawa wrote:
> > This series is a fix for RMII/MII operation mode of the dwmac-visconti driver.
> > It is composed of two parts:
> >
> > * 1/2: fix constant definitions for cleared bits in ETHER_CLK_SEL
> > register
> > * 2/2: fix configuration of ETHER_CLK_SEL register for running in RMII operation mode.
>
> Please add appropriate Fixes tag pointing to the commits where the buggy code was introduced, even if it's the initial commit adding the driver.
Best regards,
Yuji Ishikawa
^ permalink raw reply [flat|nested] 10+ messages in thread
* RE: [PATCH 0/2] net: stmmac: dwmac-visconti: Fix bit definitions and clock configuration for RMII mode
@ 2022-01-19 2:49 ` yuji2.ishikawa
0 siblings, 0 replies; 10+ messages in thread
From: yuji2.ishikawa @ 2022-01-19 2:49 UTC (permalink / raw)
To: kuba
Cc: davem, peppe.cavallaro, alexandre.torgue, joabreu, netdev,
linux-arm-kernel, linux-kernel, nobuhiro1.iwamatsu
Hi Jakub,
Thank you for your comment. I will add Fixed tags to commit messages.
-----Original Message-----
From: Jakub Kicinski <kuba@kernel.org>
Sent: Wednesday, January 19, 2022 9:50 AM
To: ishikawa yuji(石川 悠司 ○ＲＤＣ□ＡＩＴＣ○ＥＡ開) <yuji2.ishikawa@toshiba.co.jp>
Cc: David S . Miller <davem@davemloft.net>; Giuseppe Cavallaro <peppe.cavallaro@st.com>; Alexandre Torgue <alexandre.torgue@st.com>; Jose Abreu <joabreu@synopsys.com>; netdev@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; iwamatsu nobuhiro(岩松 信洋 □ＳＷＣ◯ＡＣＴ) <nobuhiro1.iwamatsu@toshiba.co.jp>
Subject: Re: [PATCH 0/2] net: stmmac: dwmac-visconti: Fix bit definitions and clock configuration for RMII mode
> On Tue, 18 Jan 2022 14:39:48 +0900 Yuji Ishikawa wrote:
> > This series is a fix for RMII/MII operation mode of the dwmac-visconti driver.
> > It is composed of two parts:
> >
> > * 1/2: fix constant definitions for cleared bits in ETHER_CLK_SEL
> > register
> > * 2/2: fix configuration of ETHER_CLK_SEL register for running in RMII operation mode.
>
> Please add appropriate Fixes tag pointing to the commits where the buggy code was introduced, even if it's the initial commit adding the driver.
Best regards,
Yuji Ishikawa
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2022-01-19 2:57 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
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2022-01-18 5:39 [PATCH 0/2] net: stmmac: dwmac-visconti: Fix bit definitions and clock configuration for RMII mode Yuji Ishikawa
2022-01-18 5:39 ` Yuji Ishikawa
2022-01-18 5:39 ` [PATCH 1/2] net: stmmac: dwmac-visconti: Fix bit definitions for ETHER_CLK_SEL Yuji Ishikawa
2022-01-18 5:39 ` Yuji Ishikawa
2022-01-18 5:39 ` [PATCH 2/2] net: stmmac: dwmac-visconti: Fix clock configuration for RMII mode Yuji Ishikawa
2022-01-18 5:39 ` Yuji Ishikawa
2022-01-19 0:50 ` [PATCH 0/2] net: stmmac: dwmac-visconti: Fix bit definitions and " Jakub Kicinski
2022-01-19 0:50 ` Jakub Kicinski
2022-01-19 2:49 ` yuji2.ishikawa
2022-01-19 2:49 ` yuji2.ishikawa
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