From: Weiwei Li <liweiwei@iscas.ac.cn> To: richard.henderson@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: wangjunqiang@iscas.ac.cn, Weiwei Li <liweiwei@iscas.ac.cn>, lazyparser@gmail.com, luruibo2000@163.com, lustrew@foxmail.com Subject: [RFC PATCH v5 08/14] target/riscv: rvk: add support for sha256 related instructions in zknh extension Date: Wed, 19 Jan 2022 19:37:48 +0800 [thread overview] Message-ID: <20220119113754.20323-9-liweiwei@iscas.ac.cn> (raw) In-Reply-To: <20220119113754.20323-1-liweiwei@iscas.ac.cn> - add sha256sig0, sha256sig1, sha256sum0 and sha256sum1 instructions Co-authored-by: Zewen Ye <lustrew@foxmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> --- target/riscv/crypto_helper.c | 31 +++++++++++++ target/riscv/helper.h | 5 +++ target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans/trans_rvk.c.inc | 58 +++++++++++++++++++++++++ 4 files changed, 99 insertions(+) diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c index 9e56668627..f5ffc262f2 100644 --- a/target/riscv/crypto_helper.c +++ b/target/riscv/crypto_helper.c @@ -272,4 +272,35 @@ target_ulong HELPER(aes64im)(target_ulong rs1) return result; } + +#define ROR32(a, amt) ((a << (-amt & 31)) | (a >> (amt & 31))) + +target_ulong HELPER(sha256sig0)(target_ulong rs1) +{ + uint32_t a = rs1; + + return sext_xlen(ROR32(a, 7) ^ ROR32(a, 18) ^ (a >> 3)); +} + +target_ulong HELPER(sha256sig1)(target_ulong rs1) +{ + uint32_t a = rs1; + + return sext_xlen(ROR32(a, 17) ^ ROR32(a, 19) ^ (a >> 10)); +} + +target_ulong HELPER(sha256sum0)(target_ulong rs1) +{ + uint32_t a = rs1; + + return sext_xlen(ROR32(a, 2) ^ ROR32(a, 13) ^ ROR32(a, 22)); +} + +target_ulong HELPER(sha256sum1)(target_ulong rs1) +{ + uint32_t a = rs1; + + return sext_xlen(ROR32(a, 6) ^ ROR32(a, 11) ^ ROR32(a, 25)); +} +#undef ROR32 #undef sext_xlen diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 2446ec22ea..c0368187fa 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1129,3 +1129,8 @@ DEF_HELPER_2(aes64dsm, tl, tl, tl) DEF_HELPER_2(aes64ks2, tl, tl, tl) DEF_HELPER_2(aes64ks1i, tl, tl, tl) DEF_HELPER_1(aes64im, tl, tl) + +DEF_HELPER_1(sha256sig0, tl, tl) +DEF_HELPER_1(sha256sig1, tl, tl) +DEF_HELPER_1(sha256sum0, tl, tl) +DEF_HELPER_1(sha256sum1, tl, tl) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 001b649c40..26d0e3a858 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -847,3 +847,8 @@ aes64esm 00 11011 ..... ..... 000 ..... 0110011 @r # *** RV64 Zkne/zknd Standard Extension *** aes64ks2 01 11111 ..... ..... 000 ..... 0110011 @r aes64ks1i 00 11000 1.... ..... 001 ..... 0010011 %rnum %rs1 %rd +# *** RV32 Zknh Standard Extension *** +sha256sig0 00 01000 00010 ..... 001 ..... 0010011 @r2 +sha256sig1 00 01000 00011 ..... 001 ..... 0010011 @r2 +sha256sum0 00 01000 00000 ..... 001 ..... 0010011 @r2 +sha256sum1 00 01000 00001 ..... 001 ..... 0010011 @r2 diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc index 224cd860a4..3a6812a46a 100644 --- a/target/riscv/insn_trans/trans_rvk.c.inc +++ b/target/riscv/insn_trans/trans_rvk.c.inc @@ -29,6 +29,12 @@ } \ } while (0) +#define REQUIRE_ZKNH(ctx) do { \ + if (!RISCV_CPU(ctx->cs)->cfg.ext_zknh) { \ + return false; \ + } \ +} while (0) + static bool trans_aes32esmi(DisasContext *ctx, arg_aes32esmi *a) { REQUIRE_ZKNE(ctx); @@ -194,3 +200,55 @@ static bool trans_aes64im(DisasContext *ctx, arg_aes64im *a) return true; } + +static bool trans_sha256sig0(DisasContext *ctx, arg_sha256sig0 *a) +{ + REQUIRE_ZKNH(ctx); + + TCGv dest = dest_gpr(ctx, a->rd); + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); + + gen_helper_sha256sig0(dest, src1); + gen_set_gpr(ctx, a->rd, dest); + + return true; +} + +static bool trans_sha256sig1(DisasContext *ctx, arg_sha256sig1 *a) +{ + REQUIRE_ZKNH(ctx); + + TCGv dest = dest_gpr(ctx, a->rd); + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); + + gen_helper_sha256sig1(dest, src1); + gen_set_gpr(ctx, a->rd, dest); + + return true; +} + +static bool trans_sha256sum0(DisasContext *ctx, arg_sha256sum0 *a) +{ + REQUIRE_ZKNH(ctx); + + TCGv dest = dest_gpr(ctx, a->rd); + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); + + gen_helper_sha256sum0(dest, src1); + gen_set_gpr(ctx, a->rd, dest); + + return true; +} + +static bool trans_sha256sum1(DisasContext *ctx, arg_sha256sum1 *a) +{ + REQUIRE_ZKNH(ctx); + + TCGv dest = dest_gpr(ctx, a->rd); + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); + + gen_helper_sha256sum1(dest, src1); + gen_set_gpr(ctx, a->rd, dest); + + return true; +} -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Weiwei Li <liweiwei@iscas.ac.cn> To: richard.henderson@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, lustrew@foxmail.com, luruibo2000@163.com, Weiwei Li <liweiwei@iscas.ac.cn> Subject: [RFC PATCH v5 08/14] target/riscv: rvk: add support for sha256 related instructions in zknh extension Date: Wed, 19 Jan 2022 19:37:48 +0800 [thread overview] Message-ID: <20220119113754.20323-9-liweiwei@iscas.ac.cn> (raw) In-Reply-To: <20220119113754.20323-1-liweiwei@iscas.ac.cn> - add sha256sig0, sha256sig1, sha256sum0 and sha256sum1 instructions Co-authored-by: Zewen Ye <lustrew@foxmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> --- target/riscv/crypto_helper.c | 31 +++++++++++++ target/riscv/helper.h | 5 +++ target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans/trans_rvk.c.inc | 58 +++++++++++++++++++++++++ 4 files changed, 99 insertions(+) diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c index 9e56668627..f5ffc262f2 100644 --- a/target/riscv/crypto_helper.c +++ b/target/riscv/crypto_helper.c @@ -272,4 +272,35 @@ target_ulong HELPER(aes64im)(target_ulong rs1) return result; } + +#define ROR32(a, amt) ((a << (-amt & 31)) | (a >> (amt & 31))) + +target_ulong HELPER(sha256sig0)(target_ulong rs1) +{ + uint32_t a = rs1; + + return sext_xlen(ROR32(a, 7) ^ ROR32(a, 18) ^ (a >> 3)); +} + +target_ulong HELPER(sha256sig1)(target_ulong rs1) +{ + uint32_t a = rs1; + + return sext_xlen(ROR32(a, 17) ^ ROR32(a, 19) ^ (a >> 10)); +} + +target_ulong HELPER(sha256sum0)(target_ulong rs1) +{ + uint32_t a = rs1; + + return sext_xlen(ROR32(a, 2) ^ ROR32(a, 13) ^ ROR32(a, 22)); +} + +target_ulong HELPER(sha256sum1)(target_ulong rs1) +{ + uint32_t a = rs1; + + return sext_xlen(ROR32(a, 6) ^ ROR32(a, 11) ^ ROR32(a, 25)); +} +#undef ROR32 #undef sext_xlen diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 2446ec22ea..c0368187fa 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1129,3 +1129,8 @@ DEF_HELPER_2(aes64dsm, tl, tl, tl) DEF_HELPER_2(aes64ks2, tl, tl, tl) DEF_HELPER_2(aes64ks1i, tl, tl, tl) DEF_HELPER_1(aes64im, tl, tl) + +DEF_HELPER_1(sha256sig0, tl, tl) +DEF_HELPER_1(sha256sig1, tl, tl) +DEF_HELPER_1(sha256sum0, tl, tl) +DEF_HELPER_1(sha256sum1, tl, tl) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 001b649c40..26d0e3a858 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -847,3 +847,8 @@ aes64esm 00 11011 ..... ..... 000 ..... 0110011 @r # *** RV64 Zkne/zknd Standard Extension *** aes64ks2 01 11111 ..... ..... 000 ..... 0110011 @r aes64ks1i 00 11000 1.... ..... 001 ..... 0010011 %rnum %rs1 %rd +# *** RV32 Zknh Standard Extension *** +sha256sig0 00 01000 00010 ..... 001 ..... 0010011 @r2 +sha256sig1 00 01000 00011 ..... 001 ..... 0010011 @r2 +sha256sum0 00 01000 00000 ..... 001 ..... 0010011 @r2 +sha256sum1 00 01000 00001 ..... 001 ..... 0010011 @r2 diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc index 224cd860a4..3a6812a46a 100644 --- a/target/riscv/insn_trans/trans_rvk.c.inc +++ b/target/riscv/insn_trans/trans_rvk.c.inc @@ -29,6 +29,12 @@ } \ } while (0) +#define REQUIRE_ZKNH(ctx) do { \ + if (!RISCV_CPU(ctx->cs)->cfg.ext_zknh) { \ + return false; \ + } \ +} while (0) + static bool trans_aes32esmi(DisasContext *ctx, arg_aes32esmi *a) { REQUIRE_ZKNE(ctx); @@ -194,3 +200,55 @@ static bool trans_aes64im(DisasContext *ctx, arg_aes64im *a) return true; } + +static bool trans_sha256sig0(DisasContext *ctx, arg_sha256sig0 *a) +{ + REQUIRE_ZKNH(ctx); + + TCGv dest = dest_gpr(ctx, a->rd); + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); + + gen_helper_sha256sig0(dest, src1); + gen_set_gpr(ctx, a->rd, dest); + + return true; +} + +static bool trans_sha256sig1(DisasContext *ctx, arg_sha256sig1 *a) +{ + REQUIRE_ZKNH(ctx); + + TCGv dest = dest_gpr(ctx, a->rd); + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); + + gen_helper_sha256sig1(dest, src1); + gen_set_gpr(ctx, a->rd, dest); + + return true; +} + +static bool trans_sha256sum0(DisasContext *ctx, arg_sha256sum0 *a) +{ + REQUIRE_ZKNH(ctx); + + TCGv dest = dest_gpr(ctx, a->rd); + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); + + gen_helper_sha256sum0(dest, src1); + gen_set_gpr(ctx, a->rd, dest); + + return true; +} + +static bool trans_sha256sum1(DisasContext *ctx, arg_sha256sum1 *a) +{ + REQUIRE_ZKNH(ctx); + + TCGv dest = dest_gpr(ctx, a->rd); + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); + + gen_helper_sha256sum1(dest, src1); + gen_set_gpr(ctx, a->rd, dest); + + return true; +} -- 2.17.1
next prev parent reply other threads:[~2022-01-19 12:10 UTC|newest] Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-01-19 11:37 [RFC PATCH v5 00/14] support subsets of scalar crypto extension Weiwei Li 2022-01-19 11:37 ` Weiwei Li 2022-01-19 11:37 ` [RFC PATCH v5 01/14] target/riscv: rvk: add cfg properties for zbk* and zk* Weiwei Li 2022-01-19 11:37 ` Weiwei Li 2022-01-19 11:37 ` [RFC PATCH v5 02/14] target/riscv: rvk: add support for zbkb extension Weiwei Li 2022-01-19 11:37 ` Weiwei Li 2022-01-21 0:08 ` Alistair Francis 2022-01-21 0:08 ` Alistair Francis 2022-01-19 11:37 ` [RFC PATCH v5 03/14] target/riscv: rvk: add support for zbkc extension Weiwei Li 2022-01-19 11:37 ` Weiwei Li 2022-01-21 0:11 ` Alistair Francis 2022-01-21 0:11 ` Alistair Francis 2022-01-19 11:37 ` [RFC PATCH v5 04/14] target/riscv: rvk: add support for zbkx extension Weiwei Li 2022-01-19 11:37 ` Weiwei Li 2022-01-19 11:37 ` [RFC PATCH v5 05/14] crypto: move sm4_sbox from target/arm Weiwei Li 2022-01-19 11:37 ` Weiwei Li 2022-01-19 11:37 ` [RFC PATCH v5 06/14] target/riscv: rvk: add support for zknd/zkne extension in RV32 Weiwei Li 2022-01-19 11:37 ` Weiwei Li 2022-01-19 11:37 ` [RFC PATCH v5 07/14] target/riscv: rvk: add support for zkne/zknd extension in RV64 Weiwei Li 2022-01-19 11:37 ` Weiwei Li 2022-01-19 11:37 ` Weiwei Li [this message] 2022-01-19 11:37 ` [RFC PATCH v5 08/14] target/riscv: rvk: add support for sha256 related instructions in zknh extension Weiwei Li 2022-01-19 11:37 ` [RFC PATCH v5 09/14] target/riscv: rvk: add support for sha512 related instructions for RV32 " Weiwei Li 2022-01-19 11:37 ` Weiwei Li 2022-01-19 11:37 ` [RFC PATCH v5 10/14] target/riscv: rvk: add support for sha512 related instructions for RV64 " Weiwei Li 2022-01-19 11:37 ` Weiwei Li 2022-01-19 11:37 ` [RFC PATCH v5 11/14] target/riscv: rvk: add support for zksed/zksh extension Weiwei Li 2022-01-19 11:37 ` Weiwei Li 2022-01-19 11:37 ` [RFC PATCH v5 12/14] target/riscv: rvk: add CSR support for Zkr Weiwei Li 2022-01-19 11:37 ` Weiwei Li 2022-01-19 11:37 ` [RFC PATCH v5 13/14] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions Weiwei Li 2022-01-19 11:37 ` Weiwei Li 2022-01-19 11:37 ` [RFC PATCH v5 14/14] target/riscv: rvk: expose zbk* and zk* properties Weiwei Li 2022-01-19 11:37 ` Weiwei Li 2022-01-21 0:35 ` Alistair Francis 2022-01-21 0:35 ` Alistair Francis 2022-01-21 8:15 ` Weiwei Li 2022-01-21 8:15 ` Weiwei Li
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20220119113754.20323-9-liweiwei@iscas.ac.cn \ --to=liweiwei@iscas.ac.cn \ --cc=alistair.francis@wdc.com \ --cc=bin.meng@windriver.com \ --cc=lazyparser@gmail.com \ --cc=luruibo2000@163.com \ --cc=lustrew@foxmail.com \ --cc=palmer@dabbelt.com \ --cc=qemu-devel@nongnu.org \ --cc=qemu-riscv@nongnu.org \ --cc=richard.henderson@linaro.org \ --cc=wangjunqiang@iscas.ac.cn \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.