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From: Mark Brown <broonie@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
	Shuah Khan <skhan@linuxfoundation.org>,
	Shuah Khan <shuah@kernel.org>
Cc: Basant Kumar Dwivedi <Basant.KumarDwivedi@arm.com>,
	Luis Machado <luis.machado@arm.com>,
	Szabolcs Nagy <szabolcs.nagy@arm.com>,
	Mark Brown <broonie@kernel.org>,
	linux-arm-kernel@lists.infradead.org,
	linux-kselftest@vger.kernel.org,
	Alan Hayward <alan.hayward@arm.com>,
	kvmarm@lists.cs.columbia.edu,
	Salil Akerkar <Salil.Akerkar@arm.com>
Subject: [PATCH v8 12/38] arm64/sme: Implement support for TPIDR2
Date: Tue, 25 Jan 2022 00:10:48 +0000	[thread overview]
Message-ID: <20220125001114.193425-13-broonie@kernel.org> (raw)
In-Reply-To: <20220125001114.193425-1-broonie@kernel.org>

The Scalable Matrix Extension introduces support for a new thread specific
data register TPIDR2 intended for use by libc. The kernel must save the
value of TPIDR2 on context switch and should ensure that all new threads
start off with a default value of 0. Add a field to the thread_struct to
store TPIDR2 and context switch it with the other thread specific data.

In case there are future extensions which also use TPIDR2 we introduce
system_supports_tpidr2() and use that rather than system_supports_sme()
for TPIDR2 handling.

Signed-off-by: Mark Brown <broonie@kernel.org>
---
 arch/arm64/include/asm/cpufeature.h |  5 +++++
 arch/arm64/include/asm/processor.h  |  1 +
 arch/arm64/kernel/fpsimd.c          |  4 ++++
 arch/arm64/kernel/process.c         | 14 ++++++++++++--
 4 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index 9d36035acce3..12252352d2ee 100644
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -747,6 +747,11 @@ static __always_inline bool system_supports_fa64(void)
 		cpus_have_const_cap(ARM64_SME_FA64);
 }
 
+static __always_inline bool system_supports_tpidr2(void)
+{
+	return system_supports_sme();
+}
+
 static __always_inline bool system_supports_cnp(void)
 {
 	return IS_ENABLED(CONFIG_ARM64_CNP) &&
diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h
index f2c2ebd440e2..008a1767ebff 100644
--- a/arch/arm64/include/asm/processor.h
+++ b/arch/arm64/include/asm/processor.h
@@ -168,6 +168,7 @@ struct thread_struct {
 	u64			mte_ctrl;
 #endif
 	u64			sctlr_user;
+	u64			tpidr2_el0;
 };
 
 static inline unsigned int thread_get_vl(struct thread_struct *thread,
diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c
index 1edb3996f9cf..40ef89120774 100644
--- a/arch/arm64/kernel/fpsimd.c
+++ b/arch/arm64/kernel/fpsimd.c
@@ -1092,6 +1092,10 @@ void sme_kernel_enable(const struct arm64_cpu_capabilities *__always_unused p)
 	/* Allow SME in kernel */
 	write_sysreg(read_sysreg(CPACR_EL1) | CPACR_EL1_SMEN_EL1EN, CPACR_EL1);
 	isb();
+
+	/* Allow EL0 to access TPIDR2 */
+	write_sysreg(read_sysreg(SCTLR_EL1) | SCTLR_ELx_ENTP2, SCTLR_EL1);
+	isb();
 }
 
 /*
diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
index 5369e649fa79..e69a3dcdb0d9 100644
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -250,6 +250,8 @@ void show_regs(struct pt_regs *regs)
 static void tls_thread_flush(void)
 {
 	write_sysreg(0, tpidr_el0);
+	if (system_supports_tpidr2())
+		write_sysreg_s(0, SYS_TPIDR2_EL0);
 
 	if (is_compat_task()) {
 		current->thread.uw.tp_value = 0;
@@ -343,6 +345,8 @@ int copy_thread(unsigned long clone_flags, unsigned long stack_start,
 		 * out-of-sync with the saved value.
 		 */
 		*task_user_tls(p) = read_sysreg(tpidr_el0);
+		if (system_supports_tpidr2())
+			p->thread.tpidr2_el0 = read_sysreg_s(SYS_TPIDR2_EL0);
 
 		if (stack_start) {
 			if (is_compat_thread(task_thread_info(p)))
@@ -353,10 +357,12 @@ int copy_thread(unsigned long clone_flags, unsigned long stack_start,
 
 		/*
 		 * If a TLS pointer was passed to clone, use it for the new
-		 * thread.
+		 * thread.  We also reset TPIDR2 if it's in use.
 		 */
-		if (clone_flags & CLONE_SETTLS)
+		if (clone_flags & CLONE_SETTLS) {
 			p->thread.uw.tp_value = tls;
+			p->thread.tpidr2_el0 = 0;
+		}
 	} else {
 		/*
 		 * A kthread has no context to ERET to, so ensure any buggy
@@ -387,6 +393,8 @@ int copy_thread(unsigned long clone_flags, unsigned long stack_start,
 void tls_preserve_current_state(void)
 {
 	*task_user_tls(current) = read_sysreg(tpidr_el0);
+	if (system_supports_tpidr2() && !is_compat_task())
+		current->thread.tpidr2_el0 = read_sysreg_s(SYS_TPIDR2_EL0);
 }
 
 static void tls_thread_switch(struct task_struct *next)
@@ -399,6 +407,8 @@ static void tls_thread_switch(struct task_struct *next)
 		write_sysreg(0, tpidrro_el0);
 
 	write_sysreg(*task_user_tls(next), tpidr_el0);
+	if (system_supports_tpidr2())
+		write_sysreg_s(next->thread.tpidr2_el0, SYS_TPIDR2_EL0);
 }
 
 /*
-- 
2.30.2

_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

WARNING: multiple messages have this Message-ID (diff)
From: Mark Brown <broonie@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
	Shuah Khan <skhan@linuxfoundation.org>,
	Shuah Khan <shuah@kernel.org>
Cc: Alan Hayward <alan.hayward@arm.com>,
	Luis Machado <luis.machado@arm.com>,
	Salil Akerkar <Salil.Akerkar@arm.com>,
	Basant Kumar Dwivedi <Basant.KumarDwivedi@arm.com>,
	Szabolcs Nagy <szabolcs.nagy@arm.com>,
	James Morse <james.morse@arm.com>,
	Alexandru Elisei <alexandru.elisei@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-kselftest@vger.kernel.org, kvmarm@lists.cs.columbia.edu,
	Mark Brown <broonie@kernel.org>
Subject: [PATCH v8 12/38] arm64/sme: Implement support for TPIDR2
Date: Tue, 25 Jan 2022 00:10:48 +0000	[thread overview]
Message-ID: <20220125001114.193425-13-broonie@kernel.org> (raw)
In-Reply-To: <20220125001114.193425-1-broonie@kernel.org>

The Scalable Matrix Extension introduces support for a new thread specific
data register TPIDR2 intended for use by libc. The kernel must save the
value of TPIDR2 on context switch and should ensure that all new threads
start off with a default value of 0. Add a field to the thread_struct to
store TPIDR2 and context switch it with the other thread specific data.

In case there are future extensions which also use TPIDR2 we introduce
system_supports_tpidr2() and use that rather than system_supports_sme()
for TPIDR2 handling.

Signed-off-by: Mark Brown <broonie@kernel.org>
---
 arch/arm64/include/asm/cpufeature.h |  5 +++++
 arch/arm64/include/asm/processor.h  |  1 +
 arch/arm64/kernel/fpsimd.c          |  4 ++++
 arch/arm64/kernel/process.c         | 14 ++++++++++++--
 4 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index 9d36035acce3..12252352d2ee 100644
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -747,6 +747,11 @@ static __always_inline bool system_supports_fa64(void)
 		cpus_have_const_cap(ARM64_SME_FA64);
 }
 
+static __always_inline bool system_supports_tpidr2(void)
+{
+	return system_supports_sme();
+}
+
 static __always_inline bool system_supports_cnp(void)
 {
 	return IS_ENABLED(CONFIG_ARM64_CNP) &&
diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h
index f2c2ebd440e2..008a1767ebff 100644
--- a/arch/arm64/include/asm/processor.h
+++ b/arch/arm64/include/asm/processor.h
@@ -168,6 +168,7 @@ struct thread_struct {
 	u64			mte_ctrl;
 #endif
 	u64			sctlr_user;
+	u64			tpidr2_el0;
 };
 
 static inline unsigned int thread_get_vl(struct thread_struct *thread,
diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c
index 1edb3996f9cf..40ef89120774 100644
--- a/arch/arm64/kernel/fpsimd.c
+++ b/arch/arm64/kernel/fpsimd.c
@@ -1092,6 +1092,10 @@ void sme_kernel_enable(const struct arm64_cpu_capabilities *__always_unused p)
 	/* Allow SME in kernel */
 	write_sysreg(read_sysreg(CPACR_EL1) | CPACR_EL1_SMEN_EL1EN, CPACR_EL1);
 	isb();
+
+	/* Allow EL0 to access TPIDR2 */
+	write_sysreg(read_sysreg(SCTLR_EL1) | SCTLR_ELx_ENTP2, SCTLR_EL1);
+	isb();
 }
 
 /*
diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
index 5369e649fa79..e69a3dcdb0d9 100644
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -250,6 +250,8 @@ void show_regs(struct pt_regs *regs)
 static void tls_thread_flush(void)
 {
 	write_sysreg(0, tpidr_el0);
+	if (system_supports_tpidr2())
+		write_sysreg_s(0, SYS_TPIDR2_EL0);
 
 	if (is_compat_task()) {
 		current->thread.uw.tp_value = 0;
@@ -343,6 +345,8 @@ int copy_thread(unsigned long clone_flags, unsigned long stack_start,
 		 * out-of-sync with the saved value.
 		 */
 		*task_user_tls(p) = read_sysreg(tpidr_el0);
+		if (system_supports_tpidr2())
+			p->thread.tpidr2_el0 = read_sysreg_s(SYS_TPIDR2_EL0);
 
 		if (stack_start) {
 			if (is_compat_thread(task_thread_info(p)))
@@ -353,10 +357,12 @@ int copy_thread(unsigned long clone_flags, unsigned long stack_start,
 
 		/*
 		 * If a TLS pointer was passed to clone, use it for the new
-		 * thread.
+		 * thread.  We also reset TPIDR2 if it's in use.
 		 */
-		if (clone_flags & CLONE_SETTLS)
+		if (clone_flags & CLONE_SETTLS) {
 			p->thread.uw.tp_value = tls;
+			p->thread.tpidr2_el0 = 0;
+		}
 	} else {
 		/*
 		 * A kthread has no context to ERET to, so ensure any buggy
@@ -387,6 +393,8 @@ int copy_thread(unsigned long clone_flags, unsigned long stack_start,
 void tls_preserve_current_state(void)
 {
 	*task_user_tls(current) = read_sysreg(tpidr_el0);
+	if (system_supports_tpidr2() && !is_compat_task())
+		current->thread.tpidr2_el0 = read_sysreg_s(SYS_TPIDR2_EL0);
 }
 
 static void tls_thread_switch(struct task_struct *next)
@@ -399,6 +407,8 @@ static void tls_thread_switch(struct task_struct *next)
 		write_sysreg(0, tpidrro_el0);
 
 	write_sysreg(*task_user_tls(next), tpidr_el0);
+	if (system_supports_tpidr2())
+		write_sysreg_s(next->thread.tpidr2_el0, SYS_TPIDR2_EL0);
 }
 
 /*
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: Mark Brown <broonie@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
	Shuah Khan <skhan@linuxfoundation.org>,
	Shuah Khan <shuah@kernel.org>
Cc: Alan Hayward <alan.hayward@arm.com>,
	Luis Machado <luis.machado@arm.com>,
	Salil Akerkar <Salil.Akerkar@arm.com>,
	Basant Kumar Dwivedi <Basant.KumarDwivedi@arm.com>,
	Szabolcs Nagy <szabolcs.nagy@arm.com>,
	James Morse <james.morse@arm.com>,
	Alexandru Elisei <alexandru.elisei@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-kselftest@vger.kernel.org, kvmarm@lists.cs.columbia.edu,
	Mark Brown <broonie@kernel.org>
Subject: [PATCH v8 12/38] arm64/sme: Implement support for TPIDR2
Date: Tue, 25 Jan 2022 00:10:48 +0000	[thread overview]
Message-ID: <20220125001114.193425-13-broonie@kernel.org> (raw)
In-Reply-To: <20220125001114.193425-1-broonie@kernel.org>

The Scalable Matrix Extension introduces support for a new thread specific
data register TPIDR2 intended for use by libc. The kernel must save the
value of TPIDR2 on context switch and should ensure that all new threads
start off with a default value of 0. Add a field to the thread_struct to
store TPIDR2 and context switch it with the other thread specific data.

In case there are future extensions which also use TPIDR2 we introduce
system_supports_tpidr2() and use that rather than system_supports_sme()
for TPIDR2 handling.

Signed-off-by: Mark Brown <broonie@kernel.org>
---
 arch/arm64/include/asm/cpufeature.h |  5 +++++
 arch/arm64/include/asm/processor.h  |  1 +
 arch/arm64/kernel/fpsimd.c          |  4 ++++
 arch/arm64/kernel/process.c         | 14 ++++++++++++--
 4 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index 9d36035acce3..12252352d2ee 100644
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -747,6 +747,11 @@ static __always_inline bool system_supports_fa64(void)
 		cpus_have_const_cap(ARM64_SME_FA64);
 }
 
+static __always_inline bool system_supports_tpidr2(void)
+{
+	return system_supports_sme();
+}
+
 static __always_inline bool system_supports_cnp(void)
 {
 	return IS_ENABLED(CONFIG_ARM64_CNP) &&
diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h
index f2c2ebd440e2..008a1767ebff 100644
--- a/arch/arm64/include/asm/processor.h
+++ b/arch/arm64/include/asm/processor.h
@@ -168,6 +168,7 @@ struct thread_struct {
 	u64			mte_ctrl;
 #endif
 	u64			sctlr_user;
+	u64			tpidr2_el0;
 };
 
 static inline unsigned int thread_get_vl(struct thread_struct *thread,
diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c
index 1edb3996f9cf..40ef89120774 100644
--- a/arch/arm64/kernel/fpsimd.c
+++ b/arch/arm64/kernel/fpsimd.c
@@ -1092,6 +1092,10 @@ void sme_kernel_enable(const struct arm64_cpu_capabilities *__always_unused p)
 	/* Allow SME in kernel */
 	write_sysreg(read_sysreg(CPACR_EL1) | CPACR_EL1_SMEN_EL1EN, CPACR_EL1);
 	isb();
+
+	/* Allow EL0 to access TPIDR2 */
+	write_sysreg(read_sysreg(SCTLR_EL1) | SCTLR_ELx_ENTP2, SCTLR_EL1);
+	isb();
 }
 
 /*
diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
index 5369e649fa79..e69a3dcdb0d9 100644
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -250,6 +250,8 @@ void show_regs(struct pt_regs *regs)
 static void tls_thread_flush(void)
 {
 	write_sysreg(0, tpidr_el0);
+	if (system_supports_tpidr2())
+		write_sysreg_s(0, SYS_TPIDR2_EL0);
 
 	if (is_compat_task()) {
 		current->thread.uw.tp_value = 0;
@@ -343,6 +345,8 @@ int copy_thread(unsigned long clone_flags, unsigned long stack_start,
 		 * out-of-sync with the saved value.
 		 */
 		*task_user_tls(p) = read_sysreg(tpidr_el0);
+		if (system_supports_tpidr2())
+			p->thread.tpidr2_el0 = read_sysreg_s(SYS_TPIDR2_EL0);
 
 		if (stack_start) {
 			if (is_compat_thread(task_thread_info(p)))
@@ -353,10 +357,12 @@ int copy_thread(unsigned long clone_flags, unsigned long stack_start,
 
 		/*
 		 * If a TLS pointer was passed to clone, use it for the new
-		 * thread.
+		 * thread.  We also reset TPIDR2 if it's in use.
 		 */
-		if (clone_flags & CLONE_SETTLS)
+		if (clone_flags & CLONE_SETTLS) {
 			p->thread.uw.tp_value = tls;
+			p->thread.tpidr2_el0 = 0;
+		}
 	} else {
 		/*
 		 * A kthread has no context to ERET to, so ensure any buggy
@@ -387,6 +393,8 @@ int copy_thread(unsigned long clone_flags, unsigned long stack_start,
 void tls_preserve_current_state(void)
 {
 	*task_user_tls(current) = read_sysreg(tpidr_el0);
+	if (system_supports_tpidr2() && !is_compat_task())
+		current->thread.tpidr2_el0 = read_sysreg_s(SYS_TPIDR2_EL0);
 }
 
 static void tls_thread_switch(struct task_struct *next)
@@ -399,6 +407,8 @@ static void tls_thread_switch(struct task_struct *next)
 		write_sysreg(0, tpidrro_el0);
 
 	write_sysreg(*task_user_tls(next), tpidr_el0);
+	if (system_supports_tpidr2())
+		write_sysreg_s(next->thread.tpidr2_el0, SYS_TPIDR2_EL0);
 }
 
 /*
-- 
2.30.2


  parent reply	other threads:[~2022-01-25  0:16 UTC|newest]

Thread overview: 154+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-25  0:10 [PATCH v8 00/38] arm64/sme: Initial support for the Scalable Matrix Extension Mark Brown
2022-01-25  0:10 ` Mark Brown
2022-01-25  0:10 ` Mark Brown
2022-01-25  0:10 ` [PATCH v8 01/38] arm64: cpufeature: Always specify and use a field width for capabilities Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25 10:57   ` Suzuki K Poulose
2022-01-25 10:57     ` Suzuki K Poulose
2022-01-25 10:57     ` Suzuki K Poulose
2022-01-25 12:10     ` Mark Brown
2022-01-25 12:10       ` Mark Brown
2022-01-25 12:10       ` Mark Brown
2022-01-25  0:10 ` [PATCH v8 02/38] arm64: Add feature detection for fine grained traps Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10 ` [PATCH v8 03/38] kselftest/arm64: Remove local ARRAY_SIZE() definitions Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10 ` [PATCH v8 04/38] arm64/sme: Provide ABI documentation for SME Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10 ` [PATCH v8 05/38] arm64/sme: System register and exception syndrome definitions Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25 11:25   ` Marc Zyngier
2022-01-25 11:25     ` Marc Zyngier
2022-01-25 11:25     ` Marc Zyngier
2022-01-25 12:15     ` Mark Brown
2022-01-25 12:15       ` Mark Brown
2022-01-25 12:15       ` Mark Brown
2022-01-25  0:10 ` [PATCH v8 06/38] arm64/sme: Manually encode SME instructions Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10 ` [PATCH v8 07/38] arm64/sme: Early CPU setup for SME Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10 ` [PATCH v8 08/38] arm64/sme: Basic enumeration support Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10 ` [PATCH v8 09/38] arm64/sme: Identify supported SME vector lengths at boot Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10 ` [PATCH v8 10/38] arm64/sme: Implement sysctl to set the default vector length Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10 ` [PATCH v8 11/38] arm64/sme: Implement vector length configuration prctl()s Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10 ` Mark Brown [this message]
2022-01-25  0:10   ` [PATCH v8 12/38] arm64/sme: Implement support for TPIDR2 Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10 ` [PATCH v8 13/38] arm64/sme: Implement SVCR context switching Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10 ` [PATCH v8 14/38] arm64/sme: Implement streaming SVE " Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10 ` [PATCH v8 15/38] arm64/sme: Implement ZA " Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10 ` [PATCH v8 16/38] arm64/sme: Implement traps and syscall handling for SME Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10 ` [PATCH v8 17/38] arm64/sme: Disable ZA and streaming mode when handling signals Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10 ` [PATCH v8 18/38] arm64/sme: Implement streaming SVE signal handling Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10 ` [PATCH v8 19/38] arm64/sme: Implement ZA " Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10 ` [PATCH v8 20/38] arm64/sme: Implement ptrace support for streaming mode SVE registers Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10 ` [PATCH v8 21/38] arm64/sme: Add ptrace support for ZA Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10 ` [PATCH v8 22/38] arm64/sme: Disable streaming mode and ZA when flushing CPU state Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10 ` [PATCH v8 23/38] arm64/sme: Save and restore streaming mode over EFI runtime calls Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:10   ` Mark Brown
2022-01-25  0:11 ` [PATCH v8 24/38] KVM: arm64: Hide SME system registers from guests Mark Brown
2022-01-25  0:11   ` Mark Brown
2022-01-25  0:11   ` Mark Brown
2022-01-25  0:11 ` [PATCH v8 25/38] KVM: arm64: Trap SME usage in guest Mark Brown
2022-01-25  0:11   ` Mark Brown
2022-01-25  0:11   ` Mark Brown
2022-01-25 11:27   ` Marc Zyngier
2022-01-25 11:27     ` Marc Zyngier
2022-01-25 11:27     ` Marc Zyngier
2022-01-25 12:25     ` Mark Brown
2022-01-25 12:25       ` Mark Brown
2022-01-25 12:25       ` Mark Brown
2022-01-25 13:21       ` Marc Zyngier
2022-01-25 13:21         ` Marc Zyngier
2022-01-25 13:21         ` Marc Zyngier
2022-01-25 14:25         ` Mark Brown
2022-01-25 14:25           ` Mark Brown
2022-01-25 14:25           ` Mark Brown
2022-01-25 12:29   ` kernel test robot
2022-01-25  0:11 ` [PATCH v8 26/38] KVM: arm64: Handle SME host state when running guests Mark Brown
2022-01-25  0:11   ` Mark Brown
2022-01-25  0:11   ` Mark Brown
2022-01-25 11:59   ` Marc Zyngier
2022-01-25 11:59     ` Marc Zyngier
2022-01-25 11:59     ` Marc Zyngier
2022-01-25 12:52     ` Mark Brown
2022-01-25 12:52       ` Mark Brown
2022-01-25 12:52       ` Mark Brown
2022-01-25 13:22       ` Marc Zyngier
2022-01-25 13:22         ` Marc Zyngier
2022-01-25 13:22         ` Marc Zyngier
2022-01-25 13:34         ` Mark Brown
2022-01-25 13:34           ` Mark Brown
2022-01-25 13:34           ` Mark Brown
2022-01-25  0:11 ` [PATCH v8 27/38] arm64/sme: Provide Kconfig for SME Mark Brown
2022-01-25  0:11   ` Mark Brown
2022-01-25  0:11   ` Mark Brown
2022-01-25  0:11 ` [PATCH v8 28/38] kselftest/arm64: sme: Add streaming SME support to vlset Mark Brown
2022-01-25  0:11   ` Mark Brown
2022-01-25  0:11   ` Mark Brown
2022-01-25  0:11 ` [PATCH v8 29/38] kselftest/arm64: Add tests for TPIDR2 Mark Brown
2022-01-25  0:11   ` Mark Brown
2022-01-25  0:11   ` Mark Brown
2022-01-25  0:11 ` [PATCH v8 30/38] kselftest/arm64: Extend vector configuration API tests to cover SME Mark Brown
2022-01-25  0:11   ` Mark Brown
2022-01-25  0:11   ` Mark Brown
2022-01-25  0:11 ` [PATCH v8 31/38] kselftest/arm64: sme: Provide streaming mode SVE stress test Mark Brown
2022-01-25  0:11   ` Mark Brown
2022-01-25  0:11   ` Mark Brown
2022-01-25  0:11 ` [PATCH v8 32/38] kselftest/arm64: signal: Allow tests to be incompatible with features Mark Brown
2022-01-25  0:11   ` Mark Brown
2022-01-25  0:11   ` Mark Brown
2022-01-25  0:11 ` [PATCH v8 33/38] kselftest/arm64: signal: Handle ZA signal context in core code Mark Brown
2022-01-25  0:11   ` Mark Brown
2022-01-25  0:11   ` Mark Brown
2022-01-25  0:11 ` [PATCH v8 34/38] kselftest/arm64: Add stress test for SME ZA context switching Mark Brown
2022-01-25  0:11   ` Mark Brown
2022-01-25  0:11   ` Mark Brown
2022-01-25  0:11 ` [PATCH v8 35/38] kselftest/arm64: signal: Add SME signal handling tests Mark Brown
2022-01-25  0:11   ` Mark Brown
2022-01-25  0:11   ` Mark Brown
2022-01-25  0:11 ` [PATCH v8 36/38] kselftest/arm64: Add streaming SVE to SVE ptrace tests Mark Brown
2022-01-25  0:11   ` Mark Brown
2022-01-25  0:11   ` Mark Brown
2022-01-25  0:11 ` [PATCH v8 37/38] kselftest/arm64: Add coverage for the ZA ptrace interface Mark Brown
2022-01-25  0:11   ` Mark Brown
2022-01-25  0:11   ` Mark Brown
2022-01-25  0:11 ` [PATCH v8 38/38] kselftest/arm64: Add SME support to syscall ABI test Mark Brown
2022-01-25  0:11   ` Mark Brown
2022-01-25  0:11   ` Mark Brown

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