From: Miquel Raynal <miquel.raynal@bootlin.com> To: Richard Weinberger <richard@nod.at>, Vignesh Raghavendra <vigneshr@ti.com>, Tudor Ambarus <Tudor.Ambarus@microchip.com>, Pratyush Yadav <p.yadav@ti.com>, Michael Walle <michael@walle.cc>, <linux-mtd@lists.infradead.org> Cc: Rob Herring <robh+dt@kernel.org>, <devicetree@vger.kernel.org>, Michal Simek <monstr@monstr.eu>, Thomas Petazzoni <thomas.petazzoni@bootlin.com>, Mark Brown <broonie@kernel.org>, <linux-spi@vger.kernel.org>, Miquel Raynal <miquel.raynal@bootlin.com>, Rob Herring <robh@kernel.org> Subject: [PATCH v6 1/3] dt-bindings: mtd: spi-nor: Allow two CS per device Date: Wed, 26 Jan 2022 12:26:05 +0100 [thread overview] Message-ID: <20220126112608.955728-2-miquel.raynal@bootlin.com> (raw) In-Reply-To: <20220126112608.955728-1-miquel.raynal@bootlin.com> The Xilinx QSPI controller has two advanced modes which allow the controller to behave differently and consider two flashes as one single storage. One of these two modes is quite complex to support from a binding point of view and is the dual parallel memories. In this mode, each byte of data is stored in both devices: the even bits in one, the odd bits in the other. The split is automatically handled by the QSPI controller and is transparent for the user. The other mode is simpler to support, it is called dual stacked memories. The controller shares the same SPI bus but each of the devices contain half of the data. Once in this mode, the controller does not follow CS requests but instead internally wires the two CS levels with the value of the most significant address bit. Supporting these two modes will involve core changes which include the possibility of providing two CS for a single SPI device Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> --- Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml index 39421f7233e4..4abfb4cfc157 100644 --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml @@ -47,7 +47,8 @@ properties: identified by the JEDEC READ ID opcode (0x9F). reg: - maxItems: 1 + minItems: 1 + maxItems: 2 spi-max-frequency: true spi-rx-bus-width: true -- 2.27.0
WARNING: multiple messages have this Message-ID (diff)
From: Miquel Raynal <miquel.raynal@bootlin.com> To: Richard Weinberger <richard@nod.at>, Vignesh Raghavendra <vigneshr@ti.com>, Tudor Ambarus <Tudor.Ambarus@microchip.com>, Pratyush Yadav <p.yadav@ti.com>, Michael Walle <michael@walle.cc>, <linux-mtd@lists.infradead.org> Cc: Rob Herring <robh+dt@kernel.org>, <devicetree@vger.kernel.org>, Michal Simek <monstr@monstr.eu>, Thomas Petazzoni <thomas.petazzoni@bootlin.com>, Mark Brown <broonie@kernel.org>, <linux-spi@vger.kernel.org>, Miquel Raynal <miquel.raynal@bootlin.com>, Rob Herring <robh@kernel.org> Subject: [PATCH v6 1/3] dt-bindings: mtd: spi-nor: Allow two CS per device Date: Wed, 26 Jan 2022 12:26:05 +0100 [thread overview] Message-ID: <20220126112608.955728-2-miquel.raynal@bootlin.com> (raw) In-Reply-To: <20220126112608.955728-1-miquel.raynal@bootlin.com> The Xilinx QSPI controller has two advanced modes which allow the controller to behave differently and consider two flashes as one single storage. One of these two modes is quite complex to support from a binding point of view and is the dual parallel memories. In this mode, each byte of data is stored in both devices: the even bits in one, the odd bits in the other. The split is automatically handled by the QSPI controller and is transparent for the user. The other mode is simpler to support, it is called dual stacked memories. The controller shares the same SPI bus but each of the devices contain half of the data. Once in this mode, the controller does not follow CS requests but instead internally wires the two CS levels with the value of the most significant address bit. Supporting these two modes will involve core changes which include the possibility of providing two CS for a single SPI device Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> --- Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml index 39421f7233e4..4abfb4cfc157 100644 --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml @@ -47,7 +47,8 @@ properties: identified by the JEDEC READ ID opcode (0x9F). reg: - maxItems: 1 + minItems: 1 + maxItems: 2 spi-max-frequency: true spi-rx-bus-width: true -- 2.27.0 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
next prev parent reply other threads:[~2022-01-26 11:26 UTC|newest] Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-01-26 11:26 [PATCH v6 0/3] Stacked/parallel memories bindings Miquel Raynal 2022-01-26 11:26 ` Miquel Raynal 2022-01-26 11:26 ` Miquel Raynal [this message] 2022-01-26 11:26 ` [PATCH v6 1/3] dt-bindings: mtd: spi-nor: Allow two CS per device Miquel Raynal 2022-01-26 11:26 ` [PATCH v6 2/3] spi: dt-bindings: Describe stacked/parallel memories modes Miquel Raynal 2022-01-26 11:26 ` Miquel Raynal 2022-02-04 22:20 ` Rob Herring 2022-02-04 22:20 ` Rob Herring 2022-01-26 11:26 ` [PATCH v6 3/3] spi: dt-bindings: Add an example with two stacked flashes Miquel Raynal 2022-01-26 11:26 ` Miquel Raynal 2022-02-18 11:53 ` [PATCH v6 0/3] Stacked/parallel memories bindings Michal Simek 2022-02-18 11:53 ` Michal Simek 2022-02-21 15:24 ` Mark Brown 2022-02-21 15:24 ` Mark Brown
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