* [PATCH 1/8] target/ppc: Introduce powerpc_excp_74xx
2022-01-26 16:41 [PATCH 0/8] target/ppc: powerpc_excp improvements [74xx] (5/n) Fabiano Rosas
@ 2022-01-26 16:41 ` Fabiano Rosas
2022-01-26 16:41 ` [PATCH 2/8] target/ppc: Simplify powerpc_excp_74xx Fabiano Rosas
` (8 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Fabiano Rosas @ 2022-01-26 16:41 UTC (permalink / raw)
To: qemu-devel; +Cc: mark.cave-ayland, danielhb413, qemu-ppc, clg, david
Introduce a new powerpc_excp function specific for PowerPC 74xx
CPUs. This commit copies powerpc_excp_legacy verbatim so the next one
has a clean diff.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 474 +++++++++++++++++++++++++++++++++++++++
1 file changed, 474 insertions(+)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 0e84cecc68..0e3d3ffcf4 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -551,6 +551,477 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
powerpc_set_excp_state(cpu, vector, new_msr);
}
+static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
+{
+ CPUState *cs = CPU(cpu);
+ CPUPPCState *env = &cpu->env;
+ int excp_model = env->excp_model;
+ target_ulong msr, new_msr, vector;
+ int srr0, srr1, lev = -1;
+
+ if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
+ cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
+ }
+
+ qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
+ " => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
+ excp, env->error_code);
+
+ /* new srr1 value excluding must-be-zero bits */
+ if (excp_model == POWERPC_EXCP_BOOKE) {
+ msr = env->msr;
+ } else {
+ msr = env->msr & ~0x783f0000ULL;
+ }
+
+ /*
+ * new interrupt handler msr preserves existing HV and ME unless
+ * explicitly overriden
+ */
+ new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
+
+ /* target registers */
+ srr0 = SPR_SRR0;
+ srr1 = SPR_SRR1;
+
+ /*
+ * check for special resume at 0x100 from doze/nap/sleep/winkle on
+ * P7/P8/P9
+ */
+ if (env->resume_as_sreset) {
+ excp = powerpc_reset_wakeup(cs, env, excp, &msr);
+ }
+
+ /*
+ * Hypervisor emulation assistance interrupt only exists on server
+ * arch 2.05 server or later. We also don't want to generate it if
+ * we don't have HVB in msr_mask (PAPR mode).
+ */
+ if (excp == POWERPC_EXCP_HV_EMU
+#if defined(TARGET_PPC64)
+ && !(mmu_is_64bit(env->mmu_model) && (env->msr_mask & MSR_HVB))
+#endif /* defined(TARGET_PPC64) */
+
+ ) {
+ excp = POWERPC_EXCP_PROGRAM;
+ }
+
+#ifdef TARGET_PPC64
+ /*
+ * SPEU and VPU share the same IVOR but they exist in different
+ * processors. SPEU is e500v1/2 only and VPU is e6500 only.
+ */
+ if (excp_model == POWERPC_EXCP_BOOKE && excp == POWERPC_EXCP_VPU) {
+ excp = POWERPC_EXCP_SPEU;
+ }
+#endif
+
+ vector = env->excp_vectors[excp];
+ if (vector == (target_ulong)-1ULL) {
+ cpu_abort(cs, "Raised an exception without defined vector %d\n",
+ excp);
+ }
+
+ vector |= env->excp_prefix;
+
+ switch (excp) {
+ case POWERPC_EXCP_CRITICAL: /* Critical input */
+ switch (excp_model) {
+ case POWERPC_EXCP_40x:
+ srr0 = SPR_40x_SRR2;
+ srr1 = SPR_40x_SRR3;
+ break;
+ case POWERPC_EXCP_BOOKE:
+ srr0 = SPR_BOOKE_CSRR0;
+ srr1 = SPR_BOOKE_CSRR1;
+ break;
+ case POWERPC_EXCP_G2:
+ break;
+ default:
+ goto excp_invalid;
+ }
+ break;
+ case POWERPC_EXCP_MCHECK: /* Machine check exception */
+ if (msr_me == 0) {
+ /*
+ * Machine check exception is not enabled. Enter
+ * checkstop state.
+ */
+ fprintf(stderr, "Machine check while not allowed. "
+ "Entering checkstop state\n");
+ if (qemu_log_separate()) {
+ qemu_log("Machine check while not allowed. "
+ "Entering checkstop state\n");
+ }
+ cs->halted = 1;
+ cpu_interrupt_exittb(cs);
+ }
+ if (env->msr_mask & MSR_HVB) {
+ /*
+ * ISA specifies HV, but can be delivered to guest with HV
+ * clear (e.g., see FWNMI in PAPR).
+ */
+ new_msr |= (target_ulong)MSR_HVB;
+ }
+
+ /* machine check exceptions don't have ME set */
+ new_msr &= ~((target_ulong)1 << MSR_ME);
+
+ /* XXX: should also have something loaded in DAR / DSISR */
+ switch (excp_model) {
+ case POWERPC_EXCP_40x:
+ srr0 = SPR_40x_SRR2;
+ srr1 = SPR_40x_SRR3;
+ break;
+ case POWERPC_EXCP_BOOKE:
+ /* FIXME: choose one or the other based on CPU type */
+ srr0 = SPR_BOOKE_MCSRR0;
+ srr1 = SPR_BOOKE_MCSRR1;
+
+ env->spr[SPR_BOOKE_CSRR0] = env->nip;
+ env->spr[SPR_BOOKE_CSRR1] = msr;
+ break;
+ default:
+ break;
+ }
+ break;
+ case POWERPC_EXCP_DSI: /* Data storage exception */
+ trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
+ break;
+ case POWERPC_EXCP_ISI: /* Instruction storage exception */
+ trace_ppc_excp_isi(msr, env->nip);
+ msr |= env->error_code;
+ break;
+ case POWERPC_EXCP_EXTERNAL: /* External input */
+ {
+ bool lpes0;
+
+ cs = CPU(cpu);
+
+ /*
+ * Exception targeting modifiers
+ *
+ * LPES0 is supported on POWER7/8/9
+ * LPES1 is not supported (old iSeries mode)
+ *
+ * On anything else, we behave as if LPES0 is 1
+ * (externals don't alter MSR:HV)
+ */
+#if defined(TARGET_PPC64)
+ if (excp_model == POWERPC_EXCP_POWER7 ||
+ excp_model == POWERPC_EXCP_POWER8 ||
+ excp_model == POWERPC_EXCP_POWER9 ||
+ excp_model == POWERPC_EXCP_POWER10) {
+ lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
+ } else
+#endif /* defined(TARGET_PPC64) */
+ {
+ lpes0 = true;
+ }
+
+ if (!lpes0) {
+ new_msr |= (target_ulong)MSR_HVB;
+ new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
+ srr0 = SPR_HSRR0;
+ srr1 = SPR_HSRR1;
+ }
+ if (env->mpic_proxy) {
+ /* IACK the IRQ on delivery */
+ env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
+ }
+ break;
+ }
+ case POWERPC_EXCP_ALIGN: /* Alignment exception */
+ /* Get rS/rD and rA from faulting opcode */
+ /*
+ * Note: the opcode fields will not be set properly for a
+ * direct store load/store, but nobody cares as nobody
+ * actually uses direct store segments.
+ */
+ env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
+ break;
+ case POWERPC_EXCP_PROGRAM: /* Program exception */
+ switch (env->error_code & ~0xF) {
+ case POWERPC_EXCP_FP:
+ if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
+ trace_ppc_excp_fp_ignore();
+ cs->exception_index = POWERPC_EXCP_NONE;
+ env->error_code = 0;
+ return;
+ }
+
+ /*
+ * FP exceptions always have NIP pointing to the faulting
+ * instruction, so always use store_next and claim we are
+ * precise in the MSR.
+ */
+ msr |= 0x00100000;
+ env->spr[SPR_BOOKE_ESR] = ESR_FP;
+ break;
+ case POWERPC_EXCP_INVAL:
+ trace_ppc_excp_inval(env->nip);
+ msr |= 0x00080000;
+ env->spr[SPR_BOOKE_ESR] = ESR_PIL;
+ break;
+ case POWERPC_EXCP_PRIV:
+ msr |= 0x00040000;
+ env->spr[SPR_BOOKE_ESR] = ESR_PPR;
+ break;
+ case POWERPC_EXCP_TRAP:
+ msr |= 0x00020000;
+ env->spr[SPR_BOOKE_ESR] = ESR_PTR;
+ break;
+ default:
+ /* Should never occur */
+ cpu_abort(cs, "Invalid program exception %d. Aborting\n",
+ env->error_code);
+ break;
+ }
+ break;
+ case POWERPC_EXCP_SYSCALL: /* System call exception */
+ lev = env->error_code;
+
+ if ((lev == 1) && cpu->vhyp) {
+ dump_hcall(env);
+ } else {
+ dump_syscall(env);
+ }
+
+ /*
+ * We need to correct the NIP which in this case is supposed
+ * to point to the next instruction
+ */
+ env->nip += 4;
+
+ /* "PAPR mode" built-in hypercall emulation */
+ if ((lev == 1) && cpu->vhyp) {
+ PPCVirtualHypervisorClass *vhc =
+ PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
+ vhc->hypercall(cpu->vhyp, cpu);
+ return;
+ }
+ if (lev == 1) {
+ new_msr |= (target_ulong)MSR_HVB;
+ }
+ break;
+ case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception */
+ lev = env->error_code;
+ dump_syscall(env);
+ env->nip += 4;
+ new_msr |= env->msr & ((target_ulong)1 << MSR_EE);
+ new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
+
+ vector += lev * 0x20;
+
+ env->lr = env->nip;
+ env->ctr = msr;
+ break;
+ case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
+ case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
+ case POWERPC_EXCP_DECR: /* Decrementer exception */
+ break;
+ case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
+ /* FIT on 4xx */
+ trace_ppc_excp_print("FIT");
+ break;
+ case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
+ trace_ppc_excp_print("WDT");
+ switch (excp_model) {
+ case POWERPC_EXCP_BOOKE:
+ srr0 = SPR_BOOKE_CSRR0;
+ srr1 = SPR_BOOKE_CSRR1;
+ break;
+ default:
+ break;
+ }
+ break;
+ case POWERPC_EXCP_DTLB: /* Data TLB error */
+ case POWERPC_EXCP_ITLB: /* Instruction TLB error */
+ break;
+ case POWERPC_EXCP_DEBUG: /* Debug interrupt */
+ if (env->flags & POWERPC_FLAG_DE) {
+ /* FIXME: choose one or the other based on CPU type */
+ srr0 = SPR_BOOKE_DSRR0;
+ srr1 = SPR_BOOKE_DSRR1;
+
+ env->spr[SPR_BOOKE_CSRR0] = env->nip;
+ env->spr[SPR_BOOKE_CSRR1] = msr;
+
+ /* DBSR already modified by caller */
+ } else {
+ cpu_abort(cs, "Debug exception triggered on unsupported model\n");
+ }
+ break;
+ case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/VPU */
+ env->spr[SPR_BOOKE_ESR] = ESR_SPV;
+ break;
+ case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
+ break;
+ case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
+ srr0 = SPR_BOOKE_CSRR0;
+ srr1 = SPR_BOOKE_CSRR1;
+ break;
+ case POWERPC_EXCP_RESET: /* System reset exception */
+ /* A power-saving exception sets ME, otherwise it is unchanged */
+ if (msr_pow) {
+ /* indicate that we resumed from power save mode */
+ msr |= 0x10000;
+ new_msr |= ((target_ulong)1 << MSR_ME);
+ }
+ if (env->msr_mask & MSR_HVB) {
+ /*
+ * ISA specifies HV, but can be delivered to guest with HV
+ * clear (e.g., see FWNMI in PAPR, NMI injection in QEMU).
+ */
+ new_msr |= (target_ulong)MSR_HVB;
+ } else {
+ if (msr_pow) {
+ cpu_abort(cs, "Trying to deliver power-saving system reset "
+ "exception %d with no HV support\n", excp);
+ }
+ }
+ break;
+ case POWERPC_EXCP_DSEG: /* Data segment exception */
+ case POWERPC_EXCP_ISEG: /* Instruction segment exception */
+ case POWERPC_EXCP_TRACE: /* Trace exception */
+ break;
+ case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
+ msr |= env->error_code;
+ /* fall through */
+ case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
+ case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
+ case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
+ case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
+ case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt */
+ case POWERPC_EXCP_HV_EMU:
+ case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization */
+ srr0 = SPR_HSRR0;
+ srr1 = SPR_HSRR1;
+ new_msr |= (target_ulong)MSR_HVB;
+ new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
+ break;
+ case POWERPC_EXCP_VPU: /* Vector unavailable exception */
+ case POWERPC_EXCP_VSXU: /* VSX unavailable exception */
+ case POWERPC_EXCP_FU: /* Facility unavailable exception */
+#ifdef TARGET_PPC64
+ env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56);
+#endif
+ break;
+ case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Exception */
+#ifdef TARGET_PPC64
+ env->spr[SPR_HFSCR] |= ((target_ulong)env->error_code << FSCR_IC_POS);
+ srr0 = SPR_HSRR0;
+ srr1 = SPR_HSRR1;
+ new_msr |= (target_ulong)MSR_HVB;
+ new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
+#endif
+ break;
+ case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
+ trace_ppc_excp_print("PIT");
+ break;
+ case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
+ case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
+ case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
+ switch (excp_model) {
+ case POWERPC_EXCP_602:
+ case POWERPC_EXCP_603:
+ case POWERPC_EXCP_G2:
+ /* Swap temporary saved registers with GPRs */
+ if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
+ new_msr |= (target_ulong)1 << MSR_TGPR;
+ hreg_swap_gpr_tgpr(env);
+ }
+ /* fall through */
+ case POWERPC_EXCP_7x5:
+ ppc_excp_debug_sw_tlb(env, excp);
+
+ msr |= env->crf[0] << 28;
+ msr |= env->error_code; /* key, D/I, S/L bits */
+ /* Set way using a LRU mechanism */
+ msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
+ break;
+ default:
+ cpu_abort(cs, "Invalid TLB miss exception\n");
+ break;
+ }
+ break;
+ case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
+ case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
+ case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
+ case POWERPC_EXCP_IO: /* IO error exception */
+ case POWERPC_EXCP_RUNM: /* Run mode exception */
+ case POWERPC_EXCP_EMUL: /* Emulation trap exception */
+ case POWERPC_EXCP_FPA: /* Floating-point assist exception */
+ case POWERPC_EXCP_DABR: /* Data address breakpoint */
+ case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
+ case POWERPC_EXCP_SMI: /* System management interrupt */
+ case POWERPC_EXCP_THERM: /* Thermal interrupt */
+ case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
+ case POWERPC_EXCP_VPUA: /* Vector assist exception */
+ case POWERPC_EXCP_SOFTP: /* Soft patch exception */
+ case POWERPC_EXCP_MAINT: /* Maintenance exception */
+ case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
+ case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
+ cpu_abort(cs, "%s exception not implemented\n",
+ powerpc_excp_name(excp));
+ break;
+ default:
+ excp_invalid:
+ cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
+ break;
+ }
+
+ /* Sanity check */
+ if (!(env->msr_mask & MSR_HVB)) {
+ if (new_msr & MSR_HVB) {
+ cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
+ "no HV support\n", excp);
+ }
+ if (srr0 == SPR_HSRR0) {
+ cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
+ "no HV support\n", excp);
+ }
+ }
+
+ /*
+ * Sort out endianness of interrupt, this differs depending on the
+ * CPU, the HV mode, etc...
+ */
+ if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) {
+ new_msr |= (target_ulong)1 << MSR_LE;
+ }
+
+#if defined(TARGET_PPC64)
+ if (excp_model == POWERPC_EXCP_BOOKE) {
+ if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
+ /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
+ new_msr |= (target_ulong)1 << MSR_CM;
+ } else {
+ vector = (uint32_t)vector;
+ }
+ } else {
+ if (!msr_isf && !mmu_is_64bit(env->mmu_model)) {
+ vector = (uint32_t)vector;
+ } else {
+ new_msr |= (target_ulong)1 << MSR_SF;
+ }
+ }
+#endif
+
+ if (excp != POWERPC_EXCP_SYSCALL_VECTORED) {
+ /* Save PC */
+ env->spr[srr0] = env->nip;
+
+ /* Save MSR */
+ env->spr[srr1] = msr;
+ }
+
+ /* This can update new_msr and vector if AIL applies */
+ ppc_excp_apply_ail(cpu, excp_model, excp, msr, &new_msr, &vector);
+
+ powerpc_set_excp_state(cpu, vector, new_msr);
+}
+
#ifdef TARGET_PPC64
static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
{
@@ -1335,6 +1806,9 @@ static void powerpc_excp(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_40x:
powerpc_excp_40x(cpu, excp);
break;
+ case POWERPC_EXCP_74xx:
+ powerpc_excp_74xx(cpu, excp);
+ break;
case POWERPC_EXCP_970:
case POWERPC_EXCP_POWER7:
case POWERPC_EXCP_POWER8:
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 2/8] target/ppc: Simplify powerpc_excp_74xx
2022-01-26 16:41 [PATCH 0/8] target/ppc: powerpc_excp improvements [74xx] (5/n) Fabiano Rosas
2022-01-26 16:41 ` [PATCH 1/8] target/ppc: Introduce powerpc_excp_74xx Fabiano Rosas
@ 2022-01-26 16:41 ` Fabiano Rosas
2022-01-26 16:41 ` [PATCH 3/8] target/ppc: 74xx: Machine Check exception cleanup Fabiano Rosas
` (7 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Fabiano Rosas @ 2022-01-26 16:41 UTC (permalink / raw)
To: qemu-devel; +Cc: mark.cave-ayland, danielhb413, qemu-ppc, clg, david
Differences from the generic powerpc_excp code:
- Not BookE, so some MSR bits are cleared at interrupt dispatch;
- No MSR_HV;
- No power saving states;
- No Hypervisor Emulation Assistance;
- Not 64 bits;
- No System call vectored;
- No Alternate Interrupt Location.
Exceptions used:
POWERPC_EXCP_ALIGN
POWERPC_EXCP_DECR
POWERPC_EXCP_DSI
POWERPC_EXCP_EXTERNAL
POWERPC_EXCP_FPU
POWERPC_EXCP_IABR
POWERPC_EXCP_ISI
POWERPC_EXCP_MCHECK
POWERPC_EXCP_PERFM
POWERPC_EXCP_PROGRAM
POWERPC_EXCP_RESET
POWERPC_EXCP_SMI
POWERPC_EXCP_SYSCALL
POWERPC_EXCP_THERM
POWERPC_EXCP_TRACE
POWERPC_EXCP_VPU
POWERPC_EXCP_VPUA
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 211 ++-------------------------------------
1 file changed, 9 insertions(+), 202 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 0e3d3ffcf4..13e5cb3ddc 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -568,54 +568,26 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
excp, env->error_code);
/* new srr1 value excluding must-be-zero bits */
- if (excp_model == POWERPC_EXCP_BOOKE) {
- msr = env->msr;
- } else {
- msr = env->msr & ~0x783f0000ULL;
- }
+ msr = env->msr & ~0x783f0000ULL;
/*
- * new interrupt handler msr preserves existing HV and ME unless
+ * new interrupt handler msr preserves existing ME unless
* explicitly overriden
*/
- new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
+ new_msr = env->msr & ((target_ulong)1 << MSR_ME);
/* target registers */
srr0 = SPR_SRR0;
srr1 = SPR_SRR1;
- /*
- * check for special resume at 0x100 from doze/nap/sleep/winkle on
- * P7/P8/P9
- */
- if (env->resume_as_sreset) {
- excp = powerpc_reset_wakeup(cs, env, excp, &msr);
- }
-
/*
* Hypervisor emulation assistance interrupt only exists on server
- * arch 2.05 server or later. We also don't want to generate it if
- * we don't have HVB in msr_mask (PAPR mode).
+ * arch 2.05 server or later.
*/
- if (excp == POWERPC_EXCP_HV_EMU
-#if defined(TARGET_PPC64)
- && !(mmu_is_64bit(env->mmu_model) && (env->msr_mask & MSR_HVB))
-#endif /* defined(TARGET_PPC64) */
-
- ) {
+ if (excp == POWERPC_EXCP_HV_EMU) {
excp = POWERPC_EXCP_PROGRAM;
}
-#ifdef TARGET_PPC64
- /*
- * SPEU and VPU share the same IVOR but they exist in different
- * processors. SPEU is e500v1/2 only and VPU is e6500 only.
- */
- if (excp_model == POWERPC_EXCP_BOOKE && excp == POWERPC_EXCP_VPU) {
- excp = POWERPC_EXCP_SPEU;
- }
-#endif
-
vector = env->excp_vectors[excp];
if (vector == (target_ulong)-1ULL) {
cpu_abort(cs, "Raised an exception without defined vector %d\n",
@@ -625,22 +597,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
vector |= env->excp_prefix;
switch (excp) {
- case POWERPC_EXCP_CRITICAL: /* Critical input */
- switch (excp_model) {
- case POWERPC_EXCP_40x:
- srr0 = SPR_40x_SRR2;
- srr1 = SPR_40x_SRR3;
- break;
- case POWERPC_EXCP_BOOKE:
- srr0 = SPR_BOOKE_CSRR0;
- srr1 = SPR_BOOKE_CSRR1;
- break;
- case POWERPC_EXCP_G2:
- break;
- default:
- goto excp_invalid;
- }
- break;
case POWERPC_EXCP_MCHECK: /* Machine check exception */
if (msr_me == 0) {
/*
@@ -804,63 +760,9 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
new_msr |= (target_ulong)MSR_HVB;
}
break;
- case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception */
- lev = env->error_code;
- dump_syscall(env);
- env->nip += 4;
- new_msr |= env->msr & ((target_ulong)1 << MSR_EE);
- new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
-
- vector += lev * 0x20;
-
- env->lr = env->nip;
- env->ctr = msr;
- break;
case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
- case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
case POWERPC_EXCP_DECR: /* Decrementer exception */
break;
- case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
- /* FIT on 4xx */
- trace_ppc_excp_print("FIT");
- break;
- case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
- trace_ppc_excp_print("WDT");
- switch (excp_model) {
- case POWERPC_EXCP_BOOKE:
- srr0 = SPR_BOOKE_CSRR0;
- srr1 = SPR_BOOKE_CSRR1;
- break;
- default:
- break;
- }
- break;
- case POWERPC_EXCP_DTLB: /* Data TLB error */
- case POWERPC_EXCP_ITLB: /* Instruction TLB error */
- break;
- case POWERPC_EXCP_DEBUG: /* Debug interrupt */
- if (env->flags & POWERPC_FLAG_DE) {
- /* FIXME: choose one or the other based on CPU type */
- srr0 = SPR_BOOKE_DSRR0;
- srr1 = SPR_BOOKE_DSRR1;
-
- env->spr[SPR_BOOKE_CSRR0] = env->nip;
- env->spr[SPR_BOOKE_CSRR1] = msr;
-
- /* DBSR already modified by caller */
- } else {
- cpu_abort(cs, "Debug exception triggered on unsupported model\n");
- }
- break;
- case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/VPU */
- env->spr[SPR_BOOKE_ESR] = ESR_SPV;
- break;
- case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
- break;
- case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
- srr0 = SPR_BOOKE_CSRR0;
- srr1 = SPR_BOOKE_CSRR1;
- break;
case POWERPC_EXCP_RESET: /* System reset exception */
/* A power-saving exception sets ME, otherwise it is unchanged */
if (msr_pow) {
@@ -881,92 +783,19 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
}
}
break;
- case POWERPC_EXCP_DSEG: /* Data segment exception */
- case POWERPC_EXCP_ISEG: /* Instruction segment exception */
case POWERPC_EXCP_TRACE: /* Trace exception */
break;
- case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
- msr |= env->error_code;
- /* fall through */
- case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
- case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
- case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
- case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
- case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt */
- case POWERPC_EXCP_HV_EMU:
- case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization */
- srr0 = SPR_HSRR0;
- srr1 = SPR_HSRR1;
- new_msr |= (target_ulong)MSR_HVB;
- new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
- break;
case POWERPC_EXCP_VPU: /* Vector unavailable exception */
- case POWERPC_EXCP_VSXU: /* VSX unavailable exception */
- case POWERPC_EXCP_FU: /* Facility unavailable exception */
-#ifdef TARGET_PPC64
- env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56);
-#endif
break;
- case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Exception */
-#ifdef TARGET_PPC64
- env->spr[SPR_HFSCR] |= ((target_ulong)env->error_code << FSCR_IC_POS);
- srr0 = SPR_HSRR0;
- srr1 = SPR_HSRR1;
- new_msr |= (target_ulong)MSR_HVB;
- new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
-#endif
- break;
- case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
- trace_ppc_excp_print("PIT");
- break;
- case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
- case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
- case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
- switch (excp_model) {
- case POWERPC_EXCP_602:
- case POWERPC_EXCP_603:
- case POWERPC_EXCP_G2:
- /* Swap temporary saved registers with GPRs */
- if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
- new_msr |= (target_ulong)1 << MSR_TGPR;
- hreg_swap_gpr_tgpr(env);
- }
- /* fall through */
- case POWERPC_EXCP_7x5:
- ppc_excp_debug_sw_tlb(env, excp);
-
- msr |= env->crf[0] << 28;
- msr |= env->error_code; /* key, D/I, S/L bits */
- /* Set way using a LRU mechanism */
- msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
- break;
- default:
- cpu_abort(cs, "Invalid TLB miss exception\n");
- break;
- }
- break;
- case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
- case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
- case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
- case POWERPC_EXCP_IO: /* IO error exception */
- case POWERPC_EXCP_RUNM: /* Run mode exception */
- case POWERPC_EXCP_EMUL: /* Emulation trap exception */
- case POWERPC_EXCP_FPA: /* Floating-point assist exception */
- case POWERPC_EXCP_DABR: /* Data address breakpoint */
case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
case POWERPC_EXCP_SMI: /* System management interrupt */
case POWERPC_EXCP_THERM: /* Thermal interrupt */
case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
case POWERPC_EXCP_VPUA: /* Vector assist exception */
- case POWERPC_EXCP_SOFTP: /* Soft patch exception */
- case POWERPC_EXCP_MAINT: /* Maintenance exception */
- case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
- case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
cpu_abort(cs, "%s exception not implemented\n",
powerpc_excp_name(excp));
break;
default:
- excp_invalid:
cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
break;
}
@@ -991,33 +820,11 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
new_msr |= (target_ulong)1 << MSR_LE;
}
-#if defined(TARGET_PPC64)
- if (excp_model == POWERPC_EXCP_BOOKE) {
- if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
- /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
- new_msr |= (target_ulong)1 << MSR_CM;
- } else {
- vector = (uint32_t)vector;
- }
- } else {
- if (!msr_isf && !mmu_is_64bit(env->mmu_model)) {
- vector = (uint32_t)vector;
- } else {
- new_msr |= (target_ulong)1 << MSR_SF;
- }
- }
-#endif
+ /* Save PC */
+ env->spr[srr0] = env->nip;
- if (excp != POWERPC_EXCP_SYSCALL_VECTORED) {
- /* Save PC */
- env->spr[srr0] = env->nip;
-
- /* Save MSR */
- env->spr[srr1] = msr;
- }
-
- /* This can update new_msr and vector if AIL applies */
- ppc_excp_apply_ail(cpu, excp_model, excp, msr, &new_msr, &vector);
+ /* Save MSR */
+ env->spr[srr1] = msr;
powerpc_set_excp_state(cpu, vector, new_msr);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 3/8] target/ppc: 74xx: Machine Check exception cleanup
2022-01-26 16:41 [PATCH 0/8] target/ppc: powerpc_excp improvements [74xx] (5/n) Fabiano Rosas
2022-01-26 16:41 ` [PATCH 1/8] target/ppc: Introduce powerpc_excp_74xx Fabiano Rosas
2022-01-26 16:41 ` [PATCH 2/8] target/ppc: Simplify powerpc_excp_74xx Fabiano Rosas
@ 2022-01-26 16:41 ` Fabiano Rosas
2022-01-26 16:41 ` [PATCH 4/8] target/ppc: 74xx: External interrupt cleanup Fabiano Rosas
` (6 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Fabiano Rosas @ 2022-01-26 16:41 UTC (permalink / raw)
To: qemu-devel; +Cc: mark.cave-ayland, danielhb413, qemu-ppc, clg, david
The 74xx don't have an MSR_HV.
Also remove 40x and BookE code.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 24 ------------------------
1 file changed, 24 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 13e5cb3ddc..0d8c66b98f 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -612,34 +612,10 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
cs->halted = 1;
cpu_interrupt_exittb(cs);
}
- if (env->msr_mask & MSR_HVB) {
- /*
- * ISA specifies HV, but can be delivered to guest with HV
- * clear (e.g., see FWNMI in PAPR).
- */
- new_msr |= (target_ulong)MSR_HVB;
- }
/* machine check exceptions don't have ME set */
new_msr &= ~((target_ulong)1 << MSR_ME);
- /* XXX: should also have something loaded in DAR / DSISR */
- switch (excp_model) {
- case POWERPC_EXCP_40x:
- srr0 = SPR_40x_SRR2;
- srr1 = SPR_40x_SRR3;
- break;
- case POWERPC_EXCP_BOOKE:
- /* FIXME: choose one or the other based on CPU type */
- srr0 = SPR_BOOKE_MCSRR0;
- srr1 = SPR_BOOKE_MCSRR1;
-
- env->spr[SPR_BOOKE_CSRR0] = env->nip;
- env->spr[SPR_BOOKE_CSRR1] = msr;
- break;
- default:
- break;
- }
break;
case POWERPC_EXCP_DSI: /* Data storage exception */
trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 4/8] target/ppc: 74xx: External interrupt cleanup
2022-01-26 16:41 [PATCH 0/8] target/ppc: powerpc_excp improvements [74xx] (5/n) Fabiano Rosas
` (2 preceding siblings ...)
2022-01-26 16:41 ` [PATCH 3/8] target/ppc: 74xx: Machine Check exception cleanup Fabiano Rosas
@ 2022-01-26 16:41 ` Fabiano Rosas
2022-01-26 16:41 ` [PATCH 5/8] target/ppc: 74xx: Program exception cleanup Fabiano Rosas
` (5 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Fabiano Rosas @ 2022-01-26 16:41 UTC (permalink / raw)
To: qemu-devel; +Cc: mark.cave-ayland, danielhb413, qemu-ppc, clg, david
The 74xx don't have MSR_HV so all the LPES0 logic can be removed.
Also remove the BookE IRQ code.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 38 --------------------------------------
1 file changed, 38 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 0d8c66b98f..b9a1d7ae7e 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -555,7 +555,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
{
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
- int excp_model = env->excp_model;
target_ulong msr, new_msr, vector;
int srr0, srr1, lev = -1;
@@ -625,44 +624,7 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
msr |= env->error_code;
break;
case POWERPC_EXCP_EXTERNAL: /* External input */
- {
- bool lpes0;
-
- cs = CPU(cpu);
-
- /*
- * Exception targeting modifiers
- *
- * LPES0 is supported on POWER7/8/9
- * LPES1 is not supported (old iSeries mode)
- *
- * On anything else, we behave as if LPES0 is 1
- * (externals don't alter MSR:HV)
- */
-#if defined(TARGET_PPC64)
- if (excp_model == POWERPC_EXCP_POWER7 ||
- excp_model == POWERPC_EXCP_POWER8 ||
- excp_model == POWERPC_EXCP_POWER9 ||
- excp_model == POWERPC_EXCP_POWER10) {
- lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
- } else
-#endif /* defined(TARGET_PPC64) */
- {
- lpes0 = true;
- }
-
- if (!lpes0) {
- new_msr |= (target_ulong)MSR_HVB;
- new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
- srr0 = SPR_HSRR0;
- srr1 = SPR_HSRR1;
- }
- if (env->mpic_proxy) {
- /* IACK the IRQ on delivery */
- env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
- }
break;
- }
case POWERPC_EXCP_ALIGN: /* Alignment exception */
/* Get rS/rD and rA from faulting opcode */
/*
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 5/8] target/ppc: 74xx: Program exception cleanup
2022-01-26 16:41 [PATCH 0/8] target/ppc: powerpc_excp improvements [74xx] (5/n) Fabiano Rosas
` (3 preceding siblings ...)
2022-01-26 16:41 ` [PATCH 4/8] target/ppc: 74xx: External interrupt cleanup Fabiano Rosas
@ 2022-01-26 16:41 ` Fabiano Rosas
2022-01-26 16:41 ` [PATCH 6/8] target/ppc: 74xx: System Call " Fabiano Rosas
` (4 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Fabiano Rosas @ 2022-01-26 16:41 UTC (permalink / raw)
To: qemu-devel; +Cc: mark.cave-ayland, danielhb413, qemu-ppc, clg, david
Remove the BookE ESR setting.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index b9a1d7ae7e..bb17b65dc0 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -650,20 +650,16 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
* precise in the MSR.
*/
msr |= 0x00100000;
- env->spr[SPR_BOOKE_ESR] = ESR_FP;
break;
case POWERPC_EXCP_INVAL:
trace_ppc_excp_inval(env->nip);
msr |= 0x00080000;
- env->spr[SPR_BOOKE_ESR] = ESR_PIL;
break;
case POWERPC_EXCP_PRIV:
msr |= 0x00040000;
- env->spr[SPR_BOOKE_ESR] = ESR_PPR;
break;
case POWERPC_EXCP_TRAP:
msr |= 0x00020000;
- env->spr[SPR_BOOKE_ESR] = ESR_PTR;
break;
default:
/* Should never occur */
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 6/8] target/ppc: 74xx: System Call exception cleanup
2022-01-26 16:41 [PATCH 0/8] target/ppc: powerpc_excp improvements [74xx] (5/n) Fabiano Rosas
` (4 preceding siblings ...)
2022-01-26 16:41 ` [PATCH 5/8] target/ppc: 74xx: Program exception cleanup Fabiano Rosas
@ 2022-01-26 16:41 ` Fabiano Rosas
2022-01-26 16:41 ` [PATCH 7/8] target/ppc: 74xx: System Reset interrupt cleanup Fabiano Rosas
` (3 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Fabiano Rosas @ 2022-01-26 16:41 UTC (permalink / raw)
To: qemu-devel; +Cc: mark.cave-ayland, danielhb413, qemu-ppc, clg, david
There is no sc 1 and no HV mode.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 21 ++-------------------
1 file changed, 2 insertions(+), 19 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index bb17b65dc0..070c9779ad 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -556,7 +556,7 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
- int srr0, srr1, lev = -1;
+ int srr0, srr1;
if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
@@ -669,30 +669,13 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
}
break;
case POWERPC_EXCP_SYSCALL: /* System call exception */
- lev = env->error_code;
-
- if ((lev == 1) && cpu->vhyp) {
- dump_hcall(env);
- } else {
- dump_syscall(env);
- }
+ dump_syscall(env);
/*
* We need to correct the NIP which in this case is supposed
* to point to the next instruction
*/
env->nip += 4;
-
- /* "PAPR mode" built-in hypercall emulation */
- if ((lev == 1) && cpu->vhyp) {
- PPCVirtualHypervisorClass *vhc =
- PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
- vhc->hypercall(cpu->vhyp, cpu);
- return;
- }
- if (lev == 1) {
- new_msr |= (target_ulong)MSR_HVB;
- }
break;
case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
case POWERPC_EXCP_DECR: /* Decrementer exception */
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 7/8] target/ppc: 74xx: System Reset interrupt cleanup
2022-01-26 16:41 [PATCH 0/8] target/ppc: powerpc_excp improvements [74xx] (5/n) Fabiano Rosas
` (5 preceding siblings ...)
2022-01-26 16:41 ` [PATCH 6/8] target/ppc: 74xx: System Call " Fabiano Rosas
@ 2022-01-26 16:41 ` Fabiano Rosas
2022-01-26 16:42 ` [PATCH 8/8] target/ppc: 74xx: Set SRRs directly in exception code Fabiano Rosas
` (2 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Fabiano Rosas @ 2022-01-26 16:41 UTC (permalink / raw)
To: qemu-devel; +Cc: mark.cave-ayland, danielhb413, qemu-ppc, clg, david
The whole power saving states logic seems to be dependent on HV mode,
which don't exist for 74xx so I'm removing it all and leaving the
abort message.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 18 ++----------------
1 file changed, 2 insertions(+), 16 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 070c9779ad..9d4ee7f928 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -681,23 +681,9 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_DECR: /* Decrementer exception */
break;
case POWERPC_EXCP_RESET: /* System reset exception */
- /* A power-saving exception sets ME, otherwise it is unchanged */
if (msr_pow) {
- /* indicate that we resumed from power save mode */
- msr |= 0x10000;
- new_msr |= ((target_ulong)1 << MSR_ME);
- }
- if (env->msr_mask & MSR_HVB) {
- /*
- * ISA specifies HV, but can be delivered to guest with HV
- * clear (e.g., see FWNMI in PAPR, NMI injection in QEMU).
- */
- new_msr |= (target_ulong)MSR_HVB;
- } else {
- if (msr_pow) {
- cpu_abort(cs, "Trying to deliver power-saving system reset "
- "exception %d with no HV support\n", excp);
- }
+ cpu_abort(cs, "Trying to deliver power-saving system reset "
+ "exception %d with no HV support\n", excp);
}
break;
case POWERPC_EXCP_TRACE: /* Trace exception */
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 8/8] target/ppc: 74xx: Set SRRs directly in exception code
2022-01-26 16:41 [PATCH 0/8] target/ppc: powerpc_excp improvements [74xx] (5/n) Fabiano Rosas
` (6 preceding siblings ...)
2022-01-26 16:41 ` [PATCH 7/8] target/ppc: 74xx: System Reset interrupt cleanup Fabiano Rosas
@ 2022-01-26 16:42 ` Fabiano Rosas
2022-01-26 17:55 ` [PATCH 0/8] target/ppc: powerpc_excp improvements [74xx] (5/n) BALATON Zoltan
2022-01-27 14:40 ` Mark Cave-Ayland
9 siblings, 0 replies; 16+ messages in thread
From: Fabiano Rosas @ 2022-01-26 16:42 UTC (permalink / raw)
To: qemu-devel; +Cc: mark.cave-ayland, danielhb413, qemu-ppc, clg, david
The 74xx does not have alternate/hypervisor Save and Restore
Registers, so we can set SRR0 and SRR1 directly.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 13 ++-----------
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 9d4ee7f928..087257462a 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -556,7 +556,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
- int srr0, srr1;
if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
@@ -575,10 +574,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
*/
new_msr = env->msr & ((target_ulong)1 << MSR_ME);
- /* target registers */
- srr0 = SPR_SRR0;
- srr1 = SPR_SRR1;
-
/*
* Hypervisor emulation assistance interrupt only exists on server
* arch 2.05 server or later.
@@ -709,10 +704,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
"no HV support\n", excp);
}
- if (srr0 == SPR_HSRR0) {
- cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
- "no HV support\n", excp);
- }
}
/*
@@ -724,10 +715,10 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
}
/* Save PC */
- env->spr[srr0] = env->nip;
+ env->spr[SPR_SRR0] = env->nip;
/* Save MSR */
- env->spr[srr1] = msr;
+ env->spr[SPR_SRR1] = msr;
powerpc_set_excp_state(cpu, vector, new_msr);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 0/8] target/ppc: powerpc_excp improvements [74xx] (5/n)
2022-01-26 16:41 [PATCH 0/8] target/ppc: powerpc_excp improvements [74xx] (5/n) Fabiano Rosas
` (7 preceding siblings ...)
2022-01-26 16:42 ` [PATCH 8/8] target/ppc: 74xx: Set SRRs directly in exception code Fabiano Rosas
@ 2022-01-26 17:55 ` BALATON Zoltan
2022-01-26 18:23 ` Cédric Le Goater
2022-01-26 21:58 ` Fabiano Rosas
2022-01-27 14:40 ` Mark Cave-Ayland
9 siblings, 2 replies; 16+ messages in thread
From: BALATON Zoltan @ 2022-01-26 17:55 UTC (permalink / raw)
To: Fabiano Rosas; +Cc: danielhb413, qemu-ppc, qemu-devel, david, clg
On Wed, 26 Jan 2022, Fabiano Rosas wrote:
> This handles the exception code for the 74xx family, i.e. 7400, 7410,
> 7440, 7445, 7450, 7455, 7457.
>
> This is another family that is quite well known, so it should be
> straight-forward as well.
I guess this is what may break VOF on pegasos2. Was Philippe's test case
for this machine ever merged? (Although that may use the firmware ROM that
was preferred as it tests more of the machine and may predate VOF so not
sure it also tests with VOF.) The way to test it is this:
Get morphos demo ISO from https://www.morphos-team.net/morphos-3.15.iso
Extract boot.img from the root directory of the CD
Run QEMU as shown at http://zero.eik.bme.hu/~balaton/qemu/amiga/#morphos
(For debugging maybe enabling vof traces would give more info but it was
a while so I don't remember the details any more.)
> Based on legoater/ppc-7.0
I could test when it's merged or when it applies on master but I don't
usually test on branches. Did you verify it still works with pegasos2 or
could you please make sure it won't break that use case?
Regards,
BALATON Zoltan
> Fabiano Rosas (8):
> target/ppc: Introduce powerpc_excp_74xx
> target/ppc: Simplify powerpc_excp_74xx
> target/ppc: 74xx: Machine Check exception cleanup
> target/ppc: 74xx: External interrupt cleanup
> target/ppc: 74xx: Program exception cleanup
> target/ppc: 74xx: System Call exception cleanup
> target/ppc: 74xx: System Reset interrupt cleanup
> target/ppc: 74xx: Set SRRs directly in exception code
>
> target/ppc/excp_helper.c | 175 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 175 insertions(+)
>
>
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH 0/8] target/ppc: powerpc_excp improvements [74xx] (5/n)
2022-01-26 17:55 ` [PATCH 0/8] target/ppc: powerpc_excp improvements [74xx] (5/n) BALATON Zoltan
@ 2022-01-26 18:23 ` Cédric Le Goater
2022-01-26 20:00 ` BALATON Zoltan
2022-01-26 21:58 ` Fabiano Rosas
1 sibling, 1 reply; 16+ messages in thread
From: Cédric Le Goater @ 2022-01-26 18:23 UTC (permalink / raw)
To: BALATON Zoltan, Fabiano Rosas; +Cc: danielhb413, qemu-ppc, qemu-devel, david
On 1/26/22 18:55, BALATON Zoltan wrote:
> On Wed, 26 Jan 2022, Fabiano Rosas wrote:
>> This handles the exception code for the 74xx family, i.e. 7400, 7410,
>> 7440, 7445, 7450, 7455, 7457.
>>
>> This is another family that is quite well known, so it should be
>> straight-forward as well.
>
> I guess this is what may break VOF on pegasos2. Was Philippe's test case for this machine ever merged? (Although that may use the firmware ROM that was preferred as it tests more of the machine and may predate VOF so not sure it also tests with VOF.) The way to test it is this:
>
> Get morphos demo ISO from https://www.morphos-team.net/morphos-3.15.iso
> Extract boot.img from the root directory of the CD
> Run QEMU as shown at http://zero.eik.bme.hu/~balaton/qemu/amiga/#morphos
I could never make it work :/
>
> (For debugging maybe enabling vof traces would give more info but it was a while so I don't remember the details any more.)
>
>> Based on legoater/ppc-7.0
>
> I could test when it's merged or when it applies on master but I don't usually test on branches. Did you verify it still works with pegasos2 or could you please make sure it won't break that use case?
I have a large set of images, here, that I use for non regression tests :
https://github.com/legoater/qemu-ppc-boot
If we could add a pegasos, that would be nice.
Thanks,
C.
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 0/8] target/ppc: powerpc_excp improvements [74xx] (5/n)
2022-01-26 18:23 ` Cédric Le Goater
@ 2022-01-26 20:00 ` BALATON Zoltan
0 siblings, 0 replies; 16+ messages in thread
From: BALATON Zoltan @ 2022-01-26 20:00 UTC (permalink / raw)
To: Cédric Le Goater
Cc: danielhb413, qemu-ppc, qemu-devel, david, Fabiano Rosas
[-- Attachment #1: Type: text/plain, Size: 1739 bytes --]
On Wed, 26 Jan 2022, Cédric Le Goater wrote:
> On 1/26/22 18:55, BALATON Zoltan wrote:
>> On Wed, 26 Jan 2022, Fabiano Rosas wrote:
>>> This handles the exception code for the 74xx family, i.e. 7400, 7410,
>>> 7440, 7445, 7450, 7455, 7457.
>>>
>>> This is another family that is quite well known, so it should be
>>> straight-forward as well.
>>
>> I guess this is what may break VOF on pegasos2. Was Philippe's test case
>> for this machine ever merged? (Although that may use the firmware ROM that
>> was preferred as it tests more of the machine and may predate VOF so not
>> sure it also tests with VOF.) The way to test it is this:
>>
>> Get morphos demo ISO from https://www.morphos-team.net/morphos-3.15.iso
>> Extract boot.img from the root directory of the CD
>> Run QEMU as shown at http://zero.eik.bme.hu/~balaton/qemu/amiga/#morphos
>
> I could never make it work :/
Philippe's test or the MorphOS iso? If the MorphOS boot, what problem do
you get? I don't have or use avocado so can't comment on the former.
>> (For debugging maybe enabling vof traces would give more info but it was a
>> while so I don't remember the details any more.)
>>
>>> Based on legoater/ppc-7.0
>>
>> I could test when it's merged or when it applies on master but I don't
>> usually test on branches. Did you verify it still works with pegasos2 or
>> could you please make sure it won't break that use case?
>
> I have a large set of images, here, that I use for non regression tests :
>
> https://github.com/legoater/qemu-ppc-boot
>
> If we could add a pegasos, that would be nice.
I'm not sure how could I help with that. Once you can boot from command
line it should be easy to add to the script as well.
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 0/8] target/ppc: powerpc_excp improvements [74xx] (5/n)
2022-01-26 17:55 ` [PATCH 0/8] target/ppc: powerpc_excp improvements [74xx] (5/n) BALATON Zoltan
2022-01-26 18:23 ` Cédric Le Goater
@ 2022-01-26 21:58 ` Fabiano Rosas
1 sibling, 0 replies; 16+ messages in thread
From: Fabiano Rosas @ 2022-01-26 21:58 UTC (permalink / raw)
To: BALATON Zoltan; +Cc: clg, danielhb413, qemu-ppc, qemu-devel, david
BALATON Zoltan <balaton@eik.bme.hu> writes:
> On Wed, 26 Jan 2022, Fabiano Rosas wrote:
>> This handles the exception code for the 74xx family, i.e. 7400, 7410,
>> 7440, 7445, 7450, 7455, 7457.
>>
>> This is another family that is quite well known, so it should be
>> straight-forward as well.
>
> I guess this is what may break VOF on pegasos2. Was Philippe's test case
> for this machine ever merged? (Although that may use the firmware ROM that
> was preferred as it tests more of the machine and may predate VOF so not
> sure it also tests with VOF.) The way to test it is this:
>
> Get morphos demo ISO from https://www.morphos-team.net/morphos-3.15.iso
> Extract boot.img from the root directory of the CD
> Run QEMU as shown at http://zero.eik.bme.hu/~balaton/qemu/amiga/#morphos
>
> (For debugging maybe enabling vof traces would give more info but it was
> a while so I don't remember the details any more.)
>
>> Based on legoater/ppc-7.0
>
> I could test when it's merged or when it applies on master but I don't
> usually test on branches. Did you verify it still works with pegasos2 or
> could you please make sure it won't break that use case?
I can test with pegasos2. I'll make sure we don't merge this before
testing there.
That said, I forgot about the sc 1 thing and it is indeed broken. I'll
send a v2 fixing it.
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 0/8] target/ppc: powerpc_excp improvements [74xx] (5/n)
2022-01-26 16:41 [PATCH 0/8] target/ppc: powerpc_excp improvements [74xx] (5/n) Fabiano Rosas
` (8 preceding siblings ...)
2022-01-26 17:55 ` [PATCH 0/8] target/ppc: powerpc_excp improvements [74xx] (5/n) BALATON Zoltan
@ 2022-01-27 14:40 ` Mark Cave-Ayland
2022-01-27 15:16 ` Fabiano Rosas
9 siblings, 1 reply; 16+ messages in thread
From: Mark Cave-Ayland @ 2022-01-27 14:40 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
On 26/01/2022 16:41, Fabiano Rosas wrote:
> This handles the exception code for the 74xx family, i.e. 7400, 7410,
> 7440, 7445, 7450, 7455, 7457.
>
> This is another family that is quite well known, so it should be
> straight-forward as well.
>
> Based on legoater/ppc-7.0
>
> Fabiano Rosas (8):
> target/ppc: Introduce powerpc_excp_74xx
> target/ppc: Simplify powerpc_excp_74xx
> target/ppc: 74xx: Machine Check exception cleanup
> target/ppc: 74xx: External interrupt cleanup
> target/ppc: 74xx: Program exception cleanup
> target/ppc: 74xx: System Call exception cleanup
> target/ppc: 74xx: System Reset interrupt cleanup
> target/ppc: 74xx: Set SRRs directly in exception code
>
> target/ppc/excp_helper.c | 175 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 175 insertions(+)
I'm not overly familiar with PPC exception handling detail, so I can't offer much in
the way of review I'm afraid. I could do a quick test and make sure nothing breaks
with my MacOS images though?
Also any thoughts on Christophe's question re: e300 PVRs at
https://lists.gnu.org/archive/html/qemu-ppc/2022-01/msg00592.html? I can handle
merging the OpenBIOS changes if someone can come up with a suitable fix.
ATB,
Mark.
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH 0/8] target/ppc: powerpc_excp improvements [74xx] (5/n)
2022-01-27 14:40 ` Mark Cave-Ayland
@ 2022-01-27 15:16 ` Fabiano Rosas
2022-01-27 16:51 ` Cédric Le Goater
0 siblings, 1 reply; 16+ messages in thread
From: Fabiano Rosas @ 2022-01-27 15:16 UTC (permalink / raw)
To: Mark Cave-Ayland, qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> writes:
> On 26/01/2022 16:41, Fabiano Rosas wrote:
>
>> This handles the exception code for the 74xx family, i.e. 7400, 7410,
>> 7440, 7445, 7450, 7455, 7457.
>>
>> This is another family that is quite well known, so it should be
>> straight-forward as well.
>>
>> Based on legoater/ppc-7.0
>>
>> Fabiano Rosas (8):
>> target/ppc: Introduce powerpc_excp_74xx
>> target/ppc: Simplify powerpc_excp_74xx
>> target/ppc: 74xx: Machine Check exception cleanup
>> target/ppc: 74xx: External interrupt cleanup
>> target/ppc: 74xx: Program exception cleanup
>> target/ppc: 74xx: System Call exception cleanup
>> target/ppc: 74xx: System Reset interrupt cleanup
>> target/ppc: 74xx: Set SRRs directly in exception code
>>
>> target/ppc/excp_helper.c | 175 +++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 175 insertions(+)
>
> I'm not overly familiar with PPC exception handling detail, so I can't offer much in
> the way of review I'm afraid. I could do a quick test and make sure nothing breaks
> with my MacOS images though?
Sure, no problem. This is more of an FYI and so you know whom to yell at
in case anything breaks for you.
I have some MacOS images I can use to test as well. I'll do a thorough
pass before sending the v2.
> Also any thoughts on Christophe's question re: e300 PVRs at
> https://lists.gnu.org/archive/html/qemu-ppc/2022-01/msg00592.html? I can handle
> merging the OpenBIOS changes if someone can come up with a suitable fix.
I believe Cédric has been looking at the 60x, maybe he has some
input. We currently can only run the 604 if I'm not mistaken, so there's
some work to be done to bring all of the 60x back to life. The e300 will
be in the mix.
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 0/8] target/ppc: powerpc_excp improvements [74xx] (5/n)
2022-01-27 15:16 ` Fabiano Rosas
@ 2022-01-27 16:51 ` Cédric Le Goater
0 siblings, 0 replies; 16+ messages in thread
From: Cédric Le Goater @ 2022-01-27 16:51 UTC (permalink / raw)
To: Fabiano Rosas, Mark Cave-Ayland, qemu-devel
Cc: danielhb413, qemu-ppc, Christophe Leroy, david
On 1/27/22 16:16, Fabiano Rosas wrote:
> Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> writes:
>
>> On 26/01/2022 16:41, Fabiano Rosas wrote:
>>
>>> This handles the exception code for the 74xx family, i.e. 7400, 7410,
>>> 7440, 7445, 7450, 7455, 7457.
>>>
>>> This is another family that is quite well known, so it should be
>>> straight-forward as well.
>>>
>>> Based on legoater/ppc-7.0
>>>
>>> Fabiano Rosas (8):
>>> target/ppc: Introduce powerpc_excp_74xx
>>> target/ppc: Simplify powerpc_excp_74xx
>>> target/ppc: 74xx: Machine Check exception cleanup
>>> target/ppc: 74xx: External interrupt cleanup
>>> target/ppc: 74xx: Program exception cleanup
>>> target/ppc: 74xx: System Call exception cleanup
>>> target/ppc: 74xx: System Reset interrupt cleanup
>>> target/ppc: 74xx: Set SRRs directly in exception code
>>>
>>> target/ppc/excp_helper.c | 175 +++++++++++++++++++++++++++++++++++++++
>>> 1 file changed, 175 insertions(+)
>>
>> I'm not overly familiar with PPC exception handling detail, so I can't offer much in
>> the way of review I'm afraid. I could do a quick test and make sure nothing breaks
>> with my MacOS images though?
>
> Sure, no problem. This is more of an FYI and so you know whom to yell at
> in case anything breaks for you.
yes ! Thanks,
> I have some MacOS images I can use to test as well. I'll do a thorough
> pass before sending the v2.
>
>> Also any thoughts on Christophe's question re: e300 PVRs at
>> https://lists.gnu.org/archive/html/qemu-ppc/2022-01/msg00592.html? I can handle
>> merging the OpenBIOS changes if someone can come up with a suitable fix.
Why not simply extend 'struct cpudef' with a flag/feature field ?
> I believe Cédric has been looking at the 60x, maybe he has some
> input.
yes. 604 is running fine under the 40p machine with OpenBIOS.
I have an old debian 3 disk image for it.
On the same machine, AIX 4x and 5x also run with this firmware :
http://github.com/artyom-tarasenko/openfirmware/releases/download/40p-20190413/q40pofw-serial.rom
and the g3beige supports 604.
Getting a status on 603 is more complex. We need support for the
6xx SoftTLBs in OpenBIOS to move forward. Christophe and I have
spent some time on this. Work in progress.
602 should be removed IMHO. It has no real value.
601 is a transitional processor. It think it should be good to
keep as a reference. I don't have a workload for it though.
> We currently can only run the 604 if I'm not mistaken, so there's
> some work to be done to bring all of the 60x back to life. The e300 will
> be in the mix.
It should yes. I haven't looked at it yet.
Thanks,
C.
^ permalink raw reply [flat|nested] 16+ messages in thread