[Intel-gfx] [PATCH 00/14] drm/i915: M/N cleanup

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* [Intel-gfx] [PATCH 00/14] drm/i915: M/N cleanup
@ 2022-01-27  9:32 Ville Syrjala
  2022-01-27  9:32 ` [Intel-gfx] [PATCH 01/14] drm/i915: Extract intel_{get,set}_m_n() Ville Syrjala
                   ` (17 more replies)
  0 siblings, 18 replies; 31+ messages in thread
From: Ville Syrjala @ 2022-01-27  9:32 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Start cleaning up the M/N stuff. Couple of eventual goals:
- fix/enhance DRRS (it's currently in kind of poor state)
- move towards eliminating any RMW stuff from the atomic
  commit so that we can start playing around with using
  DSB for it, and the DRRS PIPECONF RMWs are a bit in the
  way so need to think of a way to avoid them, or at least
  make them not race with the atomic commit.

Ville Syrjälä (14):
  drm/i915: Extract intel_{get,set}_m_n()
  drm/i915: Clean up M/N register defines
  drm/i915: s/gmch_{m,n}/data_{m,n}/
  drm/i915: Move drrs hardware bit frobbing to small helpers
  drm/i915: Make M/N set/get a bit more direct
  drm/i915: Move PCH transcoder M/N setup into the PCH code
  drm/i915: Move M/N setup to a more logical place on ddi platforms
  drm/i915: Extract {i9xx,ilk}_configure_cpu_transcoder()
  drm/i915: Add fdi_m2_n2
  drm/i915: Program FDI RX TUSIZE2
  drm/i915: Dump dp_m2_n2 always
  drm/i915: Extract can_enable_drrs()
  drm/i915: Set DP M2/N2 equal to M1/N1 when not doing DRRS
  drm/i915: Always check dp_m2_n2 on pre-bdw

 drivers/gpu/drm/i915/display/g4x_dp.c         |  20 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      |  18 +-
 drivers/gpu/drm/i915/display/intel_display.c  | 355 ++++++++----------
 drivers/gpu/drm/i915/display/intel_display.h  |  35 +-
 .../drm/i915/display/intel_display_types.h    |  21 +-
 drivers/gpu/drm/i915/display/intel_dp.c       |   2 +-
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |   2 -
 drivers/gpu/drm/i915/display/intel_drrs.c     | 107 +++---
 drivers/gpu/drm/i915/display/intel_fdi.c      |   9 +
 .../gpu/drm/i915/display/intel_pch_display.c  |  56 ++-
 .../gpu/drm/i915/display/intel_pch_display.h  |   6 +
 drivers/gpu/drm/i915/i915_reg.h               |  22 +-
 12 files changed, 342 insertions(+), 311 deletions(-)

-- 
2.34.1


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [Intel-gfx] [PATCH 01/14] drm/i915: Extract intel_{get,set}_m_n()
  2022-01-27  9:32 [Intel-gfx] [PATCH 00/14] drm/i915: M/N cleanup Ville Syrjala
@ 2022-01-27  9:32 ` Ville Syrjala
  2022-01-27 11:11   ` [Intel-gfx] [PATCH 01/14] drm/i915: Extract intel_{get, set}_m_n() Jani Nikula
  2022-01-27  9:32 ` [Intel-gfx] [PATCH 02/14] drm/i915: Clean up M/N register defines Ville Syrjala
                   ` (16 subsequent siblings)
  17 siblings, 1 reply; 31+ messages in thread
From: Ville Syrjala @ 2022-01-27  9:32 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Make the M/N setup/readout a bit less repitive by extracting
a few small helpers.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 109 ++++++++-----------
 1 file changed, 47 insertions(+), 62 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 91add3d85151..f76faa195cb9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3113,6 +3113,17 @@ static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
 	}
 }
 
+static void intel_set_m_n(struct drm_i915_private *i915,
+			  const struct intel_link_m_n *m_n,
+			  i915_reg_t data_m_reg, i915_reg_t data_n_reg,
+			  i915_reg_t link_m_reg, i915_reg_t link_n_reg)
+{
+	intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->gmch_m);
+	intel_de_write(i915, data_n_reg, m_n->gmch_n);
+	intel_de_write(i915, link_m_reg, m_n->link_m);
+	intel_de_write(i915, link_n_reg, m_n->link_n);
+}
+
 static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
 					 const struct intel_link_m_n *m_n)
 {
@@ -3120,11 +3131,9 @@ static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_sta
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 
-	intel_de_write(dev_priv, PCH_TRANS_DATA_M1(pipe),
-		       TU_SIZE(m_n->tu) | m_n->gmch_m);
-	intel_de_write(dev_priv, PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
-	intel_de_write(dev_priv, PCH_TRANS_LINK_M1(pipe), m_n->link_m);
-	intel_de_write(dev_priv, PCH_TRANS_LINK_N1(pipe), m_n->link_n);
+	intel_set_m_n(dev_priv, m_n,
+		      PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe),
+		      PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe));
 }
 
 static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
@@ -3150,35 +3159,23 @@ static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_sta
 	enum transcoder transcoder = crtc_state->cpu_transcoder;
 
 	if (DISPLAY_VER(dev_priv) >= 5) {
-		intel_de_write(dev_priv, PIPE_DATA_M1(transcoder),
-			       TU_SIZE(m_n->tu) | m_n->gmch_m);
-		intel_de_write(dev_priv, PIPE_DATA_N1(transcoder),
-			       m_n->gmch_n);
-		intel_de_write(dev_priv, PIPE_LINK_M1(transcoder),
-			       m_n->link_m);
-		intel_de_write(dev_priv, PIPE_LINK_N1(transcoder),
-			       m_n->link_n);
+		intel_set_m_n(dev_priv, m_n,
+			      PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
+			      PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
 		/*
 		 *  M2_N2 registers are set only if DRRS is supported
 		 * (to make sure the registers are not unnecessarily accessed).
 		 */
 		if (m2_n2 && crtc_state->has_drrs &&
 		    transcoder_has_m2_n2(dev_priv, transcoder)) {
-			intel_de_write(dev_priv, PIPE_DATA_M2(transcoder),
-				       TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
-			intel_de_write(dev_priv, PIPE_DATA_N2(transcoder),
-				       m2_n2->gmch_n);
-			intel_de_write(dev_priv, PIPE_LINK_M2(transcoder),
-				       m2_n2->link_m);
-			intel_de_write(dev_priv, PIPE_LINK_N2(transcoder),
-				       m2_n2->link_n);
+			intel_set_m_n(dev_priv, m2_n2,
+				      PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
+				      PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
 		}
 	} else {
-		intel_de_write(dev_priv, PIPE_DATA_M_G4X(pipe),
-			       TU_SIZE(m_n->tu) | m_n->gmch_m);
-		intel_de_write(dev_priv, PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
-		intel_de_write(dev_priv, PIPE_LINK_M_G4X(pipe), m_n->link_m);
-		intel_de_write(dev_priv, PIPE_LINK_N_G4X(pipe), m_n->link_n);
+		intel_set_m_n(dev_priv, m_n,
+			      PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
+			      PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
 	}
 }
 
@@ -3863,6 +3860,18 @@ int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
 	return DIV_ROUND_UP(bps, link_bw * 8);
 }
 
+static void intel_get_m_n(struct drm_i915_private *i915,
+			  struct intel_link_m_n *m_n,
+			  i915_reg_t data_m_reg, i915_reg_t data_n_reg,
+			  i915_reg_t link_m_reg, i915_reg_t link_n_reg)
+{
+	m_n->link_m = intel_de_read(i915, link_m_reg);
+	m_n->link_n = intel_de_read(i915, link_n_reg);
+	m_n->gmch_m = intel_de_read(i915, data_m_reg) & ~TU_SIZE_MASK;
+	m_n->gmch_n = intel_de_read(i915, data_n_reg);
+	m_n->tu = ((intel_de_read(i915, data_m_reg) & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
+}
+
 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
 					 struct intel_link_m_n *m_n)
 {
@@ -3870,13 +3879,9 @@ static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	enum pipe pipe = crtc->pipe;
 
-	m_n->link_m = intel_de_read(dev_priv, PCH_TRANS_LINK_M1(pipe));
-	m_n->link_n = intel_de_read(dev_priv, PCH_TRANS_LINK_N1(pipe));
-	m_n->gmch_m = intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
-		& ~TU_SIZE_MASK;
-	m_n->gmch_n = intel_de_read(dev_priv, PCH_TRANS_DATA_N1(pipe));
-	m_n->tu = ((intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
-		    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
+	intel_get_m_n(dev_priv, m_n,
+		      PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe),
+		      PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe));
 }
 
 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
@@ -3888,39 +3893,19 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
 	enum pipe pipe = crtc->pipe;
 
 	if (DISPLAY_VER(dev_priv) >= 5) {
-		m_n->link_m = intel_de_read(dev_priv,
-					    PIPE_LINK_M1(transcoder));
-		m_n->link_n = intel_de_read(dev_priv,
-					    PIPE_LINK_N1(transcoder));
-		m_n->gmch_m = intel_de_read(dev_priv,
-					    PIPE_DATA_M1(transcoder))
-			& ~TU_SIZE_MASK;
-		m_n->gmch_n = intel_de_read(dev_priv,
-					    PIPE_DATA_N1(transcoder));
-		m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M1(transcoder))
-			    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
+		intel_get_m_n(dev_priv, m_n,
+			      PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
+			      PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
 
 		if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {
-			m2_n2->link_m = intel_de_read(dev_priv,
-						      PIPE_LINK_M2(transcoder));
-			m2_n2->link_n =	intel_de_read(dev_priv,
-							     PIPE_LINK_N2(transcoder));
-			m2_n2->gmch_m =	intel_de_read(dev_priv,
-							     PIPE_DATA_M2(transcoder))
-					& ~TU_SIZE_MASK;
-			m2_n2->gmch_n =	intel_de_read(dev_priv,
-							     PIPE_DATA_N2(transcoder));
-			m2_n2->tu = ((intel_de_read(dev_priv, PIPE_DATA_M2(transcoder))
-					& TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
+			intel_get_m_n(dev_priv, m2_n2,
+				      PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
+				      PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
 		}
 	} else {
-		m_n->link_m = intel_de_read(dev_priv, PIPE_LINK_M_G4X(pipe));
-		m_n->link_n = intel_de_read(dev_priv, PIPE_LINK_N_G4X(pipe));
-		m_n->gmch_m = intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
-			& ~TU_SIZE_MASK;
-		m_n->gmch_n = intel_de_read(dev_priv, PIPE_DATA_N_G4X(pipe));
-		m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
-			    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
+		intel_get_m_n(dev_priv, m_n,
+			      PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
+			      PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
 	}
 }
 
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 31+ messages in thread

* Re: [Intel-gfx] [PATCH 01/14] drm/i915: Extract intel_{get, set}_m_n()
  2022-01-27  9:32 ` [Intel-gfx] [PATCH 01/14] drm/i915: Extract intel_{get,set}_m_n() Ville Syrjala
@ 2022-01-27 11:11   ` Jani Nikula
  0 siblings, 0 replies; 31+ messages in thread
From: Jani Nikula @ 2022-01-27 11:11 UTC (permalink / raw)
  To: Ville Syrjala, intel-gfx

On Thu, 27 Jan 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Make the M/N setup/readout a bit less repitive by extracting
> a few small helpers.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Nice!

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 109 ++++++++-----------
>  1 file changed, 47 insertions(+), 62 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 91add3d85151..f76faa195cb9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3113,6 +3113,17 @@ static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
>  	}
>  }
>  
> +static void intel_set_m_n(struct drm_i915_private *i915,
> +			  const struct intel_link_m_n *m_n,
> +			  i915_reg_t data_m_reg, i915_reg_t data_n_reg,
> +			  i915_reg_t link_m_reg, i915_reg_t link_n_reg)
> +{
> +	intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->gmch_m);
> +	intel_de_write(i915, data_n_reg, m_n->gmch_n);
> +	intel_de_write(i915, link_m_reg, m_n->link_m);
> +	intel_de_write(i915, link_n_reg, m_n->link_n);
> +}
> +
>  static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
>  					 const struct intel_link_m_n *m_n)
>  {
> @@ -3120,11 +3131,9 @@ static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_sta
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum pipe pipe = crtc->pipe;
>  
> -	intel_de_write(dev_priv, PCH_TRANS_DATA_M1(pipe),
> -		       TU_SIZE(m_n->tu) | m_n->gmch_m);
> -	intel_de_write(dev_priv, PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
> -	intel_de_write(dev_priv, PCH_TRANS_LINK_M1(pipe), m_n->link_m);
> -	intel_de_write(dev_priv, PCH_TRANS_LINK_N1(pipe), m_n->link_n);
> +	intel_set_m_n(dev_priv, m_n,
> +		      PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe),
> +		      PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe));
>  }
>  
>  static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
> @@ -3150,35 +3159,23 @@ static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_sta
>  	enum transcoder transcoder = crtc_state->cpu_transcoder;
>  
>  	if (DISPLAY_VER(dev_priv) >= 5) {
> -		intel_de_write(dev_priv, PIPE_DATA_M1(transcoder),
> -			       TU_SIZE(m_n->tu) | m_n->gmch_m);
> -		intel_de_write(dev_priv, PIPE_DATA_N1(transcoder),
> -			       m_n->gmch_n);
> -		intel_de_write(dev_priv, PIPE_LINK_M1(transcoder),
> -			       m_n->link_m);
> -		intel_de_write(dev_priv, PIPE_LINK_N1(transcoder),
> -			       m_n->link_n);
> +		intel_set_m_n(dev_priv, m_n,
> +			      PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
> +			      PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
>  		/*
>  		 *  M2_N2 registers are set only if DRRS is supported
>  		 * (to make sure the registers are not unnecessarily accessed).
>  		 */
>  		if (m2_n2 && crtc_state->has_drrs &&
>  		    transcoder_has_m2_n2(dev_priv, transcoder)) {
> -			intel_de_write(dev_priv, PIPE_DATA_M2(transcoder),
> -				       TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
> -			intel_de_write(dev_priv, PIPE_DATA_N2(transcoder),
> -				       m2_n2->gmch_n);
> -			intel_de_write(dev_priv, PIPE_LINK_M2(transcoder),
> -				       m2_n2->link_m);
> -			intel_de_write(dev_priv, PIPE_LINK_N2(transcoder),
> -				       m2_n2->link_n);
> +			intel_set_m_n(dev_priv, m2_n2,
> +				      PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
> +				      PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
>  		}
>  	} else {
> -		intel_de_write(dev_priv, PIPE_DATA_M_G4X(pipe),
> -			       TU_SIZE(m_n->tu) | m_n->gmch_m);
> -		intel_de_write(dev_priv, PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
> -		intel_de_write(dev_priv, PIPE_LINK_M_G4X(pipe), m_n->link_m);
> -		intel_de_write(dev_priv, PIPE_LINK_N_G4X(pipe), m_n->link_n);
> +		intel_set_m_n(dev_priv, m_n,
> +			      PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
> +			      PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
>  	}
>  }
>  
> @@ -3863,6 +3860,18 @@ int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
>  	return DIV_ROUND_UP(bps, link_bw * 8);
>  }
>  
> +static void intel_get_m_n(struct drm_i915_private *i915,
> +			  struct intel_link_m_n *m_n,
> +			  i915_reg_t data_m_reg, i915_reg_t data_n_reg,
> +			  i915_reg_t link_m_reg, i915_reg_t link_n_reg)
> +{
> +	m_n->link_m = intel_de_read(i915, link_m_reg);
> +	m_n->link_n = intel_de_read(i915, link_n_reg);
> +	m_n->gmch_m = intel_de_read(i915, data_m_reg) & ~TU_SIZE_MASK;
> +	m_n->gmch_n = intel_de_read(i915, data_n_reg);
> +	m_n->tu = ((intel_de_read(i915, data_m_reg) & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
> +}
> +
>  static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
>  					 struct intel_link_m_n *m_n)
>  {
> @@ -3870,13 +3879,9 @@ static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	enum pipe pipe = crtc->pipe;
>  
> -	m_n->link_m = intel_de_read(dev_priv, PCH_TRANS_LINK_M1(pipe));
> -	m_n->link_n = intel_de_read(dev_priv, PCH_TRANS_LINK_N1(pipe));
> -	m_n->gmch_m = intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
> -		& ~TU_SIZE_MASK;
> -	m_n->gmch_n = intel_de_read(dev_priv, PCH_TRANS_DATA_N1(pipe));
> -	m_n->tu = ((intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
> -		    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
> +	intel_get_m_n(dev_priv, m_n,
> +		      PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe),
> +		      PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe));
>  }
>  
>  static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
> @@ -3888,39 +3893,19 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
>  	enum pipe pipe = crtc->pipe;
>  
>  	if (DISPLAY_VER(dev_priv) >= 5) {
> -		m_n->link_m = intel_de_read(dev_priv,
> -					    PIPE_LINK_M1(transcoder));
> -		m_n->link_n = intel_de_read(dev_priv,
> -					    PIPE_LINK_N1(transcoder));
> -		m_n->gmch_m = intel_de_read(dev_priv,
> -					    PIPE_DATA_M1(transcoder))
> -			& ~TU_SIZE_MASK;
> -		m_n->gmch_n = intel_de_read(dev_priv,
> -					    PIPE_DATA_N1(transcoder));
> -		m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M1(transcoder))
> -			    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
> +		intel_get_m_n(dev_priv, m_n,
> +			      PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
> +			      PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
>  
>  		if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {
> -			m2_n2->link_m = intel_de_read(dev_priv,
> -						      PIPE_LINK_M2(transcoder));
> -			m2_n2->link_n =	intel_de_read(dev_priv,
> -							     PIPE_LINK_N2(transcoder));
> -			m2_n2->gmch_m =	intel_de_read(dev_priv,
> -							     PIPE_DATA_M2(transcoder))
> -					& ~TU_SIZE_MASK;
> -			m2_n2->gmch_n =	intel_de_read(dev_priv,
> -							     PIPE_DATA_N2(transcoder));
> -			m2_n2->tu = ((intel_de_read(dev_priv, PIPE_DATA_M2(transcoder))
> -					& TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
> +			intel_get_m_n(dev_priv, m2_n2,
> +				      PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
> +				      PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
>  		}
>  	} else {
> -		m_n->link_m = intel_de_read(dev_priv, PIPE_LINK_M_G4X(pipe));
> -		m_n->link_n = intel_de_read(dev_priv, PIPE_LINK_N_G4X(pipe));
> -		m_n->gmch_m = intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
> -			& ~TU_SIZE_MASK;
> -		m_n->gmch_n = intel_de_read(dev_priv, PIPE_DATA_N_G4X(pipe));
> -		m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
> -			    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
> +		intel_get_m_n(dev_priv, m_n,
> +			      PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
> +			      PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
>  	}
>  }

-- 
Jani Nikula, Intel Open Source Graphics Center

^ permalink raw reply	[flat|nested] 31+ messages in thread

* [Intel-gfx] [PATCH 02/14] drm/i915: Clean up M/N register defines
  2022-01-27  9:32 [Intel-gfx] [PATCH 00/14] drm/i915: M/N cleanup Ville Syrjala
  2022-01-27  9:32 ` [Intel-gfx] [PATCH 01/14] drm/i915: Extract intel_{get,set}_m_n() Ville Syrjala
@ 2022-01-27  9:32 ` Ville Syrjala
  2022-01-27 11:17   ` Jani Nikula
                     ` (2 more replies)
  2022-01-27  9:32 ` [Intel-gfx] [PATCH 03/14] drm/i915: s/gmch_{m,n}/data_{m,n}/ Ville Syrjala
                   ` (15 subsequent siblings)
  17 siblings, 3 replies; 31+ messages in thread
From: Ville Syrjala @ 2022-01-27  9:32 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use REG_GENMASK() & co. for the M/N register values. There are
also a lot of weird unused defines (eg. *_OFFSET) we can just
throw out.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 10 ++++-----
 drivers/gpu/drm/i915/i915_reg.h              | 22 +++-----------------
 2 files changed, 8 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f76faa195cb9..d91164d1eb92 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3865,11 +3865,11 @@ static void intel_get_m_n(struct drm_i915_private *i915,
 			  i915_reg_t data_m_reg, i915_reg_t data_n_reg,
 			  i915_reg_t link_m_reg, i915_reg_t link_n_reg)
 {
-	m_n->link_m = intel_de_read(i915, link_m_reg);
-	m_n->link_n = intel_de_read(i915, link_n_reg);
-	m_n->gmch_m = intel_de_read(i915, data_m_reg) & ~TU_SIZE_MASK;
-	m_n->gmch_n = intel_de_read(i915, data_n_reg);
-	m_n->tu = ((intel_de_read(i915, data_m_reg) & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
+	m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK;
+	m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK;
+	m_n->gmch_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK;
+	m_n->gmch_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK;
+	m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1;
 }
 
 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2e4dd9db63fe..ec48406eb37a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5209,16 +5209,14 @@ enum {
 #define _PIPEB_DATA_M_G4X	0x71050
 
 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
-#define  TU_SIZE(x)             (((x) - 1) << 25) /* default size 64 */
-#define  TU_SIZE_SHIFT		25
-#define  TU_SIZE_MASK           (0x3f << 25)
+#define  TU_SIZE_MASK		REG_GENMASK(30, 25)
+#define  TU_SIZE(x)		REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */
 
-#define  DATA_LINK_M_N_MASK	(0xffffff)
+#define  DATA_LINK_M_N_MASK	REG_GENMASK(23, 0)
 #define  DATA_LINK_N_MAX	(0x800000)
 
 #define _PIPEA_DATA_N_G4X	0x70054
 #define _PIPEB_DATA_N_G4X	0x71054
-#define   PIPE_GMCH_DATA_N_MASK			(0xffffff)
 
 /*
  * Computing Link M and N values for the Display Port link
@@ -5233,11 +5231,8 @@ enum {
 
 #define _PIPEA_LINK_M_G4X	0x70060
 #define _PIPEB_LINK_M_G4X	0x71060
-#define   PIPEA_DP_LINK_M_MASK			(0xffffff)
-
 #define _PIPEA_LINK_N_G4X	0x70064
 #define _PIPEB_LINK_N_G4X	0x71064
-#define   PIPEA_DP_LINK_N_MASK			(0xffffff)
 
 #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
 #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
@@ -6840,24 +6835,13 @@ enum {
 
 
 #define _PIPEA_DATA_M1		0x60030
-#define  PIPE_DATA_M1_OFFSET    0
 #define _PIPEA_DATA_N1		0x60034
-#define  PIPE_DATA_N1_OFFSET    0
-
 #define _PIPEA_DATA_M2		0x60038
-#define  PIPE_DATA_M2_OFFSET    0
 #define _PIPEA_DATA_N2		0x6003c
-#define  PIPE_DATA_N2_OFFSET    0
-
 #define _PIPEA_LINK_M1		0x60040
-#define  PIPE_LINK_M1_OFFSET    0
 #define _PIPEA_LINK_N1		0x60044
-#define  PIPE_LINK_N1_OFFSET    0
-
 #define _PIPEA_LINK_M2		0x60048
-#define  PIPE_LINK_M2_OFFSET    0
 #define _PIPEA_LINK_N2		0x6004c
-#define  PIPE_LINK_N2_OFFSET    0
 
 /* PIPEB timing regs are same start from 0x61000 */
 
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 31+ messages in thread

* Re: [Intel-gfx] [PATCH 02/14] drm/i915: Clean up M/N register defines
  2022-01-27  9:32 ` [Intel-gfx] [PATCH 02/14] drm/i915: Clean up M/N register defines Ville Syrjala
@ 2022-01-27 11:17   ` Jani Nikula
  2022-01-27 11:32     ` Ville Syrjälä
  2022-01-27 12:02   ` [Intel-gfx] [PATCH v2 " Ville Syrjala
  2022-01-27 17:36     ` kernel test robot
  2 siblings, 1 reply; 31+ messages in thread
From: Jani Nikula @ 2022-01-27 11:17 UTC (permalink / raw)
  To: Ville Syrjala, intel-gfx

On Thu, 27 Jan 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use REG_GENMASK() & co. for the M/N register values. There are
> also a lot of weird unused defines (eg. *_OFFSET) we can just
> throw out.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 10 ++++-----
>  drivers/gpu/drm/i915/i915_reg.h              | 22 +++-----------------
>  2 files changed, 8 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index f76faa195cb9..d91164d1eb92 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3865,11 +3865,11 @@ static void intel_get_m_n(struct drm_i915_private *i915,
>  			  i915_reg_t data_m_reg, i915_reg_t data_n_reg,
>  			  i915_reg_t link_m_reg, i915_reg_t link_n_reg)
>  {
> -	m_n->link_m = intel_de_read(i915, link_m_reg);
> -	m_n->link_n = intel_de_read(i915, link_n_reg);
> -	m_n->gmch_m = intel_de_read(i915, data_m_reg) & ~TU_SIZE_MASK;
> -	m_n->gmch_n = intel_de_read(i915, data_n_reg);
> -	m_n->tu = ((intel_de_read(i915, data_m_reg) & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
> +	m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK;
> +	m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK;
> +	m_n->gmch_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK;
> +	m_n->gmch_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK;
> +	m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1;

The commit message might mention we throw some bits away while reading.

A follow-up could perhasps axe the double read of the data_m_reg, but
*shrug*.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


>  }
>  
>  static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2e4dd9db63fe..ec48406eb37a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5209,16 +5209,14 @@ enum {
>  #define _PIPEB_DATA_M_G4X	0x71050
>  
>  /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
> -#define  TU_SIZE(x)             (((x) - 1) << 25) /* default size 64 */
> -#define  TU_SIZE_SHIFT		25
> -#define  TU_SIZE_MASK           (0x3f << 25)
> +#define  TU_SIZE_MASK		REG_GENMASK(30, 25)
> +#define  TU_SIZE(x)		REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */
>  
> -#define  DATA_LINK_M_N_MASK	(0xffffff)
> +#define  DATA_LINK_M_N_MASK	REG_GENMASK(23, 0)
>  #define  DATA_LINK_N_MAX	(0x800000)
>  
>  #define _PIPEA_DATA_N_G4X	0x70054
>  #define _PIPEB_DATA_N_G4X	0x71054
> -#define   PIPE_GMCH_DATA_N_MASK			(0xffffff)
>  
>  /*
>   * Computing Link M and N values for the Display Port link
> @@ -5233,11 +5231,8 @@ enum {
>  
>  #define _PIPEA_LINK_M_G4X	0x70060
>  #define _PIPEB_LINK_M_G4X	0x71060
> -#define   PIPEA_DP_LINK_M_MASK			(0xffffff)
> -
>  #define _PIPEA_LINK_N_G4X	0x70064
>  #define _PIPEB_LINK_N_G4X	0x71064
> -#define   PIPEA_DP_LINK_N_MASK			(0xffffff)
>  
>  #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
>  #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
> @@ -6840,24 +6835,13 @@ enum {
>  
>  
>  #define _PIPEA_DATA_M1		0x60030
> -#define  PIPE_DATA_M1_OFFSET    0
>  #define _PIPEA_DATA_N1		0x60034
> -#define  PIPE_DATA_N1_OFFSET    0
> -
>  #define _PIPEA_DATA_M2		0x60038
> -#define  PIPE_DATA_M2_OFFSET    0
>  #define _PIPEA_DATA_N2		0x6003c
> -#define  PIPE_DATA_N2_OFFSET    0
> -
>  #define _PIPEA_LINK_M1		0x60040
> -#define  PIPE_LINK_M1_OFFSET    0
>  #define _PIPEA_LINK_N1		0x60044
> -#define  PIPE_LINK_N1_OFFSET    0
> -
>  #define _PIPEA_LINK_M2		0x60048
> -#define  PIPE_LINK_M2_OFFSET    0
>  #define _PIPEA_LINK_N2		0x6004c
> -#define  PIPE_LINK_N2_OFFSET    0
>  
>  /* PIPEB timing regs are same start from 0x61000 */

-- 
Jani Nikula, Intel Open Source Graphics Center

^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [Intel-gfx] [PATCH 02/14] drm/i915: Clean up M/N register defines
  2022-01-27 11:17   ` Jani Nikula
@ 2022-01-27 11:32     ` Ville Syrjälä
  2022-01-27 11:41       ` Jani Nikula
  0 siblings, 1 reply; 31+ messages in thread
From: Ville Syrjälä @ 2022-01-27 11:32 UTC (permalink / raw)
  To: Jani Nikula; +Cc: intel-gfx

On Thu, Jan 27, 2022 at 01:17:21PM +0200, Jani Nikula wrote:
> On Thu, 27 Jan 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Use REG_GENMASK() & co. for the M/N register values. There are
> > also a lot of weird unused defines (eg. *_OFFSET) we can just
> > throw out.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c | 10 ++++-----
> >  drivers/gpu/drm/i915/i915_reg.h              | 22 +++-----------------
> >  2 files changed, 8 insertions(+), 24 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index f76faa195cb9..d91164d1eb92 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -3865,11 +3865,11 @@ static void intel_get_m_n(struct drm_i915_private *i915,
> >  			  i915_reg_t data_m_reg, i915_reg_t data_n_reg,
> >  			  i915_reg_t link_m_reg, i915_reg_t link_n_reg)
> >  {
> > -	m_n->link_m = intel_de_read(i915, link_m_reg);
> > -	m_n->link_n = intel_de_read(i915, link_n_reg);
> > -	m_n->gmch_m = intel_de_read(i915, data_m_reg) & ~TU_SIZE_MASK;
> > -	m_n->gmch_n = intel_de_read(i915, data_n_reg);
> > -	m_n->tu = ((intel_de_read(i915, data_m_reg) & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
> > +	m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK;
> > +	m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK;
> > +	m_n->gmch_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK;
> > +	m_n->gmch_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK;
> > +	m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1;
> 
> The commit message might mention we throw some bits away while reading.

Right, forgot to note that.

> 
> A follow-up could perhasps axe the double read of the data_m_reg, but
> *shrug*.

I was going back and forth between keeping the double read vs. reading
each just once here vs. reading straight in the callers and just passing
the values through (would avoid needing i915_reg_t for the prototype
in the headrer in a later patch). Somehow none of them tasted quit right
so opted to keep the current thing for now.

> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> 
> >  }
> >  
> >  static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 2e4dd9db63fe..ec48406eb37a 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -5209,16 +5209,14 @@ enum {
> >  #define _PIPEB_DATA_M_G4X	0x71050
> >  
> >  /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
> > -#define  TU_SIZE(x)             (((x) - 1) << 25) /* default size 64 */
> > -#define  TU_SIZE_SHIFT		25
> > -#define  TU_SIZE_MASK           (0x3f << 25)
> > +#define  TU_SIZE_MASK		REG_GENMASK(30, 25)
> > +#define  TU_SIZE(x)		REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */
> >  
> > -#define  DATA_LINK_M_N_MASK	(0xffffff)
> > +#define  DATA_LINK_M_N_MASK	REG_GENMASK(23, 0)
> >  #define  DATA_LINK_N_MAX	(0x800000)
> >  
> >  #define _PIPEA_DATA_N_G4X	0x70054
> >  #define _PIPEB_DATA_N_G4X	0x71054
> > -#define   PIPE_GMCH_DATA_N_MASK			(0xffffff)
> >  
> >  /*
> >   * Computing Link M and N values for the Display Port link
> > @@ -5233,11 +5231,8 @@ enum {
> >  
> >  #define _PIPEA_LINK_M_G4X	0x70060
> >  #define _PIPEB_LINK_M_G4X	0x71060
> > -#define   PIPEA_DP_LINK_M_MASK			(0xffffff)
> > -
> >  #define _PIPEA_LINK_N_G4X	0x70064
> >  #define _PIPEB_LINK_N_G4X	0x71064
> > -#define   PIPEA_DP_LINK_N_MASK			(0xffffff)
> >  
> >  #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
> >  #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
> > @@ -6840,24 +6835,13 @@ enum {
> >  
> >  
> >  #define _PIPEA_DATA_M1		0x60030
> > -#define  PIPE_DATA_M1_OFFSET    0
> >  #define _PIPEA_DATA_N1		0x60034
> > -#define  PIPE_DATA_N1_OFFSET    0
> > -
> >  #define _PIPEA_DATA_M2		0x60038
> > -#define  PIPE_DATA_M2_OFFSET    0
> >  #define _PIPEA_DATA_N2		0x6003c
> > -#define  PIPE_DATA_N2_OFFSET    0
> > -
> >  #define _PIPEA_LINK_M1		0x60040
> > -#define  PIPE_LINK_M1_OFFSET    0
> >  #define _PIPEA_LINK_N1		0x60044
> > -#define  PIPE_LINK_N1_OFFSET    0
> > -
> >  #define _PIPEA_LINK_M2		0x60048
> > -#define  PIPE_LINK_M2_OFFSET    0
> >  #define _PIPEA_LINK_N2		0x6004c
> > -#define  PIPE_LINK_N2_OFFSET    0
> >  
> >  /* PIPEB timing regs are same start from 0x61000 */
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center

-- 
Ville Syrjälä
Intel

^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [Intel-gfx] [PATCH 02/14] drm/i915: Clean up M/N register defines
  2022-01-27 11:32     ` Ville Syrjälä
@ 2022-01-27 11:41       ` Jani Nikula
  0 siblings, 0 replies; 31+ messages in thread
From: Jani Nikula @ 2022-01-27 11:41 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx

On Thu, 27 Jan 2022, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Thu, Jan 27, 2022 at 01:17:21PM +0200, Jani Nikula wrote:
>> On Thu, 27 Jan 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
>> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >
>> > Use REG_GENMASK() & co. for the M/N register values. There are
>> > also a lot of weird unused defines (eg. *_OFFSET) we can just
>> > throw out.
>> >
>> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/display/intel_display.c | 10 ++++-----
>> >  drivers/gpu/drm/i915/i915_reg.h              | 22 +++-----------------
>> >  2 files changed, 8 insertions(+), 24 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> > index f76faa195cb9..d91164d1eb92 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_display.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> > @@ -3865,11 +3865,11 @@ static void intel_get_m_n(struct drm_i915_private *i915,
>> >  			  i915_reg_t data_m_reg, i915_reg_t data_n_reg,
>> >  			  i915_reg_t link_m_reg, i915_reg_t link_n_reg)
>> >  {
>> > -	m_n->link_m = intel_de_read(i915, link_m_reg);
>> > -	m_n->link_n = intel_de_read(i915, link_n_reg);
>> > -	m_n->gmch_m = intel_de_read(i915, data_m_reg) & ~TU_SIZE_MASK;
>> > -	m_n->gmch_n = intel_de_read(i915, data_n_reg);
>> > -	m_n->tu = ((intel_de_read(i915, data_m_reg) & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
>> > +	m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK;
>> > +	m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK;
>> > +	m_n->gmch_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK;
>> > +	m_n->gmch_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK;
>> > +	m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1;
>> 
>> The commit message might mention we throw some bits away while reading.
>
> Right, forgot to note that.
>
>> 
>> A follow-up could perhasps axe the double read of the data_m_reg, but
>> *shrug*.
>
> I was going back and forth between keeping the double read vs. reading
> each just once here vs. reading straight in the callers and just passing
> the values through (would avoid needing i915_reg_t for the prototype
> in the headrer in a later patch). Somehow none of them tasted quit right
> so opted to keep the current thing for now.

Yeah, not a big deal. Also now that i915_reg_t is in i915_reg_defs.h I
think the overhead for that is neglible.

BR,
Jani.

>
>> 
>> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>> 
>> 
>> >  }
>> >  
>> >  static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
>> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> > index 2e4dd9db63fe..ec48406eb37a 100644
>> > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > @@ -5209,16 +5209,14 @@ enum {
>> >  #define _PIPEB_DATA_M_G4X	0x71050
>> >  
>> >  /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
>> > -#define  TU_SIZE(x)             (((x) - 1) << 25) /* default size 64 */
>> > -#define  TU_SIZE_SHIFT		25
>> > -#define  TU_SIZE_MASK           (0x3f << 25)
>> > +#define  TU_SIZE_MASK		REG_GENMASK(30, 25)
>> > +#define  TU_SIZE(x)		REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */
>> >  
>> > -#define  DATA_LINK_M_N_MASK	(0xffffff)
>> > +#define  DATA_LINK_M_N_MASK	REG_GENMASK(23, 0)
>> >  #define  DATA_LINK_N_MAX	(0x800000)
>> >  
>> >  #define _PIPEA_DATA_N_G4X	0x70054
>> >  #define _PIPEB_DATA_N_G4X	0x71054
>> > -#define   PIPE_GMCH_DATA_N_MASK			(0xffffff)
>> >  
>> >  /*
>> >   * Computing Link M and N values for the Display Port link
>> > @@ -5233,11 +5231,8 @@ enum {
>> >  
>> >  #define _PIPEA_LINK_M_G4X	0x70060
>> >  #define _PIPEB_LINK_M_G4X	0x71060
>> > -#define   PIPEA_DP_LINK_M_MASK			(0xffffff)
>> > -
>> >  #define _PIPEA_LINK_N_G4X	0x70064
>> >  #define _PIPEB_LINK_N_G4X	0x71064
>> > -#define   PIPEA_DP_LINK_N_MASK			(0xffffff)
>> >  
>> >  #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
>> >  #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
>> > @@ -6840,24 +6835,13 @@ enum {
>> >  
>> >  
>> >  #define _PIPEA_DATA_M1		0x60030
>> > -#define  PIPE_DATA_M1_OFFSET    0
>> >  #define _PIPEA_DATA_N1		0x60034
>> > -#define  PIPE_DATA_N1_OFFSET    0
>> > -
>> >  #define _PIPEA_DATA_M2		0x60038
>> > -#define  PIPE_DATA_M2_OFFSET    0
>> >  #define _PIPEA_DATA_N2		0x6003c
>> > -#define  PIPE_DATA_N2_OFFSET    0
>> > -
>> >  #define _PIPEA_LINK_M1		0x60040
>> > -#define  PIPE_LINK_M1_OFFSET    0
>> >  #define _PIPEA_LINK_N1		0x60044
>> > -#define  PIPE_LINK_N1_OFFSET    0
>> > -
>> >  #define _PIPEA_LINK_M2		0x60048
>> > -#define  PIPE_LINK_M2_OFFSET    0
>> >  #define _PIPEA_LINK_N2		0x6004c
>> > -#define  PIPE_LINK_N2_OFFSET    0
>> >  
>> >  /* PIPEB timing regs are same start from 0x61000 */
>> 
>> -- 
>> Jani Nikula, Intel Open Source Graphics Center

-- 
Jani Nikula, Intel Open Source Graphics Center

^ permalink raw reply	[flat|nested] 31+ messages in thread

* [Intel-gfx] [PATCH v2 02/14] drm/i915: Clean up M/N register defines
  2022-01-27  9:32 ` [Intel-gfx] [PATCH 02/14] drm/i915: Clean up M/N register defines Ville Syrjala
  2022-01-27 11:17   ` Jani Nikula
@ 2022-01-27 12:02   ` Ville Syrjala
  2022-01-27 17:36     ` kernel test robot
  2 siblings, 0 replies; 31+ messages in thread
From: Ville Syrjala @ 2022-01-27 12:02 UTC (permalink / raw)
  To: intel-gfx; +Cc: Jani Nikula

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use REG_GENMASK() & co. for the M/N register values. There are
also a lot of weird unused defines (eg. *_OFFSET) we can just
throw out.

Also let's mask out the unused bits during readout for good
measure. Previously we only masked out the TU_SIZE from one
of the registers, which was a bit too inconsistent for my
taste.

v2: Mention the readout masking in the commit msg  (Jani)
    Dal wth gvt

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 10 ++++-----
 drivers/gpu/drm/i915/gvt/display.c           |  4 ++--
 drivers/gpu/drm/i915/i915_reg.h              | 22 +++-----------------
 3 files changed, 10 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f76faa195cb9..d91164d1eb92 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3865,11 +3865,11 @@ static void intel_get_m_n(struct drm_i915_private *i915,
 			  i915_reg_t data_m_reg, i915_reg_t data_n_reg,
 			  i915_reg_t link_m_reg, i915_reg_t link_n_reg)
 {
-	m_n->link_m = intel_de_read(i915, link_m_reg);
-	m_n->link_n = intel_de_read(i915, link_n_reg);
-	m_n->gmch_m = intel_de_read(i915, data_m_reg) & ~TU_SIZE_MASK;
-	m_n->gmch_n = intel_de_read(i915, data_n_reg);
-	m_n->tu = ((intel_de_read(i915, data_m_reg) & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
+	m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK;
+	m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK;
+	m_n->gmch_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK;
+	m_n->gmch_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK;
+	m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1;
 }
 
 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index 7198d02edc74..3ce88dea525c 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -253,7 +253,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
 		 *   DP link clk 1620 MHz and non-constant_n.
 		 * TODO: calculate DP link symbol clk and stream clk m/n.
 		 */
-		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT;
+		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = TU_SIZE(64);
 		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;
 		vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
 		vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
@@ -387,7 +387,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
 		 *   DP link clk 1620 MHz and non-constant_n.
 		 * TODO: calculate DP link symbol clk and stream clk m/n.
 		 */
-		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT;
+		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = TU_SIZE(64);
 		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;
 		vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
 		vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2e4dd9db63fe..ec48406eb37a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5209,16 +5209,14 @@ enum {
 #define _PIPEB_DATA_M_G4X	0x71050
 
 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
-#define  TU_SIZE(x)             (((x) - 1) << 25) /* default size 64 */
-#define  TU_SIZE_SHIFT		25
-#define  TU_SIZE_MASK           (0x3f << 25)
+#define  TU_SIZE_MASK		REG_GENMASK(30, 25)
+#define  TU_SIZE(x)		REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */
 
-#define  DATA_LINK_M_N_MASK	(0xffffff)
+#define  DATA_LINK_M_N_MASK	REG_GENMASK(23, 0)
 #define  DATA_LINK_N_MAX	(0x800000)
 
 #define _PIPEA_DATA_N_G4X	0x70054
 #define _PIPEB_DATA_N_G4X	0x71054
-#define   PIPE_GMCH_DATA_N_MASK			(0xffffff)
 
 /*
  * Computing Link M and N values for the Display Port link
@@ -5233,11 +5231,8 @@ enum {
 
 #define _PIPEA_LINK_M_G4X	0x70060
 #define _PIPEB_LINK_M_G4X	0x71060
-#define   PIPEA_DP_LINK_M_MASK			(0xffffff)
-
 #define _PIPEA_LINK_N_G4X	0x70064
 #define _PIPEB_LINK_N_G4X	0x71064
-#define   PIPEA_DP_LINK_N_MASK			(0xffffff)
 
 #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
 #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
@@ -6840,24 +6835,13 @@ enum {
 
 
 #define _PIPEA_DATA_M1		0x60030
-#define  PIPE_DATA_M1_OFFSET    0
 #define _PIPEA_DATA_N1		0x60034
-#define  PIPE_DATA_N1_OFFSET    0
-
 #define _PIPEA_DATA_M2		0x60038
-#define  PIPE_DATA_M2_OFFSET    0
 #define _PIPEA_DATA_N2		0x6003c
-#define  PIPE_DATA_N2_OFFSET    0
-
 #define _PIPEA_LINK_M1		0x60040
-#define  PIPE_LINK_M1_OFFSET    0
 #define _PIPEA_LINK_N1		0x60044
-#define  PIPE_LINK_N1_OFFSET    0
-
 #define _PIPEA_LINK_M2		0x60048
-#define  PIPE_LINK_M2_OFFSET    0
 #define _PIPEA_LINK_N2		0x6004c
-#define  PIPE_LINK_N2_OFFSET    0
 
 /* PIPEB timing regs are same start from 0x61000 */
 
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 31+ messages in thread

* Re: [Intel-gfx] [PATCH 02/14] drm/i915: Clean up M/N register defines
  2022-01-27  9:32 ` [Intel-gfx] [PATCH 02/14] drm/i915: Clean up M/N register defines Ville Syrjala
@ 2022-01-27 17:36     ` kernel test robot
  2022-01-27 12:02   ` [Intel-gfx] [PATCH v2 " Ville Syrjala
  2022-01-27 17:36     ` kernel test robot
  2 siblings, 0 replies; 31+ messages in thread
From: kernel test robot @ 2022-01-27 17:36 UTC (permalink / raw)
  To: Ville Syrjala, intel-gfx; +Cc: llvm, kbuild-all

Hi Ville,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip v5.17-rc1 next-20220127]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Ville-Syrjala/drm-i915-M-N-cleanup/20220127-173547
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-a013-20220124 (https://download.01.org/0day-ci/archive/20220128/202201280100.lCCRgOpP-lkp@intel.com/config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project f32dccb9a43b02ce4e540d6ba5dbbdb188f2dc7d)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/aefa3bba3a5e19c68a1d130b79db7f82f7e77480
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Ville-Syrjala/drm-i915-M-N-cleanup/20220127-173547
        git checkout aefa3bba3a5e19c68a1d130b79db7f82f7e77480
        # save the config file to linux build tree
        mkdir build_dir
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

>> drivers/gpu/drm/i915/gvt/display.c:256:57: error: use of undeclared identifier 'TU_SIZE_SHIFT'
                   vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT;
                                                                         ^
   drivers/gpu/drm/i915/gvt/display.c:390:57: error: use of undeclared identifier 'TU_SIZE_SHIFT'
                   vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT;
                                                                         ^
   2 errors generated.


vim +/TU_SIZE_SHIFT +256 drivers/gpu/drm/i915/gvt/display.c

04d348ae3f0aea Zhi Wang      2016-04-25  169  
04d348ae3f0aea Zhi Wang      2016-04-25  170  static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
04d348ae3f0aea Zhi Wang      2016-04-25  171  {
a61ac1e75105a0 Chris Wilson  2020-03-06  172  	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
65eff272330c72 Xiong Zhang   2018-03-28  173  	int pipe;
65eff272330c72 Xiong Zhang   2018-03-28  174  
72bad997287693 Colin Xu      2018-06-11  175  	if (IS_BROXTON(dev_priv)) {
a5a8ef937cfa79 Colin Xu      2020-11-09  176  		enum transcoder trans;
a5a8ef937cfa79 Colin Xu      2020-11-09  177  		enum port port;
72bad997287693 Colin Xu      2018-06-11  178  
a5a8ef937cfa79 Colin Xu      2020-11-09  179  		/* Clear PIPE, DDI, PHY, HPD before setting new */
8625b221f307ef Ville Syrjälä 2020-10-28  180  		vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
e5abaab30eca51 Ville Syrjälä 2020-10-28  181  			~(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) |
e5abaab30eca51 Ville Syrjälä 2020-10-28  182  			  GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) |
e5abaab30eca51 Ville Syrjälä 2020-10-28  183  			  GEN8_DE_PORT_HOTPLUG(HPD_PORT_C));
72bad997287693 Colin Xu      2018-06-11  184  
a5a8ef937cfa79 Colin Xu      2020-11-09  185  		for_each_pipe(dev_priv, pipe) {
a5a8ef937cfa79 Colin Xu      2020-11-09  186  			vgpu_vreg_t(vgpu, PIPECONF(pipe)) &=
6a6d914de30f15 Ville Syrjälä 2021-11-12  187  				~(PIPECONF_ENABLE | PIPECONF_STATE_ENABLE);
428cb15d5b0031 Ville Syrjälä 2022-01-21  188  			vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE;
a5a8ef937cfa79 Colin Xu      2020-11-09  189  			vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
348abd4cf353ab Ville Syrjälä 2021-12-01  190  			vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE_MASK;
a5a8ef937cfa79 Colin Xu      2020-11-09  191  			vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;
a5a8ef937cfa79 Colin Xu      2020-11-09  192  		}
a5a8ef937cfa79 Colin Xu      2020-11-09  193  
a5a8ef937cfa79 Colin Xu      2020-11-09  194  		for (trans = TRANSCODER_A; trans <= TRANSCODER_EDP; trans++) {
a5a8ef937cfa79 Colin Xu      2020-11-09  195  			vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(trans)) &=
a5a8ef937cfa79 Colin Xu      2020-11-09  196  				~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
a5a8ef937cfa79 Colin Xu      2020-11-09  197  				  TRANS_DDI_PORT_MASK | TRANS_DDI_FUNC_ENABLE);
a5a8ef937cfa79 Colin Xu      2020-11-09  198  		}
a5a8ef937cfa79 Colin Xu      2020-11-09  199  		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
a5a8ef937cfa79 Colin Xu      2020-11-09  200  			~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
a5a8ef937cfa79 Colin Xu      2020-11-09  201  			  TRANS_DDI_PORT_MASK);
a5a8ef937cfa79 Colin Xu      2020-11-09  202  
a5a8ef937cfa79 Colin Xu      2020-11-09  203  		for (port = PORT_A; port <= PORT_C; port++) {
a5a8ef937cfa79 Colin Xu      2020-11-09  204  			vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) &=
a5a8ef937cfa79 Colin Xu      2020-11-09  205  				~BXT_PHY_LANE_ENABLED;
a5a8ef937cfa79 Colin Xu      2020-11-09  206  			vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) |=
a5a8ef937cfa79 Colin Xu      2020-11-09  207  				(BXT_PHY_CMNLANE_POWERDOWN_ACK |
a5a8ef937cfa79 Colin Xu      2020-11-09  208  				 BXT_PHY_LANE_POWERDOWN_ACK);
a5a8ef937cfa79 Colin Xu      2020-11-09  209  
a5a8ef937cfa79 Colin Xu      2020-11-09  210  			vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)) &=
a5a8ef937cfa79 Colin Xu      2020-11-09  211  				~(PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
a5a8ef937cfa79 Colin Xu      2020-11-09  212  				  PORT_PLL_REF_SEL | PORT_PLL_LOCK |
a5a8ef937cfa79 Colin Xu      2020-11-09  213  				  PORT_PLL_ENABLE);
a5a8ef937cfa79 Colin Xu      2020-11-09  214  
a5a8ef937cfa79 Colin Xu      2020-11-09  215  			vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) &=
a5a8ef937cfa79 Colin Xu      2020-11-09  216  				~(DDI_INIT_DISPLAY_DETECTED |
a5a8ef937cfa79 Colin Xu      2020-11-09  217  				  DDI_BUF_CTL_ENABLE);
a5a8ef937cfa79 Colin Xu      2020-11-09  218  			vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE;
a5a8ef937cfa79 Colin Xu      2020-11-09  219  		}
4ceb06e7c336f4 Colin Xu      2020-12-01  220  		vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
4ceb06e7c336f4 Colin Xu      2020-12-01  221  			~(PORTA_HOTPLUG_ENABLE | PORTA_HOTPLUG_STATUS_MASK);
4ceb06e7c336f4 Colin Xu      2020-12-01  222  		vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
4ceb06e7c336f4 Colin Xu      2020-12-01  223  			~(PORTB_HOTPLUG_ENABLE | PORTB_HOTPLUG_STATUS_MASK);
4ceb06e7c336f4 Colin Xu      2020-12-01  224  		vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
4ceb06e7c336f4 Colin Xu      2020-12-01  225  			~(PORTC_HOTPLUG_ENABLE | PORTC_HOTPLUG_STATUS_MASK);
4ceb06e7c336f4 Colin Xu      2020-12-01  226  		/* No hpd_invert set in vgpu vbt, need to clear invert mask */
4ceb06e7c336f4 Colin Xu      2020-12-01  227  		vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= ~BXT_DDI_HPD_INVERT_MASK;
4ceb06e7c336f4 Colin Xu      2020-12-01  228  		vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~BXT_DE_PORT_HOTPLUG_MASK;
a5a8ef937cfa79 Colin Xu      2020-11-09  229  
a5a8ef937cfa79 Colin Xu      2020-11-09  230  		vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= ~(BIT(0) | BIT(1));
a5a8ef937cfa79 Colin Xu      2020-11-09  231  		vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
a5a8ef937cfa79 Colin Xu      2020-11-09  232  			~PHY_POWER_GOOD;
a5a8ef937cfa79 Colin Xu      2020-11-09  233  		vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
a5a8ef937cfa79 Colin Xu      2020-11-09  234  			~PHY_POWER_GOOD;
a5a8ef937cfa79 Colin Xu      2020-11-09  235  		vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= ~BIT(30);
a5a8ef937cfa79 Colin Xu      2020-11-09  236  		vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= ~BIT(30);
a5a8ef937cfa79 Colin Xu      2020-11-09  237  
a5a8ef937cfa79 Colin Xu      2020-11-09  238  		vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIB_DETECTED;
a5a8ef937cfa79 Colin Xu      2020-11-09  239  		vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIC_DETECTED;
a5a8ef937cfa79 Colin Xu      2020-11-09  240  
a5a8ef937cfa79 Colin Xu      2020-11-09  241  		/*
a5a8ef937cfa79 Colin Xu      2020-11-09  242  		 * Only 1 PIPE enabled in current vGPU display and PIPE_A is
a5a8ef937cfa79 Colin Xu      2020-11-09  243  		 *  tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A,
a5a8ef937cfa79 Colin Xu      2020-11-09  244  		 *   TRANSCODER_A can be enabled. PORT_x depends on the input of
a5a8ef937cfa79 Colin Xu      2020-11-09  245  		 *   setup_virtual_dp_monitor.
a5a8ef937cfa79 Colin Xu      2020-11-09  246  		 */
a5a8ef937cfa79 Colin Xu      2020-11-09  247  		vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
6a6d914de30f15 Ville Syrjälä 2021-11-12  248  		vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_STATE_ENABLE;
a5a8ef937cfa79 Colin Xu      2020-11-09  249  
a5a8ef937cfa79 Colin Xu      2020-11-09  250  		/*
a5a8ef937cfa79 Colin Xu      2020-11-09  251  		 * Golden M/N are calculated based on:
a5a8ef937cfa79 Colin Xu      2020-11-09  252  		 *   24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID),
a5a8ef937cfa79 Colin Xu      2020-11-09  253  		 *   DP link clk 1620 MHz and non-constant_n.
a5a8ef937cfa79 Colin Xu      2020-11-09  254  		 * TODO: calculate DP link symbol clk and stream clk m/n.
a5a8ef937cfa79 Colin Xu      2020-11-09  255  		 */
a5a8ef937cfa79 Colin Xu      2020-11-09 @256  		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT;
a5a8ef937cfa79 Colin Xu      2020-11-09  257  		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;
a5a8ef937cfa79 Colin Xu      2020-11-09  258  		vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
a5a8ef937cfa79 Colin Xu      2020-11-09  259  		vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
a5a8ef937cfa79 Colin Xu      2020-11-09  260  		vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
a5a8ef937cfa79 Colin Xu      2020-11-09  261  
a5a8ef937cfa79 Colin Xu      2020-11-09  262  		/* Enable per-DDI/PORT vreg */
72bad997287693 Colin Xu      2018-06-11  263  		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
a5a8ef937cfa79 Colin Xu      2020-11-09  264  			vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(1);
a5a8ef937cfa79 Colin Xu      2020-11-09  265  			vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |=
a5a8ef937cfa79 Colin Xu      2020-11-09  266  				PHY_POWER_GOOD;
a5a8ef937cfa79 Colin Xu      2020-11-09  267  			vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) |=
a5a8ef937cfa79 Colin Xu      2020-11-09  268  				BIT(30);
a5a8ef937cfa79 Colin Xu      2020-11-09  269  			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |=
a5a8ef937cfa79 Colin Xu      2020-11-09  270  				BXT_PHY_LANE_ENABLED;
a5a8ef937cfa79 Colin Xu      2020-11-09  271  			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &=
a5a8ef937cfa79 Colin Xu      2020-11-09  272  				~(BXT_PHY_CMNLANE_POWERDOWN_ACK |
a5a8ef937cfa79 Colin Xu      2020-11-09  273  				  BXT_PHY_LANE_POWERDOWN_ACK);
a5a8ef937cfa79 Colin Xu      2020-11-09  274  			vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_A)) |=
a5a8ef937cfa79 Colin Xu      2020-11-09  275  				(PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
a5a8ef937cfa79 Colin Xu      2020-11-09  276  				 PORT_PLL_REF_SEL | PORT_PLL_LOCK |
a5a8ef937cfa79 Colin Xu      2020-11-09  277  				 PORT_PLL_ENABLE);
a5a8ef937cfa79 Colin Xu      2020-11-09  278  			vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |=
a5a8ef937cfa79 Colin Xu      2020-11-09  279  				(DDI_BUF_CTL_ENABLE | DDI_INIT_DISPLAY_DETECTED);
a5a8ef937cfa79 Colin Xu      2020-11-09  280  			vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &=
a5a8ef937cfa79 Colin Xu      2020-11-09  281  				~DDI_BUF_IS_IDLE;
a5a8ef937cfa79 Colin Xu      2020-11-09  282  			vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)) |=
a5a8ef937cfa79 Colin Xu      2020-11-09  283  				(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
a5a8ef937cfa79 Colin Xu      2020-11-09  284  				 TRANS_DDI_FUNC_ENABLE);
4ceb06e7c336f4 Colin Xu      2020-12-01  285  			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
4ceb06e7c336f4 Colin Xu      2020-12-01  286  				PORTA_HOTPLUG_ENABLE;
72bad997287693 Colin Xu      2018-06-11  287  			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
e5abaab30eca51 Ville Syrjälä 2020-10-28  288  				GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
72bad997287693 Colin Xu      2018-06-11  289  		}
72bad997287693 Colin Xu      2018-06-11  290  
72bad997287693 Colin Xu      2018-06-11  291  		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
a5a8ef937cfa79 Colin Xu      2020-11-09  292  			vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
a5a8ef937cfa79 Colin Xu      2020-11-09  293  			vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);
a5a8ef937cfa79 Colin Xu      2020-11-09  294  			vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
a5a8ef937cfa79 Colin Xu      2020-11-09  295  				PHY_POWER_GOOD;
a5a8ef937cfa79 Colin Xu      2020-11-09  296  			vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |=
a5a8ef937cfa79 Colin Xu      2020-11-09  297  				BIT(30);
a5a8ef937cfa79 Colin Xu      2020-11-09  298  			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |=
a5a8ef937cfa79 Colin Xu      2020-11-09  299  				BXT_PHY_LANE_ENABLED;
a5a8ef937cfa79 Colin Xu      2020-11-09  300  			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &=
a5a8ef937cfa79 Colin Xu      2020-11-09  301  				~(BXT_PHY_CMNLANE_POWERDOWN_ACK |
a5a8ef937cfa79 Colin Xu      2020-11-09  302  				  BXT_PHY_LANE_POWERDOWN_ACK);
a5a8ef937cfa79 Colin Xu      2020-11-09  303  			vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_B)) |=
a5a8ef937cfa79 Colin Xu      2020-11-09  304  				(PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
a5a8ef937cfa79 Colin Xu      2020-11-09  305  				 PORT_PLL_REF_SEL | PORT_PLL_LOCK |
a5a8ef937cfa79 Colin Xu      2020-11-09  306  				 PORT_PLL_ENABLE);
a5a8ef937cfa79 Colin Xu      2020-11-09  307  			vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |=
a5a8ef937cfa79 Colin Xu      2020-11-09  308  				DDI_BUF_CTL_ENABLE;
a5a8ef937cfa79 Colin Xu      2020-11-09  309  			vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &=
a5a8ef937cfa79 Colin Xu      2020-11-09  310  				~DDI_BUF_IS_IDLE;
a5a8ef937cfa79 Colin Xu      2020-11-09  311  			vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
a5a8ef937cfa79 Colin Xu      2020-11-09  312  				(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
a5a8ef937cfa79 Colin Xu      2020-11-09  313  				 (PORT_B << TRANS_DDI_PORT_SHIFT) |
a5a8ef937cfa79 Colin Xu      2020-11-09  314  				 TRANS_DDI_FUNC_ENABLE);
4ceb06e7c336f4 Colin Xu      2020-12-01  315  			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
4ceb06e7c336f4 Colin Xu      2020-12-01  316  				PORTB_HOTPLUG_ENABLE;
72bad997287693 Colin Xu      2018-06-11  317  			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
e5abaab30eca51 Ville Syrjälä 2020-10-28  318  				GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);
72bad997287693 Colin Xu      2018-06-11  319  		}
72bad997287693 Colin Xu      2018-06-11  320  
72bad997287693 Colin Xu      2018-06-11  321  		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
a5a8ef937cfa79 Colin Xu      2020-11-09  322  			vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
a5a8ef937cfa79 Colin Xu      2020-11-09  323  			vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);
a5a8ef937cfa79 Colin Xu      2020-11-09  324  			vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
a5a8ef937cfa79 Colin Xu      2020-11-09  325  				PHY_POWER_GOOD;
a5a8ef937cfa79 Colin Xu      2020-11-09  326  			vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |=
a5a8ef937cfa79 Colin Xu      2020-11-09  327  				BIT(30);
a5a8ef937cfa79 Colin Xu      2020-11-09  328  			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |=
a5a8ef937cfa79 Colin Xu      2020-11-09  329  				BXT_PHY_LANE_ENABLED;
a5a8ef937cfa79 Colin Xu      2020-11-09  330  			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &=
a5a8ef937cfa79 Colin Xu      2020-11-09  331  				~(BXT_PHY_CMNLANE_POWERDOWN_ACK |
a5a8ef937cfa79 Colin Xu      2020-11-09  332  				  BXT_PHY_LANE_POWERDOWN_ACK);
a5a8ef937cfa79 Colin Xu      2020-11-09  333  			vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_C)) |=
a5a8ef937cfa79 Colin Xu      2020-11-09  334  				(PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
a5a8ef937cfa79 Colin Xu      2020-11-09  335  				 PORT_PLL_REF_SEL | PORT_PLL_LOCK |
a5a8ef937cfa79 Colin Xu      2020-11-09  336  				 PORT_PLL_ENABLE);
a5a8ef937cfa79 Colin Xu      2020-11-09  337  			vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |=
a5a8ef937cfa79 Colin Xu      2020-11-09  338  				DDI_BUF_CTL_ENABLE;
a5a8ef937cfa79 Colin Xu      2020-11-09  339  			vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &=
a5a8ef937cfa79 Colin Xu      2020-11-09  340  				~DDI_BUF_IS_IDLE;
a5a8ef937cfa79 Colin Xu      2020-11-09  341  			vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
a5a8ef937cfa79 Colin Xu      2020-11-09  342  				(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
a5a8ef937cfa79 Colin Xu      2020-11-09  343  				 (PORT_B << TRANS_DDI_PORT_SHIFT) |
a5a8ef937cfa79 Colin Xu      2020-11-09  344  				 TRANS_DDI_FUNC_ENABLE);
4ceb06e7c336f4 Colin Xu      2020-12-01  345  			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
4ceb06e7c336f4 Colin Xu      2020-12-01  346  				PORTC_HOTPLUG_ENABLE;
72bad997287693 Colin Xu      2018-06-11  347  			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
e5abaab30eca51 Ville Syrjälä 2020-10-28  348  				GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);
72bad997287693 Colin Xu      2018-06-11  349  		}
72bad997287693 Colin Xu      2018-06-11  350  
72bad997287693 Colin Xu      2018-06-11  351  		return;
72bad997287693 Colin Xu      2018-06-11  352  	}
72bad997287693 Colin Xu      2018-06-11  353  
90551a1296d4db Zhenyu Wang   2017-12-19  354  	vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT |
04d348ae3f0aea Zhi Wang      2016-04-25  355  			SDE_PORTC_HOTPLUG_CPT |
04d348ae3f0aea Zhi Wang      2016-04-25  356  			SDE_PORTD_HOTPLUG_CPT);
04d348ae3f0aea Zhi Wang      2016-04-25  357  
5f4ae2704d59ee Chris Wilson  2020-06-02  358  	if (IS_SKYLAKE(dev_priv) ||
5f4ae2704d59ee Chris Wilson  2020-06-02  359  	    IS_KABYLAKE(dev_priv) ||
5f4ae2704d59ee Chris Wilson  2020-06-02  360  	    IS_COFFEELAKE(dev_priv) ||
5f4ae2704d59ee Chris Wilson  2020-06-02  361  	    IS_COMETLAKE(dev_priv)) {
90551a1296d4db Zhenyu Wang   2017-12-19  362  		vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |
04d348ae3f0aea Zhi Wang      2016-04-25  363  				SDE_PORTE_HOTPLUG_SPT);
90551a1296d4db Zhenyu Wang   2017-12-19  364  		vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=
88a16b64c3f48d Weinan Li     2017-03-17  365  				SKL_FUSE_DOWNLOAD_STATUS |
b2891eb2531e5e Imre Deak     2017-07-11  366  				SKL_FUSE_PG_DIST_STATUS(SKL_PG0) |
b2891eb2531e5e Imre Deak     2017-07-11  367  				SKL_FUSE_PG_DIST_STATUS(SKL_PG1) |
b2891eb2531e5e Imre Deak     2017-07-11  368  				SKL_FUSE_PG_DIST_STATUS(SKL_PG2);
f965b68188ab59 Colin Xu      2020-05-08  369  		/*
f965b68188ab59 Colin Xu      2020-05-08  370  		 * Only 1 PIPE enabled in current vGPU display and PIPE_A is
f965b68188ab59 Colin Xu      2020-05-08  371  		 *  tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A,
f965b68188ab59 Colin Xu      2020-05-08  372  		 *   TRANSCODER_A can be enabled. PORT_x depends on the input of
f965b68188ab59 Colin Xu      2020-05-08  373  		 *   setup_virtual_dp_monitor, we can bind DPLL0 to any PORT_x
f965b68188ab59 Colin Xu      2020-05-08  374  		 *   so we fixed to DPLL0 here.
f965b68188ab59 Colin Xu      2020-05-08  375  		 * Setup DPLL0: DP link clk 1620 MHz, non SSC, DP Mode
f965b68188ab59 Colin Xu      2020-05-08  376  		 */
f965b68188ab59 Colin Xu      2020-05-08  377  		vgpu_vreg_t(vgpu, DPLL_CTRL1) =
f965b68188ab59 Colin Xu      2020-05-08  378  			DPLL_CTRL1_OVERRIDE(DPLL_ID_SKL_DPLL0);
f965b68188ab59 Colin Xu      2020-05-08  379  		vgpu_vreg_t(vgpu, DPLL_CTRL1) |=
f965b68188ab59 Colin Xu      2020-05-08  380  			DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, DPLL_ID_SKL_DPLL0);
f965b68188ab59 Colin Xu      2020-05-08  381  		vgpu_vreg_t(vgpu, LCPLL1_CTL) =
f965b68188ab59 Colin Xu      2020-05-08  382  			LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK;
f965b68188ab59 Colin Xu      2020-05-08  383  		vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0);
f965b68188ab59 Colin Xu      2020-05-08  384  		/*
f965b68188ab59 Colin Xu      2020-05-08  385  		 * Golden M/N are calculated based on:
f965b68188ab59 Colin Xu      2020-05-08  386  		 *   24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID),
f965b68188ab59 Colin Xu      2020-05-08  387  		 *   DP link clk 1620 MHz and non-constant_n.
f965b68188ab59 Colin Xu      2020-05-08  388  		 * TODO: calculate DP link symbol clk and stream clk m/n.
f965b68188ab59 Colin Xu      2020-05-08  389  		 */
f965b68188ab59 Colin Xu      2020-05-08  390  		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT;
f965b68188ab59 Colin Xu      2020-05-08  391  		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;
f965b68188ab59 Colin Xu      2020-05-08  392  		vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
f965b68188ab59 Colin Xu      2020-05-08  393  		vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
f965b68188ab59 Colin Xu      2020-05-08  394  		vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
88a16b64c3f48d Weinan Li     2017-03-17  395  	}
04d348ae3f0aea Zhi Wang      2016-04-25  396  
858b0f571d3091 Bing Niu      2017-02-28  397  	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
f965b68188ab59 Colin Xu      2020-05-08  398  		vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
f965b68188ab59 Colin Xu      2020-05-08  399  			~DPLL_CTRL2_DDI_CLK_OFF(PORT_B);
f965b68188ab59 Colin Xu      2020-05-08  400  		vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
f965b68188ab59 Colin Xu      2020-05-08  401  			DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_B);
f965b68188ab59 Colin Xu      2020-05-08  402  		vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
f965b68188ab59 Colin Xu      2020-05-08  403  			DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_B);
90551a1296d4db Zhenyu Wang   2017-12-19  404  		vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
90551a1296d4db Zhenyu Wang   2017-12-19  405  		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
efa69d734adbf8 Pei Zhang     2017-04-07  406  			~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
efa69d734adbf8 Pei Zhang     2017-04-07  407  			TRANS_DDI_PORT_MASK);
90551a1296d4db Zhenyu Wang   2017-12-19  408  		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
75db1a5b2aea2a Tina Zhang    2020-03-17  409  			(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
efa69d734adbf8 Pei Zhang     2017-04-07  410  			(PORT_B << TRANS_DDI_PORT_SHIFT) |
efa69d734adbf8 Pei Zhang     2017-04-07  411  			TRANS_DDI_FUNC_ENABLE);
295a0d0b55269f Xiong Zhang   2017-06-20  412  		if (IS_BROADWELL(dev_priv)) {
90551a1296d4db Zhenyu Wang   2017-12-19  413  			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &=
295a0d0b55269f Xiong Zhang   2017-06-20  414  				~PORT_CLK_SEL_MASK;
90551a1296d4db Zhenyu Wang   2017-12-19  415  			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |=
295a0d0b55269f Xiong Zhang   2017-06-20  416  				PORT_CLK_SEL_LCPLL_810;
295a0d0b55269f Xiong Zhang   2017-06-20  417  		}
90551a1296d4db Zhenyu Wang   2017-12-19  418  		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE;
90551a1296d4db Zhenyu Wang   2017-12-19  419  		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE;
90551a1296d4db Zhenyu Wang   2017-12-19  420  		vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;
858b0f571d3091 Bing Niu      2017-02-28  421  	}
04d348ae3f0aea Zhi Wang      2016-04-25  422  
858b0f571d3091 Bing Niu      2017-02-28  423  	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
f965b68188ab59 Colin Xu      2020-05-08  424  		vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
f965b68188ab59 Colin Xu      2020-05-08  425  			~DPLL_CTRL2_DDI_CLK_OFF(PORT_C);
f965b68188ab59 Colin Xu      2020-05-08  426  		vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
f965b68188ab59 Colin Xu      2020-05-08  427  			DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_C);
f965b68188ab59 Colin Xu      2020-05-08  428  		vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
f965b68188ab59 Colin Xu      2020-05-08  429  			DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_C);
90551a1296d4db Zhenyu Wang   2017-12-19  430  		vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;
90551a1296d4db Zhenyu Wang   2017-12-19  431  		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
efa69d734adbf8 Pei Zhang     2017-04-07  432  			~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
efa69d734adbf8 Pei Zhang     2017-04-07  433  			TRANS_DDI_PORT_MASK);
90551a1296d4db Zhenyu Wang   2017-12-19  434  		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
75db1a5b2aea2a Tina Zhang    2020-03-17  435  			(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
efa69d734adbf8 Pei Zhang     2017-04-07  436  			(PORT_C << TRANS_DDI_PORT_SHIFT) |
efa69d734adbf8 Pei Zhang     2017-04-07  437  			TRANS_DDI_FUNC_ENABLE);
295a0d0b55269f Xiong Zhang   2017-06-20  438  		if (IS_BROADWELL(dev_priv)) {
90551a1296d4db Zhenyu Wang   2017-12-19  439  			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &=
295a0d0b55269f Xiong Zhang   2017-06-20  440  				~PORT_CLK_SEL_MASK;
90551a1296d4db Zhenyu Wang   2017-12-19  441  			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |=
295a0d0b55269f Xiong Zhang   2017-06-20  442  				PORT_CLK_SEL_LCPLL_810;
295a0d0b55269f Xiong Zhang   2017-06-20  443  		}
90551a1296d4db Zhenyu Wang   2017-12-19  444  		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE;
90551a1296d4db Zhenyu Wang   2017-12-19  445  		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE;
90551a1296d4db Zhenyu Wang   2017-12-19  446  		vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
858b0f571d3091 Bing Niu      2017-02-28  447  	}
04d348ae3f0aea Zhi Wang      2016-04-25  448  
858b0f571d3091 Bing Niu      2017-02-28  449  	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) {
f965b68188ab59 Colin Xu      2020-05-08  450  		vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
f965b68188ab59 Colin Xu      2020-05-08  451  			~DPLL_CTRL2_DDI_CLK_OFF(PORT_D);
f965b68188ab59 Colin Xu      2020-05-08  452  		vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
f965b68188ab59 Colin Xu      2020-05-08  453  			DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_D);
f965b68188ab59 Colin Xu      2020-05-08  454  		vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
f965b68188ab59 Colin Xu      2020-05-08  455  			DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_D);
90551a1296d4db Zhenyu Wang   2017-12-19  456  		vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
90551a1296d4db Zhenyu Wang   2017-12-19  457  		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
efa69d734adbf8 Pei Zhang     2017-04-07  458  			~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
efa69d734adbf8 Pei Zhang     2017-04-07  459  			TRANS_DDI_PORT_MASK);
90551a1296d4db Zhenyu Wang   2017-12-19  460  		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
75db1a5b2aea2a Tina Zhang    2020-03-17  461  			(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
efa69d734adbf8 Pei Zhang     2017-04-07  462  			(PORT_D << TRANS_DDI_PORT_SHIFT) |
efa69d734adbf8 Pei Zhang     2017-04-07  463  			TRANS_DDI_FUNC_ENABLE);
295a0d0b55269f Xiong Zhang   2017-06-20  464  		if (IS_BROADWELL(dev_priv)) {
90551a1296d4db Zhenyu Wang   2017-12-19  465  			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &=
295a0d0b55269f Xiong Zhang   2017-06-20  466  				~PORT_CLK_SEL_MASK;
90551a1296d4db Zhenyu Wang   2017-12-19  467  			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |=
295a0d0b55269f Xiong Zhang   2017-06-20  468  				PORT_CLK_SEL_LCPLL_810;
295a0d0b55269f Xiong Zhang   2017-06-20  469  		}
90551a1296d4db Zhenyu Wang   2017-12-19  470  		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE;
90551a1296d4db Zhenyu Wang   2017-12-19  471  		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE;
90551a1296d4db Zhenyu Wang   2017-12-19  472  		vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;
858b0f571d3091 Bing Niu      2017-02-28  473  	}
04d348ae3f0aea Zhi Wang      2016-04-25  474  
5f4ae2704d59ee Chris Wilson  2020-06-02  475  	if ((IS_SKYLAKE(dev_priv) ||
5f4ae2704d59ee Chris Wilson  2020-06-02  476  	     IS_KABYLAKE(dev_priv) ||
5f4ae2704d59ee Chris Wilson  2020-06-02  477  	     IS_COFFEELAKE(dev_priv) ||
5f4ae2704d59ee Chris Wilson  2020-06-02  478  	     IS_COMETLAKE(dev_priv)) &&
04d348ae3f0aea Zhi Wang      2016-04-25  479  			intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {
90551a1296d4db Zhenyu Wang   2017-12-19  480  		vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;
04d348ae3f0aea Zhi Wang      2016-04-25  481  	}
04d348ae3f0aea Zhi Wang      2016-04-25  482  
04d348ae3f0aea Zhi Wang      2016-04-25  483  	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
04d348ae3f0aea Zhi Wang      2016-04-25  484  		if (IS_BROADWELL(dev_priv))
90551a1296d4db Zhenyu Wang   2017-12-19  485  			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
e5abaab30eca51 Ville Syrjälä 2020-10-28  486  				GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
04d348ae3f0aea Zhi Wang      2016-04-25  487  		else
90551a1296d4db Zhenyu Wang   2017-12-19  488  			vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;
858b0f571d3091 Bing Niu      2017-02-28  489  
90551a1296d4db Zhenyu Wang   2017-12-19  490  		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED;
04d348ae3f0aea Zhi Wang      2016-04-25  491  	}
75e64ff2c2f5ce Xiong Zhang   2017-06-28  492  
75e64ff2c2f5ce Xiong Zhang   2017-06-28  493  	/* Clear host CRT status, so guest couldn't detect this host CRT. */
75e64ff2c2f5ce Xiong Zhang   2017-06-28  494  	if (IS_BROADWELL(dev_priv))
90551a1296d4db Zhenyu Wang   2017-12-19  495  		vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK;
4e889d62b89d00 Xiaolin Zhang 2017-12-05  496  
65eff272330c72 Xiong Zhang   2018-03-28  497  	/* Disable Primary/Sprite/Cursor plane */
65eff272330c72 Xiong Zhang   2018-03-28  498  	for_each_pipe(dev_priv, pipe) {
428cb15d5b0031 Ville Syrjälä 2022-01-21  499  		vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE;
65eff272330c72 Xiong Zhang   2018-03-28  500  		vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
348abd4cf353ab Ville Syrjälä 2021-12-01  501  		vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE_MASK;
b99b9ec1d374fd Ville Syrjälä 2018-01-31  502  		vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;
65eff272330c72 Xiong Zhang   2018-03-28  503  	}
65eff272330c72 Xiong Zhang   2018-03-28  504  
90551a1296d4db Zhenyu Wang   2017-12-19  505  	vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
04d348ae3f0aea Zhi Wang      2016-04-25  506  }
04d348ae3f0aea Zhi Wang      2016-04-25  507  

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [Intel-gfx] [PATCH 02/14] drm/i915: Clean up M/N register defines
@ 2022-01-27 17:36     ` kernel test robot
  0 siblings, 0 replies; 31+ messages in thread
From: kernel test robot @ 2022-01-27 17:36 UTC (permalink / raw)
  To: kbuild-all

[-- Attachment #1: Type: text/plain, Size: 31200 bytes --]

Hi Ville,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip v5.17-rc1 next-20220127]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Ville-Syrjala/drm-i915-M-N-cleanup/20220127-173547
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-a013-20220124 (https://download.01.org/0day-ci/archive/20220128/202201280100.lCCRgOpP-lkp(a)intel.com/config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project f32dccb9a43b02ce4e540d6ba5dbbdb188f2dc7d)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/aefa3bba3a5e19c68a1d130b79db7f82f7e77480
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Ville-Syrjala/drm-i915-M-N-cleanup/20220127-173547
        git checkout aefa3bba3a5e19c68a1d130b79db7f82f7e77480
        # save the config file to linux build tree
        mkdir build_dir
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

>> drivers/gpu/drm/i915/gvt/display.c:256:57: error: use of undeclared identifier 'TU_SIZE_SHIFT'
                   vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT;
                                                                         ^
   drivers/gpu/drm/i915/gvt/display.c:390:57: error: use of undeclared identifier 'TU_SIZE_SHIFT'
                   vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT;
                                                                         ^
   2 errors generated.


vim +/TU_SIZE_SHIFT +256 drivers/gpu/drm/i915/gvt/display.c

04d348ae3f0aea Zhi Wang      2016-04-25  169  
04d348ae3f0aea Zhi Wang      2016-04-25  170  static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
04d348ae3f0aea Zhi Wang      2016-04-25  171  {
a61ac1e75105a0 Chris Wilson  2020-03-06  172  	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
65eff272330c72 Xiong Zhang   2018-03-28  173  	int pipe;
65eff272330c72 Xiong Zhang   2018-03-28  174  
72bad997287693 Colin Xu      2018-06-11  175  	if (IS_BROXTON(dev_priv)) {
a5a8ef937cfa79 Colin Xu      2020-11-09  176  		enum transcoder trans;
a5a8ef937cfa79 Colin Xu      2020-11-09  177  		enum port port;
72bad997287693 Colin Xu      2018-06-11  178  
a5a8ef937cfa79 Colin Xu      2020-11-09  179  		/* Clear PIPE, DDI, PHY, HPD before setting new */
8625b221f307ef Ville Syrjälä 2020-10-28  180  		vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
e5abaab30eca51 Ville Syrjälä 2020-10-28  181  			~(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) |
e5abaab30eca51 Ville Syrjälä 2020-10-28  182  			  GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) |
e5abaab30eca51 Ville Syrjälä 2020-10-28  183  			  GEN8_DE_PORT_HOTPLUG(HPD_PORT_C));
72bad997287693 Colin Xu      2018-06-11  184  
a5a8ef937cfa79 Colin Xu      2020-11-09  185  		for_each_pipe(dev_priv, pipe) {
a5a8ef937cfa79 Colin Xu      2020-11-09  186  			vgpu_vreg_t(vgpu, PIPECONF(pipe)) &=
6a6d914de30f15 Ville Syrjälä 2021-11-12  187  				~(PIPECONF_ENABLE | PIPECONF_STATE_ENABLE);
428cb15d5b0031 Ville Syrjälä 2022-01-21  188  			vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE;
a5a8ef937cfa79 Colin Xu      2020-11-09  189  			vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
348abd4cf353ab Ville Syrjälä 2021-12-01  190  			vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE_MASK;
a5a8ef937cfa79 Colin Xu      2020-11-09  191  			vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;
a5a8ef937cfa79 Colin Xu      2020-11-09  192  		}
a5a8ef937cfa79 Colin Xu      2020-11-09  193  
a5a8ef937cfa79 Colin Xu      2020-11-09  194  		for (trans = TRANSCODER_A; trans <= TRANSCODER_EDP; trans++) {
a5a8ef937cfa79 Colin Xu      2020-11-09  195  			vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(trans)) &=
a5a8ef937cfa79 Colin Xu      2020-11-09  196  				~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
a5a8ef937cfa79 Colin Xu      2020-11-09  197  				  TRANS_DDI_PORT_MASK | TRANS_DDI_FUNC_ENABLE);
a5a8ef937cfa79 Colin Xu      2020-11-09  198  		}
a5a8ef937cfa79 Colin Xu      2020-11-09  199  		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
a5a8ef937cfa79 Colin Xu      2020-11-09  200  			~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
a5a8ef937cfa79 Colin Xu      2020-11-09  201  			  TRANS_DDI_PORT_MASK);
a5a8ef937cfa79 Colin Xu      2020-11-09  202  
a5a8ef937cfa79 Colin Xu      2020-11-09  203  		for (port = PORT_A; port <= PORT_C; port++) {
a5a8ef937cfa79 Colin Xu      2020-11-09  204  			vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) &=
a5a8ef937cfa79 Colin Xu      2020-11-09  205  				~BXT_PHY_LANE_ENABLED;
a5a8ef937cfa79 Colin Xu      2020-11-09  206  			vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) |=
a5a8ef937cfa79 Colin Xu      2020-11-09  207  				(BXT_PHY_CMNLANE_POWERDOWN_ACK |
a5a8ef937cfa79 Colin Xu      2020-11-09  208  				 BXT_PHY_LANE_POWERDOWN_ACK);
a5a8ef937cfa79 Colin Xu      2020-11-09  209  
a5a8ef937cfa79 Colin Xu      2020-11-09  210  			vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)) &=
a5a8ef937cfa79 Colin Xu      2020-11-09  211  				~(PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
a5a8ef937cfa79 Colin Xu      2020-11-09  212  				  PORT_PLL_REF_SEL | PORT_PLL_LOCK |
a5a8ef937cfa79 Colin Xu      2020-11-09  213  				  PORT_PLL_ENABLE);
a5a8ef937cfa79 Colin Xu      2020-11-09  214  
a5a8ef937cfa79 Colin Xu      2020-11-09  215  			vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) &=
a5a8ef937cfa79 Colin Xu      2020-11-09  216  				~(DDI_INIT_DISPLAY_DETECTED |
a5a8ef937cfa79 Colin Xu      2020-11-09  217  				  DDI_BUF_CTL_ENABLE);
a5a8ef937cfa79 Colin Xu      2020-11-09  218  			vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE;
a5a8ef937cfa79 Colin Xu      2020-11-09  219  		}
4ceb06e7c336f4 Colin Xu      2020-12-01  220  		vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
4ceb06e7c336f4 Colin Xu      2020-12-01  221  			~(PORTA_HOTPLUG_ENABLE | PORTA_HOTPLUG_STATUS_MASK);
4ceb06e7c336f4 Colin Xu      2020-12-01  222  		vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
4ceb06e7c336f4 Colin Xu      2020-12-01  223  			~(PORTB_HOTPLUG_ENABLE | PORTB_HOTPLUG_STATUS_MASK);
4ceb06e7c336f4 Colin Xu      2020-12-01  224  		vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
4ceb06e7c336f4 Colin Xu      2020-12-01  225  			~(PORTC_HOTPLUG_ENABLE | PORTC_HOTPLUG_STATUS_MASK);
4ceb06e7c336f4 Colin Xu      2020-12-01  226  		/* No hpd_invert set in vgpu vbt, need to clear invert mask */
4ceb06e7c336f4 Colin Xu      2020-12-01  227  		vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= ~BXT_DDI_HPD_INVERT_MASK;
4ceb06e7c336f4 Colin Xu      2020-12-01  228  		vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~BXT_DE_PORT_HOTPLUG_MASK;
a5a8ef937cfa79 Colin Xu      2020-11-09  229  
a5a8ef937cfa79 Colin Xu      2020-11-09  230  		vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= ~(BIT(0) | BIT(1));
a5a8ef937cfa79 Colin Xu      2020-11-09  231  		vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
a5a8ef937cfa79 Colin Xu      2020-11-09  232  			~PHY_POWER_GOOD;
a5a8ef937cfa79 Colin Xu      2020-11-09  233  		vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
a5a8ef937cfa79 Colin Xu      2020-11-09  234  			~PHY_POWER_GOOD;
a5a8ef937cfa79 Colin Xu      2020-11-09  235  		vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= ~BIT(30);
a5a8ef937cfa79 Colin Xu      2020-11-09  236  		vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= ~BIT(30);
a5a8ef937cfa79 Colin Xu      2020-11-09  237  
a5a8ef937cfa79 Colin Xu      2020-11-09  238  		vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIB_DETECTED;
a5a8ef937cfa79 Colin Xu      2020-11-09  239  		vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIC_DETECTED;
a5a8ef937cfa79 Colin Xu      2020-11-09  240  
a5a8ef937cfa79 Colin Xu      2020-11-09  241  		/*
a5a8ef937cfa79 Colin Xu      2020-11-09  242  		 * Only 1 PIPE enabled in current vGPU display and PIPE_A is
a5a8ef937cfa79 Colin Xu      2020-11-09  243  		 *  tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A,
a5a8ef937cfa79 Colin Xu      2020-11-09  244  		 *   TRANSCODER_A can be enabled. PORT_x depends on the input of
a5a8ef937cfa79 Colin Xu      2020-11-09  245  		 *   setup_virtual_dp_monitor.
a5a8ef937cfa79 Colin Xu      2020-11-09  246  		 */
a5a8ef937cfa79 Colin Xu      2020-11-09  247  		vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
6a6d914de30f15 Ville Syrjälä 2021-11-12  248  		vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_STATE_ENABLE;
a5a8ef937cfa79 Colin Xu      2020-11-09  249  
a5a8ef937cfa79 Colin Xu      2020-11-09  250  		/*
a5a8ef937cfa79 Colin Xu      2020-11-09  251  		 * Golden M/N are calculated based on:
a5a8ef937cfa79 Colin Xu      2020-11-09  252  		 *   24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID),
a5a8ef937cfa79 Colin Xu      2020-11-09  253  		 *   DP link clk 1620 MHz and non-constant_n.
a5a8ef937cfa79 Colin Xu      2020-11-09  254  		 * TODO: calculate DP link symbol clk and stream clk m/n.
a5a8ef937cfa79 Colin Xu      2020-11-09  255  		 */
a5a8ef937cfa79 Colin Xu      2020-11-09 @256  		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT;
a5a8ef937cfa79 Colin Xu      2020-11-09  257  		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;
a5a8ef937cfa79 Colin Xu      2020-11-09  258  		vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
a5a8ef937cfa79 Colin Xu      2020-11-09  259  		vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
a5a8ef937cfa79 Colin Xu      2020-11-09  260  		vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
a5a8ef937cfa79 Colin Xu      2020-11-09  261  
a5a8ef937cfa79 Colin Xu      2020-11-09  262  		/* Enable per-DDI/PORT vreg */
72bad997287693 Colin Xu      2018-06-11  263  		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
a5a8ef937cfa79 Colin Xu      2020-11-09  264  			vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(1);
a5a8ef937cfa79 Colin Xu      2020-11-09  265  			vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |=
a5a8ef937cfa79 Colin Xu      2020-11-09  266  				PHY_POWER_GOOD;
a5a8ef937cfa79 Colin Xu      2020-11-09  267  			vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) |=
a5a8ef937cfa79 Colin Xu      2020-11-09  268  				BIT(30);
a5a8ef937cfa79 Colin Xu      2020-11-09  269  			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |=
a5a8ef937cfa79 Colin Xu      2020-11-09  270  				BXT_PHY_LANE_ENABLED;
a5a8ef937cfa79 Colin Xu      2020-11-09  271  			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &=
a5a8ef937cfa79 Colin Xu      2020-11-09  272  				~(BXT_PHY_CMNLANE_POWERDOWN_ACK |
a5a8ef937cfa79 Colin Xu      2020-11-09  273  				  BXT_PHY_LANE_POWERDOWN_ACK);
a5a8ef937cfa79 Colin Xu      2020-11-09  274  			vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_A)) |=
a5a8ef937cfa79 Colin Xu      2020-11-09  275  				(PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
a5a8ef937cfa79 Colin Xu      2020-11-09  276  				 PORT_PLL_REF_SEL | PORT_PLL_LOCK |
a5a8ef937cfa79 Colin Xu      2020-11-09  277  				 PORT_PLL_ENABLE);
a5a8ef937cfa79 Colin Xu      2020-11-09  278  			vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |=
a5a8ef937cfa79 Colin Xu      2020-11-09  279  				(DDI_BUF_CTL_ENABLE | DDI_INIT_DISPLAY_DETECTED);
a5a8ef937cfa79 Colin Xu      2020-11-09  280  			vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &=
a5a8ef937cfa79 Colin Xu      2020-11-09  281  				~DDI_BUF_IS_IDLE;
a5a8ef937cfa79 Colin Xu      2020-11-09  282  			vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)) |=
a5a8ef937cfa79 Colin Xu      2020-11-09  283  				(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
a5a8ef937cfa79 Colin Xu      2020-11-09  284  				 TRANS_DDI_FUNC_ENABLE);
4ceb06e7c336f4 Colin Xu      2020-12-01  285  			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
4ceb06e7c336f4 Colin Xu      2020-12-01  286  				PORTA_HOTPLUG_ENABLE;
72bad997287693 Colin Xu      2018-06-11  287  			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
e5abaab30eca51 Ville Syrjälä 2020-10-28  288  				GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
72bad997287693 Colin Xu      2018-06-11  289  		}
72bad997287693 Colin Xu      2018-06-11  290  
72bad997287693 Colin Xu      2018-06-11  291  		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
a5a8ef937cfa79 Colin Xu      2020-11-09  292  			vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
a5a8ef937cfa79 Colin Xu      2020-11-09  293  			vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);
a5a8ef937cfa79 Colin Xu      2020-11-09  294  			vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
a5a8ef937cfa79 Colin Xu      2020-11-09  295  				PHY_POWER_GOOD;
a5a8ef937cfa79 Colin Xu      2020-11-09  296  			vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |=
a5a8ef937cfa79 Colin Xu      2020-11-09  297  				BIT(30);
a5a8ef937cfa79 Colin Xu      2020-11-09  298  			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |=
a5a8ef937cfa79 Colin Xu      2020-11-09  299  				BXT_PHY_LANE_ENABLED;
a5a8ef937cfa79 Colin Xu      2020-11-09  300  			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &=
a5a8ef937cfa79 Colin Xu      2020-11-09  301  				~(BXT_PHY_CMNLANE_POWERDOWN_ACK |
a5a8ef937cfa79 Colin Xu      2020-11-09  302  				  BXT_PHY_LANE_POWERDOWN_ACK);
a5a8ef937cfa79 Colin Xu      2020-11-09  303  			vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_B)) |=
a5a8ef937cfa79 Colin Xu      2020-11-09  304  				(PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
a5a8ef937cfa79 Colin Xu      2020-11-09  305  				 PORT_PLL_REF_SEL | PORT_PLL_LOCK |
a5a8ef937cfa79 Colin Xu      2020-11-09  306  				 PORT_PLL_ENABLE);
a5a8ef937cfa79 Colin Xu      2020-11-09  307  			vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |=
a5a8ef937cfa79 Colin Xu      2020-11-09  308  				DDI_BUF_CTL_ENABLE;
a5a8ef937cfa79 Colin Xu      2020-11-09  309  			vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &=
a5a8ef937cfa79 Colin Xu      2020-11-09  310  				~DDI_BUF_IS_IDLE;
a5a8ef937cfa79 Colin Xu      2020-11-09  311  			vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
a5a8ef937cfa79 Colin Xu      2020-11-09  312  				(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
a5a8ef937cfa79 Colin Xu      2020-11-09  313  				 (PORT_B << TRANS_DDI_PORT_SHIFT) |
a5a8ef937cfa79 Colin Xu      2020-11-09  314  				 TRANS_DDI_FUNC_ENABLE);
4ceb06e7c336f4 Colin Xu      2020-12-01  315  			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
4ceb06e7c336f4 Colin Xu      2020-12-01  316  				PORTB_HOTPLUG_ENABLE;
72bad997287693 Colin Xu      2018-06-11  317  			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
e5abaab30eca51 Ville Syrjälä 2020-10-28  318  				GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);
72bad997287693 Colin Xu      2018-06-11  319  		}
72bad997287693 Colin Xu      2018-06-11  320  
72bad997287693 Colin Xu      2018-06-11  321  		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
a5a8ef937cfa79 Colin Xu      2020-11-09  322  			vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
a5a8ef937cfa79 Colin Xu      2020-11-09  323  			vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);
a5a8ef937cfa79 Colin Xu      2020-11-09  324  			vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
a5a8ef937cfa79 Colin Xu      2020-11-09  325  				PHY_POWER_GOOD;
a5a8ef937cfa79 Colin Xu      2020-11-09  326  			vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |=
a5a8ef937cfa79 Colin Xu      2020-11-09  327  				BIT(30);
a5a8ef937cfa79 Colin Xu      2020-11-09  328  			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |=
a5a8ef937cfa79 Colin Xu      2020-11-09  329  				BXT_PHY_LANE_ENABLED;
a5a8ef937cfa79 Colin Xu      2020-11-09  330  			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &=
a5a8ef937cfa79 Colin Xu      2020-11-09  331  				~(BXT_PHY_CMNLANE_POWERDOWN_ACK |
a5a8ef937cfa79 Colin Xu      2020-11-09  332  				  BXT_PHY_LANE_POWERDOWN_ACK);
a5a8ef937cfa79 Colin Xu      2020-11-09  333  			vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_C)) |=
a5a8ef937cfa79 Colin Xu      2020-11-09  334  				(PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
a5a8ef937cfa79 Colin Xu      2020-11-09  335  				 PORT_PLL_REF_SEL | PORT_PLL_LOCK |
a5a8ef937cfa79 Colin Xu      2020-11-09  336  				 PORT_PLL_ENABLE);
a5a8ef937cfa79 Colin Xu      2020-11-09  337  			vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |=
a5a8ef937cfa79 Colin Xu      2020-11-09  338  				DDI_BUF_CTL_ENABLE;
a5a8ef937cfa79 Colin Xu      2020-11-09  339  			vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &=
a5a8ef937cfa79 Colin Xu      2020-11-09  340  				~DDI_BUF_IS_IDLE;
a5a8ef937cfa79 Colin Xu      2020-11-09  341  			vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
a5a8ef937cfa79 Colin Xu      2020-11-09  342  				(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
a5a8ef937cfa79 Colin Xu      2020-11-09  343  				 (PORT_B << TRANS_DDI_PORT_SHIFT) |
a5a8ef937cfa79 Colin Xu      2020-11-09  344  				 TRANS_DDI_FUNC_ENABLE);
4ceb06e7c336f4 Colin Xu      2020-12-01  345  			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
4ceb06e7c336f4 Colin Xu      2020-12-01  346  				PORTC_HOTPLUG_ENABLE;
72bad997287693 Colin Xu      2018-06-11  347  			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
e5abaab30eca51 Ville Syrjälä 2020-10-28  348  				GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);
72bad997287693 Colin Xu      2018-06-11  349  		}
72bad997287693 Colin Xu      2018-06-11  350  
72bad997287693 Colin Xu      2018-06-11  351  		return;
72bad997287693 Colin Xu      2018-06-11  352  	}
72bad997287693 Colin Xu      2018-06-11  353  
90551a1296d4db Zhenyu Wang   2017-12-19  354  	vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT |
04d348ae3f0aea Zhi Wang      2016-04-25  355  			SDE_PORTC_HOTPLUG_CPT |
04d348ae3f0aea Zhi Wang      2016-04-25  356  			SDE_PORTD_HOTPLUG_CPT);
04d348ae3f0aea Zhi Wang      2016-04-25  357  
5f4ae2704d59ee Chris Wilson  2020-06-02  358  	if (IS_SKYLAKE(dev_priv) ||
5f4ae2704d59ee Chris Wilson  2020-06-02  359  	    IS_KABYLAKE(dev_priv) ||
5f4ae2704d59ee Chris Wilson  2020-06-02  360  	    IS_COFFEELAKE(dev_priv) ||
5f4ae2704d59ee Chris Wilson  2020-06-02  361  	    IS_COMETLAKE(dev_priv)) {
90551a1296d4db Zhenyu Wang   2017-12-19  362  		vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |
04d348ae3f0aea Zhi Wang      2016-04-25  363  				SDE_PORTE_HOTPLUG_SPT);
90551a1296d4db Zhenyu Wang   2017-12-19  364  		vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=
88a16b64c3f48d Weinan Li     2017-03-17  365  				SKL_FUSE_DOWNLOAD_STATUS |
b2891eb2531e5e Imre Deak     2017-07-11  366  				SKL_FUSE_PG_DIST_STATUS(SKL_PG0) |
b2891eb2531e5e Imre Deak     2017-07-11  367  				SKL_FUSE_PG_DIST_STATUS(SKL_PG1) |
b2891eb2531e5e Imre Deak     2017-07-11  368  				SKL_FUSE_PG_DIST_STATUS(SKL_PG2);
f965b68188ab59 Colin Xu      2020-05-08  369  		/*
f965b68188ab59 Colin Xu      2020-05-08  370  		 * Only 1 PIPE enabled in current vGPU display and PIPE_A is
f965b68188ab59 Colin Xu      2020-05-08  371  		 *  tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A,
f965b68188ab59 Colin Xu      2020-05-08  372  		 *   TRANSCODER_A can be enabled. PORT_x depends on the input of
f965b68188ab59 Colin Xu      2020-05-08  373  		 *   setup_virtual_dp_monitor, we can bind DPLL0 to any PORT_x
f965b68188ab59 Colin Xu      2020-05-08  374  		 *   so we fixed to DPLL0 here.
f965b68188ab59 Colin Xu      2020-05-08  375  		 * Setup DPLL0: DP link clk 1620 MHz, non SSC, DP Mode
f965b68188ab59 Colin Xu      2020-05-08  376  		 */
f965b68188ab59 Colin Xu      2020-05-08  377  		vgpu_vreg_t(vgpu, DPLL_CTRL1) =
f965b68188ab59 Colin Xu      2020-05-08  378  			DPLL_CTRL1_OVERRIDE(DPLL_ID_SKL_DPLL0);
f965b68188ab59 Colin Xu      2020-05-08  379  		vgpu_vreg_t(vgpu, DPLL_CTRL1) |=
f965b68188ab59 Colin Xu      2020-05-08  380  			DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, DPLL_ID_SKL_DPLL0);
f965b68188ab59 Colin Xu      2020-05-08  381  		vgpu_vreg_t(vgpu, LCPLL1_CTL) =
f965b68188ab59 Colin Xu      2020-05-08  382  			LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK;
f965b68188ab59 Colin Xu      2020-05-08  383  		vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0);
f965b68188ab59 Colin Xu      2020-05-08  384  		/*
f965b68188ab59 Colin Xu      2020-05-08  385  		 * Golden M/N are calculated based on:
f965b68188ab59 Colin Xu      2020-05-08  386  		 *   24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID),
f965b68188ab59 Colin Xu      2020-05-08  387  		 *   DP link clk 1620 MHz and non-constant_n.
f965b68188ab59 Colin Xu      2020-05-08  388  		 * TODO: calculate DP link symbol clk and stream clk m/n.
f965b68188ab59 Colin Xu      2020-05-08  389  		 */
f965b68188ab59 Colin Xu      2020-05-08  390  		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT;
f965b68188ab59 Colin Xu      2020-05-08  391  		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;
f965b68188ab59 Colin Xu      2020-05-08  392  		vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
f965b68188ab59 Colin Xu      2020-05-08  393  		vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
f965b68188ab59 Colin Xu      2020-05-08  394  		vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
88a16b64c3f48d Weinan Li     2017-03-17  395  	}
04d348ae3f0aea Zhi Wang      2016-04-25  396  
858b0f571d3091 Bing Niu      2017-02-28  397  	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
f965b68188ab59 Colin Xu      2020-05-08  398  		vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
f965b68188ab59 Colin Xu      2020-05-08  399  			~DPLL_CTRL2_DDI_CLK_OFF(PORT_B);
f965b68188ab59 Colin Xu      2020-05-08  400  		vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
f965b68188ab59 Colin Xu      2020-05-08  401  			DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_B);
f965b68188ab59 Colin Xu      2020-05-08  402  		vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
f965b68188ab59 Colin Xu      2020-05-08  403  			DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_B);
90551a1296d4db Zhenyu Wang   2017-12-19  404  		vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
90551a1296d4db Zhenyu Wang   2017-12-19  405  		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
efa69d734adbf8 Pei Zhang     2017-04-07  406  			~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
efa69d734adbf8 Pei Zhang     2017-04-07  407  			TRANS_DDI_PORT_MASK);
90551a1296d4db Zhenyu Wang   2017-12-19  408  		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
75db1a5b2aea2a Tina Zhang    2020-03-17  409  			(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
efa69d734adbf8 Pei Zhang     2017-04-07  410  			(PORT_B << TRANS_DDI_PORT_SHIFT) |
efa69d734adbf8 Pei Zhang     2017-04-07  411  			TRANS_DDI_FUNC_ENABLE);
295a0d0b55269f Xiong Zhang   2017-06-20  412  		if (IS_BROADWELL(dev_priv)) {
90551a1296d4db Zhenyu Wang   2017-12-19  413  			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &=
295a0d0b55269f Xiong Zhang   2017-06-20  414  				~PORT_CLK_SEL_MASK;
90551a1296d4db Zhenyu Wang   2017-12-19  415  			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |=
295a0d0b55269f Xiong Zhang   2017-06-20  416  				PORT_CLK_SEL_LCPLL_810;
295a0d0b55269f Xiong Zhang   2017-06-20  417  		}
90551a1296d4db Zhenyu Wang   2017-12-19  418  		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE;
90551a1296d4db Zhenyu Wang   2017-12-19  419  		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE;
90551a1296d4db Zhenyu Wang   2017-12-19  420  		vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;
858b0f571d3091 Bing Niu      2017-02-28  421  	}
04d348ae3f0aea Zhi Wang      2016-04-25  422  
858b0f571d3091 Bing Niu      2017-02-28  423  	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
f965b68188ab59 Colin Xu      2020-05-08  424  		vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
f965b68188ab59 Colin Xu      2020-05-08  425  			~DPLL_CTRL2_DDI_CLK_OFF(PORT_C);
f965b68188ab59 Colin Xu      2020-05-08  426  		vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
f965b68188ab59 Colin Xu      2020-05-08  427  			DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_C);
f965b68188ab59 Colin Xu      2020-05-08  428  		vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
f965b68188ab59 Colin Xu      2020-05-08  429  			DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_C);
90551a1296d4db Zhenyu Wang   2017-12-19  430  		vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;
90551a1296d4db Zhenyu Wang   2017-12-19  431  		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
efa69d734adbf8 Pei Zhang     2017-04-07  432  			~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
efa69d734adbf8 Pei Zhang     2017-04-07  433  			TRANS_DDI_PORT_MASK);
90551a1296d4db Zhenyu Wang   2017-12-19  434  		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
75db1a5b2aea2a Tina Zhang    2020-03-17  435  			(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
efa69d734adbf8 Pei Zhang     2017-04-07  436  			(PORT_C << TRANS_DDI_PORT_SHIFT) |
efa69d734adbf8 Pei Zhang     2017-04-07  437  			TRANS_DDI_FUNC_ENABLE);
295a0d0b55269f Xiong Zhang   2017-06-20  438  		if (IS_BROADWELL(dev_priv)) {
90551a1296d4db Zhenyu Wang   2017-12-19  439  			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &=
295a0d0b55269f Xiong Zhang   2017-06-20  440  				~PORT_CLK_SEL_MASK;
90551a1296d4db Zhenyu Wang   2017-12-19  441  			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |=
295a0d0b55269f Xiong Zhang   2017-06-20  442  				PORT_CLK_SEL_LCPLL_810;
295a0d0b55269f Xiong Zhang   2017-06-20  443  		}
90551a1296d4db Zhenyu Wang   2017-12-19  444  		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE;
90551a1296d4db Zhenyu Wang   2017-12-19  445  		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE;
90551a1296d4db Zhenyu Wang   2017-12-19  446  		vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
858b0f571d3091 Bing Niu      2017-02-28  447  	}
04d348ae3f0aea Zhi Wang      2016-04-25  448  
858b0f571d3091 Bing Niu      2017-02-28  449  	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) {
f965b68188ab59 Colin Xu      2020-05-08  450  		vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
f965b68188ab59 Colin Xu      2020-05-08  451  			~DPLL_CTRL2_DDI_CLK_OFF(PORT_D);
f965b68188ab59 Colin Xu      2020-05-08  452  		vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
f965b68188ab59 Colin Xu      2020-05-08  453  			DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_D);
f965b68188ab59 Colin Xu      2020-05-08  454  		vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
f965b68188ab59 Colin Xu      2020-05-08  455  			DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_D);
90551a1296d4db Zhenyu Wang   2017-12-19  456  		vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
90551a1296d4db Zhenyu Wang   2017-12-19  457  		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
efa69d734adbf8 Pei Zhang     2017-04-07  458  			~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
efa69d734adbf8 Pei Zhang     2017-04-07  459  			TRANS_DDI_PORT_MASK);
90551a1296d4db Zhenyu Wang   2017-12-19  460  		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
75db1a5b2aea2a Tina Zhang    2020-03-17  461  			(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
efa69d734adbf8 Pei Zhang     2017-04-07  462  			(PORT_D << TRANS_DDI_PORT_SHIFT) |
efa69d734adbf8 Pei Zhang     2017-04-07  463  			TRANS_DDI_FUNC_ENABLE);
295a0d0b55269f Xiong Zhang   2017-06-20  464  		if (IS_BROADWELL(dev_priv)) {
90551a1296d4db Zhenyu Wang   2017-12-19  465  			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &=
295a0d0b55269f Xiong Zhang   2017-06-20  466  				~PORT_CLK_SEL_MASK;
90551a1296d4db Zhenyu Wang   2017-12-19  467  			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |=
295a0d0b55269f Xiong Zhang   2017-06-20  468  				PORT_CLK_SEL_LCPLL_810;
295a0d0b55269f Xiong Zhang   2017-06-20  469  		}
90551a1296d4db Zhenyu Wang   2017-12-19  470  		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE;
90551a1296d4db Zhenyu Wang   2017-12-19  471  		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE;
90551a1296d4db Zhenyu Wang   2017-12-19  472  		vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;
858b0f571d3091 Bing Niu      2017-02-28  473  	}
04d348ae3f0aea Zhi Wang      2016-04-25  474  
5f4ae2704d59ee Chris Wilson  2020-06-02  475  	if ((IS_SKYLAKE(dev_priv) ||
5f4ae2704d59ee Chris Wilson  2020-06-02  476  	     IS_KABYLAKE(dev_priv) ||
5f4ae2704d59ee Chris Wilson  2020-06-02  477  	     IS_COFFEELAKE(dev_priv) ||
5f4ae2704d59ee Chris Wilson  2020-06-02  478  	     IS_COMETLAKE(dev_priv)) &&
04d348ae3f0aea Zhi Wang      2016-04-25  479  			intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {
90551a1296d4db Zhenyu Wang   2017-12-19  480  		vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;
04d348ae3f0aea Zhi Wang      2016-04-25  481  	}
04d348ae3f0aea Zhi Wang      2016-04-25  482  
04d348ae3f0aea Zhi Wang      2016-04-25  483  	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
04d348ae3f0aea Zhi Wang      2016-04-25  484  		if (IS_BROADWELL(dev_priv))
90551a1296d4db Zhenyu Wang   2017-12-19  485  			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
e5abaab30eca51 Ville Syrjälä 2020-10-28  486  				GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
04d348ae3f0aea Zhi Wang      2016-04-25  487  		else
90551a1296d4db Zhenyu Wang   2017-12-19  488  			vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;
858b0f571d3091 Bing Niu      2017-02-28  489  
90551a1296d4db Zhenyu Wang   2017-12-19  490  		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED;
04d348ae3f0aea Zhi Wang      2016-04-25  491  	}
75e64ff2c2f5ce Xiong Zhang   2017-06-28  492  
75e64ff2c2f5ce Xiong Zhang   2017-06-28  493  	/* Clear host CRT status, so guest couldn't detect this host CRT. */
75e64ff2c2f5ce Xiong Zhang   2017-06-28  494  	if (IS_BROADWELL(dev_priv))
90551a1296d4db Zhenyu Wang   2017-12-19  495  		vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK;
4e889d62b89d00 Xiaolin Zhang 2017-12-05  496  
65eff272330c72 Xiong Zhang   2018-03-28  497  	/* Disable Primary/Sprite/Cursor plane */
65eff272330c72 Xiong Zhang   2018-03-28  498  	for_each_pipe(dev_priv, pipe) {
428cb15d5b0031 Ville Syrjälä 2022-01-21  499  		vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE;
65eff272330c72 Xiong Zhang   2018-03-28  500  		vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
348abd4cf353ab Ville Syrjälä 2021-12-01  501  		vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE_MASK;
b99b9ec1d374fd Ville Syrjälä 2018-01-31  502  		vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;
65eff272330c72 Xiong Zhang   2018-03-28  503  	}
65eff272330c72 Xiong Zhang   2018-03-28  504  
90551a1296d4db Zhenyu Wang   2017-12-19  505  	vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
04d348ae3f0aea Zhi Wang      2016-04-25  506  }
04d348ae3f0aea Zhi Wang      2016-04-25  507  

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

^ permalink raw reply	[flat|nested] 31+ messages in thread

* [Intel-gfx] [PATCH 03/14] drm/i915: s/gmch_{m,n}/data_{m,n}/
  2022-01-27  9:32 [Intel-gfx] [PATCH 00/14] drm/i915: M/N cleanup Ville Syrjala
  2022-01-27  9:32 ` [Intel-gfx] [PATCH 01/14] drm/i915: Extract intel_{get,set}_m_n() Ville Syrjala
  2022-01-27  9:32 ` [Intel-gfx] [PATCH 02/14] drm/i915: Clean up M/N register defines Ville Syrjala
@ 2022-01-27  9:32 ` Ville Syrjala
  2022-01-27 11:18   ` Jani Nikula
  2022-01-27  9:32 ` [Intel-gfx] [PATCH 04/14] drm/i915: Move drrs hardware bit frobbing to small helpers Ville Syrjala
                   ` (14 subsequent siblings)
  17 siblings, 1 reply; 31+ messages in thread
From: Ville Syrjala @ 2022-01-27  9:32 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Rename the gmch_* M/N members to data_* to match the register
definitions and thus make life a little less confusing.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c     |  4 +-
 drivers/gpu/drm/i915/display/intel_display.c | 48 ++++++++++----------
 drivers/gpu/drm/i915/display/intel_display.h |  4 +-
 drivers/gpu/drm/i915/display/intel_dp.c      |  2 +-
 drivers/gpu/drm/i915/display/intel_drrs.c    |  2 +-
 5 files changed, 30 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 5d1f7d6218c5..ca8becb07e45 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3684,8 +3684,8 @@ static bool m_n_equal(const struct intel_link_m_n *m_n_1,
 		      const struct intel_link_m_n *m_n_2)
 {
 	return m_n_1->tu == m_n_2->tu &&
-		m_n_1->gmch_m == m_n_2->gmch_m &&
-		m_n_1->gmch_n == m_n_2->gmch_n &&
+		m_n_1->data_m == m_n_2->data_m &&
+		m_n_1->data_n == m_n_2->data_n &&
 		m_n_1->link_m == m_n_2->link_m &&
 		m_n_1->link_n == m_n_2->link_n;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d91164d1eb92..75de794185b2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3082,7 +3082,7 @@ intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
 	m_n->tu = 64;
 	compute_m_n(data_clock,
 		    link_clock * nlanes * 8,
-		    &m_n->gmch_m, &m_n->gmch_n,
+		    &m_n->data_m, &m_n->data_n,
 		    constant_n);
 
 	compute_m_n(pixel_clock, link_clock,
@@ -3118,8 +3118,8 @@ static void intel_set_m_n(struct drm_i915_private *i915,
 			  i915_reg_t data_m_reg, i915_reg_t data_n_reg,
 			  i915_reg_t link_m_reg, i915_reg_t link_n_reg)
 {
-	intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->gmch_m);
-	intel_de_write(i915, data_n_reg, m_n->gmch_n);
+	intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
+	intel_de_write(i915, data_n_reg, m_n->data_n);
 	intel_de_write(i915, link_m_reg, m_n->link_m);
 	intel_de_write(i915, link_n_reg, m_n->link_n);
 }
@@ -3867,8 +3867,8 @@ static void intel_get_m_n(struct drm_i915_private *i915,
 {
 	m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK;
 	m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK;
-	m_n->gmch_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK;
-	m_n->gmch_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK;
+	m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK;
+	m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK;
 	m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1;
 }
 
@@ -5498,9 +5498,9 @@ intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
 	struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
 
 	drm_dbg_kms(&i915->drm,
-		    "%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
+		    "%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u\n",
 		    id, lane_count,
-		    m_n->gmch_m, m_n->gmch_n,
+		    m_n->data_m, m_n->data_n,
 		    m_n->link_m, m_n->link_n, m_n->tu);
 }
 
@@ -6196,8 +6196,8 @@ intel_compare_link_m_n(const struct intel_link_m_n *m_n,
 		       bool exact)
 {
 	return m_n->tu == m2_n2->tu &&
-		intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
-				  m2_n2->gmch_m, m2_n2->gmch_n, exact) &&
+		intel_compare_m_n(m_n->data_m, m_n->data_n,
+				  m2_n2->data_m, m2_n2->data_n, exact) &&
 		intel_compare_m_n(m_n->link_m, m_n->link_n,
 				  m2_n2->link_m, m2_n2->link_n, exact);
 }
@@ -6396,16 +6396,16 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 				    &pipe_config->name,\
 				    !fastset)) { \
 		pipe_config_mismatch(fastset, crtc, __stringify(name), \
-				     "(expected tu %i gmch %i/%i link %i/%i, " \
-				     "found tu %i, gmch %i/%i link %i/%i)", \
+				     "(expected tu %i data %i/%i link %i/%i, " \
+				     "found tu %i, data %i/%i link %i/%i)", \
 				     current_config->name.tu, \
-				     current_config->name.gmch_m, \
-				     current_config->name.gmch_n, \
+				     current_config->name.data_m, \
+				     current_config->name.data_n, \
 				     current_config->name.link_m, \
 				     current_config->name.link_n, \
 				     pipe_config->name.tu, \
-				     pipe_config->name.gmch_m, \
-				     pipe_config->name.gmch_n, \
+				     pipe_config->name.data_m, \
+				     pipe_config->name.data_n, \
 				     pipe_config->name.link_m, \
 				     pipe_config->name.link_n); \
 		ret = false; \
@@ -6423,22 +6423,22 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	    !intel_compare_link_m_n(&current_config->alt_name, \
 				    &pipe_config->name, !fastset)) { \
 		pipe_config_mismatch(fastset, crtc, __stringify(name), \
-				     "(expected tu %i gmch %i/%i link %i/%i, " \
-				     "or tu %i gmch %i/%i link %i/%i, " \
-				     "found tu %i, gmch %i/%i link %i/%i)", \
+				     "(expected tu %i data %i/%i link %i/%i, " \
+				     "or tu %i data %i/%i link %i/%i, " \
+				     "found tu %i, data %i/%i link %i/%i)", \
 				     current_config->name.tu, \
-				     current_config->name.gmch_m, \
-				     current_config->name.gmch_n, \
+				     current_config->name.data_m, \
+				     current_config->name.data_n, \
 				     current_config->name.link_m, \
 				     current_config->name.link_n, \
 				     current_config->alt_name.tu, \
-				     current_config->alt_name.gmch_m, \
-				     current_config->alt_name.gmch_n, \
+				     current_config->alt_name.data_m, \
+				     current_config->alt_name.data_n, \
 				     current_config->alt_name.link_m, \
 				     current_config->alt_name.link_n, \
 				     pipe_config->name.tu, \
-				     pipe_config->name.gmch_m, \
-				     pipe_config->name.gmch_n, \
+				     pipe_config->name.data_m, \
+				     pipe_config->name.data_n, \
 				     pipe_config->name.link_m, \
 				     pipe_config->name.link_n); \
 		ret = false; \
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index b61b75248ded..a241007f5c82 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -317,8 +317,8 @@ enum aux_ch {
 /* Used by dp and fdi links */
 struct intel_link_m_n {
 	u32 tu;
-	u32 gmch_m;
-	u32 gmch_n;
+	u32 data_m;
+	u32 data_n;
 	u32 link_m;
 	u32 link_n;
 };
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4d4579a301f6..146b83916005 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1895,7 +1895,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 
 	/* FIXME: abstract this better */
 	if (pipe_config->splitter.enable)
-		pipe_config->dp_m_n.gmch_m *= pipe_config->splitter.link_count;
+		pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;
 
 	if (!HAS_DDI(dev_priv))
 		g4x_dp_set_clock(encoder, pipe_config);
diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c
index c1439fcb5a95..46be46f2c47e 100644
--- a/drivers/gpu/drm/i915/display/intel_drrs.c
+++ b/drivers/gpu/drm/i915/display/intel_drrs.c
@@ -84,7 +84,7 @@ intel_drrs_compute_config(struct intel_dp *intel_dp,
 
 	/* FIXME: abstract this better */
 	if (pipe_config->splitter.enable)
-		pipe_config->dp_m2_n2.gmch_m *= pipe_config->splitter.link_count;
+		pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;
 }
 
 static void intel_drrs_set_state(struct drm_i915_private *dev_priv,
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 31+ messages in thread

* Re: [Intel-gfx] [PATCH 03/14] drm/i915: s/gmch_{m,n}/data_{m,n}/
  2022-01-27  9:32 ` [Intel-gfx] [PATCH 03/14] drm/i915: s/gmch_{m,n}/data_{m,n}/ Ville Syrjala
@ 2022-01-27 11:18   ` Jani Nikula
  0 siblings, 0 replies; 31+ messages in thread
From: Jani Nikula @ 2022-01-27 11:18 UTC (permalink / raw)
  To: Ville Syrjala, intel-gfx

On Thu, 27 Jan 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Rename the gmch_* M/N members to data_* to match the register
> definitions and thus make life a little less confusing.

Yes, please!

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c     |  4 +-
>  drivers/gpu/drm/i915/display/intel_display.c | 48 ++++++++++----------
>  drivers/gpu/drm/i915/display/intel_display.h |  4 +-
>  drivers/gpu/drm/i915/display/intel_dp.c      |  2 +-
>  drivers/gpu/drm/i915/display/intel_drrs.c    |  2 +-
>  5 files changed, 30 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 5d1f7d6218c5..ca8becb07e45 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3684,8 +3684,8 @@ static bool m_n_equal(const struct intel_link_m_n *m_n_1,
>  		      const struct intel_link_m_n *m_n_2)
>  {
>  	return m_n_1->tu == m_n_2->tu &&
> -		m_n_1->gmch_m == m_n_2->gmch_m &&
> -		m_n_1->gmch_n == m_n_2->gmch_n &&
> +		m_n_1->data_m == m_n_2->data_m &&
> +		m_n_1->data_n == m_n_2->data_n &&
>  		m_n_1->link_m == m_n_2->link_m &&
>  		m_n_1->link_n == m_n_2->link_n;
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index d91164d1eb92..75de794185b2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3082,7 +3082,7 @@ intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
>  	m_n->tu = 64;
>  	compute_m_n(data_clock,
>  		    link_clock * nlanes * 8,
> -		    &m_n->gmch_m, &m_n->gmch_n,
> +		    &m_n->data_m, &m_n->data_n,
>  		    constant_n);
>  
>  	compute_m_n(pixel_clock, link_clock,
> @@ -3118,8 +3118,8 @@ static void intel_set_m_n(struct drm_i915_private *i915,
>  			  i915_reg_t data_m_reg, i915_reg_t data_n_reg,
>  			  i915_reg_t link_m_reg, i915_reg_t link_n_reg)
>  {
> -	intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->gmch_m);
> -	intel_de_write(i915, data_n_reg, m_n->gmch_n);
> +	intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
> +	intel_de_write(i915, data_n_reg, m_n->data_n);
>  	intel_de_write(i915, link_m_reg, m_n->link_m);
>  	intel_de_write(i915, link_n_reg, m_n->link_n);
>  }
> @@ -3867,8 +3867,8 @@ static void intel_get_m_n(struct drm_i915_private *i915,
>  {
>  	m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK;
>  	m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK;
> -	m_n->gmch_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK;
> -	m_n->gmch_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK;
> +	m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK;
> +	m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK;
>  	m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1;
>  }
>  
> @@ -5498,9 +5498,9 @@ intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
>  	struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
>  
>  	drm_dbg_kms(&i915->drm,
> -		    "%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
> +		    "%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u\n",
>  		    id, lane_count,
> -		    m_n->gmch_m, m_n->gmch_n,
> +		    m_n->data_m, m_n->data_n,
>  		    m_n->link_m, m_n->link_n, m_n->tu);
>  }
>  
> @@ -6196,8 +6196,8 @@ intel_compare_link_m_n(const struct intel_link_m_n *m_n,
>  		       bool exact)
>  {
>  	return m_n->tu == m2_n2->tu &&
> -		intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
> -				  m2_n2->gmch_m, m2_n2->gmch_n, exact) &&
> +		intel_compare_m_n(m_n->data_m, m_n->data_n,
> +				  m2_n2->data_m, m2_n2->data_n, exact) &&
>  		intel_compare_m_n(m_n->link_m, m_n->link_n,
>  				  m2_n2->link_m, m2_n2->link_n, exact);
>  }
> @@ -6396,16 +6396,16 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  				    &pipe_config->name,\
>  				    !fastset)) { \
>  		pipe_config_mismatch(fastset, crtc, __stringify(name), \
> -				     "(expected tu %i gmch %i/%i link %i/%i, " \
> -				     "found tu %i, gmch %i/%i link %i/%i)", \
> +				     "(expected tu %i data %i/%i link %i/%i, " \
> +				     "found tu %i, data %i/%i link %i/%i)", \
>  				     current_config->name.tu, \
> -				     current_config->name.gmch_m, \
> -				     current_config->name.gmch_n, \
> +				     current_config->name.data_m, \
> +				     current_config->name.data_n, \
>  				     current_config->name.link_m, \
>  				     current_config->name.link_n, \
>  				     pipe_config->name.tu, \
> -				     pipe_config->name.gmch_m, \
> -				     pipe_config->name.gmch_n, \
> +				     pipe_config->name.data_m, \
> +				     pipe_config->name.data_n, \
>  				     pipe_config->name.link_m, \
>  				     pipe_config->name.link_n); \
>  		ret = false; \
> @@ -6423,22 +6423,22 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  	    !intel_compare_link_m_n(&current_config->alt_name, \
>  				    &pipe_config->name, !fastset)) { \
>  		pipe_config_mismatch(fastset, crtc, __stringify(name), \
> -				     "(expected tu %i gmch %i/%i link %i/%i, " \
> -				     "or tu %i gmch %i/%i link %i/%i, " \
> -				     "found tu %i, gmch %i/%i link %i/%i)", \
> +				     "(expected tu %i data %i/%i link %i/%i, " \
> +				     "or tu %i data %i/%i link %i/%i, " \
> +				     "found tu %i, data %i/%i link %i/%i)", \
>  				     current_config->name.tu, \
> -				     current_config->name.gmch_m, \
> -				     current_config->name.gmch_n, \
> +				     current_config->name.data_m, \
> +				     current_config->name.data_n, \
>  				     current_config->name.link_m, \
>  				     current_config->name.link_n, \
>  				     current_config->alt_name.tu, \
> -				     current_config->alt_name.gmch_m, \
> -				     current_config->alt_name.gmch_n, \
> +				     current_config->alt_name.data_m, \
> +				     current_config->alt_name.data_n, \
>  				     current_config->alt_name.link_m, \
>  				     current_config->alt_name.link_n, \
>  				     pipe_config->name.tu, \
> -				     pipe_config->name.gmch_m, \
> -				     pipe_config->name.gmch_n, \
> +				     pipe_config->name.data_m, \
> +				     pipe_config->name.data_n, \
>  				     pipe_config->name.link_m, \
>  				     pipe_config->name.link_n); \
>  		ret = false; \
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index b61b75248ded..a241007f5c82 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -317,8 +317,8 @@ enum aux_ch {
>  /* Used by dp and fdi links */
>  struct intel_link_m_n {
>  	u32 tu;
> -	u32 gmch_m;
> -	u32 gmch_n;
> +	u32 data_m;
> +	u32 data_n;
>  	u32 link_m;
>  	u32 link_n;
>  };
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 4d4579a301f6..146b83916005 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1895,7 +1895,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  
>  	/* FIXME: abstract this better */
>  	if (pipe_config->splitter.enable)
> -		pipe_config->dp_m_n.gmch_m *= pipe_config->splitter.link_count;
> +		pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;
>  
>  	if (!HAS_DDI(dev_priv))
>  		g4x_dp_set_clock(encoder, pipe_config);
> diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c
> index c1439fcb5a95..46be46f2c47e 100644
> --- a/drivers/gpu/drm/i915/display/intel_drrs.c
> +++ b/drivers/gpu/drm/i915/display/intel_drrs.c
> @@ -84,7 +84,7 @@ intel_drrs_compute_config(struct intel_dp *intel_dp,
>  
>  	/* FIXME: abstract this better */
>  	if (pipe_config->splitter.enable)
> -		pipe_config->dp_m2_n2.gmch_m *= pipe_config->splitter.link_count;
> +		pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;
>  }
>  
>  static void intel_drrs_set_state(struct drm_i915_private *dev_priv,

-- 
Jani Nikula, Intel Open Source Graphics Center

^ permalink raw reply	[flat|nested] 31+ messages in thread

* [Intel-gfx] [PATCH 04/14] drm/i915: Move drrs hardware bit frobbing to small helpers
  2022-01-27  9:32 [Intel-gfx] [PATCH 00/14] drm/i915: M/N cleanup Ville Syrjala
                   ` (2 preceding siblings ...)
  2022-01-27  9:32 ` [Intel-gfx] [PATCH 03/14] drm/i915: s/gmch_{m,n}/data_{m,n}/ Ville Syrjala
@ 2022-01-27  9:32 ` Ville Syrjala
  2022-01-27 11:23   ` Jani Nikula
  2022-01-27  9:32 ` [Intel-gfx] [PATCH 05/14] drm/i915: Make M/N set/get a bit more direct Ville Syrjala
                   ` (13 subsequent siblings)
  17 siblings, 1 reply; 31+ messages in thread
From: Ville Syrjala @ 2022-01-27  9:32 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Split the drrs code that actually changes the refresh rate
(via PIPECONF or M/N values) to small helper functions that
only deal with the hardware details an nothing else. We'll
soon have a third way of doing this, and it's less confusing
when each difference method lives in its own funciton.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_drrs.c | 67 ++++++++++++-----------
 1 file changed, 36 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c
index 46be46f2c47e..0cacdb174fd0 100644
--- a/drivers/gpu/drm/i915/display/intel_drrs.c
+++ b/drivers/gpu/drm/i915/display/intel_drrs.c
@@ -87,6 +87,38 @@ intel_drrs_compute_config(struct intel_dp *intel_dp,
 		pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;
 }
 
+static void
+intel_drrs_set_refresh_rate_pipeconf(const struct intel_crtc_state *crtc_state,
+				     enum drrs_refresh_rate_type refresh_type)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 val, bit;
+
+	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+		bit = PIPECONF_EDP_RR_MODE_SWITCH_VLV;
+	else
+		bit = PIPECONF_EDP_RR_MODE_SWITCH;
+
+	val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
+
+	if (refresh_type == DRRS_LOW_RR)
+		val |= bit;
+	else
+		val &= ~bit;
+
+	intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val);
+}
+
+static void
+intel_drrs_set_refresh_rate_m_n(const struct intel_crtc_state *crtc_state,
+				enum drrs_refresh_rate_type refresh_type)
+{
+	intel_dp_set_m_n(crtc_state,
+			 refresh_type == DRRS_LOW_RR ? M2_N2 : M1_N1);
+}
+
 static void intel_drrs_set_state(struct drm_i915_private *dev_priv,
 				 const struct intel_crtc_state *crtc_state,
 				 enum drrs_refresh_rate_type refresh_type)
@@ -120,37 +152,10 @@ static void intel_drrs_set_state(struct drm_i915_private *dev_priv,
 		return;
 	}
 
-	if (DISPLAY_VER(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
-		switch (refresh_type) {
-		case DRRS_HIGH_RR:
-			intel_dp_set_m_n(crtc_state, M1_N1);
-			break;
-		case DRRS_LOW_RR:
-			intel_dp_set_m_n(crtc_state, M2_N2);
-			break;
-		case DRRS_MAX_RR:
-		default:
-			drm_err(&dev_priv->drm,
-				"Unsupported refreshrate type\n");
-		}
-	} else if (DISPLAY_VER(dev_priv) > 6) {
-		i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
-		u32 val;
-
-		val = intel_de_read(dev_priv, reg);
-		if (refresh_type == DRRS_LOW_RR) {
-			if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
-				val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
-			else
-				val |= PIPECONF_EDP_RR_MODE_SWITCH;
-		} else {
-			if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
-				val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
-			else
-				val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
-		}
-		intel_de_write(dev_priv, reg, val);
-	}
+	if (DISPLAY_VER(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv))
+		intel_drrs_set_refresh_rate_m_n(crtc_state, refresh_type);
+	else if (DISPLAY_VER(dev_priv) > 6)
+		intel_drrs_set_refresh_rate_pipeconf(crtc_state, refresh_type);
 
 	dev_priv->drrs.refresh_rate_type = refresh_type;
 
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 31+ messages in thread

* Re: [Intel-gfx] [PATCH 04/14] drm/i915: Move drrs hardware bit frobbing to small helpers
  2022-01-27  9:32 ` [Intel-gfx] [PATCH 04/14] drm/i915: Move drrs hardware bit frobbing to small helpers Ville Syrjala
@ 2022-01-27 11:23   ` Jani Nikula
  2022-01-27 11:24     ` Jani Nikula
  0 siblings, 1 reply; 31+ messages in thread
From: Jani Nikula @ 2022-01-27 11:23 UTC (permalink / raw)
  To: Ville Syrjala, intel-gfx

On Thu, 27 Jan 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Split the drrs code that actually changes the refresh rate
> (via PIPECONF or M/N values) to small helper functions that
> only deal with the hardware details an nothing else. We'll
> soon have a third way of doing this, and it's less confusing
> when each difference method lives in its own funciton.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_drrs.c | 67 ++++++++++++-----------
>  1 file changed, 36 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c
> index 46be46f2c47e..0cacdb174fd0 100644
> --- a/drivers/gpu/drm/i915/display/intel_drrs.c
> +++ b/drivers/gpu/drm/i915/display/intel_drrs.c
> @@ -87,6 +87,38 @@ intel_drrs_compute_config(struct intel_dp *intel_dp,
>  		pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;
>  }
>  
> +static void
> +intel_drrs_set_refresh_rate_pipeconf(const struct intel_crtc_state *crtc_state,
> +				     enum drrs_refresh_rate_type refresh_type)

Side note, for future, does this really need to be an enum? Could it
just be a bool "reduced" or something?

Anyway,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>



> +{
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	u32 val, bit;
> +
> +	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> +		bit = PIPECONF_EDP_RR_MODE_SWITCH_VLV;
> +	else
> +		bit = PIPECONF_EDP_RR_MODE_SWITCH;
> +
> +	val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
> +
> +	if (refresh_type == DRRS_LOW_RR)
> +		val |= bit;
> +	else
> +		val &= ~bit;
> +
> +	intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val);
> +}
> +
> +static void
> +intel_drrs_set_refresh_rate_m_n(const struct intel_crtc_state *crtc_state,
> +				enum drrs_refresh_rate_type refresh_type)
> +{
> +	intel_dp_set_m_n(crtc_state,
> +			 refresh_type == DRRS_LOW_RR ? M2_N2 : M1_N1);
> +}
> +
>  static void intel_drrs_set_state(struct drm_i915_private *dev_priv,
>  				 const struct intel_crtc_state *crtc_state,
>  				 enum drrs_refresh_rate_type refresh_type)
> @@ -120,37 +152,10 @@ static void intel_drrs_set_state(struct drm_i915_private *dev_priv,
>  		return;
>  	}
>  
> -	if (DISPLAY_VER(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
> -		switch (refresh_type) {
> -		case DRRS_HIGH_RR:
> -			intel_dp_set_m_n(crtc_state, M1_N1);
> -			break;
> -		case DRRS_LOW_RR:
> -			intel_dp_set_m_n(crtc_state, M2_N2);
> -			break;
> -		case DRRS_MAX_RR:
> -		default:
> -			drm_err(&dev_priv->drm,
> -				"Unsupported refreshrate type\n");
> -		}
> -	} else if (DISPLAY_VER(dev_priv) > 6) {
> -		i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
> -		u32 val;
> -
> -		val = intel_de_read(dev_priv, reg);
> -		if (refresh_type == DRRS_LOW_RR) {
> -			if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> -				val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
> -			else
> -				val |= PIPECONF_EDP_RR_MODE_SWITCH;
> -		} else {
> -			if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> -				val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
> -			else
> -				val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
> -		}
> -		intel_de_write(dev_priv, reg, val);
> -	}
> +	if (DISPLAY_VER(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv))
> +		intel_drrs_set_refresh_rate_m_n(crtc_state, refresh_type);
> +	else if (DISPLAY_VER(dev_priv) > 6)
> +		intel_drrs_set_refresh_rate_pipeconf(crtc_state, refresh_type);
>  
>  	dev_priv->drrs.refresh_rate_type = refresh_type;

-- 
Jani Nikula, Intel Open Source Graphics Center

^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [Intel-gfx] [PATCH 04/14] drm/i915: Move drrs hardware bit frobbing to small helpers
  2022-01-27 11:23   ` Jani Nikula
@ 2022-01-27 11:24     ` Jani Nikula
  2022-01-27 11:35       ` Ville Syrjälä
  0 siblings, 1 reply; 31+ messages in thread
From: Jani Nikula @ 2022-01-27 11:24 UTC (permalink / raw)
  To: Ville Syrjala, intel-gfx

On Thu, 27 Jan 2022, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Thu, 27 Jan 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> Split the drrs code that actually changes the refresh rate
>> (via PIPECONF or M/N values) to small helper functions that
>> only deal with the hardware details an nothing else. We'll
>> soon have a third way of doing this, and it's less confusing
>> when each difference method lives in its own funciton.
>>
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_drrs.c | 67 ++++++++++++-----------
>>  1 file changed, 36 insertions(+), 31 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c
>> index 46be46f2c47e..0cacdb174fd0 100644
>> --- a/drivers/gpu/drm/i915/display/intel_drrs.c
>> +++ b/drivers/gpu/drm/i915/display/intel_drrs.c
>> @@ -87,6 +87,38 @@ intel_drrs_compute_config(struct intel_dp *intel_dp,
>>  		pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;
>>  }
>>  
>> +static void
>> +intel_drrs_set_refresh_rate_pipeconf(const struct intel_crtc_state *crtc_state,
>> +				     enum drrs_refresh_rate_type refresh_type)
>
> Side note, for future, does this really need to be an enum? Could it
> just be a bool "reduced" or something?

And I mean throughout the driver, not just right here.

>
> Anyway,
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
>
>
>> +{
>> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>> +	u32 val, bit;
>> +
>> +	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>> +		bit = PIPECONF_EDP_RR_MODE_SWITCH_VLV;
>> +	else
>> +		bit = PIPECONF_EDP_RR_MODE_SWITCH;
>> +
>> +	val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
>> +
>> +	if (refresh_type == DRRS_LOW_RR)
>> +		val |= bit;
>> +	else
>> +		val &= ~bit;
>> +
>> +	intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val);
>> +}
>> +
>> +static void
>> +intel_drrs_set_refresh_rate_m_n(const struct intel_crtc_state *crtc_state,
>> +				enum drrs_refresh_rate_type refresh_type)
>> +{
>> +	intel_dp_set_m_n(crtc_state,
>> +			 refresh_type == DRRS_LOW_RR ? M2_N2 : M1_N1);
>> +}
>> +
>>  static void intel_drrs_set_state(struct drm_i915_private *dev_priv,
>>  				 const struct intel_crtc_state *crtc_state,
>>  				 enum drrs_refresh_rate_type refresh_type)
>> @@ -120,37 +152,10 @@ static void intel_drrs_set_state(struct drm_i915_private *dev_priv,
>>  		return;
>>  	}
>>  
>> -	if (DISPLAY_VER(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
>> -		switch (refresh_type) {
>> -		case DRRS_HIGH_RR:
>> -			intel_dp_set_m_n(crtc_state, M1_N1);
>> -			break;
>> -		case DRRS_LOW_RR:
>> -			intel_dp_set_m_n(crtc_state, M2_N2);
>> -			break;
>> -		case DRRS_MAX_RR:
>> -		default:
>> -			drm_err(&dev_priv->drm,
>> -				"Unsupported refreshrate type\n");
>> -		}
>> -	} else if (DISPLAY_VER(dev_priv) > 6) {
>> -		i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
>> -		u32 val;
>> -
>> -		val = intel_de_read(dev_priv, reg);
>> -		if (refresh_type == DRRS_LOW_RR) {
>> -			if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>> -				val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
>> -			else
>> -				val |= PIPECONF_EDP_RR_MODE_SWITCH;
>> -		} else {
>> -			if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>> -				val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
>> -			else
>> -				val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
>> -		}
>> -		intel_de_write(dev_priv, reg, val);
>> -	}
>> +	if (DISPLAY_VER(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv))
>> +		intel_drrs_set_refresh_rate_m_n(crtc_state, refresh_type);
>> +	else if (DISPLAY_VER(dev_priv) > 6)
>> +		intel_drrs_set_refresh_rate_pipeconf(crtc_state, refresh_type);
>>  
>>  	dev_priv->drrs.refresh_rate_type = refresh_type;

-- 
Jani Nikula, Intel Open Source Graphics Center

^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [Intel-gfx] [PATCH 04/14] drm/i915: Move drrs hardware bit frobbing to small helpers
  2022-01-27 11:24     ` Jani Nikula
@ 2022-01-27 11:35       ` Ville Syrjälä
  2022-01-27 11:42         ` Jani Nikula
  0 siblings, 1 reply; 31+ messages in thread
From: Ville Syrjälä @ 2022-01-27 11:35 UTC (permalink / raw)
  To: Jani Nikula; +Cc: intel-gfx

On Thu, Jan 27, 2022 at 01:24:05PM +0200, Jani Nikula wrote:
> On Thu, 27 Jan 2022, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> > On Thu, 27 Jan 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> >> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >>
> >> Split the drrs code that actually changes the refresh rate
> >> (via PIPECONF or M/N values) to small helper functions that
> >> only deal with the hardware details an nothing else. We'll
> >> soon have a third way of doing this, and it's less confusing
> >> when each difference method lives in its own funciton.
> >>
> >> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/display/intel_drrs.c | 67 ++++++++++++-----------
> >>  1 file changed, 36 insertions(+), 31 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c
> >> index 46be46f2c47e..0cacdb174fd0 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_drrs.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_drrs.c
> >> @@ -87,6 +87,38 @@ intel_drrs_compute_config(struct intel_dp *intel_dp,
> >>  		pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;
> >>  }
> >>  
> >> +static void
> >> +intel_drrs_set_refresh_rate_pipeconf(const struct intel_crtc_state *crtc_state,
> >> +				     enum drrs_refresh_rate_type refresh_type)
> >
> > Side note, for future, does this really need to be an enum? Could it
> > just be a bool "reduced" or something?
> 
> And I mean throughout the driver, not just right here.

I suppose a bool would suffice. I was going to rename it to
at least have a bit more consistent namespace, but perhaps
we could just nuke it entirely.

-- 
Ville Syrjälä
Intel

^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [Intel-gfx] [PATCH 04/14] drm/i915: Move drrs hardware bit frobbing to small helpers
  2022-01-27 11:35       ` Ville Syrjälä
@ 2022-01-27 11:42         ` Jani Nikula
  0 siblings, 0 replies; 31+ messages in thread
From: Jani Nikula @ 2022-01-27 11:42 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx

On Thu, 27 Jan 2022, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Thu, Jan 27, 2022 at 01:24:05PM +0200, Jani Nikula wrote:
>> On Thu, 27 Jan 2022, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>> > On Thu, 27 Jan 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
>> >> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >>
>> >> Split the drrs code that actually changes the refresh rate
>> >> (via PIPECONF or M/N values) to small helper functions that
>> >> only deal with the hardware details an nothing else. We'll
>> >> soon have a third way of doing this, and it's less confusing
>> >> when each difference method lives in its own funciton.
>> >>
>> >> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >> ---
>> >>  drivers/gpu/drm/i915/display/intel_drrs.c | 67 ++++++++++++-----------
>> >>  1 file changed, 36 insertions(+), 31 deletions(-)
>> >>
>> >> diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c
>> >> index 46be46f2c47e..0cacdb174fd0 100644
>> >> --- a/drivers/gpu/drm/i915/display/intel_drrs.c
>> >> +++ b/drivers/gpu/drm/i915/display/intel_drrs.c
>> >> @@ -87,6 +87,38 @@ intel_drrs_compute_config(struct intel_dp *intel_dp,
>> >>  		pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;
>> >>  }
>> >>  
>> >> +static void
>> >> +intel_drrs_set_refresh_rate_pipeconf(const struct intel_crtc_state *crtc_state,
>> >> +				     enum drrs_refresh_rate_type refresh_type)
>> >
>> > Side note, for future, does this really need to be an enum? Could it
>> > just be a bool "reduced" or something?
>> 
>> And I mean throughout the driver, not just right here.
>
> I suppose a bool would suffice. I was going to rename it to
> at least have a bit more consistent namespace, but perhaps
> we could just nuke it entirely.

Also, should be done in follow-up, let's not complicate this set any
more.

BR,
Jani.

-- 
Jani Nikula, Intel Open Source Graphics Center

^ permalink raw reply	[flat|nested] 31+ messages in thread

* [Intel-gfx] [PATCH 05/14] drm/i915: Make M/N set/get a bit more direct
  2022-01-27  9:32 [Intel-gfx] [PATCH 00/14] drm/i915: M/N cleanup Ville Syrjala
                   ` (3 preceding siblings ...)
  2022-01-27  9:32 ` [Intel-gfx] [PATCH 04/14] drm/i915: Move drrs hardware bit frobbing to small helpers Ville Syrjala
@ 2022-01-27  9:32 ` Ville Syrjala
  2022-01-27  9:32 ` [Intel-gfx] [PATCH 06/14] drm/i915: Move PCH transcoder M/N setup into the PCH code Ville Syrjala
                   ` (12 subsequent siblings)
  17 siblings, 0 replies; 31+ messages in thread
From: Ville Syrjala @ 2022-01-27  9:32 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Throw out the middle-men (dp_{get/set}_m_n()) and just call
the cpu/pch transcoder functions directly. Let's us nuke
this enum link_m_n_set stuff.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/g4x_dp.c         |  19 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      |  16 +-
 drivers/gpu/drm/i915/display/intel_display.c  | 189 +++++++++---------
 drivers/gpu/drm/i915/display/intel_display.h  |  23 ++-
 .../drm/i915/display/intel_display_types.h    |  19 --
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |   4 +-
 drivers/gpu/drm/i915/display/intel_drrs.c     |   7 +-
 .../gpu/drm/i915/display/intel_pch_display.c  |   6 +-
 8 files changed, 153 insertions(+), 130 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
index f37677df6ebf..da2b59d990bb 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -100,6 +100,23 @@ void g4x_dp_set_clock(struct intel_encoder *encoder,
 	}
 }
 
+static void g4x_dp_get_m_n(struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+	if (crtc_state->has_pch_encoder) {
+		intel_pch_transcoder_get_m1_n1(crtc, &crtc_state->dp_m_n);
+		intel_pch_transcoder_get_m2_n2(crtc, &crtc_state->dp_m2_n2);
+	} else {
+		enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+		intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder,
+					       &crtc_state->dp_m_n);
+		intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder,
+					       &crtc_state->dp_m2_n2);
+	}
+}
+
 static void intel_dp_prepare(struct intel_encoder *encoder,
 			     const struct intel_crtc_state *pipe_config)
 {
@@ -384,7 +401,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
 	pipe_config->lane_count =
 		((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
 
-	intel_dp_get_m_n(crtc, pipe_config);
+	g4x_dp_get_m_n(pipe_config);
 
 	if (port == PORT_A) {
 		if ((intel_de_read(dev_priv, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index ca8becb07e45..9bc916d36bd2 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2498,6 +2498,8 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
 				    const struct drm_connector_state *conn_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
 	if (DISPLAY_VER(dev_priv) >= 12)
 		tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
@@ -2510,7 +2512,10 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
 	if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
 		intel_ddi_set_dp_msa(crtc_state, conn_state);
 
-		intel_dp_set_m_n(crtc_state, M1_N1);
+		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
+					       &crtc_state->dp_m_n);
+		intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
+					       &crtc_state->dp_m2_n2);
 	}
 }
 
@@ -3358,7 +3363,6 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
 			pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
 		pipe_config->lane_count =
 			((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
-		intel_dp_get_m_n(crtc, pipe_config);
 
 		if (DISPLAY_VER(dev_priv) >= 11) {
 			i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config);
@@ -3372,6 +3376,11 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
 				    pipe_config->fec_enable);
 		}
 
+		intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder,
+					       &pipe_config->dp_m_n);
+		intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder,
+					       &pipe_config->dp_m2_n2);
+
 		if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink)
 			pipe_config->infoframes.enable |=
 				intel_lspcon_infoframes_enabled(encoder, pipe_config);
@@ -3395,7 +3404,8 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
 			pipe_config->mst_master_transcoder =
 					REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
 
-		intel_dp_get_m_n(crtc, pipe_config);
+		intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder,
+					       &pipe_config->dp_m_n);
 
 		pipe_config->infoframes.enable |=
 			intel_hdmi_infoframes_enabled(encoder, pipe_config);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 75de794185b2..3b40a0b0b79e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -118,9 +118,10 @@
 
 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
-static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
-					 const struct intel_link_m_n *m_n,
-					 const struct intel_link_m_n *m2_n2);
+static void intel_pch_transcoder_set_m1_n1(struct intel_crtc *crtc,
+					   const struct intel_link_m_n *m_n);
+static void intel_pch_transcoder_set_m2_n2(struct intel_crtc *crtc,
+					   const struct intel_link_m_n *m_n);
 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);
@@ -1817,6 +1818,7 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,
 	const struct intel_crtc_state *new_crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
 	enum pipe pipe = crtc->pipe;
 
 	if (drm_WARN_ON(&dev_priv->drm, crtc->active))
@@ -1835,15 +1837,26 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,
 	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
 	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
 
-	if (intel_crtc_has_dp_encoder(new_crtc_state))
-		intel_dp_set_m_n(new_crtc_state, M1_N1);
+	if (intel_crtc_has_dp_encoder(new_crtc_state)) {
+		if (new_crtc_state->has_pch_encoder) {
+			intel_pch_transcoder_set_m1_n1(crtc,
+						       &new_crtc_state->dp_m_n);
+			intel_pch_transcoder_set_m2_n2(crtc,
+						       &new_crtc_state->dp_m2_n2);
+		} else {
+			intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
+						       &new_crtc_state->dp_m_n);
+			intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
+						       &new_crtc_state->dp_m2_n2);
+		}
+	}
 
 	intel_set_transcoder_timings(new_crtc_state);
 	intel_set_pipe_src_size(new_crtc_state);
 
 	if (new_crtc_state->has_pch_encoder)
-		intel_cpu_transcoder_set_m_n(new_crtc_state,
-					     &new_crtc_state->fdi_m_n, NULL);
+		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
+					       &new_crtc_state->fdi_m_n);
 
 	ilk_set_pipeconf(new_crtc_state);
 
@@ -2009,8 +2022,8 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta
 			       crtc_state->pixel_multiplier - 1);
 
 	if (crtc_state->has_pch_encoder)
-		intel_cpu_transcoder_set_m_n(crtc_state,
-					     &crtc_state->fdi_m_n, NULL);
+		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
+					       &crtc_state->fdi_m_n);
 
 	hsw_set_frame_start_delay(crtc_state);
 
@@ -2444,13 +2457,18 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state,
 	const struct intel_crtc_state *new_crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
 	enum pipe pipe = crtc->pipe;
 
 	if (drm_WARN_ON(&dev_priv->drm, crtc->active))
 		return;
 
-	if (intel_crtc_has_dp_encoder(new_crtc_state))
-		intel_dp_set_m_n(new_crtc_state, M1_N1);
+	if (intel_crtc_has_dp_encoder(new_crtc_state)) {
+		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
+					       &new_crtc_state->dp_m_n);
+		intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
+					       &new_crtc_state->dp_m2_n2);
+	}
 
 	intel_set_transcoder_timings(new_crtc_state);
 	intel_set_pipe_src_size(new_crtc_state);
@@ -2496,13 +2514,15 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,
 	const struct intel_crtc_state *new_crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
 	enum pipe pipe = crtc->pipe;
 
 	if (drm_WARN_ON(&dev_priv->drm, crtc->active))
 		return;
 
 	if (intel_crtc_has_dp_encoder(new_crtc_state))
-		intel_dp_set_m_n(new_crtc_state, M1_N1);
+		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
+					       &new_crtc_state->dp_m_n);
 
 	intel_set_transcoder_timings(new_crtc_state);
 	intel_set_pipe_src_size(new_crtc_state);
@@ -3124,10 +3144,9 @@ static void intel_set_m_n(struct drm_i915_private *i915,
 	intel_de_write(i915, link_n_reg, m_n->link_n);
 }
 
-static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
-					 const struct intel_link_m_n *m_n)
+static void intel_pch_transcoder_set_m1_n1(struct intel_crtc *crtc,
+					   const struct intel_link_m_n *m_n)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 
@@ -3136,73 +3155,55 @@ static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_sta
 		      PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe));
 }
 
+static void intel_pch_transcoder_set_m2_n2(struct intel_crtc *crtc,
+					   const struct intel_link_m_n *m_n)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum pipe pipe = crtc->pipe;
+
+	intel_set_m_n(dev_priv, m_n,
+		      PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe),
+		      PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe));
+}
+
 static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
-				 enum transcoder transcoder)
+				 enum transcoder cpu_transcoder)
 {
 	if (IS_HASWELL(dev_priv))
-		return transcoder == TRANSCODER_EDP;
+		return cpu_transcoder == TRANSCODER_EDP;
 
-	/*
-	 * Strictly speaking some registers are available before
-	 * gen7, but we only support DRRS on gen7+
-	 */
-	return DISPLAY_VER(dev_priv) == 7 || IS_CHERRYVIEW(dev_priv);
+	return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv);
 }
 
-static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
-					 const struct intel_link_m_n *m_n,
-					 const struct intel_link_m_n *m2_n2)
+void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
+				    enum transcoder cpu_transcoder,
+				    const struct intel_link_m_n *m_n)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
-	enum transcoder transcoder = crtc_state->cpu_transcoder;
 
-	if (DISPLAY_VER(dev_priv) >= 5) {
+	if (DISPLAY_VER(dev_priv) >= 5)
 		intel_set_m_n(dev_priv, m_n,
-			      PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
-			      PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
-		/*
-		 *  M2_N2 registers are set only if DRRS is supported
-		 * (to make sure the registers are not unnecessarily accessed).
-		 */
-		if (m2_n2 && crtc_state->has_drrs &&
-		    transcoder_has_m2_n2(dev_priv, transcoder)) {
-			intel_set_m_n(dev_priv, m2_n2,
-				      PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
-				      PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
-		}
-	} else {
+			      PIPE_DATA_M1(cpu_transcoder), PIPE_DATA_N1(cpu_transcoder),
+			      PIPE_LINK_M1(cpu_transcoder), PIPE_LINK_N1(cpu_transcoder));
+	else
 		intel_set_m_n(dev_priv, m_n,
 			      PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
 			      PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
-	}
 }
 
-void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n)
+void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
+				    enum transcoder cpu_transcoder,
+				    const struct intel_link_m_n *m_n)
 {
-	const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
-	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
-	if (m_n == M1_N1) {
-		dp_m_n = &crtc_state->dp_m_n;
-		dp_m2_n2 = &crtc_state->dp_m2_n2;
-	} else if (m_n == M2_N2) {
-
-		/*
-		 * M2_N2 registers are not supported. Hence m2_n2 divider value
-		 * needs to be programmed into M1_N1.
-		 */
-		dp_m_n = &crtc_state->dp_m2_n2;
-	} else {
-		drm_err(&i915->drm, "Unsupported divider value\n");
+	if (!transcoder_has_m2_n2(dev_priv, cpu_transcoder))
 		return;
-	}
 
-	if (crtc_state->has_pch_encoder)
-		intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n);
-	else
-		intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2);
+	intel_set_m_n(dev_priv, m_n,
+		      PIPE_DATA_M2(cpu_transcoder), PIPE_DATA_N2(cpu_transcoder),
+		      PIPE_LINK_M2(cpu_transcoder), PIPE_LINK_N2(cpu_transcoder));
 }
 
 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
@@ -3872,11 +3873,10 @@ static void intel_get_m_n(struct drm_i915_private *i915,
 	m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1;
 }
 
-static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
-					 struct intel_link_m_n *m_n)
+void intel_pch_transcoder_get_m1_n1(struct intel_crtc *crtc,
+				    struct intel_link_m_n *m_n)
 {
-	struct drm_device *dev = crtc->base.dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 
 	intel_get_m_n(dev_priv, m_n,
@@ -3884,47 +3884,46 @@ static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
 		      PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe));
 }
 
-static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
-					 enum transcoder transcoder,
-					 struct intel_link_m_n *m_n,
-					 struct intel_link_m_n *m2_n2)
+void intel_pch_transcoder_get_m2_n2(struct intel_crtc *crtc,
+				    struct intel_link_m_n *m_n)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 
-	if (DISPLAY_VER(dev_priv) >= 5) {
+	intel_get_m_n(dev_priv, m_n,
+		      PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe),
+		      PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe));
+}
+
+void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
+				    enum transcoder cpu_transcoder,
+				    struct intel_link_m_n *m_n)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum pipe pipe = crtc->pipe;
+
+	if (DISPLAY_VER(dev_priv) >= 5)
 		intel_get_m_n(dev_priv, m_n,
-			      PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
-			      PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
-
-		if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {
-			intel_get_m_n(dev_priv, m2_n2,
-				      PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
-				      PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
-		}
-	} else {
+			      PIPE_DATA_M1(cpu_transcoder), PIPE_DATA_N1(cpu_transcoder),
+			      PIPE_LINK_M1(cpu_transcoder), PIPE_LINK_N1(cpu_transcoder));
+	else
 		intel_get_m_n(dev_priv, m_n,
 			      PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
 			      PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
-	}
 }
 
-void intel_dp_get_m_n(struct intel_crtc *crtc,
-		      struct intel_crtc_state *pipe_config)
+void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
+				    enum transcoder cpu_transcoder,
+				    struct intel_link_m_n *m_n)
 {
-	if (pipe_config->has_pch_encoder)
-		intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
-	else
-		intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
-					     &pipe_config->dp_m_n,
-					     &pipe_config->dp_m2_n2);
-}
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
-void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
-			    struct intel_crtc_state *pipe_config)
-{
-	intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
-				     &pipe_config->fdi_m_n, NULL);
+	if (!transcoder_has_m2_n2(dev_priv, cpu_transcoder))
+		return;
+
+	intel_get_m_n(dev_priv, m_n,
+		      PIPE_DATA_M2(cpu_transcoder), PIPE_DATA_N2(cpu_transcoder),
+		      PIPE_LINK_M2(cpu_transcoder), PIPE_LINK_N2(cpu_transcoder));
 }
 
 static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index a241007f5c82..090534eb4535 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -27,7 +27,6 @@
 
 #include <drm/drm_util.h>
 
-enum link_m_n_set;
 enum drm_scaling_filter;
 struct dpll;
 struct drm_connector;
@@ -554,6 +553,22 @@ intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
 				bool bigjoiner);
 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
 bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
+void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
+				    enum transcoder cpu_transcoder,
+				    const struct intel_link_m_n *m_n);
+void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
+				    enum transcoder cpu_transcoder,
+				    const struct intel_link_m_n *m_n);
+void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
+				    enum transcoder cpu_transcoder,
+				    struct intel_link_m_n *m_n);
+void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
+				    enum transcoder cpu_transcoder,
+				    struct intel_link_m_n *m_n);
+void intel_pch_transcoder_get_m1_n1(struct intel_crtc *crtc,
+				    struct intel_link_m_n *m_n);
+void intel_pch_transcoder_get_m2_n2(struct intel_crtc *crtc,
+				    struct intel_link_m_n *m_n);
 
 void intel_plane_destroy(struct drm_plane *plane);
 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state);
@@ -605,12 +620,6 @@ bool intel_fuzzy_clock_check(int clock1, int clock2);
 
 void intel_display_prepare_reset(struct drm_i915_private *dev_priv);
 void intel_display_finish_reset(struct drm_i915_private *dev_priv);
-void intel_dp_get_m_n(struct intel_crtc *crtc,
-		      struct intel_crtc_state *pipe_config);
-void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
-		      enum link_m_n_set m_n);
-void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
-			    struct intel_crtc_state *pipe_config);
 void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 			 struct intel_crtc_state *pipe_config);
 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 6b107872ad39..60e15226a8cb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1445,25 +1445,6 @@ struct intel_hdmi {
 };
 
 struct intel_dp_mst_encoder;
-/*
- * enum link_m_n_set:
- *	When platform provides two set of M_N registers for dp, we can
- *	program them and switch between them incase of DRRS.
- *	But When only one such register is provided, we have to program the
- *	required divider value on that registers itself based on the DRRS state.
- *
- * M1_N1	: Program dp_m_n on M1_N1 registers
- *			  dp_m2_n2 on M2_N2 registers (If supported)
- *
- * M2_N2	: Program dp_m2_n2 on M1_N1 registers
- *			  M2_N2 registers are not supported
- */
-
-enum link_m_n_set {
-	/* Sets the m1_n1 and m2_n2 */
-	M1_N1 = 0,
-	M2_N2
-};
 
 struct intel_dp_compliance_data {
 	unsigned long edid;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index b8bc7d397c81..95f9a5c03a47 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -472,6 +472,7 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
 	struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 	struct intel_digital_port *dig_port = intel_mst->primary;
 	struct intel_dp *intel_dp = &dig_port->dp;
+	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_connector *connector =
 		to_intel_connector(conn_state->connector);
@@ -523,7 +524,8 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
 
 	intel_ddi_set_dp_msa(pipe_config, conn_state);
 
-	intel_dp_set_m_n(pipe_config, M1_N1);
+	intel_cpu_transcoder_set_m1_n1(crtc, pipe_config->cpu_transcoder,
+				       &pipe_config->dp_m_n);
 }
 
 static void intel_mst_enable_dp(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c
index 0cacdb174fd0..53f014b4436b 100644
--- a/drivers/gpu/drm/i915/display/intel_drrs.c
+++ b/drivers/gpu/drm/i915/display/intel_drrs.c
@@ -115,8 +115,11 @@ static void
 intel_drrs_set_refresh_rate_m_n(const struct intel_crtc_state *crtc_state,
 				enum drrs_refresh_rate_type refresh_type)
 {
-	intel_dp_set_m_n(crtc_state,
-			 refresh_type == DRRS_LOW_RR ? M2_N2 : M1_N1);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+	intel_cpu_transcoder_set_m1_n1(crtc, crtc_state->cpu_transcoder,
+				       refresh_type == DRRS_LOW_RR ?
+				       &crtc_state->dp_m2_n2 : &crtc_state->dp_m_n);
 }
 
 static void intel_drrs_set_state(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 7ef2d40997b2..dd010be534a2 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -386,7 +386,8 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
 	crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
 				 FDI_DP_PORT_WIDTH_SHIFT) + 1;
 
-	ilk_get_fdi_m_n_config(crtc, crtc_state);
+	intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder,
+				       &crtc_state->fdi_m_n);
 
 	if (HAS_PCH_IBX(dev_priv)) {
 		/*
@@ -509,7 +510,8 @@ void lpt_pch_get_config(struct intel_crtc_state *crtc_state)
 	crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
 				 FDI_DP_PORT_WIDTH_SHIFT) + 1;
 
-	ilk_get_fdi_m_n_config(crtc, crtc_state);
+	intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder,
+				       &crtc_state->fdi_m_n);
 
 	crtc_state->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
 }
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [Intel-gfx] [PATCH 06/14] drm/i915: Move PCH transcoder M/N setup into the PCH code
  2022-01-27  9:32 [Intel-gfx] [PATCH 00/14] drm/i915: M/N cleanup Ville Syrjala
                   ` (4 preceding siblings ...)
  2022-01-27  9:32 ` [Intel-gfx] [PATCH 05/14] drm/i915: Make M/N set/get a bit more direct Ville Syrjala
@ 2022-01-27  9:32 ` Ville Syrjala
  2022-01-27  9:32 ` [Intel-gfx] [PATCH 07/14] drm/i915: Move M/N setup to a more logical place on ddi platforms Ville Syrjala
                   ` (11 subsequent siblings)
  17 siblings, 0 replies; 31+ messages in thread
From: Ville Syrjala @ 2022-01-27  9:32 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Do the PCH transcoder M/N setup next to where all the other
PCH transcoder stuff is programmed.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/g4x_dp.c         |  1 +
 drivers/gpu/drm/i915/display/intel_display.c  | 92 ++++---------------
 drivers/gpu/drm/i915/display/intel_display.h  | 14 ++-
 .../gpu/drm/i915/display/intel_pch_display.c  | 48 ++++++++++
 .../gpu/drm/i915/display/intel_pch_display.h  |  6 ++
 5 files changed, 83 insertions(+), 78 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
index da2b59d990bb..a08936d8c0e7 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -18,6 +18,7 @@
 #include "intel_fifo_underrun.h"
 #include "intel_hdmi.h"
 #include "intel_hotplug.h"
+#include "intel_pch_display.h"
 #include "intel_pps.h"
 #include "vlv_sideband.h"
 
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 3b40a0b0b79e..602ea6d15628 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -118,10 +118,6 @@
 
 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
-static void intel_pch_transcoder_set_m1_n1(struct intel_crtc *crtc,
-					   const struct intel_link_m_n *m_n);
-static void intel_pch_transcoder_set_m2_n2(struct intel_crtc *crtc,
-					   const struct intel_link_m_n *m_n);
 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);
@@ -1837,26 +1833,18 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,
 	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
 	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
 
-	if (intel_crtc_has_dp_encoder(new_crtc_state)) {
-		if (new_crtc_state->has_pch_encoder) {
-			intel_pch_transcoder_set_m1_n1(crtc,
-						       &new_crtc_state->dp_m_n);
-			intel_pch_transcoder_set_m2_n2(crtc,
-						       &new_crtc_state->dp_m2_n2);
-		} else {
-			intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
-						       &new_crtc_state->dp_m_n);
-			intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
-						       &new_crtc_state->dp_m2_n2);
-		}
-	}
-
-	intel_set_transcoder_timings(new_crtc_state);
-	intel_set_pipe_src_size(new_crtc_state);
-
-	if (new_crtc_state->has_pch_encoder)
+	if (new_crtc_state->has_pch_encoder) {
 		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
 					       &new_crtc_state->fdi_m_n);
+	} else if (intel_crtc_has_dp_encoder(new_crtc_state)) {
+		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
+					       &new_crtc_state->dp_m_n);
+		intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
+					       &new_crtc_state->dp_m2_n2);
+	}
+
+	intel_set_transcoder_timings(new_crtc_state);
+	intel_set_pipe_src_size(new_crtc_state);
 
 	ilk_set_pipeconf(new_crtc_state);
 
@@ -3133,10 +3121,10 @@ static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
 	}
 }
 
-static void intel_set_m_n(struct drm_i915_private *i915,
-			  const struct intel_link_m_n *m_n,
-			  i915_reg_t data_m_reg, i915_reg_t data_n_reg,
-			  i915_reg_t link_m_reg, i915_reg_t link_n_reg)
+void intel_set_m_n(struct drm_i915_private *i915,
+		   const struct intel_link_m_n *m_n,
+		   i915_reg_t data_m_reg, i915_reg_t data_n_reg,
+		   i915_reg_t link_m_reg, i915_reg_t link_n_reg)
 {
 	intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
 	intel_de_write(i915, data_n_reg, m_n->data_n);
@@ -3144,28 +3132,6 @@ static void intel_set_m_n(struct drm_i915_private *i915,
 	intel_de_write(i915, link_n_reg, m_n->link_n);
 }
 
-static void intel_pch_transcoder_set_m1_n1(struct intel_crtc *crtc,
-					   const struct intel_link_m_n *m_n)
-{
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	enum pipe pipe = crtc->pipe;
-
-	intel_set_m_n(dev_priv, m_n,
-		      PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe),
-		      PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe));
-}
-
-static void intel_pch_transcoder_set_m2_n2(struct intel_crtc *crtc,
-					   const struct intel_link_m_n *m_n)
-{
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	enum pipe pipe = crtc->pipe;
-
-	intel_set_m_n(dev_priv, m_n,
-		      PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe),
-		      PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe));
-}
-
 static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
 				 enum transcoder cpu_transcoder)
 {
@@ -3861,10 +3827,10 @@ int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
 	return DIV_ROUND_UP(bps, link_bw * 8);
 }
 
-static void intel_get_m_n(struct drm_i915_private *i915,
-			  struct intel_link_m_n *m_n,
-			  i915_reg_t data_m_reg, i915_reg_t data_n_reg,
-			  i915_reg_t link_m_reg, i915_reg_t link_n_reg)
+void intel_get_m_n(struct drm_i915_private *i915,
+		   struct intel_link_m_n *m_n,
+		   i915_reg_t data_m_reg, i915_reg_t data_n_reg,
+		   i915_reg_t link_m_reg, i915_reg_t link_n_reg)
 {
 	m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK;
 	m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK;
@@ -3873,28 +3839,6 @@ static void intel_get_m_n(struct drm_i915_private *i915,
 	m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1;
 }
 
-void intel_pch_transcoder_get_m1_n1(struct intel_crtc *crtc,
-				    struct intel_link_m_n *m_n)
-{
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	enum pipe pipe = crtc->pipe;
-
-	intel_get_m_n(dev_priv, m_n,
-		      PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe),
-		      PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe));
-}
-
-void intel_pch_transcoder_get_m2_n2(struct intel_crtc *crtc,
-				    struct intel_link_m_n *m_n)
-{
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	enum pipe pipe = crtc->pipe;
-
-	intel_get_m_n(dev_priv, m_n,
-		      PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe),
-		      PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe));
-}
-
 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
 				    enum transcoder cpu_transcoder,
 				    struct intel_link_m_n *m_n)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 090534eb4535..afa312e11624 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -27,6 +27,8 @@
 
 #include <drm/drm_util.h>
 
+#include "i915_reg_defs.h"
+
 enum drm_scaling_filter;
 struct dpll;
 struct drm_connector;
@@ -553,6 +555,14 @@ intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
 				bool bigjoiner);
 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
 bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
+void intel_set_m_n(struct drm_i915_private *i915,
+		   const struct intel_link_m_n *m_n,
+		   i915_reg_t data_m_reg, i915_reg_t data_n_reg,
+		   i915_reg_t link_m_reg, i915_reg_t link_n_reg);
+void intel_get_m_n(struct drm_i915_private *i915,
+		   struct intel_link_m_n *m_n,
+		   i915_reg_t data_m_reg, i915_reg_t data_n_reg,
+		   i915_reg_t link_m_reg, i915_reg_t link_n_reg);
 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
 				    enum transcoder cpu_transcoder,
 				    const struct intel_link_m_n *m_n);
@@ -565,10 +575,6 @@ void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
 				    enum transcoder cpu_transcoder,
 				    struct intel_link_m_n *m_n);
-void intel_pch_transcoder_get_m1_n1(struct intel_crtc *crtc,
-				    struct intel_link_m_n *m_n);
-void intel_pch_transcoder_get_m2_n2(struct intel_crtc *crtc,
-				    struct intel_link_m_n *m_n);
 
 void intel_plane_destroy(struct drm_plane *plane);
 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index dd010be534a2..9192769e3337 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -88,6 +88,50 @@ static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
 			pipe_name(pipe));
 }
 
+static void intel_pch_transcoder_set_m1_n1(struct intel_crtc *crtc,
+					   const struct intel_link_m_n *m_n)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum pipe pipe = crtc->pipe;
+
+	intel_set_m_n(dev_priv, m_n,
+		      PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe),
+		      PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe));
+}
+
+static void intel_pch_transcoder_set_m2_n2(struct intel_crtc *crtc,
+					   const struct intel_link_m_n *m_n)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum pipe pipe = crtc->pipe;
+
+	intel_set_m_n(dev_priv, m_n,
+		      PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe),
+		      PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe));
+}
+
+void intel_pch_transcoder_get_m1_n1(struct intel_crtc *crtc,
+				    struct intel_link_m_n *m_n)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum pipe pipe = crtc->pipe;
+
+	intel_get_m_n(dev_priv, m_n,
+		      PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe),
+		      PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe));
+}
+
+void intel_pch_transcoder_get_m2_n2(struct intel_crtc *crtc,
+				    struct intel_link_m_n *m_n)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum pipe pipe = crtc->pipe;
+
+	intel_get_m_n(dev_priv, m_n,
+		      PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe),
+		      PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe));
+}
+
 static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
 					   enum pipe pch_transcoder)
 {
@@ -278,6 +322,10 @@ void ilk_pch_enable(struct intel_atomic_state *state,
 
 	/* set transcoder timing, panel must allow it */
 	assert_pps_unlocked(dev_priv, pipe);
+	if (intel_crtc_has_dp_encoder(crtc_state)) {
+		intel_pch_transcoder_set_m1_n1(crtc, &crtc_state->dp_m_n);
+		intel_pch_transcoder_set_m2_n2(crtc, &crtc_state->dp_m2_n2);
+	}
 	ilk_pch_transcoder_set_timings(crtc_state, pipe);
 
 	intel_fdi_normal_train(crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.h b/drivers/gpu/drm/i915/display/intel_pch_display.h
index f915fa4241d7..749473d99320 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.h
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.h
@@ -9,6 +9,7 @@
 struct intel_atomic_state;
 struct intel_crtc;
 struct intel_crtc_state;
+struct intel_link_m_n;
 
 void ilk_pch_pre_enable(struct intel_atomic_state *state,
 			struct intel_crtc *crtc);
@@ -26,4 +27,9 @@ void lpt_pch_disable(struct intel_atomic_state *state,
 		     struct intel_crtc *crtc);
 void lpt_pch_get_config(struct intel_crtc_state *crtc_state);
 
+void intel_pch_transcoder_get_m1_n1(struct intel_crtc *crtc,
+				    struct intel_link_m_n *m_n);
+void intel_pch_transcoder_get_m2_n2(struct intel_crtc *crtc,
+				    struct intel_link_m_n *m_n);
+
 #endif
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [Intel-gfx] [PATCH 07/14] drm/i915: Move M/N setup to a more logical place on ddi platforms
  2022-01-27  9:32 [Intel-gfx] [PATCH 00/14] drm/i915: M/N cleanup Ville Syrjala
                   ` (5 preceding siblings ...)
  2022-01-27  9:32 ` [Intel-gfx] [PATCH 06/14] drm/i915: Move PCH transcoder M/N setup into the PCH code Ville Syrjala
@ 2022-01-27  9:32 ` Ville Syrjala
  2022-01-27  9:32 ` [Intel-gfx] [PATCH 08/14] drm/i915: Extract {i9xx, ilk}_configure_cpu_transcoder() Ville Syrjala
                   ` (10 subsequent siblings)
  17 siblings, 0 replies; 31+ messages in thread
From: Ville Syrjala @ 2022-01-27  9:32 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Let's do the cpu transcoder M/N setup next to where we program
most other cpu transcoder timings/etc.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c     | 10 +---------
 drivers/gpu/drm/i915/display/intel_display.c | 14 ++++++++++----
 drivers/gpu/drm/i915/display/intel_dp_mst.c  |  4 ----
 3 files changed, 11 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 9bc916d36bd2..b170ebb387f8 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2498,8 +2498,6 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
 				    const struct drm_connector_state *conn_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
 	if (DISPLAY_VER(dev_priv) >= 12)
 		tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
@@ -2509,14 +2507,8 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
 	/* MST will call a setting of MSA after an allocating of Virtual Channel
 	 * from MST encoder pre_enable callback.
 	 */
-	if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
+	if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
 		intel_ddi_set_dp_msa(crtc_state, conn_state);
-
-		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
-					       &crtc_state->dp_m_n);
-		intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
-					       &crtc_state->dp_m2_n2);
-	}
 }
 
 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 602ea6d15628..50dbc2116c14 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2003,16 +2003,22 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
+	if (crtc_state->has_pch_encoder) {
+		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
+					       &crtc_state->fdi_m_n);
+	} else if (intel_crtc_has_dp_encoder(crtc_state)) {
+		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
+					       &crtc_state->dp_m_n);
+		intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
+					       &crtc_state->dp_m2_n2);
+	}
+
 	intel_set_transcoder_timings(crtc_state);
 
 	if (cpu_transcoder != TRANSCODER_EDP)
 		intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
 			       crtc_state->pixel_multiplier - 1);
 
-	if (crtc_state->has_pch_encoder)
-		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
-					       &crtc_state->fdi_m_n);
-
 	hsw_set_frame_start_delay(crtc_state);
 
 	hsw_set_transconf(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 95f9a5c03a47..6b6eab507d30 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -472,7 +472,6 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
 	struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 	struct intel_digital_port *dig_port = intel_mst->primary;
 	struct intel_dp *intel_dp = &dig_port->dp;
-	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_connector *connector =
 		to_intel_connector(conn_state->connector);
@@ -523,9 +522,6 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
 		intel_ddi_enable_pipe_clock(encoder, pipe_config);
 
 	intel_ddi_set_dp_msa(pipe_config, conn_state);
-
-	intel_cpu_transcoder_set_m1_n1(crtc, pipe_config->cpu_transcoder,
-				       &pipe_config->dp_m_n);
 }
 
 static void intel_mst_enable_dp(struct intel_atomic_state *state,
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [Intel-gfx] [PATCH 08/14] drm/i915: Extract {i9xx, ilk}_configure_cpu_transcoder()
  2022-01-27  9:32 [Intel-gfx] [PATCH 00/14] drm/i915: M/N cleanup Ville Syrjala
                   ` (6 preceding siblings ...)
  2022-01-27  9:32 ` [Intel-gfx] [PATCH 07/14] drm/i915: Move M/N setup to a more logical place on ddi platforms Ville Syrjala
@ 2022-01-27  9:32 ` Ville Syrjala
  2022-01-27  9:32 ` [Intel-gfx] [PATCH 09/14] drm/i915: Add fdi_m2_n2 Ville Syrjala
                   ` (9 subsequent siblings)
  17 siblings, 0 replies; 31+ messages in thread
From: Ville Syrjala @ 2022-01-27  9:32 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Follow the path laid out by hsw+ and extract helpers to configure
the cpu transcoder for earlier platforms as well.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 65 +++++++++++---------
 1 file changed, 35 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 50dbc2116c14..0a58ecf21b70 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1808,13 +1808,29 @@ static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_stat
 	plane->disable_arm(plane, crtc_state);
 }
 
+static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+	if (crtc_state->has_pch_encoder) {
+		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, &crtc_state->fdi_m_n);
+	} else if (intel_crtc_has_dp_encoder(crtc_state)) {
+		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n);
+		intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, &crtc_state->dp_m2_n2);
+	}
+
+	intel_set_transcoder_timings(crtc_state);
+
+	ilk_set_pipeconf(crtc_state);
+}
+
 static void ilk_crtc_enable(struct intel_atomic_state *state,
 			    struct intel_crtc *crtc)
 {
 	const struct intel_crtc_state *new_crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
 	enum pipe pipe = crtc->pipe;
 
 	if (drm_WARN_ON(&dev_priv->drm, crtc->active))
@@ -1833,21 +1849,10 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,
 	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
 	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
 
-	if (new_crtc_state->has_pch_encoder) {
-		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
-					       &new_crtc_state->fdi_m_n);
-	} else if (intel_crtc_has_dp_encoder(new_crtc_state)) {
-		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
-					       &new_crtc_state->dp_m_n);
-		intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
-					       &new_crtc_state->dp_m2_n2);
-	}
+	ilk_configure_cpu_transcoder(new_crtc_state);
 
-	intel_set_transcoder_timings(new_crtc_state);
 	intel_set_pipe_src_size(new_crtc_state);
 
-	ilk_set_pipeconf(new_crtc_state);
-
 	crtc->active = true;
 
 	intel_encoders_pre_enable(state, crtc);
@@ -2445,26 +2450,34 @@ static void modeset_put_crtc_power_domains(struct intel_crtc *crtc,
 					    domains);
 }
 
+static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+	if (intel_crtc_has_dp_encoder(crtc_state)) {
+		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n);
+		intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, &crtc_state->dp_m2_n2);
+	}
+
+	intel_set_transcoder_timings(crtc_state);
+
+	i9xx_set_pipeconf(crtc_state);
+}
+
 static void valleyview_crtc_enable(struct intel_atomic_state *state,
 				   struct intel_crtc *crtc)
 {
 	const struct intel_crtc_state *new_crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
 	enum pipe pipe = crtc->pipe;
 
 	if (drm_WARN_ON(&dev_priv->drm, crtc->active))
 		return;
 
-	if (intel_crtc_has_dp_encoder(new_crtc_state)) {
-		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
-					       &new_crtc_state->dp_m_n);
-		intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
-					       &new_crtc_state->dp_m2_n2);
-	}
+	i9xx_configure_cpu_transcoder(new_crtc_state);
 
-	intel_set_transcoder_timings(new_crtc_state);
 	intel_set_pipe_src_size(new_crtc_state);
 
 	if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
@@ -2472,8 +2485,6 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state,
 		intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
 	}
 
-	i9xx_set_pipeconf(new_crtc_state);
-
 	crtc->active = true;
 
 	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
@@ -2508,21 +2519,15 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,
 	const struct intel_crtc_state *new_crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
 	enum pipe pipe = crtc->pipe;
 
 	if (drm_WARN_ON(&dev_priv->drm, crtc->active))
 		return;
 
-	if (intel_crtc_has_dp_encoder(new_crtc_state))
-		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
-					       &new_crtc_state->dp_m_n);
+	i9xx_configure_cpu_transcoder(new_crtc_state);
 
-	intel_set_transcoder_timings(new_crtc_state);
 	intel_set_pipe_src_size(new_crtc_state);
 
-	i9xx_set_pipeconf(new_crtc_state);
-
 	crtc->active = true;
 
 	if (DISPLAY_VER(dev_priv) != 2)
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [Intel-gfx] [PATCH 09/14] drm/i915: Add fdi_m2_n2
  2022-01-27  9:32 [Intel-gfx] [PATCH 00/14] drm/i915: M/N cleanup Ville Syrjala
                   ` (7 preceding siblings ...)
  2022-01-27  9:32 ` [Intel-gfx] [PATCH 08/14] drm/i915: Extract {i9xx, ilk}_configure_cpu_transcoder() Ville Syrjala
@ 2022-01-27  9:32 ` Ville Syrjala
  2022-01-27  9:32 ` [Intel-gfx] [PATCH 10/14] drm/i915: Program FDI RX TUSIZE2 Ville Syrjala
                   ` (8 subsequent siblings)
  17 siblings, 0 replies; 31+ messages in thread
From: Ville Syrjala @ 2022-01-27  9:32 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We're going to need M2/N2 for FDI when doing refresh rate switching
with PCH ports. We'll start by setting to match the FDI M1/N1.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  | 19 +++++++++++++------
 drivers/gpu/drm/i915/display/intel_display.h  |  2 ++
 .../drm/i915/display/intel_display_types.h    |  2 +-
 drivers/gpu/drm/i915/display/intel_fdi.c      |  3 +++
 .../gpu/drm/i915/display/intel_pch_display.c  |  2 ++
 5 files changed, 21 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0a58ecf21b70..8b4d842e2ee0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1815,6 +1815,7 @@ static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta
 
 	if (crtc_state->has_pch_encoder) {
 		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, &crtc_state->fdi_m_n);
+		intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, &crtc_state->fdi_m2_n2);
 	} else if (intel_crtc_has_dp_encoder(crtc_state)) {
 		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n);
 		intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, &crtc_state->dp_m2_n2);
@@ -3143,8 +3144,8 @@ void intel_set_m_n(struct drm_i915_private *i915,
 	intel_de_write(i915, link_n_reg, m_n->link_n);
 }
 
-static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
-				 enum transcoder cpu_transcoder)
+bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
+				    enum transcoder cpu_transcoder)
 {
 	if (IS_HASWELL(dev_priv))
 		return cpu_transcoder == TRANSCODER_EDP;
@@ -3175,7 +3176,7 @@ void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
-	if (!transcoder_has_m2_n2(dev_priv, cpu_transcoder))
+	if (!intel_cpu_transcoder_has_m2_n2(dev_priv, cpu_transcoder))
 		return;
 
 	intel_set_m_n(dev_priv, m_n,
@@ -3873,7 +3874,7 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
-	if (!transcoder_has_m2_n2(dev_priv, cpu_transcoder))
+	if (!intel_cpu_transcoder_has_m2_n2(dev_priv, cpu_transcoder))
 		return;
 
 	intel_get_m_n(dev_priv, m_n,
@@ -5612,10 +5613,14 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
 		    pipe_config->splitter.link_count,
 		    pipe_config->splitter.pixel_overlap);
 
-	if (pipe_config->has_pch_encoder)
-		intel_dump_m_n_config(pipe_config, "fdi",
+	if (pipe_config->has_pch_encoder) {
+		intel_dump_m_n_config(pipe_config, "fdi m_n",
 				      pipe_config->fdi_lanes,
 				      &pipe_config->fdi_m_n);
+		intel_dump_m_n_config(pipe_config, "fdi m2_n2",
+				      pipe_config->fdi_lanes,
+				      &pipe_config->fdi_m2_n2);
+	}
 
 	if (intel_crtc_has_dp_encoder(pipe_config)) {
 		intel_dump_m_n_config(pipe_config, "dp m_n",
@@ -6467,6 +6472,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	PIPE_CONF_CHECK_BOOL(has_pch_encoder);
 	PIPE_CONF_CHECK_I(fdi_lanes);
 	PIPE_CONF_CHECK_M_N(fdi_m_n);
+	PIPE_CONF_CHECK_M_N(fdi_m2_n2);
 
 	PIPE_CONF_CHECK_I(lane_count);
 	PIPE_CONF_CHECK_X(lane_lat_optim_mask);
@@ -7375,6 +7381,7 @@ static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_stat
 	 * FIXME: should really copy more fuzzy state here
 	 */
 	new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n;
+	new_crtc_state->fdi_m2_n2 = old_crtc_state->fdi_m2_n2;
 	new_crtc_state->dp_m_n = old_crtc_state->dp_m_n;
 	new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2;
 	new_crtc_state->has_drrs = old_crtc_state->has_drrs;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index afa312e11624..71a27285cf99 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -575,6 +575,8 @@ void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
 				    enum transcoder cpu_transcoder,
 				    struct intel_link_m_n *m_n);
+bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
+				    enum transcoder cpu_transcoder);
 
 void intel_plane_destroy(struct drm_plane *plane);
 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 60e15226a8cb..4f29146b916e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1124,7 +1124,7 @@ struct intel_crtc_state {
 
 	/* FDI configuration, only valid if has_pch_encoder is set. */
 	int fdi_lanes;
-	struct intel_link_m_n fdi_m_n;
+	struct intel_link_m_n fdi_m_n, fdi_m2_n2;
 
 	bool ips_enabled;
 
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index 3d6e22923601..fdbeaf6f38f4 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -251,6 +251,9 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc,
 	intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
 			       link_bw, &pipe_config->fdi_m_n, false, false);
 
+	if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))
+		pipe_config->fdi_m2_n2 = pipe_config->fdi_m_n;
+
 	ret = ilk_check_fdi_lanes(dev, crtc->pipe, pipe_config);
 	if (ret == -EDEADLK)
 		return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 9192769e3337..69b8a4e77c71 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -436,6 +436,8 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
 
 	intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder,
 				       &crtc_state->fdi_m_n);
+	intel_cpu_transcoder_get_m2_n2(crtc, crtc_state->cpu_transcoder,
+				       &crtc_state->fdi_m2_n2);
 
 	if (HAS_PCH_IBX(dev_priv)) {
 		/*
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [Intel-gfx] [PATCH 10/14] drm/i915: Program FDI RX TUSIZE2
  2022-01-27  9:32 [Intel-gfx] [PATCH 00/14] drm/i915: M/N cleanup Ville Syrjala
                   ` (8 preceding siblings ...)
  2022-01-27  9:32 ` [Intel-gfx] [PATCH 09/14] drm/i915: Add fdi_m2_n2 Ville Syrjala
@ 2022-01-27  9:32 ` Ville Syrjala
  2022-01-27  9:33 ` [Intel-gfx] [PATCH 11/14] drm/i915: Dump dp_m2_n2 always Ville Syrjala
                   ` (7 subsequent siblings)
  17 siblings, 0 replies; 31+ messages in thread
From: Ville Syrjala @ 2022-01-27  9:32 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

When using the refresh rate swithching with FDI we must program
RXTUSIZE2 in addition to RXTUSIZE1.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_fdi.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index fdbeaf6f38f4..4b634c1d2837 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -381,6 +381,8 @@ static void ilk_fdi_link_train(struct intel_crtc *crtc,
 	 */
 	intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe),
 		       intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
+	intel_de_write(dev_priv, FDI_RX_TUSIZE2(pipe),
+		       intel_de_read(dev_priv, PIPE_DATA_M2(pipe)) & TU_SIZE_MASK);
 
 	/* FDI needs bits from pipe first */
 	assert_transcoder_enabled(dev_priv, crtc_state->cpu_transcoder);
@@ -491,6 +493,8 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc,
 	 */
 	intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe),
 		       intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
+	intel_de_write(dev_priv, FDI_RX_TUSIZE2(pipe),
+		       intel_de_read(dev_priv, PIPE_DATA_M2(pipe)) & TU_SIZE_MASK);
 
 	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
 	   for train result */
@@ -637,6 +641,8 @@ static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
 	 */
 	intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe),
 		       intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
+	intel_de_write(dev_priv, FDI_RX_TUSIZE2(pipe),
+		       intel_de_read(dev_priv, PIPE_DATA_M2(pipe)) & TU_SIZE_MASK);
 
 	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
 	   for train result */
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [Intel-gfx] [PATCH 11/14] drm/i915: Dump dp_m2_n2 always
  2022-01-27  9:32 [Intel-gfx] [PATCH 00/14] drm/i915: M/N cleanup Ville Syrjala
                   ` (9 preceding siblings ...)
  2022-01-27  9:32 ` [Intel-gfx] [PATCH 10/14] drm/i915: Program FDI RX TUSIZE2 Ville Syrjala
@ 2022-01-27  9:33 ` Ville Syrjala
  2022-01-27  9:33 ` [Intel-gfx] [PATCH 12/14] drm/i915: Extract can_enable_drrs() Ville Syrjala
                   ` (6 subsequent siblings)
  17 siblings, 0 replies; 31+ messages in thread
From: Ville Syrjala @ 2022-01-27  9:33 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

No point in special casing the dp_m2_n2 dumping. Just do it always.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 8b4d842e2ee0..93bb4f577960 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5624,11 +5624,11 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
 
 	if (intel_crtc_has_dp_encoder(pipe_config)) {
 		intel_dump_m_n_config(pipe_config, "dp m_n",
-				pipe_config->lane_count, &pipe_config->dp_m_n);
-		if (pipe_config->has_drrs)
-			intel_dump_m_n_config(pipe_config, "dp m2_n2",
-					      pipe_config->lane_count,
-					      &pipe_config->dp_m2_n2);
+				      pipe_config->lane_count,
+				      &pipe_config->dp_m_n);
+		intel_dump_m_n_config(pipe_config, "dp m2_n2",
+				      pipe_config->lane_count,
+				      &pipe_config->dp_m2_n2);
 	}
 
 	drm_dbg_kms(&dev_priv->drm,
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [Intel-gfx] [PATCH 12/14] drm/i915: Extract can_enable_drrs()
  2022-01-27  9:32 [Intel-gfx] [PATCH 00/14] drm/i915: M/N cleanup Ville Syrjala
                   ` (10 preceding siblings ...)
  2022-01-27  9:33 ` [Intel-gfx] [PATCH 11/14] drm/i915: Dump dp_m2_n2 always Ville Syrjala
@ 2022-01-27  9:33 ` Ville Syrjala
  2022-01-27  9:33 ` [Intel-gfx] [PATCH 13/14] drm/i915: Set DP M2/N2 equal to M1/N1 when not doing DRRS Ville Syrjala
                   ` (5 subsequent siblings)
  17 siblings, 0 replies; 31+ messages in thread
From: Ville Syrjala @ 2022-01-27  9:33 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Pull the "can we do DRRS?" check into helper in order
to reduce the clutter in intel_drrs_compute_config().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_drrs.c | 31 ++++++++++++++---------
 1 file changed, 19 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c
index 53f014b4436b..c46fcf1e7596 100644
--- a/drivers/gpu/drm/i915/display/intel_drrs.c
+++ b/drivers/gpu/drm/i915/display/intel_drrs.c
@@ -47,17 +47,13 @@
  * requested by userspace.
  */
 
-void
-intel_drrs_compute_config(struct intel_dp *intel_dp,
-			  struct intel_crtc_state *pipe_config,
-			  int output_bpp, bool constant_n)
+static bool can_enable_drrs(struct intel_connector *connector,
+			    const struct intel_crtc_state *pipe_config)
 {
-	struct intel_connector *intel_connector = intel_dp->attached_connector;
-	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-	int pixel_clock;
+	const struct drm_i915_private *i915 = to_i915(connector->base.dev);
 
 	if (pipe_config->vrr.enable)
-		return;
+		return false;
 
 	/*
 	 * DRRS and PSR can't be enable together, so giving preference to PSR
@@ -66,15 +62,26 @@ intel_drrs_compute_config(struct intel_dp *intel_dp,
 	 * after intel_psr_compute_config().
 	 */
 	if (pipe_config->has_psr)
-		return;
+		return false;
 
-	if (!intel_connector->panel.downclock_mode ||
-	    dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
+	return connector->panel.downclock_mode &&
+		i915->drrs.type == SEAMLESS_DRRS_SUPPORT;
+}
+
+void
+intel_drrs_compute_config(struct intel_dp *intel_dp,
+			  struct intel_crtc_state *pipe_config,
+			  int output_bpp, bool constant_n)
+{
+	struct intel_connector *connector = intel_dp->attached_connector;
+	int pixel_clock;
+
+	if (!can_enable_drrs(connector, pipe_config))
 		return;
 
 	pipe_config->has_drrs = true;
 
-	pixel_clock = intel_connector->panel.downclock_mode->clock;
+	pixel_clock = connector->panel.downclock_mode->clock;
 	if (pipe_config->splitter.enable)
 		pixel_clock /= pipe_config->splitter.link_count;
 
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [Intel-gfx] [PATCH 13/14] drm/i915: Set DP M2/N2 equal to M1/N1 when not doing DRRS
  2022-01-27  9:32 [Intel-gfx] [PATCH 00/14] drm/i915: M/N cleanup Ville Syrjala
                   ` (11 preceding siblings ...)
  2022-01-27  9:33 ` [Intel-gfx] [PATCH 12/14] drm/i915: Extract can_enable_drrs() Ville Syrjala
@ 2022-01-27  9:33 ` Ville Syrjala
  2022-01-27  9:33 ` [Intel-gfx] [PATCH 14/14] drm/i915: Always check dp_m2_n2 on pre-bdw Ville Syrjala
                   ` (4 subsequent siblings)
  17 siblings, 0 replies; 31+ messages in thread
From: Ville Syrjala @ 2022-01-27  9:33 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Make life simpler by always programming DP M2/N2.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_drrs.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c
index c46fcf1e7596..27d0fbf0372e 100644
--- a/drivers/gpu/drm/i915/display/intel_drrs.c
+++ b/drivers/gpu/drm/i915/display/intel_drrs.c
@@ -74,10 +74,14 @@ intel_drrs_compute_config(struct intel_dp *intel_dp,
 			  int output_bpp, bool constant_n)
 {
 	struct intel_connector *connector = intel_dp->attached_connector;
+	struct drm_i915_private *i915 = to_i915(connector->base.dev);
 	int pixel_clock;
 
-	if (!can_enable_drrs(connector, pipe_config))
+	if (!can_enable_drrs(connector, pipe_config)) {
+		if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))
+			pipe_config->dp_m2_n2 = pipe_config->dp_m_n;
 		return;
+	}
 
 	pipe_config->has_drrs = true;
 
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [Intel-gfx] [PATCH 14/14] drm/i915: Always check dp_m2_n2 on pre-bdw
  2022-01-27  9:32 [Intel-gfx] [PATCH 00/14] drm/i915: M/N cleanup Ville Syrjala
                   ` (12 preceding siblings ...)
  2022-01-27  9:33 ` [Intel-gfx] [PATCH 13/14] drm/i915: Set DP M2/N2 equal to M1/N1 when not doing DRRS Ville Syrjala
@ 2022-01-27  9:33 ` Ville Syrjala
  2022-01-27 11:01 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: M/N cleanup Patchwork
                   ` (3 subsequent siblings)
  17 siblings, 0 replies; 31+ messages in thread
From: Ville Syrjala @ 2022-01-27  9:33 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

No point in special casing the check of dp_m2_n2 on pre-bdw platforms.
Either the transcoder has M2/N2 in which case the values should be
set to something sensible, or it doesn't in which case dp_m2_n2 is
always zeroed.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 93bb4f577960..4464beb2ce68 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6477,13 +6477,12 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	PIPE_CONF_CHECK_I(lane_count);
 	PIPE_CONF_CHECK_X(lane_lat_optim_mask);
 
-	if (DISPLAY_VER(dev_priv) < 8) {
-		PIPE_CONF_CHECK_M_N(dp_m_n);
-
-		if (current_config->has_drrs)
-			PIPE_CONF_CHECK_M_N(dp_m2_n2);
-	} else
+	if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) {
 		PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
+	} else {
+		PIPE_CONF_CHECK_M_N(dp_m_n);
+		PIPE_CONF_CHECK_M_N(dp_m2_n2);
+	}
 
 	PIPE_CONF_CHECK_X(output_types);
 
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 31+ messages in thread

* [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: M/N cleanup
  2022-01-27  9:32 [Intel-gfx] [PATCH 00/14] drm/i915: M/N cleanup Ville Syrjala
                   ` (13 preceding siblings ...)
  2022-01-27  9:33 ` [Intel-gfx] [PATCH 14/14] drm/i915: Always check dp_m2_n2 on pre-bdw Ville Syrjala
@ 2022-01-27 11:01 ` Patchwork
  2022-01-27 14:43 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: M/N cleanup (rev2) Patchwork
                   ` (2 subsequent siblings)
  17 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2022-01-27 11:01 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: M/N cleanup
URL   : https://patchwork.freedesktop.org/series/99409/
State : failure

== Summary ==

CALL    scripts/checksyscalls.sh
  CALL    scripts/atomic/check-atomics.sh
  DESCEND objtool
  CHK     include/generated/compile.h
  CC [M]  drivers/gpu/drm/i915/gvt/display.o
drivers/gpu/drm/i915/gvt/display.c: In function ‘emulate_monitor_status_change’:
drivers/gpu/drm/i915/gvt/display.c:256:57: error: ‘TU_SIZE_SHIFT’ undeclared (first use in this function); did you mean ‘TV_XSIZE_SHIFT’?
   vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT;
                                                         ^~~~~~~~~~~~~
                                                         TV_XSIZE_SHIFT
drivers/gpu/drm/i915/gvt/display.c:256:57: note: each undeclared identifier is reported only once for each function it appears in
scripts/Makefile.build:288: recipe for target 'drivers/gpu/drm/i915/gvt/display.o' failed
make[4]: *** [drivers/gpu/drm/i915/gvt/display.o] Error 1
scripts/Makefile.build:550: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:550: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:550: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1831: recipe for target 'drivers' failed
make: *** [drivers] Error 2



^ permalink raw reply	[flat|nested] 31+ messages in thread

* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: M/N cleanup (rev2)
  2022-01-27  9:32 [Intel-gfx] [PATCH 00/14] drm/i915: M/N cleanup Ville Syrjala
                   ` (14 preceding siblings ...)
  2022-01-27 11:01 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: M/N cleanup Patchwork
@ 2022-01-27 14:43 ` Patchwork
  2022-01-27 15:13 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
  2022-01-27 19:55 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
  17 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2022-01-27 14:43 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: M/N cleanup (rev2)
URL   : https://patchwork.freedesktop.org/series/99409/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.



^ permalink raw reply	[flat|nested] 31+ messages in thread

* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: M/N cleanup (rev2)
  2022-01-27  9:32 [Intel-gfx] [PATCH 00/14] drm/i915: M/N cleanup Ville Syrjala
                   ` (15 preceding siblings ...)
  2022-01-27 14:43 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: M/N cleanup (rev2) Patchwork
@ 2022-01-27 15:13 ` Patchwork
  2022-01-27 19:55 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
  17 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2022-01-27 15:13 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

[-- Attachment #1: Type: text/plain, Size: 5503 bytes --]

== Series Details ==

Series: drm/i915: M/N cleanup (rev2)
URL   : https://patchwork.freedesktop.org/series/99409/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11151 -> Patchwork_22126
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/index.html

Participating hosts (46 -> 41)
------------------------------

  Additional (1): fi-icl-u2 
  Missing    (6): bat-adls-5 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-pnv-d510 fi-bdw-samus 

Known issues
------------

  Here are the changes found in Patchwork_22126 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_cs_nop@fork-gfx0:
    - fi-icl-u2:          NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/fi-icl-u2/igt@amdgpu/amd_cs_nop@fork-gfx0.html

  * igt@debugfs_test@read_all_entries:
    - fi-kbl-soraka:      [PASS][2] -> [DMESG-WARN][3] ([i915#1982] / [i915#262])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/fi-kbl-soraka/igt@debugfs_test@read_all_entries.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/fi-kbl-soraka/igt@debugfs_test@read_all_entries.html

  * igt@gem_huc_copy@huc-copy:
    - fi-icl-u2:          NOTRUN -> [SKIP][4] ([i915#2190])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/fi-icl-u2/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - fi-icl-u2:          NOTRUN -> [SKIP][5] ([i915#4613]) +3 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/fi-icl-u2/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-icl-u2:          NOTRUN -> [SKIP][6] ([fdo#111827]) +8 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - fi-icl-u2:          NOTRUN -> [SKIP][7] ([fdo#109278]) +2 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_force_connector_basic@force-load-detect:
    - fi-icl-u2:          NOTRUN -> [SKIP][8] ([fdo#109285])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/fi-icl-u2/igt@kms_force_connector_basic@force-load-detect.html

  * igt@prime_vgem@basic-userptr:
    - fi-icl-u2:          NOTRUN -> [SKIP][9] ([i915#3301])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/fi-icl-u2/igt@prime_vgem@basic-userptr.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@hangcheck:
    - bat-dg1-5:          [DMESG-FAIL][10] ([i915#4957]) -> [PASS][11]
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
    - bat-dg1-6:          [DMESG-FAIL][12] ([i915#4494] / [i915#4957]) -> [PASS][13]
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/bat-dg1-6/igt@i915_selftest@live@hangcheck.html

  
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957


Build changes
-------------

  * Linux: CI_DRM_11151 -> Patchwork_22126

  CI-20190529: 20190529
  CI_DRM_11151: 627e2885b51ab503a98aa89f0a0bd68416c731fc @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6336: ae2eb9e18bc58a4c45f28cfd80962938198dec3c @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_22126: 3e76fda4145c87cdb50479a1dcce612dd06af4b9 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

3e76fda4145c drm/i915: Always check dp_m2_n2 on pre-bdw
d89ddd51579a drm/i915: Set DP M2/N2 equal to M1/N1 when not doing DRRS
1903fafd4880 drm/i915: Extract can_enable_drrs()
79a7f565dc7f drm/i915: Dump dp_m2_n2 always
bd6c4321ad8a drm/i915: Program FDI RX TUSIZE2
f0bc3753acef drm/i915: Add fdi_m2_n2
8d6349a876d0 drm/i915: Extract {i9xx, ilk}_configure_cpu_transcoder()
952ca77dbfcb drm/i915: Move M/N setup to a more logical place on ddi platforms
702da3bc0023 drm/i915: Move PCH transcoder M/N setup into the PCH code
3e9f7cc66785 drm/i915: Make M/N set/get a bit more direct
a3e9f651ff61 drm/i915: Move drrs hardware bit frobbing to small helpers
2b9648f102a5 drm/i915: s/gmch_{m,n}/data_{m,n}/
1b16d116de26 drm/i915: Clean up M/N register defines
6e8d396dc4af drm/i915: Extract intel_{get,set}_m_n()

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/index.html

[-- Attachment #2: Type: text/html, Size: 6501 bytes --]

^ permalink raw reply	[flat|nested] 31+ messages in thread

* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: M/N cleanup (rev2)
  2022-01-27  9:32 [Intel-gfx] [PATCH 00/14] drm/i915: M/N cleanup Ville Syrjala
                   ` (16 preceding siblings ...)
  2022-01-27 15:13 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-01-27 19:55 ` Patchwork
  17 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2022-01-27 19:55 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx

[-- Attachment #1: Type: text/plain, Size: 30244 bytes --]

== Series Details ==

Series: drm/i915: M/N cleanup (rev2)
URL   : https://patchwork.freedesktop.org/series/99409/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11151_full -> Patchwork_22126_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_22126_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22126_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_22126_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_flip@busy-flip@b-edp1:
    - shard-skl:          [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-skl7/igt@kms_flip@busy-flip@b-edp1.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-skl7/igt@kms_flip@busy-flip@b-edp1.html

  
Known issues
------------

  Here are the changes found in Patchwork_22126_full that come from known issues:

### CI changes ###

#### Possible fixes ####

  * boot:
    - shard-apl:          ([PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [FAIL][24], [PASS][25], [PASS][26], [PASS][27]) ([i915#4386]) -> ([PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-apl2/boot.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-apl3/boot.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-apl3/boot.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-apl3/boot.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-apl4/boot.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-apl4/boot.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-apl4/boot.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-apl6/boot.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-apl6/boot.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-apl6/boot.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-apl6/boot.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-apl7/boot.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-apl2/boot.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-apl2/boot.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-apl2/boot.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-apl7/boot.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-apl7/boot.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-apl8/boot.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-apl1/boot.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-apl1/boot.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-apl8/boot.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-apl1/boot.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-apl1/boot.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-apl8/boot.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-apl8/boot.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl8/boot.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl8/boot.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl1/boot.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl1/boot.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl1/boot.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl2/boot.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl2/boot.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl2/boot.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl2/boot.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl3/boot.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl3/boot.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl3/boot.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl3/boot.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl4/boot.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl4/boot.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl4/boot.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl4/boot.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl6/boot.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl6/boot.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl6/boot.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl7/boot.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl7/boot.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl7/boot.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl8/boot.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl8/boot.html

  

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@preservation-s3@vecs0:
    - shard-skl:          [PASS][53] -> [INCOMPLETE][54] ([i915#4939])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-skl6/igt@gem_ctx_isolation@preservation-s3@vecs0.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-skl7/igt@gem_ctx_isolation@preservation-s3@vecs0.html

  * igt@gem_ctx_sseu@invalid-args:
    - shard-tglb:         NOTRUN -> [SKIP][55] ([i915#280])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-tglb2/igt@gem_ctx_sseu@invalid-args.html

  * igt@gem_exec_balancer@parallel-keep-submit-fence:
    - shard-iclb:         [PASS][56] -> [SKIP][57] ([i915#4525])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-iclb1/igt@gem_exec_balancer@parallel-keep-submit-fence.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-iclb3/igt@gem_exec_balancer@parallel-keep-submit-fence.html

  * igt@gem_exec_capture@pi@bcs0:
    - shard-skl:          NOTRUN -> [INCOMPLETE][58] ([i915#4547])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-skl6/igt@gem_exec_capture@pi@bcs0.html

  * igt@gem_exec_fair@basic-none@vecs0:
    - shard-apl:          [PASS][59] -> [FAIL][60] ([i915#2842])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-apl6/igt@gem_exec_fair@basic-none@vecs0.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl4/igt@gem_exec_fair@basic-none@vecs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-tglb:         NOTRUN -> [FAIL][61] ([i915#2842])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-tglb2/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_exec_fair@basic-pace@rcs0:
    - shard-glk:          [PASS][62] -> [FAIL][63] ([i915#2842])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-glk6/igt@gem_exec_fair@basic-pace@rcs0.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-glk9/igt@gem_exec_fair@basic-pace@rcs0.html

  * igt@gem_exec_schedule@submit-golden-slice@bcs0:
    - shard-tglb:         [PASS][64] -> [INCOMPLETE][65] ([i915#3797])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-tglb1/igt@gem_exec_schedule@submit-golden-slice@bcs0.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-tglb7/igt@gem_exec_schedule@submit-golden-slice@bcs0.html

  * igt@gem_exec_whisper@basic-queues-priority-all:
    - shard-glk:          [PASS][66] -> [DMESG-WARN][67] ([i915#118])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-glk9/igt@gem_exec_whisper@basic-queues-priority-all.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-glk7/igt@gem_exec_whisper@basic-queues-priority-all.html

  * igt@gem_lmem_swapping@heavy-random:
    - shard-skl:          NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#4613])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-skl8/igt@gem_lmem_swapping@heavy-random.html

  * igt@gem_lmem_swapping@random:
    - shard-apl:          NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#4613]) +1 similar issue
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl1/igt@gem_lmem_swapping@random.html

  * igt@gem_pread@exhaustion:
    - shard-skl:          NOTRUN -> [WARN][70] ([i915#2658])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-skl8/igt@gem_pread@exhaustion.html

  * igt@gem_userptr_blits@access-control:
    - shard-iclb:         NOTRUN -> [SKIP][71] ([i915#3297])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-iclb3/igt@gem_userptr_blits@access-control.html

  * igt@gem_userptr_blits@input-checking:
    - shard-skl:          NOTRUN -> [DMESG-WARN][72] ([i915#4990])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-skl4/igt@gem_userptr_blits@input-checking.html

  * igt@i915_pm_dc@dc9-dpms:
    - shard-iclb:         [PASS][73] -> [SKIP][74] ([i915#4281])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-iclb4/igt@i915_pm_dc@dc9-dpms.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html

  * igt@i915_selftest@live@hangcheck:
    - shard-snb:          [PASS][75] -> [INCOMPLETE][76] ([i915#3921])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-snb7/igt@i915_selftest@live@hangcheck.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-snb7/igt@i915_selftest@live@hangcheck.html

  * igt@kms_big_fb@linear-16bpp-rotate-90:
    - shard-tglb:         NOTRUN -> [SKIP][77] ([fdo#111614])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-tglb2/igt@kms_big_fb@linear-16bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-apl:          NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#3777])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl1/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@yf-tiled-64bpp-rotate-270:
    - shard-tglb:         NOTRUN -> [SKIP][79] ([fdo#111615])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-tglb2/igt@kms_big_fb@yf-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-64bpp-rotate-90:
    - shard-iclb:         NOTRUN -> [SKIP][80] ([fdo#110723])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-iclb3/igt@kms_big_fb@yf-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
    - shard-apl:          NOTRUN -> [SKIP][81] ([fdo#109271]) +91 similar issues
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl1/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html

  * igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_mc_ccs:
    - shard-iclb:         NOTRUN -> [SKIP][82] ([fdo#109278] / [i915#3886])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-iclb3/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs:
    - shard-skl:          NOTRUN -> [SKIP][83] ([fdo#109271] / [i915#3886]) +3 similar issues
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-skl8/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
    - shard-apl:          NOTRUN -> [SKIP][84] ([fdo#109271] / [i915#3886]) +1 similar issue
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl1/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html

  * igt@kms_chamelium@dp-crc-single:
    - shard-iclb:         NOTRUN -> [SKIP][85] ([fdo#109284] / [fdo#111827])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-iclb3/igt@kms_chamelium@dp-crc-single.html

  * igt@kms_chamelium@dp-mode-timings:
    - shard-apl:          NOTRUN -> [SKIP][86] ([fdo#109271] / [fdo#111827]) +5 similar issues
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl1/igt@kms_chamelium@dp-mode-timings.html

  * igt@kms_chamelium@hdmi-crc-multiple:
    - shard-tglb:         NOTRUN -> [SKIP][87] ([fdo#109284] / [fdo#111827])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-tglb2/igt@kms_chamelium@hdmi-crc-multiple.html

  * igt@kms_color_chamelium@pipe-b-ctm-0-25:
    - shard-skl:          NOTRUN -> [SKIP][88] ([fdo#109271] / [fdo#111827]) +6 similar issues
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-skl4/igt@kms_color_chamelium@pipe-b-ctm-0-25.html

  * igt@kms_content_protection@legacy:
    - shard-apl:          NOTRUN -> [TIMEOUT][89] ([i915#1319])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl1/igt@kms_content_protection@legacy.html

  * igt@kms_content_protection@lic:
    - shard-tglb:         NOTRUN -> [SKIP][90] ([i915#1063])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-tglb2/igt@kms_content_protection@lic.html

  * igt@kms_cursor_crc@pipe-a-cursor-max-size-offscreen:
    - shard-tglb:         NOTRUN -> [SKIP][91] ([i915#3359]) +1 similar issue
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-tglb2/igt@kms_cursor_crc@pipe-a-cursor-max-size-offscreen.html

  * igt@kms_cursor_crc@pipe-c-cursor-32x32-random:
    - shard-iclb:         NOTRUN -> [SKIP][92] ([fdo#109278])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-iclb3/igt@kms_cursor_crc@pipe-c-cursor-32x32-random.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
    - shard-tglb:         NOTRUN -> [SKIP][93] ([fdo#109274] / [fdo#111825])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-tglb2/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html

  * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ac-hdmi-a1-hdmi-a2:
    - shard-glk:          [PASS][94] -> [FAIL][95] ([i915#2122])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-glk7/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ac-hdmi-a1-hdmi-a2.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-glk2/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ac-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1:
    - shard-apl:          [PASS][96] -> [FAIL][97] ([i915#79])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-apl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-skl:          [PASS][98] -> [FAIL][99] ([i915#79]) +1 similar issue
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-skl1/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-skl1/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
    - shard-skl:          [PASS][100] -> [FAIL][101] ([i915#2122])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-skl10/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-skl8/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-render:
    - shard-tglb:         NOTRUN -> [SKIP][102] ([fdo#109280] / [fdo#111825]) +1 similar issue
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
    - shard-skl:          NOTRUN -> [SKIP][103] ([fdo#109271]) +76 similar issues
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-skl4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - shard-skl:          NOTRUN -> [SKIP][104] ([fdo#109271] / [i915#533])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-skl8/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_plane@pixel-format-source-clamping@pipe-a-planes:
    - shard-skl:          [PASS][105] -> [DMESG-WARN][106] ([i915#1982])
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-skl6/igt@kms_plane@pixel-format-source-clamping@pipe-a-planes.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-skl7/igt@kms_plane@pixel-format-source-clamping@pipe-a-planes.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
    - shard-apl:          [PASS][107] -> [DMESG-WARN][108] ([i915#180]) +1 similar issue
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-apl2/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl8/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [PASS][109] -> [FAIL][110] ([fdo#108145] / [i915#265])
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
    - shard-skl:          NOTRUN -> [FAIL][111] ([fdo#108145] / [i915#265]) +1 similar issue
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
    - shard-apl:          NOTRUN -> [FAIL][112] ([fdo#108145] / [i915#265])
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl1/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html

  * igt@kms_psr@psr2_sprite_blt:
    - shard-iclb:         [PASS][113] -> [SKIP][114] ([fdo#109441])
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-iclb8/igt@kms_psr@psr2_sprite_blt.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-apl:          NOTRUN -> [DMESG-WARN][115] ([i915#180] / [i915#295])
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  * igt@kms_vblank@pipe-d-wait-idle:
    - shard-apl:          NOTRUN -> [SKIP][116] ([fdo#109271] / [i915#533]) +1 similar issue
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl1/igt@kms_vblank@pipe-d-wait-idle.html

  * igt@perf@per-context-mode-unprivileged:
    - shard-tglb:         NOTRUN -> [SKIP][117] ([fdo#109289])
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-tglb2/igt@perf@per-context-mode-unprivileged.html

  * igt@perf@polling-parameterized:
    - shard-skl:          [PASS][118] -> [FAIL][119] ([i915#1542])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-skl6/igt@perf@polling-parameterized.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-skl4/igt@perf@polling-parameterized.html

  * igt@prime_nv_pcopy@test3_3:
    - shard-tglb:         NOTRUN -> [SKIP][120] ([fdo#109291])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-tglb2/igt@prime_nv_pcopy@test3_3.html

  * igt@prime_vgem@coherency-gtt:
    - shard-iclb:         NOTRUN -> [SKIP][121] ([fdo#109292])
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-iclb3/igt@prime_vgem@coherency-gtt.html

  * igt@sysfs_clients@recycle-many:
    - shard-apl:          NOTRUN -> [SKIP][122] ([fdo#109271] / [i915#2994])
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl1/igt@sysfs_clients@recycle-many.html

  * igt@sysfs_clients@split-10:
    - shard-skl:          NOTRUN -> [SKIP][123] ([fdo#109271] / [i915#2994])
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-skl8/igt@sysfs_clients@split-10.html

  
#### Possible fixes ####

  * igt@gem_exec_balancer@parallel:
    - shard-iclb:         [SKIP][124] ([i915#4525]) -> [PASS][125]
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-iclb6/igt@gem_exec_balancer@parallel.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-iclb1/igt@gem_exec_balancer@parallel.html

  * igt@gem_exec_capture@pi@rcs0:
    - shard-skl:          [INCOMPLETE][126] ([i915#4547]) -> [PASS][127]
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-skl8/igt@gem_exec_capture@pi@rcs0.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-skl6/igt@gem_exec_capture@pi@rcs0.html

  * igt@gem_exec_endless@dispatch@vcs0:
    - shard-tglb:         [INCOMPLETE][128] ([i915#3778]) -> [PASS][129]
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-tglb5/igt@gem_exec_endless@dispatch@vcs0.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-tglb8/igt@gem_exec_endless@dispatch@vcs0.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-tglb:         [FAIL][130] ([i915#2842]) -> [PASS][131] +1 similar issue
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-tglb3/igt@gem_exec_fair@basic-none-solo@rcs0.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-tglb6/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs0:
    - shard-kbl:          [FAIL][132] ([i915#2842]) -> [PASS][133]
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-kbl7/igt@gem_exec_fair@basic-none@vcs0.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-kbl6/igt@gem_exec_fair@basic-none@vcs0.html
    - shard-apl:          [FAIL][134] ([i915#2842]) -> [PASS][135]
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-apl6/igt@gem_exec_fair@basic-none@vcs0.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl4/igt@gem_exec_fair@basic-none@vcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-glk:          [FAIL][136] ([i915#2842]) -> [PASS][137] +1 similar issue
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-glk9/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-glk9/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace@bcs0:
    - shard-iclb:         [FAIL][138] ([i915#2842]) -> [PASS][139]
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-iclb5/igt@gem_exec_fair@basic-pace@bcs0.html
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-iclb5/igt@gem_exec_fair@basic-pace@bcs0.html

  * igt@gem_exec_schedule@smoketest@vecs0:
    - shard-skl:          [DMESG-WARN][140] ([i915#1982]) -> [PASS][141]
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-skl1/igt@gem_exec_schedule@smoketest@vecs0.html
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-skl1/igt@gem_exec_schedule@smoketest@vecs0.html

  * igt@gem_ppgtt@flink-and-close-vma-leak:
    - shard-apl:          [FAIL][142] ([i915#644]) -> [PASS][143]
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-apl4/igt@gem_ppgtt@flink-and-close-vma-leak.html
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl3/igt@gem_ppgtt@flink-and-close-vma-leak.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-iclb:         [FAIL][144] ([i915#454]) -> [PASS][145]
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-iclb4/igt@i915_pm_dc@dc6-psr.html
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-iclb8/igt@i915_pm_dc@dc6-psr.html

  * igt@i915_suspend@fence-restore-untiled:
    - shard-apl:          [DMESG-WARN][146] ([i915#180]) -> [PASS][147] +1 similar issue
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-apl3/igt@i915_suspend@fence-restore-untiled.html
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-apl1/igt@i915_suspend@fence-restore-untiled.html

  * igt@kms_cursor_crc@pipe-a-cursor-suspend:
    - shard-skl:          [INCOMPLETE][148] ([i915#2828] / [i915#300]) -> [PASS][149]
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-skl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-skl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling:
    - shard-iclb:         [SKIP][150] ([i915#3701]) -> [PASS][151]
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-iclb8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
    - shard-skl:          [FAIL][152] ([fdo#108145] / [i915#265]) -> [PASS][153]
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html

  * igt@kms_psr@psr2_sprite_mmap_cpu:
    - shard-iclb:         [SKIP][154] ([fdo#109441]) -> [PASS][155]
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-iclb8/igt@kms_psr@psr2_sprite_mmap_cpu.html
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_cpu.html

  
#### Warnings ####

  * igt@gem_eio@unwedge-stress:
    - shard-tglb:         [FAIL][156] ([i915#232]) -> [TIMEOUT][157] ([i915#3063] / [i915#3648])
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-tglb1/igt@gem_eio@unwedge-stress.html
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-tglb7/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_balancer@parallel-ordering:
    - shard-iclb:         [SKIP][158] ([i915#4525]) -> [FAIL][159] ([i915#4916])
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-iclb6/igt@gem_exec_balancer@parallel-ordering.html
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-iclb1/igt@gem_exec_balancer@parallel-ordering.html

  * igt@gem_exec_fair@basic-pace@rcs0:
    - shard-kbl:          [FAIL][160] ([i915#2842]) -> [FAIL][161] ([i915#2851])
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-kbl3/igt@gem_exec_fair@basic-pace@rcs0.html
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-kbl1/igt@gem_exec_fair@basic-pace@rcs0.html

  * igt@i915_pm_dc@dc3co-vpb-simulation:
    - shard-iclb:         [SKIP][162] ([i915#588]) -> [SKIP][163] ([i915#658])
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-iclb8/igt@i915_pm_dc@dc3co-vpb-simulation.html

  * igt@i915_pm_rc6_residency@rc6-idle:
    - shard-iclb:         [WARN][164] ([i915#1804] / [i915#2684]) -> [WARN][165] ([i915#2684])
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-iclb4/igt@i915_pm_rc6_residency@rc6-idle.html
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-iclb8/igt@i915_pm_rc6_residency@rc6-idle.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-skl:          [FAIL][166] ([i915#1188]) -> [INCOMPLETE][167] ([i915#2828])
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-skl9/igt@kms_hdr@bpc-switch-suspend.html
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-skl6/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
    - shard-iclb:         [SKIP][168] ([i915#2920]) -> [SKIP][169] ([fdo#111068] / [i915#658])
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11151/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/shard-iclb8/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22126/index.html

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^ permalink raw reply	[flat|nested] 31+ messages in thread

end of thread, other threads:[~2022-01-27 19:55 UTC | newest]

Thread overview: 31+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-01-27  9:32 [Intel-gfx] [PATCH 00/14] drm/i915: M/N cleanup Ville Syrjala
2022-01-27  9:32 ` [Intel-gfx] [PATCH 01/14] drm/i915: Extract intel_{get,set}_m_n() Ville Syrjala
2022-01-27 11:11   ` [Intel-gfx] [PATCH 01/14] drm/i915: Extract intel_{get, set}_m_n() Jani Nikula
2022-01-27  9:32 ` [Intel-gfx] [PATCH 02/14] drm/i915: Clean up M/N register defines Ville Syrjala
2022-01-27 11:17   ` Jani Nikula
2022-01-27 11:32     ` Ville Syrjälä
2022-01-27 11:41       ` Jani Nikula
2022-01-27 12:02   ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2022-01-27 17:36   ` [Intel-gfx] [PATCH " kernel test robot
2022-01-27 17:36     ` kernel test robot
2022-01-27  9:32 ` [Intel-gfx] [PATCH 03/14] drm/i915: s/gmch_{m,n}/data_{m,n}/ Ville Syrjala
2022-01-27 11:18   ` Jani Nikula
2022-01-27  9:32 ` [Intel-gfx] [PATCH 04/14] drm/i915: Move drrs hardware bit frobbing to small helpers Ville Syrjala
2022-01-27 11:23   ` Jani Nikula
2022-01-27 11:24     ` Jani Nikula
2022-01-27 11:35       ` Ville Syrjälä
2022-01-27 11:42         ` Jani Nikula
2022-01-27  9:32 ` [Intel-gfx] [PATCH 05/14] drm/i915: Make M/N set/get a bit more direct Ville Syrjala
2022-01-27  9:32 ` [Intel-gfx] [PATCH 06/14] drm/i915: Move PCH transcoder M/N setup into the PCH code Ville Syrjala
2022-01-27  9:32 ` [Intel-gfx] [PATCH 07/14] drm/i915: Move M/N setup to a more logical place on ddi platforms Ville Syrjala
2022-01-27  9:32 ` [Intel-gfx] [PATCH 08/14] drm/i915: Extract {i9xx, ilk}_configure_cpu_transcoder() Ville Syrjala
2022-01-27  9:32 ` [Intel-gfx] [PATCH 09/14] drm/i915: Add fdi_m2_n2 Ville Syrjala
2022-01-27  9:32 ` [Intel-gfx] [PATCH 10/14] drm/i915: Program FDI RX TUSIZE2 Ville Syrjala
2022-01-27  9:33 ` [Intel-gfx] [PATCH 11/14] drm/i915: Dump dp_m2_n2 always Ville Syrjala
2022-01-27  9:33 ` [Intel-gfx] [PATCH 12/14] drm/i915: Extract can_enable_drrs() Ville Syrjala
2022-01-27  9:33 ` [Intel-gfx] [PATCH 13/14] drm/i915: Set DP M2/N2 equal to M1/N1 when not doing DRRS Ville Syrjala
2022-01-27  9:33 ` [Intel-gfx] [PATCH 14/14] drm/i915: Always check dp_m2_n2 on pre-bdw Ville Syrjala
2022-01-27 11:01 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: M/N cleanup Patchwork
2022-01-27 14:43 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: M/N cleanup (rev2) Patchwork
2022-01-27 15:13 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-01-27 19:55 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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