* [PATCH v2 00/25] SIERRA: Add support for Mulitlink Configuration
@ 2022-01-28 8:11 Aswath Govindraju
2022-01-28 8:11 ` [PATCH v2 01/25] phy: cadence: sierra: Fix for USB3 U1/U2 state Aswath Govindraju
` (24 more replies)
0 siblings, 25 replies; 51+ messages in thread
From: Aswath Govindraju @ 2022-01-28 8:11 UTC (permalink / raw)
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra,
Aswath Govindraju
The following series of patches add support for PCIe + QSGMII multilink
configuration on J721e EVM. The PHY lanes are configured in U-Boot and,
PCIe driver in Kernel and QSGMII driver in the ethernet firmware use them.
Notes:
- Patches 1 -8 and 13 - 22 are ported from upstream kernel
v5.17-rc1
- Patch 24, syncs with linux kernel dt, with the following patch
https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=608996
Changes since v1:
- Fixed the logic for skipping multilink configuration in patch 23
- Fixed the offset calcualation for SIERRA_PHY_PCS_LANE_CDB_OFFSET
and SIERRA_PHY_PMA_LANE_CDB_OFFSET in patches 18 and 21.
Aswath Govindraju (8):
phy: cadence: Sierra: Add a UCLASS_PHY device for links
phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as a clock
phy: ti: phy-j721e-wiz.c: Fix the condition for setting P_ENABLE_FORCE
board: ti: j721e: evm.c: Add support for probing SerDes0
arm: dts: k3-j721e: Add support for PLL_CMNLC clocks in SerDes0
phy: cadence: Sierra: Add support for skipping configuration
arm: dts: k3-j721e: Add support for multilink PCIe + QSGMII
include: configs: j721e_evm: Add support to boot ethfw core in j721e
Kishon Vijay Abraham I (6):
phy: cadence: Sierra: Fix PHY power_on sequence
phy: cadence: Sierra: Create PHY only for "phy" or "link" sub-nodes
phy: cadence: Sierra: Move all clk_get_*() to a separate function
phy: cadence: Sierra: Move all reset_control_get*() to a separate
function
phy: cadence: Sierra: Add array of input clocks in "struct
cdns_sierra_phy"
phy: cadence: Sierra: Add missing clk_disable_unprepare() in .remove
callback
Sanket Parmar (1):
phy: cadence: sierra: Fix for USB3 U1/U2 state
Swapnil Jakhade (10):
phy: cadence: Sierra: Prepare driver to add support for multilink
configurations
dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode
phy: cadence: Sierra: Add support to get SSC type from device tree.
phy: cadence: Sierra: Rename some regmap variables to be in sync with
Sierra documentation
phy: cadence: Sierra: Add PHY PCS common register configurations
phy: cadence: Sierra: Check cmn_ready assertion during PHY power on
phy: cadence: Sierra: Check PIPE mode PHY status to be ready for
operation
phy: cadence: Sierra: Update single link PCIe register configuration
phy: cadence: Sierra: Add support for PHY multilink configurations
phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration
.../k3-j721e-common-proc-board-u-boot.dtsi | 15 +
arch/arm/dts/k3-j721e-common-proc-board.dts | 14 +-
.../arm/dts/k3-j721e-r5-common-proc-board.dts | 32 +
board/ti/j721e/evm.c | 37 +
configs/j721e_evm_a72_defconfig | 2 +-
drivers/phy/cadence/phy-cadence-sierra.c | 1537 +++++++++++++++--
drivers/phy/ti/phy-j721e-wiz.c | 2 +-
include/configs/j721e_evm.h | 19 +-
include/dt-bindings/phy/phy-cadence.h | 4 +
9 files changed, 1494 insertions(+), 168 deletions(-)
--
2.17.1
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v2 01/25] phy: cadence: sierra: Fix for USB3 U1/U2 state
2022-01-28 8:11 [PATCH v2 00/25] SIERRA: Add support for Mulitlink Configuration Aswath Govindraju
@ 2022-01-28 8:11 ` Aswath Govindraju
2022-02-08 17:33 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 02/25] phy: cadence: Sierra: Fix PHY power_on sequence Aswath Govindraju
` (23 subsequent siblings)
24 siblings, 1 reply; 51+ messages in thread
From: Aswath Govindraju @ 2022-01-28 8:11 UTC (permalink / raw)
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra,
Aswath Govindraju
From: Sanket Parmar <sparmar@cadence.com>
Updated values of USB3 related Sierra PHY registers.
This change fixes USB3 device disconnect issue observed
while enternig U1/U2 state.
Signed-off-by: Sanket Parmar <sparmar@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
---
drivers/phy/cadence/phy-cadence-sierra.c | 27 ++++++++++++------------
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index 715def6f173b..6b26b30dcf9d 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -606,10 +606,10 @@ static struct cdns_reg_pairs cdns_usb_cmn_regs_ext_ssc[] = {
static struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = {
{0xFE0A, SIERRA_DET_STANDEC_A_PREG},
{0x000F, SIERRA_DET_STANDEC_B_PREG},
- {0x00A5, SIERRA_DET_STANDEC_C_PREG},
+ {0x55A5, SIERRA_DET_STANDEC_C_PREG},
{0x69ad, SIERRA_DET_STANDEC_D_PREG},
{0x0241, SIERRA_DET_STANDEC_E_PREG},
- {0x0010, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG},
+ {0x0110, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG},
{0x0014, SIERRA_PSM_A0IN_TMR_PREG},
{0xCF00, SIERRA_PSM_DIAG_PREG},
{0x001F, SIERRA_PSC_TX_A0_PREG},
@@ -617,7 +617,7 @@ static struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = {
{0x0003, SIERRA_PSC_TX_A2_PREG},
{0x0003, SIERRA_PSC_TX_A3_PREG},
{0x0FFF, SIERRA_PSC_RX_A0_PREG},
- {0x0619, SIERRA_PSC_RX_A1_PREG},
+ {0x0003, SIERRA_PSC_RX_A1_PREG},
{0x0003, SIERRA_PSC_RX_A2_PREG},
{0x0001, SIERRA_PSC_RX_A3_PREG},
{0x0001, SIERRA_PLLCTRL_SUBRATE_PREG},
@@ -626,19 +626,19 @@ static struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = {
{0x00CA, SIERRA_CLKPATH_BIASTRIM_PREG},
{0x2512, SIERRA_DFE_BIASTRIM_PREG},
{0x0000, SIERRA_DRVCTRL_ATTEN_PREG},
- {0x873E, SIERRA_CLKPATHCTRL_TMR_PREG},
- {0x03CF, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
- {0x01CE, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
+ {0x823E, SIERRA_CLKPATHCTRL_TMR_PREG},
+ {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
+ {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
{0x7B3C, SIERRA_CREQ_CCLKDET_MODE01_PREG},
- {0x033F, SIERRA_RX_CTLE_MAINTENANCE_PREG},
+ {0x023C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
{0x3232, SIERRA_CREQ_FSMCLK_SEL_PREG},
{0x0000, SIERRA_CREQ_EQ_CTRL_PREG},
- {0x8000, SIERRA_CREQ_SPARE_PREG},
+ {0x0000, SIERRA_CREQ_SPARE_PREG},
{0xCC44, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
- {0x8453, SIERRA_CTLELUT_CTRL_PREG},
- {0x4110, SIERRA_DFE_ECMP_RATESEL_PREG},
- {0x4110, SIERRA_DFE_SMP_RATESEL_PREG},
- {0x0002, SIERRA_DEQ_PHALIGN_CTRL},
+ {0x8452, SIERRA_CTLELUT_CTRL_PREG},
+ {0x4121, SIERRA_DFE_ECMP_RATESEL_PREG},
+ {0x4121, SIERRA_DFE_SMP_RATESEL_PREG},
+ {0x0003, SIERRA_DEQ_PHALIGN_CTRL},
{0x3200, SIERRA_DEQ_CONCUR_CTRL1_PREG},
{0x5064, SIERRA_DEQ_CONCUR_CTRL2_PREG},
{0x0030, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
@@ -646,7 +646,7 @@ static struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = {
{0x5A5A, SIERRA_DEQ_ERRCMP_CTRL_PREG},
{0x02F5, SIERRA_DEQ_OFFSET_CTRL_PREG},
{0x02F5, SIERRA_DEQ_GAIN_CTRL_PREG},
- {0x9A8A, SIERRA_DEQ_VGATUNE_CTRL_PREG},
+ {0x9999, SIERRA_DEQ_VGATUNE_CTRL_PREG},
{0x0014, SIERRA_DEQ_GLUT0},
{0x0014, SIERRA_DEQ_GLUT1},
{0x0014, SIERRA_DEQ_GLUT2},
@@ -693,6 +693,7 @@ static struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = {
{0x000F, SIERRA_LFPSFILT_NS_PREG},
{0x0009, SIERRA_LFPSFILT_RD_PREG},
{0x0001, SIERRA_LFPSFILT_MP_PREG},
+ {0x6013, SIERRA_SIGDET_SUPPORT_PREG},
{0x8013, SIERRA_SDFILT_H2L_A_PREG},
{0x8009, SIERRA_SDFILT_L2H_PREG},
{0x0024, SIERRA_RXBUFFER_CTLECTRL_PREG},
--
2.17.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 02/25] phy: cadence: Sierra: Fix PHY power_on sequence
2022-01-28 8:11 [PATCH v2 00/25] SIERRA: Add support for Mulitlink Configuration Aswath Govindraju
2022-01-28 8:11 ` [PATCH v2 01/25] phy: cadence: sierra: Fix for USB3 U1/U2 state Aswath Govindraju
@ 2022-01-28 8:11 ` Aswath Govindraju
2022-02-08 17:33 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 03/25] phy: cadence: Sierra: Create PHY only for "phy" or "link" sub-nodes Aswath Govindraju
` (22 subsequent siblings)
24 siblings, 1 reply; 51+ messages in thread
From: Aswath Govindraju @ 2022-01-28 8:11 UTC (permalink / raw)
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra,
Aswath Govindraju
From: Kishon Vijay Abraham I <kishon@ti.com>
Commit 39b823381d9d ("phy: cadence: Add driver for Sierra PHY")
de-asserts PHY_RESET even before the configurations are loaded in
phy_init(). However PHY_RESET should be de-asserted only after
all the configurations has been initialized, instead of de-asserting
in probe. Fix it here.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
---
drivers/phy/cadence/phy-cadence-sierra.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index 6b26b30dcf9d..bd42145fcacc 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -296,6 +296,12 @@ static int cdns_sierra_phy_on(struct phy *gphy)
u32 val;
int ret;
+ ret = reset_control_deassert(sp->phy_rst);
+ if (ret) {
+ dev_err(dev, "Failed to take the PHY out of reset\n");
+ return ret;
+ }
+
/* Take the PHY lane group out of reset */
ret = reset_deassert_bulk(ins->lnk_rst);
if (ret) {
@@ -544,7 +550,6 @@ static int cdns_sierra_phy_probe(struct udevice *dev)
if (!sp->autoconf && sp->nsubnodes > 1)
regmap_field_write(sp->phy_pll_cfg_1, 0x1);
- reset_control_deassert(sp->phy_rst);
dev_info(dev, "sierra probed\n");
return 0;
--
2.17.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 03/25] phy: cadence: Sierra: Create PHY only for "phy" or "link" sub-nodes
2022-01-28 8:11 [PATCH v2 00/25] SIERRA: Add support for Mulitlink Configuration Aswath Govindraju
2022-01-28 8:11 ` [PATCH v2 01/25] phy: cadence: sierra: Fix for USB3 U1/U2 state Aswath Govindraju
2022-01-28 8:11 ` [PATCH v2 02/25] phy: cadence: Sierra: Fix PHY power_on sequence Aswath Govindraju
@ 2022-01-28 8:11 ` Aswath Govindraju
2022-02-08 17:33 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 04/25] phy: cadence: Sierra: Move all clk_get_*() to a separate function Aswath Govindraju
` (21 subsequent siblings)
24 siblings, 1 reply; 51+ messages in thread
From: Aswath Govindraju @ 2022-01-28 8:11 UTC (permalink / raw)
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra,
Aswath Govindraju
From: Kishon Vijay Abraham I <kishon@ti.com>
Cadence Sierra PHY driver registers PHY using devm_phy_create()
for all sub-nodes of Sierra device tree node. However Sierra device
tree node can have sub-nodes for the various clocks in addtion to the
PHY. Use devm_phy_create() only for nodes with name "phy" (or "link"
for old device tree) which represent the actual PHY.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
---
drivers/phy/cadence/phy-cadence-sierra.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index bd42145fcacc..45d6d6a796a5 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -523,6 +523,10 @@ static int cdns_sierra_phy_probe(struct udevice *dev)
sp->autoconf = dev_read_bool(dev, "cdns,autoconf");
ofnode_for_each_subnode(child, dev_ofnode(dev)) {
+ if (!(ofnode_name_eq(child, "phy") ||
+ ofnode_name_eq(child, "link")))
+ continue;
+
sp->phys[node].lnk_rst = devm_reset_bulk_get_by_node(dev,
child);
if (IS_ERR(sp->phys[node].lnk_rst)) {
--
2.17.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 04/25] phy: cadence: Sierra: Move all clk_get_*() to a separate function
2022-01-28 8:11 [PATCH v2 00/25] SIERRA: Add support for Mulitlink Configuration Aswath Govindraju
` (2 preceding siblings ...)
2022-01-28 8:11 ` [PATCH v2 03/25] phy: cadence: Sierra: Create PHY only for "phy" or "link" sub-nodes Aswath Govindraju
@ 2022-01-28 8:11 ` Aswath Govindraju
2022-02-08 17:34 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 05/25] phy: cadence: Sierra: Move all reset_control_get*() " Aswath Govindraju
` (20 subsequent siblings)
24 siblings, 1 reply; 51+ messages in thread
From: Aswath Govindraju @ 2022-01-28 8:11 UTC (permalink / raw)
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra,
Aswath Govindraju
From: Kishon Vijay Abraham I <kishon@ti.com>
No functional change. Group all devm_clk_get_optional() to a
separate function.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
---
drivers/phy/cadence/phy-cadence-sierra.c | 57 +++++++++++++++---------
1 file changed, 35 insertions(+), 22 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index 45d6d6a796a5..d07cf1d97df2 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -448,13 +448,44 @@ static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp,
return 0;
}
+static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp,
+ struct udevice *dev)
+{
+ struct clk *clk;
+ int ret;
+
+ clk = devm_clk_get_optional(dev, "phy_clk");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "failed to get clock phy_clk\n");
+ return PTR_ERR(clk);
+ }
+ sp->clk = clk;
+
+ clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "cmn_refclk_dig_div clock not found\n");
+ ret = PTR_ERR(clk);
+ return ret;
+ }
+ sp->cmn_refclk = clk;
+
+ clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "cmn_refclk1_dig_div clock not found\n");
+ ret = PTR_ERR(clk);
+ return ret;
+ }
+ sp->cmn_refclk1 = clk;
+
+ return 0;
+}
+
static int cdns_sierra_phy_probe(struct udevice *dev)
{
struct cdns_sierra_phy *sp = dev_get_priv(dev);
struct cdns_sierra_data *data;
unsigned int id_value;
int ret, node = 0;
- struct clk *clk;
ofnode child;
sp->dev = dev;
@@ -479,11 +510,9 @@ static int cdns_sierra_phy_probe(struct udevice *dev)
if (ret)
return ret;
- sp->clk = devm_clk_get_optional(dev, "phy_clk");
- if (IS_ERR(sp->clk)) {
- dev_err(dev, "failed to get clock phy_clk\n");
- return PTR_ERR(sp->clk);
- }
+ ret = cdns_sierra_phy_get_clocks(sp, dev);
+ if (ret)
+ return ret;
sp->phy_rst = devm_reset_control_get(dev, "sierra_reset");
if (IS_ERR(sp->phy_rst)) {
@@ -491,22 +520,6 @@ static int cdns_sierra_phy_probe(struct udevice *dev)
return PTR_ERR(sp->phy_rst);
}
- clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div");
- if (IS_ERR(clk)) {
- dev_err(dev, "cmn_refclk clock not found\n");
- ret = PTR_ERR(clk);
- return ret;
- }
- sp->cmn_refclk = clk;
-
- clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div");
- if (IS_ERR(clk)) {
- dev_err(dev, "cmn_refclk1 clock not found\n");
- ret = PTR_ERR(clk);
- return ret;
- }
- sp->cmn_refclk1 = clk;
-
ret = clk_prepare_enable(sp->clk);
if (ret)
return ret;
--
2.17.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 05/25] phy: cadence: Sierra: Move all reset_control_get*() to a separate function
2022-01-28 8:11 [PATCH v2 00/25] SIERRA: Add support for Mulitlink Configuration Aswath Govindraju
` (3 preceding siblings ...)
2022-01-28 8:11 ` [PATCH v2 04/25] phy: cadence: Sierra: Move all clk_get_*() to a separate function Aswath Govindraju
@ 2022-01-28 8:11 ` Aswath Govindraju
2022-02-08 17:34 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 06/25] phy: cadence: Sierra: Add array of input clocks in "struct cdns_sierra_phy" Aswath Govindraju
` (19 subsequent siblings)
24 siblings, 1 reply; 51+ messages in thread
From: Aswath Govindraju @ 2022-01-28 8:11 UTC (permalink / raw)
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra,
Aswath Govindraju
From: Kishon Vijay Abraham I <kishon@ti.com>
No functional change. Group devm_reset_control_get() and
devm_reset_control_get_optional() to a separate function.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
---
drivers/phy/cadence/phy-cadence-sierra.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index d07cf1d97df2..eaa32939c1c2 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -480,6 +480,21 @@ static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp,
return 0;
}
+static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp,
+ struct udevice *dev)
+{
+ struct reset_control *rst;
+
+ rst = devm_reset_control_get(dev, "sierra_reset");
+ if (IS_ERR(rst)) {
+ dev_err(dev, "failed to get reset\n");
+ return PTR_ERR(rst);
+ }
+ sp->phy_rst = rst;
+
+ return 0;
+}
+
static int cdns_sierra_phy_probe(struct udevice *dev)
{
struct cdns_sierra_phy *sp = dev_get_priv(dev);
@@ -520,6 +535,10 @@ static int cdns_sierra_phy_probe(struct udevice *dev)
return PTR_ERR(sp->phy_rst);
}
+ ret = cdns_sierra_phy_get_resets(sp, dev);
+ if (ret)
+ return ret;
+
ret = clk_prepare_enable(sp->clk);
if (ret)
return ret;
--
2.17.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 06/25] phy: cadence: Sierra: Add array of input clocks in "struct cdns_sierra_phy"
2022-01-28 8:11 [PATCH v2 00/25] SIERRA: Add support for Mulitlink Configuration Aswath Govindraju
` (4 preceding siblings ...)
2022-01-28 8:11 ` [PATCH v2 05/25] phy: cadence: Sierra: Move all reset_control_get*() " Aswath Govindraju
@ 2022-01-28 8:11 ` Aswath Govindraju
2022-02-08 17:34 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 07/25] phy: cadence: Sierra: Add missing clk_disable_unprepare() in .remove callback Aswath Govindraju
` (18 subsequent siblings)
24 siblings, 1 reply; 51+ messages in thread
From: Aswath Govindraju @ 2022-01-28 8:11 UTC (permalink / raw)
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra,
Aswath Govindraju
From: Kishon Vijay Abraham I <kishon@ti.com>
Instead of having separate structure members for each input clock, add
an array for the input clocks within "struct cdns_sierra_phy". This is
in preparation for adding more input clocks required for supporting
additional clock combination.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
---
drivers/phy/cadence/phy-cadence-sierra.c | 25 ++++++++++++++----------
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index eaa32939c1c2..0bc60bb73e88 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -147,6 +147,13 @@
#define SIERRA_MAX_LANES 16
#define PLL_LOCK_TIME 100
+#define CDNS_SIERRA_INPUT_CLOCKS 3
+enum cdns_sierra_clock_input {
+ PHY_CLK,
+ CMN_REFCLK_DIG_DIV,
+ CMN_REFCLK1_DIG_DIV,
+};
+
static const struct reg_field macro_id_type =
REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15);
static const struct reg_field phy_pll_cfg_1 =
@@ -204,9 +211,7 @@ struct cdns_sierra_phy {
struct regmap_field *macro_id_type;
struct regmap_field *phy_pll_cfg_1;
struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES];
- struct clk *clk;
- struct clk *cmn_refclk;
- struct clk *cmn_refclk1;
+ struct clk *input_clks[CDNS_SIERRA_INPUT_CLOCKS];
int nsubnodes;
u32 num_lanes;
bool autoconf;
@@ -257,8 +262,8 @@ static int cdns_sierra_phy_init(struct phy *gphy)
if (phy->autoconf)
return 0;
- clk_set_rate(phy->cmn_refclk, 25000000);
- clk_set_rate(phy->cmn_refclk1, 25000000);
+ clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 25000000);
+ clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 25000000);
if (ins->phy_type == PHY_TYPE_PCIE) {
num_cmn_regs = phy->init_data->pcie_cmn_regs;
@@ -459,7 +464,7 @@ static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp,
dev_err(dev, "failed to get clock phy_clk\n");
return PTR_ERR(clk);
}
- sp->clk = clk;
+ sp->input_clks[PHY_CLK] = clk;
clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div");
if (IS_ERR(clk)) {
@@ -467,7 +472,7 @@ static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp,
ret = PTR_ERR(clk);
return ret;
}
- sp->cmn_refclk = clk;
+ sp->input_clks[CMN_REFCLK_DIG_DIV] = clk;
clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div");
if (IS_ERR(clk)) {
@@ -475,7 +480,7 @@ static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp,
ret = PTR_ERR(clk);
return ret;
}
- sp->cmn_refclk1 = clk;
+ sp->input_clks[CMN_REFCLK1_DIG_DIV] = clk;
return 0;
}
@@ -539,7 +544,7 @@ static int cdns_sierra_phy_probe(struct udevice *dev)
if (ret)
return ret;
- ret = clk_prepare_enable(sp->clk);
+ ret = clk_prepare_enable(sp->input_clks[PHY_CLK]);
if (ret)
return ret;
@@ -594,7 +599,7 @@ put_child:
put_child2:
clk_disable:
- clk_disable_unprepare(sp->clk);
+ clk_disable_unprepare(sp->input_clks[PHY_CLK]);
return ret;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 07/25] phy: cadence: Sierra: Add missing clk_disable_unprepare() in .remove callback
2022-01-28 8:11 [PATCH v2 00/25] SIERRA: Add support for Mulitlink Configuration Aswath Govindraju
` (5 preceding siblings ...)
2022-01-28 8:11 ` [PATCH v2 06/25] phy: cadence: Sierra: Add array of input clocks in "struct cdns_sierra_phy" Aswath Govindraju
@ 2022-01-28 8:11 ` Aswath Govindraju
2022-02-08 17:34 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 08/25] phy: cadence: Sierra: Add a UCLASS_PHY device for links Aswath Govindraju
` (17 subsequent siblings)
24 siblings, 1 reply; 51+ messages in thread
From: Aswath Govindraju @ 2022-01-28 8:11 UTC (permalink / raw)
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra,
Aswath Govindraju
From: Kishon Vijay Abraham I <kishon@ti.com>
Add missing clk_disable_unprepare() in cdns_sierra_phy_remove().
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
---
drivers/phy/cadence/phy-cadence-sierra.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index 0bc60bb73e88..90699f2fa653 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -617,6 +617,8 @@ static int cdns_sierra_phy_remove(struct udevice *dev)
for (i = 0; i < phy->nsubnodes; i++)
reset_assert_bulk(phy->phys[i].lnk_rst);
+ clk_disable_unprepare(phy->input_clks[PHY_CLK]);
+
return 0;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 08/25] phy: cadence: Sierra: Add a UCLASS_PHY device for links
2022-01-28 8:11 [PATCH v2 00/25] SIERRA: Add support for Mulitlink Configuration Aswath Govindraju
` (6 preceding siblings ...)
2022-01-28 8:11 ` [PATCH v2 07/25] phy: cadence: Sierra: Add missing clk_disable_unprepare() in .remove callback Aswath Govindraju
@ 2022-01-28 8:11 ` Aswath Govindraju
2022-02-08 17:34 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 09/25] phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as a clock Aswath Govindraju
` (16 subsequent siblings)
24 siblings, 1 reply; 51+ messages in thread
From: Aswath Govindraju @ 2022-01-28 8:11 UTC (permalink / raw)
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra,
Aswath Govindraju
Add a driver of type UCLASS_PHY for each of the link nodes in the serdes
instance.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
---
drivers/phy/cadence/phy-cadence-sierra.c | 116 +++++++++++++++--------
1 file changed, 75 insertions(+), 41 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index 90699f2fa653..af67df6d06cb 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -203,7 +203,7 @@ struct cdns_sierra_phy {
size_t size;
struct regmap *regmap;
struct cdns_sierra_data *init_data;
- struct cdns_sierra_inst phys[SIERRA_MAX_LANES];
+ struct cdns_sierra_inst *phys[SIERRA_MAX_LANES];
struct reset_control *phy_rst;
struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES];
struct regmap *regmap_phy_config_ctrl;
@@ -242,8 +242,8 @@ static inline struct cdns_sierra_inst *phy_get_drvdata(struct phy *phy)
return NULL;
for (index = 0; index < sp->nsubnodes; index++) {
- if (phy->id == sp->phys[index].mlane)
- return &sp->phys[index];
+ if (phy->id == sp->phys[index]->mlane)
+ return sp->phys[index];
}
return NULL;
@@ -500,13 +500,79 @@ static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp,
return 0;
}
+static int cdns_sierra_bind_link_nodes(struct cdns_sierra_phy *sp)
+{
+ struct udevice *dev = sp->dev;
+ struct driver *link_drv;
+ ofnode child;
+ int rc;
+
+ link_drv = lists_driver_lookup_name("sierra_phy_link");
+ if (!link_drv) {
+ dev_err(dev, "Cannot find driver 'sierra_phy_link'\n");
+ return -ENOENT;
+ }
+
+ ofnode_for_each_subnode(child, dev_ofnode(dev)) {
+ if (!(ofnode_name_eq(child, "phy") ||
+ ofnode_name_eq(child, "link")))
+ continue;
+
+ rc = device_bind(dev, link_drv, "link", NULL, child, NULL);
+ if (rc) {
+ dev_err(dev, "cannot bind driver for link\n");
+ return rc;
+ }
+ }
+
+ return 0;
+}
+
+static int cdns_sierra_link_probe(struct udevice *dev)
+{
+ struct cdns_sierra_inst *inst = dev_get_priv(dev);
+ struct cdns_sierra_phy *sp = dev_get_priv(dev->parent);
+ struct reset_ctl_bulk *rst;
+ int ret, node;
+
+ rst = devm_reset_bulk_get_by_node(dev, dev_ofnode(dev));
+ if (IS_ERR(rst)) {
+ ret = PTR_ERR(rst);
+ dev_err(dev, "failed to get reset\n");
+ return ret;
+ }
+ inst->lnk_rst = rst;
+
+ ret = cdns_sierra_get_optional(inst, dev_ofnode(dev));
+ if (ret) {
+ dev_err(dev, "missing property in node\n");
+ return ret;
+ }
+ node = sp->nsubnodes;
+ sp->phys[node] = inst;
+ sp->nsubnodes += 1;
+ sp->num_lanes += inst->num_lanes;
+
+ /* If more than one subnode, configure the PHY as multilink */
+ if (!sp->autoconf && sp->nsubnodes > 1)
+ regmap_field_write(sp->phy_pll_cfg_1, 0x1);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(sierra_phy_link) = {
+ .name = "sierra_phy_link",
+ .id = UCLASS_PHY,
+ .probe = cdns_sierra_link_probe,
+ .priv_auto = sizeof(struct cdns_sierra_inst),
+};
+
static int cdns_sierra_phy_probe(struct udevice *dev)
{
struct cdns_sierra_phy *sp = dev_get_priv(dev);
struct cdns_sierra_data *data;
unsigned int id_value;
int ret, node = 0;
- ofnode child;
sp->dev = dev;
@@ -558,46 +624,14 @@ static int cdns_sierra_phy_probe(struct udevice *dev)
}
sp->autoconf = dev_read_bool(dev, "cdns,autoconf");
-
- ofnode_for_each_subnode(child, dev_ofnode(dev)) {
- if (!(ofnode_name_eq(child, "phy") ||
- ofnode_name_eq(child, "link")))
- continue;
-
- sp->phys[node].lnk_rst = devm_reset_bulk_get_by_node(dev,
- child);
- if (IS_ERR(sp->phys[node].lnk_rst)) {
- ret = PTR_ERR(sp->phys[node].lnk_rst);
- dev_err(dev, "failed to get reset %s\n",
- ofnode_get_name(child));
- goto put_child2;
- }
-
- if (!sp->autoconf) {
- ret = cdns_sierra_get_optional(&sp->phys[node], child);
- if (ret) {
- dev_err(dev, "missing property in node %s\n",
- ofnode_get_name(child));
- goto put_child;
- }
- }
- sp->num_lanes += sp->phys[node].num_lanes;
-
- node++;
- }
- sp->nsubnodes = node;
-
- /* If more than one subnode, configure the PHY as multilink */
- if (!sp->autoconf && sp->nsubnodes > 1)
- regmap_field_write(sp->phy_pll_cfg_1, 0x1);
+ /* Binding link nodes as children to serdes */
+ ret = cdns_sierra_bind_link_nodes(sp);
+ if (ret)
+ goto clk_disable;
dev_info(dev, "sierra probed\n");
return 0;
-put_child:
- node++;
-put_child2:
-
clk_disable:
clk_disable_unprepare(sp->input_clks[PHY_CLK]);
return ret;
@@ -615,7 +649,7 @@ static int cdns_sierra_phy_remove(struct udevice *dev)
* Need to put the subnode resets here though.
*/
for (i = 0; i < phy->nsubnodes; i++)
- reset_assert_bulk(phy->phys[i].lnk_rst);
+ reset_assert_bulk(phy->phys[i]->lnk_rst);
clk_disable_unprepare(phy->input_clks[PHY_CLK]);
--
2.17.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 09/25] phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as a clock
2022-01-28 8:11 [PATCH v2 00/25] SIERRA: Add support for Mulitlink Configuration Aswath Govindraju
` (7 preceding siblings ...)
2022-01-28 8:11 ` [PATCH v2 08/25] phy: cadence: Sierra: Add a UCLASS_PHY device for links Aswath Govindraju
@ 2022-01-28 8:11 ` Aswath Govindraju
2022-02-08 17:34 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 10/25] phy: ti: phy-j721e-wiz.c: Fix the condition for setting P_ENABLE_FORCE Aswath Govindraju
` (15 subsequent siblings)
24 siblings, 1 reply; 51+ messages in thread
From: Aswath Govindraju @ 2022-01-28 8:11 UTC (permalink / raw)
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra,
Aswath Govindraju
Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has
two inputs, plllc_refclk (input from pll0_refclk) and refrcv (input from
pll1_refclk). Model PLL_CMNLC and PLL_CMNLC1 as a clock so that it's
possible to select one of these two inputs from device tree.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
---
drivers/phy/cadence/phy-cadence-sierra.c | 223 +++++++++++++++++++++--
1 file changed, 210 insertions(+), 13 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index af67df6d06cb..7e52a19f0dae 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -13,6 +13,7 @@
*/
#include <common.h>
#include <clk.h>
+#include <linux/clk-provider.h>
#include <generic-phy.h>
#include <reset.h>
#include <dm/device.h>
@@ -24,11 +25,13 @@
#include <dm/devres.h>
#include <linux/io.h>
#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/phy/phy-cadence.h>
#include <regmap.h>
/* PHY register offsets */
#define SIERRA_COMMON_CDB_OFFSET 0x0
#define SIERRA_MACRO_ID_REG 0x0
+#define SIERRA_CMN_PLLLC_GEN_PREG 0x42
#define SIERRA_CMN_PLLLC_MODE_PREG 0x48
#define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG 0x49
#define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG 0x4A
@@ -36,6 +39,9 @@
#define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG 0x4F
#define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG 0x50
#define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG 0x62
+#define SIERRA_CMN_REFRCV_PREG 0x98
+#define SIERRA_CMN_REFRCV1_PREG 0xB8
+#define SIERRA_CMN_PLLLC1_GEN_PREG 0xC2
#define SIERRA_LANE_CDB_OFFSET(ln, offset) \
(0x4000 + ((ln) * (0x800 >> (2 - (offset)))))
@@ -147,13 +153,18 @@
#define SIERRA_MAX_LANES 16
#define PLL_LOCK_TIME 100
-#define CDNS_SIERRA_INPUT_CLOCKS 3
+#define CDNS_SIERRA_INPUT_CLOCKS 5
enum cdns_sierra_clock_input {
PHY_CLK,
CMN_REFCLK_DIG_DIV,
CMN_REFCLK1_DIG_DIV,
+ PLL0_REFCLK,
+ PLL1_REFCLK,
};
+#define SIERRA_NUM_CMN_PLLC 2
+#define SIERRA_NUM_CMN_PLLC_PARENTS 2
+
static const struct reg_field macro_id_type =
REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15);
static const struct reg_field phy_pll_cfg_1 =
@@ -161,6 +172,44 @@ static const struct reg_field phy_pll_cfg_1 =
static const struct reg_field pllctrl_lock =
REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0);
+static const char * const clk_names[] = {
+ [CDNS_SIERRA_PLL_CMNLC] = "pll_cmnlc",
+ [CDNS_SIERRA_PLL_CMNLC1] = "pll_cmnlc1",
+};
+
+enum cdns_sierra_cmn_plllc {
+ CMN_PLLLC,
+ CMN_PLLLC1,
+};
+
+struct cdns_sierra_pll_mux_reg_fields {
+ struct reg_field pfdclk_sel_preg;
+ struct reg_field plllc1en_field;
+ struct reg_field termen_field;
+};
+
+static const struct cdns_sierra_pll_mux_reg_fields cmn_plllc_pfdclk1_sel_preg[] = {
+ [CMN_PLLLC] = {
+ .pfdclk_sel_preg = REG_FIELD(SIERRA_CMN_PLLLC_GEN_PREG, 1, 1),
+ .plllc1en_field = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 8, 8),
+ .termen_field = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 0, 0),
+ },
+ [CMN_PLLLC1] = {
+ .pfdclk_sel_preg = REG_FIELD(SIERRA_CMN_PLLLC1_GEN_PREG, 1, 1),
+ .plllc1en_field = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 8, 8),
+ .termen_field = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 0, 0),
+ },
+};
+
+struct cdns_sierra_pll_mux {
+ struct cdns_sierra_phy *sp;
+ struct clk *clk;
+ struct clk *parent_clks[2];
+ struct regmap_field *pfdclk_sel_preg;
+ struct regmap_field *plllc1en_field;
+ struct regmap_field *termen_field;
+};
+
#define reset_control_assert(rst) cdns_reset_assert(rst)
#define reset_control_deassert(rst) cdns_reset_deassert(rst)
#define reset_control reset_ctl
@@ -191,12 +240,6 @@ struct cdns_sierra_data {
struct cdns_reg_pairs *usb_ln_vals;
};
-struct cdns_regmap_cdb_context {
- struct udevice *dev;
- void __iomem *base;
- u8 reg_offset_shift;
-};
-
struct cdns_sierra_phy {
struct udevice *dev;
void *base;
@@ -211,6 +254,9 @@ struct cdns_sierra_phy {
struct regmap_field *macro_id_type;
struct regmap_field *phy_pll_cfg_1;
struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES];
+ struct regmap_field *cmn_refrcv_refclk_plllc1en_preg[SIERRA_NUM_CMN_PLLC];
+ struct regmap_field *cmn_refrcv_refclk_termen_preg[SIERRA_NUM_CMN_PLLC];
+ struct regmap_field *cmn_plllc_pfdclk1_sel_preg[SIERRA_NUM_CMN_PLLC];
struct clk *input_clks[CDNS_SIERRA_INPUT_CLOCKS];
int nsubnodes;
u32 num_lanes;
@@ -348,6 +394,116 @@ static const struct phy_ops ops = {
.reset = cdns_sierra_phy_reset,
};
+struct cdns_sierra_pll_mux_sel {
+ enum cdns_sierra_cmn_plllc mux_sel;
+ u32 table[2];
+ const char *node_name;
+ u32 num_parents;
+ u32 parents[2];
+};
+
+static struct cdns_sierra_pll_mux_sel pll_clk_mux_sel[] = {
+ {
+ .num_parents = 2,
+ .parents = { PLL0_REFCLK, PLL1_REFCLK },
+ .mux_sel = CMN_PLLLC,
+ .table = { 0, 1 },
+ .node_name = "pll_cmnlc",
+ },
+ {
+ .num_parents = 2,
+ .parents = { PLL1_REFCLK, PLL0_REFCLK },
+ .mux_sel = CMN_PLLLC1,
+ .table = { 1, 0 },
+ .node_name = "pll_cmnlc1",
+ },
+};
+
+static int cdns_sierra_pll_mux_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct udevice *dev = clk->dev;
+ struct cdns_sierra_pll_mux *priv = dev_get_priv(dev);
+ struct cdns_sierra_pll_mux_sel *data = dev_get_plat(dev);
+ struct cdns_sierra_phy *sp = priv->sp;
+ int ret;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(priv->parent_clks); i++) {
+ if (parent->dev == priv->parent_clks[i]->dev)
+ break;
+ }
+
+ if (i == ARRAY_SIZE(priv->parent_clks))
+ return -EINVAL;
+
+ ret = regmap_field_write(sp->cmn_refrcv_refclk_plllc1en_preg[data[clk->id].mux_sel], i);
+ ret |= regmap_field_write(sp->cmn_refrcv_refclk_termen_preg[data[clk->id].mux_sel], i);
+ ret |= regmap_field_write(sp->cmn_plllc_pfdclk1_sel_preg[data[clk->id].mux_sel],
+ data[clk->id].table[i]);
+
+ return ret;
+}
+
+static const struct clk_ops cdns_sierra_pll_mux_ops = {
+ .set_parent = cdns_sierra_pll_mux_set_parent,
+};
+
+int cdns_sierra_pll_mux_probe(struct udevice *dev)
+{
+ struct cdns_sierra_pll_mux *priv = dev_get_priv(dev);
+ struct cdns_sierra_phy *sp = dev_get_priv(dev->parent);
+ struct cdns_sierra_pll_mux_sel *data = dev_get_plat(dev);
+ struct clk *clk;
+ int i, j;
+
+ for (j = 0; j < SIERRA_NUM_CMN_PLLC; j++) {
+ for (i = 0; i < ARRAY_SIZE(priv->parent_clks); i++) {
+ clk = sp->input_clks[data[j].parents[i]];
+ if (IS_ERR_OR_NULL(clk)) {
+ dev_err(dev, "No parent clock for PLL mux clocks\n");
+ return IS_ERR(clk) ? PTR_ERR(clk) : -ENOENT;
+ }
+ priv->parent_clks[i] = clk;
+ }
+ }
+
+ priv->sp = dev_get_priv(dev->parent);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(cdns_sierra_pll_mux_clk) = {
+ .name = "cdns_sierra_mux_clk",
+ .id = UCLASS_CLK,
+ .priv_auto = sizeof(struct cdns_sierra_pll_mux),
+ .ops = &cdns_sierra_pll_mux_ops,
+ .probe = cdns_sierra_pll_mux_probe,
+ .plat_auto = sizeof(struct cdns_sierra_pll_mux_sel) * SIERRA_NUM_CMN_PLLC,
+};
+
+static int cdns_sierra_pll_bind_of_clocks(struct cdns_sierra_phy *sp)
+{
+ struct udevice *dev = sp->dev;
+ struct driver *cdns_sierra_clk_drv;
+ struct cdns_sierra_pll_mux_sel *data = pll_clk_mux_sel;
+ int i, rc;
+
+ cdns_sierra_clk_drv = lists_driver_lookup_name("cdns_sierra_mux_clk");
+ if (!cdns_sierra_clk_drv) {
+ dev_err(dev, "Can not find driver 'cdns_sierra_mux_clk'\n");
+ return -ENOENT;
+ }
+
+ rc = device_bind(dev, cdns_sierra_clk_drv, "pll_mux_clk",
+ data, dev_ofnode(dev), NULL);
+ if (rc) {
+ dev_err(dev, "cannot bind driver for clock %s\n",
+ clk_names[i]);
+ }
+
+ return 0;
+}
+
static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst,
ofnode child)
{
@@ -382,6 +538,7 @@ static int cdns_regfield_init(struct cdns_sierra_phy *sp)
{
struct udevice *dev = sp->dev;
struct regmap_field *field;
+ struct reg_field reg_field;
struct regmap *regmap;
int i;
@@ -393,6 +550,32 @@ static int cdns_regfield_init(struct cdns_sierra_phy *sp)
}
sp->macro_id_type = field;
+ for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++) {
+ reg_field = cmn_plllc_pfdclk1_sel_preg[i].pfdclk_sel_preg;
+ field = devm_regmap_field_alloc(dev, regmap, reg_field);
+ if (IS_ERR(field)) {
+ dev_err(dev, "PLLLC%d_PFDCLK1_SEL failed\n", i);
+ return PTR_ERR(field);
+ }
+ sp->cmn_plllc_pfdclk1_sel_preg[i] = field;
+
+ reg_field = cmn_plllc_pfdclk1_sel_preg[i].plllc1en_field;
+ field = devm_regmap_field_alloc(dev, regmap, reg_field);
+ if (IS_ERR(field)) {
+ dev_err(dev, "REFRCV%d_REFCLK_PLLLC1EN failed\n", i);
+ return PTR_ERR(field);
+ }
+ sp->cmn_refrcv_refclk_plllc1en_preg[i] = field;
+
+ reg_field = cmn_plllc_pfdclk1_sel_preg[i].termen_field;
+ field = devm_regmap_field_alloc(dev, regmap, reg_field);
+ if (IS_ERR(field)) {
+ dev_err(dev, "REFRCV%d_REFCLK_TERMEN failed\n", i);
+ return PTR_ERR(field);
+ }
+ sp->cmn_refrcv_refclk_termen_preg[i] = field;
+ }
+
regmap = sp->regmap_phy_config_ctrl;
field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1);
if (IS_ERR(field)) {
@@ -482,6 +665,22 @@ static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp,
}
sp->input_clks[CMN_REFCLK1_DIG_DIV] = clk;
+ clk = devm_clk_get_optional(dev, "pll0_refclk");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "pll0_refclk clock not found\n");
+ ret = PTR_ERR(clk);
+ return ret;
+ }
+ sp->input_clks[PLL0_REFCLK] = clk;
+
+ clk = devm_clk_get_optional(dev, "pll1_refclk");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "pll1_refclk clock not found\n");
+ ret = PTR_ERR(clk);
+ return ret;
+ }
+ sp->input_clks[PLL1_REFCLK] = clk;
+
return 0;
}
@@ -572,7 +771,7 @@ static int cdns_sierra_phy_probe(struct udevice *dev)
struct cdns_sierra_phy *sp = dev_get_priv(dev);
struct cdns_sierra_data *data;
unsigned int id_value;
- int ret, node = 0;
+ int ret;
sp->dev = dev;
@@ -600,11 +799,9 @@ static int cdns_sierra_phy_probe(struct udevice *dev)
if (ret)
return ret;
- sp->phy_rst = devm_reset_control_get(dev, "sierra_reset");
- if (IS_ERR(sp->phy_rst)) {
- dev_err(dev, "failed to get reset\n");
- return PTR_ERR(sp->phy_rst);
- }
+ ret = cdns_sierra_pll_bind_of_clocks(sp);
+ if (ret)
+ return ret;
ret = cdns_sierra_phy_get_resets(sp, dev);
if (ret)
--
2.17.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 10/25] phy: ti: phy-j721e-wiz.c: Fix the condition for setting P_ENABLE_FORCE
2022-01-28 8:11 [PATCH v2 00/25] SIERRA: Add support for Mulitlink Configuration Aswath Govindraju
` (8 preceding siblings ...)
2022-01-28 8:11 ` [PATCH v2 09/25] phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as a clock Aswath Govindraju
@ 2022-01-28 8:11 ` Aswath Govindraju
2022-02-08 17:34 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 11/25] board: ti: j721e: evm.c: Add support for probing SerDes0 Aswath Govindraju
` (14 subsequent siblings)
24 siblings, 1 reply; 51+ messages in thread
From: Aswath Govindraju @ 2022-01-28 8:11 UTC (permalink / raw)
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra,
Aswath Govindraju
Fix the condition for setting P_ENABLE_FORCE bit, by syncing with the
driver in kernel.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
---
drivers/phy/ti/phy-j721e-wiz.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index d74efcd21208..686cdc6f7c23 100644
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -523,7 +523,7 @@ static int wiz_reset_deassert(struct reset_ctl *reset_ctl)
return ret;
}
- if (wiz->lane_phy_type[id - 1] == PHY_TYPE_PCIE)
+ if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP)
ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE);
else
ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE);
--
2.17.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 11/25] board: ti: j721e: evm.c: Add support for probing SerDes0
2022-01-28 8:11 [PATCH v2 00/25] SIERRA: Add support for Mulitlink Configuration Aswath Govindraju
` (9 preceding siblings ...)
2022-01-28 8:11 ` [PATCH v2 10/25] phy: ti: phy-j721e-wiz.c: Fix the condition for setting P_ENABLE_FORCE Aswath Govindraju
@ 2022-01-28 8:11 ` Aswath Govindraju
2022-02-08 17:34 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 12/25] arm: dts: k3-j721e: Add support for PLL_CMNLC clocks in SerDes0 Aswath Govindraju
` (13 subsequent siblings)
24 siblings, 1 reply; 51+ messages in thread
From: Aswath Govindraju @ 2022-01-28 8:11 UTC (permalink / raw)
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra,
Aswath Govindraju
Add support for probing, initializing and powering, SerDes0 instance.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
---
board/ti/j721e/evm.c | 37 +++++++++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index 077d83420c9c..ad85b9d50115 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -413,6 +413,40 @@ void configure_serdes_torrent(void)
printf("phy_power_on failed !!\n");
}
+void configure_serdes_sierra(void)
+{
+ struct udevice *dev, *lnk_dev;
+ struct phy serdes;
+ int ret, count, i;
+
+ if (!IS_ENABLED(CONFIG_PHY_CADENCE_SIERRA))
+ return;
+
+ ret = uclass_get_device_by_driver(UCLASS_PHY,
+ DM_DRIVER_GET(sierra_phy_provider),
+ &dev);
+ if (ret)
+ printf("Sierra init failed:%d\n", ret);
+
+ serdes.dev = dev;
+ serdes.id = 0;
+
+ count = device_get_child_count(dev);
+ for (i = 0; i < count; i++) {
+ ret = device_get_child(dev, i, &lnk_dev);
+ if (ret)
+ printf("probe of sierra child node %d failed\n", i);
+ }
+
+ ret = generic_phy_init(&serdes);
+ if (ret)
+ printf("phy_init failed!!\n");
+
+ ret = generic_phy_power_on(&serdes);
+ if (ret)
+ printf("phy_power_on failed !!\n");
+}
+
int board_late_init(void)
{
if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT)) {
@@ -426,6 +460,9 @@ int board_late_init(void)
if (board_is_j7200_som())
configure_serdes_torrent();
+ if (board_is_j721e_som())
+ configure_serdes_sierra();
+
return 0;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 12/25] arm: dts: k3-j721e: Add support for PLL_CMNLC clocks in SerDes0
2022-01-28 8:11 [PATCH v2 00/25] SIERRA: Add support for Mulitlink Configuration Aswath Govindraju
` (10 preceding siblings ...)
2022-01-28 8:11 ` [PATCH v2 11/25] board: ti: j721e: evm.c: Add support for probing SerDes0 Aswath Govindraju
@ 2022-01-28 8:11 ` Aswath Govindraju
2022-02-08 17:34 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 13/25] phy: cadence: Sierra: Prepare driver to add support for multilink configurations Aswath Govindraju
` (12 subsequent siblings)
24 siblings, 1 reply; 51+ messages in thread
From: Aswath Govindraju @ 2022-01-28 8:11 UTC (permalink / raw)
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra,
Aswath Govindraju
The PLL_CMNLC clocks are modelled as a child clock device of seirra. In the
function device_probe, the corresponding clocks are probed before calling
the device's probe. The PLL_CMNLC mux clock can only be created after the
device's probe. Therefore, move assigned-clocks and assigned-clock-parents
to the link nodes in U-Boot device tree file.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
---
.../k3-j721e-common-proc-board-u-boot.dtsi | 10 ++++++++
.../arm/dts/k3-j721e-r5-common-proc-board.dts | 24 +++++++++++++++++++
2 files changed, 34 insertions(+)
diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
index 3ca9b5c801f0..938e978a6b66 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
@@ -232,3 +232,13 @@
&usb_serdes_mux {
u-boot,mux-autoprobe;
};
+
+&serdes0 {
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+};
+
+&serdes0_pcie_link {
+ assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
+ assigned-clock-parents = <&wiz0_pll1_refclk>;
+};
diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
index 4b2362a5dd05..8299463c3e01 100644
--- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
@@ -8,6 +8,7 @@
#include "k3-j721e-som-p0.dtsi"
#include "k3-j721e-ddr-evm-lp4-4266.dtsi"
#include "k3-j721e-ddr.dtsi"
+#include <dt-bindings/phy/phy-cadence.h>
/ {
aliases {
@@ -361,3 +362,26 @@
&mcu_udmap {
ti,sci = <&dm_tifs>;
};
+
+&wiz0_pll1_refclk {
+ assigned-clocks = <&wiz0_pll1_refclk>;
+ assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&wiz0_refclk_dig {
+ assigned-clocks = <&wiz0_refclk_dig>;
+ assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&serdes0 {
+ assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
+ assigned-clock-parents = <&wiz0_pll1_refclk>;
+
+ serdes0_pcie_link: link@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz0 1>;
+ };
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 13/25] phy: cadence: Sierra: Prepare driver to add support for multilink configurations
2022-01-28 8:11 [PATCH v2 00/25] SIERRA: Add support for Mulitlink Configuration Aswath Govindraju
` (11 preceding siblings ...)
2022-01-28 8:11 ` [PATCH v2 12/25] arm: dts: k3-j721e: Add support for PLL_CMNLC clocks in SerDes0 Aswath Govindraju
@ 2022-01-28 8:11 ` Aswath Govindraju
2022-02-08 17:35 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 14/25] dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode Aswath Govindraju
` (11 subsequent siblings)
24 siblings, 1 reply; 51+ messages in thread
From: Aswath Govindraju @ 2022-01-28 8:11 UTC (permalink / raw)
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra,
Aswath Govindraju
From: Swapnil Jakhade <sjakhade@cadence.com>
Sierra driver currently supports single link configurations only. Prepare
driver to support multilink multiprotocol configurations along with
different SSC modes.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
---
drivers/phy/cadence/phy-cadence-sierra.c | 188 ++++++++++++++++-------
1 file changed, 135 insertions(+), 53 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index 7e52a19f0dae..745c34088a5b 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -28,6 +28,9 @@
#include <dt-bindings/phy/phy-cadence.h>
#include <regmap.h>
+#define NUM_SSC_MODE 3
+#define NUM_PHY_TYPE 3
+
/* PHY register offsets */
#define SIERRA_COMMON_CDB_OFFSET 0x0
#define SIERRA_MACRO_ID_REG 0x0
@@ -214,8 +217,20 @@ struct cdns_sierra_pll_mux {
#define reset_control_deassert(rst) cdns_reset_deassert(rst)
#define reset_control reset_ctl
+enum cdns_sierra_phy_type {
+ TYPE_NONE,
+ TYPE_PCIE,
+ TYPE_USB
+};
+
+enum cdns_sierra_ssc_mode {
+ NO_SSC,
+ EXTERNAL_SSC,
+ INTERNAL_SSC
+};
+
struct cdns_sierra_inst {
- u32 phy_type;
+ enum cdns_sierra_phy_type phy_type;
u32 num_lanes;
u32 mlane;
struct reset_ctl_bulk *lnk_rst;
@@ -226,18 +241,19 @@ struct cdns_reg_pairs {
u32 off;
};
+struct cdns_sierra_vals {
+ const struct cdns_reg_pairs *reg_pairs;
+ u32 num_regs;
+};
+
struct cdns_sierra_data {
u32 id_value;
u8 block_offset_shift;
u8 reg_offset_shift;
- u32 pcie_cmn_regs;
- u32 pcie_ln_regs;
- u32 usb_cmn_regs;
- u32 usb_ln_regs;
- struct cdns_reg_pairs *pcie_cmn_vals;
- struct cdns_reg_pairs *pcie_ln_vals;
- struct cdns_reg_pairs *usb_cmn_vals;
- struct cdns_reg_pairs *usb_ln_vals;
+ struct cdns_sierra_vals *pma_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
+ [NUM_SSC_MODE];
+ struct cdns_sierra_vals *pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
+ [NUM_SSC_MODE];
};
struct cdns_sierra_phy {
@@ -299,10 +315,14 @@ static int cdns_sierra_phy_init(struct phy *gphy)
{
struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
struct cdns_sierra_phy *phy = dev_get_priv(gphy->dev);
+ struct cdns_sierra_data *init_data = phy->init_data;
+ struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals;
+ enum cdns_sierra_phy_type phy_type = ins->phy_type;
+ enum cdns_sierra_ssc_mode ssc = EXTERNAL_SSC;
+ const struct cdns_reg_pairs *reg_pairs;
struct regmap *regmap = phy->regmap;
+ u32 num_regs;
int i, j;
- struct cdns_reg_pairs *cmn_vals, *ln_vals;
- u32 num_cmn_regs, num_ln_regs;
/* Initialise the PHY registers, unless auto configured */
if (phy->autoconf)
@@ -311,28 +331,25 @@ static int cdns_sierra_phy_init(struct phy *gphy)
clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 25000000);
clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 25000000);
- if (ins->phy_type == PHY_TYPE_PCIE) {
- num_cmn_regs = phy->init_data->pcie_cmn_regs;
- num_ln_regs = phy->init_data->pcie_ln_regs;
- cmn_vals = phy->init_data->pcie_cmn_vals;
- ln_vals = phy->init_data->pcie_ln_vals;
- } else if (ins->phy_type == PHY_TYPE_USB3) {
- num_cmn_regs = phy->init_data->usb_cmn_regs;
- num_ln_regs = phy->init_data->usb_ln_regs;
- cmn_vals = phy->init_data->usb_cmn_vals;
- ln_vals = phy->init_data->usb_ln_vals;
- } else {
- return -EINVAL;
+ /* PMA common registers configurations */
+ pma_cmn_vals = init_data->pma_cmn_vals[phy_type][TYPE_NONE][ssc];
+ if (pma_cmn_vals) {
+ reg_pairs = pma_cmn_vals->reg_pairs;
+ num_regs = pma_cmn_vals->num_regs;
+ regmap = phy->regmap_common_cdb;
+ for (i = 0; i < num_regs; i++)
+ regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val);
}
- regmap = phy->regmap_common_cdb;
- for (j = 0; j < num_cmn_regs ; j++)
- regmap_write(regmap, cmn_vals[j].off, cmn_vals[j].val);
-
- for (i = 0; i < ins->num_lanes; i++) {
- for (j = 0; j < num_ln_regs ; j++) {
+ /* PMA TX lane registers configurations */
+ pma_ln_vals = init_data->pma_ln_vals[phy_type][TYPE_NONE][ssc];
+ if (pma_ln_vals) {
+ reg_pairs = pma_ln_vals->reg_pairs;
+ num_regs = pma_ln_vals->num_regs;
+ for (i = 0; i < ins->num_lanes; i++) {
regmap = phy->regmap_lane_cdb[i + ins->mlane];
- regmap_write(regmap, ln_vals[j].off, ln_vals[j].val);
+ for (j = 0; j < num_regs; j++)
+ regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val);
}
}
@@ -507,15 +524,28 @@ static int cdns_sierra_pll_bind_of_clocks(struct cdns_sierra_phy *sp)
static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst,
ofnode child)
{
+ u32 phy_type;
+
if (ofnode_read_u32(child, "reg", &inst->mlane))
return -EINVAL;
if (ofnode_read_u32(child, "cdns,num-lanes", &inst->num_lanes))
return -EINVAL;
- if (ofnode_read_u32(child, "cdns,phy-type", &inst->phy_type))
+ if (ofnode_read_u32(child, "cdns,phy-type", &phy_type))
return -EINVAL;
+ switch (phy_type) {
+ case PHY_TYPE_PCIE:
+ inst->phy_type = TYPE_PCIE;
+ break;
+ case PHY_TYPE_USB3:
+ inst->phy_type = TYPE_USB;
+ break;
+ default:
+ return -EINVAL;
+ }
+
return 0;
}
@@ -873,6 +903,16 @@ static struct cdns_reg_pairs cdns_pcie_ln_regs_ext_ssc[] = {
{0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}
};
+static struct cdns_sierra_vals pcie_100_ext_ssc_cmn_vals = {
+ .reg_pairs = cdns_pcie_cmn_regs_ext_ssc,
+ .num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc),
+};
+
+static struct cdns_sierra_vals pcie_100_ext_ssc_ln_vals = {
+ .reg_pairs = cdns_pcie_ln_regs_ext_ssc,
+ .num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc),
+};
+
/* refclk100MHz_20b_USB_cmn_pll_ext_ssc */
static struct cdns_reg_pairs cdns_usb_cmn_regs_ext_ssc[] = {
{0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
@@ -980,32 +1020,74 @@ static struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = {
{0x4243, SIERRA_RXBUFFER_DFECTRL_PREG}
};
+static struct cdns_sierra_vals usb_100_ext_ssc_cmn_vals = {
+ .reg_pairs = cdns_usb_cmn_regs_ext_ssc,
+ .num_regs = ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc),
+};
+
+static struct cdns_sierra_vals usb_100_ext_ssc_ln_vals = {
+ .reg_pairs = cdns_usb_ln_regs_ext_ssc,
+ .num_regs = ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc),
+};
+
static const struct cdns_sierra_data cdns_map_sierra = {
- SIERRA_MACRO_ID,
- 0x2,
- 0x2,
- ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc),
- ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc),
- ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc),
- ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc),
- cdns_pcie_cmn_regs_ext_ssc,
- cdns_pcie_ln_regs_ext_ssc,
- cdns_usb_cmn_regs_ext_ssc,
- cdns_usb_ln_regs_ext_ssc,
+ .id_value = SIERRA_MACRO_ID,
+ .block_offset_shift = 0x2,
+ .reg_offset_shift = 0x2,
+ .pma_cmn_vals = {
+ [TYPE_PCIE] = {
+ [TYPE_NONE] = {
+ [EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals,
+ },
+ },
+ [TYPE_USB] = {
+ [TYPE_NONE] = {
+ [EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals,
+ },
+ },
+ },
+ .pma_ln_vals = {
+ [TYPE_PCIE] = {
+ [TYPE_NONE] = {
+ [EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals,
+ },
+ },
+ [TYPE_USB] = {
+ [TYPE_NONE] = {
+ [EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals,
+ },
+ },
+ },
};
static const struct cdns_sierra_data cdns_ti_map_sierra = {
- SIERRA_MACRO_ID,
- 0x0,
- 0x1,
- ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc),
- ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc),
- ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc),
- ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc),
- cdns_pcie_cmn_regs_ext_ssc,
- cdns_pcie_ln_regs_ext_ssc,
- cdns_usb_cmn_regs_ext_ssc,
- cdns_usb_ln_regs_ext_ssc,
+ .id_value = SIERRA_MACRO_ID,
+ .block_offset_shift = 0x0,
+ .reg_offset_shift = 0x1,
+ .pma_cmn_vals = {
+ [TYPE_PCIE] = {
+ [TYPE_NONE] = {
+ [EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals,
+ },
+ },
+ [TYPE_USB] = {
+ [TYPE_NONE] = {
+ [EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals,
+ },
+ },
+ },
+ .pma_ln_vals = {
+ [TYPE_PCIE] = {
+ [TYPE_NONE] = {
+ [EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals,
+ },
+ },
+ [TYPE_USB] = {
+ [TYPE_NONE] = {
+ [EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals,
+ },
+ },
+ },
};
static const struct udevice_id cdns_sierra_id_table[] = {
--
2.17.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 14/25] dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode
2022-01-28 8:11 [PATCH v2 00/25] SIERRA: Add support for Mulitlink Configuration Aswath Govindraju
` (12 preceding siblings ...)
2022-01-28 8:11 ` [PATCH v2 13/25] phy: cadence: Sierra: Prepare driver to add support for multilink configurations Aswath Govindraju
@ 2022-01-28 8:11 ` Aswath Govindraju
2022-02-08 17:35 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 15/25] phy: cadence: Sierra: Add support to get SSC type from device tree Aswath Govindraju
` (10 subsequent siblings)
24 siblings, 1 reply; 51+ messages in thread
From: Aswath Govindraju @ 2022-01-28 8:11 UTC (permalink / raw)
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra,
Aswath Govindraju
From: Swapnil Jakhade <sjakhade@cadence.com>
Add binding to specify Spread Spectrum Clocking mode used
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
---
include/dt-bindings/phy/phy-cadence.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/include/dt-bindings/phy/phy-cadence.h b/include/dt-bindings/phy/phy-cadence.h
index 4652bcb86265..0122c6067b17 100644
--- a/include/dt-bindings/phy/phy-cadence.h
+++ b/include/dt-bindings/phy/phy-cadence.h
@@ -17,4 +17,8 @@
#define CDNS_SIERRA_PLL_CMNLC 0
#define CDNS_SIERRA_PLL_CMNLC1 1
+#define SIERRA_SERDES_NO_SSC 0
+#define SIERRA_SERDES_EXTERNAL_SSC 1
+#define SIERRA_SERDES_INTERNAL_SSC 2
+
#endif /* _DT_BINDINGS_CADENCE_SERDES_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 15/25] phy: cadence: Sierra: Add support to get SSC type from device tree.
2022-01-28 8:11 [PATCH v2 00/25] SIERRA: Add support for Mulitlink Configuration Aswath Govindraju
` (13 preceding siblings ...)
2022-01-28 8:11 ` [PATCH v2 14/25] dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode Aswath Govindraju
@ 2022-01-28 8:11 ` Aswath Govindraju
2022-02-08 17:35 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 16/25] phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra documentation Aswath Govindraju
` (9 subsequent siblings)
24 siblings, 1 reply; 51+ messages in thread
From: Aswath Govindraju @ 2022-01-28 8:11 UTC (permalink / raw)
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra,
Aswath Govindraju
From: Swapnil Jakhade <sjakhade@cadence.com>
Add support to get SSC type from DT.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
---
drivers/phy/cadence/phy-cadence-sierra.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index 745c34088a5b..e2f631e330da 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -234,6 +234,7 @@ struct cdns_sierra_inst {
u32 num_lanes;
u32 mlane;
struct reset_ctl_bulk *lnk_rst;
+ enum cdns_sierra_ssc_mode ssc_mode;
};
struct cdns_reg_pairs {
@@ -318,7 +319,7 @@ static int cdns_sierra_phy_init(struct phy *gphy)
struct cdns_sierra_data *init_data = phy->init_data;
struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals;
enum cdns_sierra_phy_type phy_type = ins->phy_type;
- enum cdns_sierra_ssc_mode ssc = EXTERNAL_SSC;
+ enum cdns_sierra_ssc_mode ssc = ins->ssc_mode;
const struct cdns_reg_pairs *reg_pairs;
struct regmap *regmap = phy->regmap;
u32 num_regs;
@@ -546,6 +547,9 @@ static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst,
return -EINVAL;
}
+ inst->ssc_mode = EXTERNAL_SSC;
+ ofnode_read_u32(child, "cdns,ssc-mode", &inst->ssc_mode);
+
return 0;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 16/25] phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra documentation
2022-01-28 8:11 [PATCH v2 00/25] SIERRA: Add support for Mulitlink Configuration Aswath Govindraju
` (14 preceding siblings ...)
2022-01-28 8:11 ` [PATCH v2 15/25] phy: cadence: Sierra: Add support to get SSC type from device tree Aswath Govindraju
@ 2022-01-28 8:11 ` Aswath Govindraju
2022-02-08 17:35 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 17/25] phy: cadence: Sierra: Add PHY PCS common register configurations Aswath Govindraju
` (8 subsequent siblings)
24 siblings, 1 reply; 51+ messages in thread
From: Aswath Govindraju @ 2022-01-28 8:11 UTC (permalink / raw)
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra,
Aswath Govindraju
From: Swapnil Jakhade <sjakhade@cadence.com>
No functional change. Rename some regmap variables as mentioned in Sierra
register description documentation.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
---
drivers/phy/cadence/phy-cadence-sierra.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index e2f631e330da..951344f5ace5 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -149,7 +149,7 @@
#define SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG 0x14F
#define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150
-#define SIERRA_PHY_CONFIG_CTRL_OFFSET 0xc000
+#define SIERRA_PHY_PCS_COMMON_OFFSET 0xc000
#define SIERRA_PHY_PLL_CFG 0xe
#define SIERRA_MACRO_ID 0x00007364
@@ -266,7 +266,7 @@ struct cdns_sierra_phy {
struct cdns_sierra_inst *phys[SIERRA_MAX_LANES];
struct reset_control *phy_rst;
struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES];
- struct regmap *regmap_phy_config_ctrl;
+ struct regmap *regmap_phy_pcs_common_cdb;
struct regmap *regmap_common_cdb;
struct regmap_field *macro_id_type;
struct regmap_field *phy_pll_cfg_1;
@@ -610,7 +610,7 @@ static int cdns_regfield_init(struct cdns_sierra_phy *sp)
sp->cmn_refrcv_refclk_termen_preg[i] = field;
}
- regmap = sp->regmap_phy_config_ctrl;
+ regmap = sp->regmap_phy_pcs_common_cdb;
field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1);
if (IS_ERR(field)) {
dev_err(dev, "PHY_PLL_CFG_1 reg field init failed\n");
@@ -659,13 +659,13 @@ static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp,
}
sp->regmap_common_cdb = regmap;
- regmap = cdns_regmap_init(dev, base, SIERRA_PHY_CONFIG_CTRL_OFFSET,
+ regmap = cdns_regmap_init(dev, base, SIERRA_PHY_PCS_COMMON_OFFSET,
block_offset_shift, reg_offset_shift);
if (IS_ERR(regmap)) {
- dev_err(dev, "Failed to init PHY config and control regmap\n");
+ dev_err(dev, "Failed to init PHY PCS common CDB regmap\n");
return PTR_ERR(regmap);
}
- sp->regmap_phy_config_ctrl = regmap;
+ sp->regmap_phy_pcs_common_cdb = regmap;
return 0;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 17/25] phy: cadence: Sierra: Add PHY PCS common register configurations
2022-01-28 8:11 [PATCH v2 00/25] SIERRA: Add support for Mulitlink Configuration Aswath Govindraju
` (15 preceding siblings ...)
2022-01-28 8:11 ` [PATCH v2 16/25] phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra documentation Aswath Govindraju
@ 2022-01-28 8:11 ` Aswath Govindraju
2022-02-08 17:35 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 18/25] phy: cadence: Sierra: Check cmn_ready assertion during PHY power on Aswath Govindraju
` (7 subsequent siblings)
24 siblings, 1 reply; 51+ messages in thread
From: Aswath Govindraju @ 2022-01-28 8:11 UTC (permalink / raw)
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra,
Aswath Govindraju
From: Swapnil Jakhade <sjakhade@cadence.com>
Add PHY PCS common register configuration sequences for single link.
Update single link PCIe register sequence accordingly.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
---
drivers/phy/cadence/phy-cadence-sierra.c | 38 ++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index 951344f5ace5..9267293703c3 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -150,6 +150,7 @@
#define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150
#define SIERRA_PHY_PCS_COMMON_OFFSET 0xc000
+#define SIERRA_PHY_PIPE_CMN_CTRL1 0x0
#define SIERRA_PHY_PLL_CFG 0xe
#define SIERRA_MACRO_ID 0x00007364
@@ -251,6 +252,8 @@ struct cdns_sierra_data {
u32 id_value;
u8 block_offset_shift;
u8 reg_offset_shift;
+ struct cdns_sierra_vals *pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
+ [NUM_SSC_MODE];
struct cdns_sierra_vals *pma_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
[NUM_SSC_MODE];
struct cdns_sierra_vals *pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
@@ -321,6 +324,7 @@ static int cdns_sierra_phy_init(struct phy *gphy)
enum cdns_sierra_phy_type phy_type = ins->phy_type;
enum cdns_sierra_ssc_mode ssc = ins->ssc_mode;
const struct cdns_reg_pairs *reg_pairs;
+ struct cdns_sierra_vals *pcs_cmn_vals;
struct regmap *regmap = phy->regmap;
u32 num_regs;
int i, j;
@@ -332,6 +336,16 @@ static int cdns_sierra_phy_init(struct phy *gphy)
clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 25000000);
clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 25000000);
+ /* PHY PCS common registers configurations */
+ pcs_cmn_vals = init_data->pcs_cmn_vals[phy_type][TYPE_NONE][ssc];
+ if (pcs_cmn_vals) {
+ reg_pairs = pcs_cmn_vals->reg_pairs;
+ num_regs = pcs_cmn_vals->num_regs;
+ regmap = phy->regmap_phy_pcs_common_cdb;
+ for (i = 0; i < num_regs; i++)
+ regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val);
+ }
+
/* PMA common registers configurations */
pma_cmn_vals = init_data->pma_cmn_vals[phy_type][TYPE_NONE][ssc];
if (pma_cmn_vals) {
@@ -887,6 +901,16 @@ static int cdns_sierra_phy_remove(struct udevice *dev)
return 0;
}
+/* PCIE PHY PCS common configuration */
+static struct cdns_reg_pairs pcie_phy_pcs_cmn_regs[] = {
+ {0x0430, SIERRA_PHY_PIPE_CMN_CTRL1}
+};
+
+static struct cdns_sierra_vals pcie_phy_pcs_cmn_vals = {
+ .reg_pairs = pcie_phy_pcs_cmn_regs,
+ .num_regs = ARRAY_SIZE(pcie_phy_pcs_cmn_regs),
+};
+
/* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc */
static struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = {
{0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
@@ -1038,6 +1062,13 @@ static const struct cdns_sierra_data cdns_map_sierra = {
.id_value = SIERRA_MACRO_ID,
.block_offset_shift = 0x2,
.reg_offset_shift = 0x2,
+ .pcs_cmn_vals = {
+ [TYPE_PCIE] = {
+ [TYPE_NONE] = {
+ [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
+ },
+ },
+ },
.pma_cmn_vals = {
[TYPE_PCIE] = {
[TYPE_NONE] = {
@@ -1068,6 +1099,13 @@ static const struct cdns_sierra_data cdns_ti_map_sierra = {
.id_value = SIERRA_MACRO_ID,
.block_offset_shift = 0x0,
.reg_offset_shift = 0x1,
+ .pcs_cmn_vals = {
+ [TYPE_PCIE] = {
+ [TYPE_NONE] = {
+ [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
+ },
+ },
+ },
.pma_cmn_vals = {
[TYPE_PCIE] = {
[TYPE_NONE] = {
--
2.17.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 18/25] phy: cadence: Sierra: Check cmn_ready assertion during PHY power on
2022-01-28 8:11 [PATCH v2 00/25] SIERRA: Add support for Mulitlink Configuration Aswath Govindraju
` (16 preceding siblings ...)
2022-01-28 8:11 ` [PATCH v2 17/25] phy: cadence: Sierra: Add PHY PCS common register configurations Aswath Govindraju
@ 2022-01-28 8:11 ` Aswath Govindraju
2022-02-08 17:35 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 19/25] phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation Aswath Govindraju
` (6 subsequent siblings)
24 siblings, 1 reply; 51+ messages in thread
From: Aswath Govindraju @ 2022-01-28 8:11 UTC (permalink / raw)
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra,
Aswath Govindraju
From: Swapnil Jakhade <sjakhade@cadence.com>
Check if PMA cmn_ready is set indicating the startup process is complete.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
---
drivers/phy/cadence/phy-cadence-sierra.c | 35 ++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index 9267293703c3..df31fb3f19a3 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -153,6 +153,10 @@
#define SIERRA_PHY_PIPE_CMN_CTRL1 0x0
#define SIERRA_PHY_PLL_CFG 0xe
+/* PHY PMA common registers */
+#define SIERRA_PHY_PMA_COMMON_OFFSET 0xe000
+#define SIERRA_PHY_PMA_CMN_CTRL 0x0
+
#define SIERRA_MACRO_ID 0x00007364
#define SIERRA_MAX_LANES 16
#define PLL_LOCK_TIME 100
@@ -173,6 +177,8 @@ static const struct reg_field macro_id_type =
REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15);
static const struct reg_field phy_pll_cfg_1 =
REG_FIELD(SIERRA_PHY_PLL_CFG, 1, 1);
+static const struct reg_field pma_cmn_ready =
+ REG_FIELD(SIERRA_PHY_PMA_CMN_CTRL, 0, 0);
static const struct reg_field pllctrl_lock =
REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0);
@@ -270,9 +276,11 @@ struct cdns_sierra_phy {
struct reset_control *phy_rst;
struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES];
struct regmap *regmap_phy_pcs_common_cdb;
+ struct regmap *regmap_phy_pma_common_cdb;
struct regmap *regmap_common_cdb;
struct regmap_field *macro_id_type;
struct regmap_field *phy_pll_cfg_1;
+ struct regmap_field *pma_cmn_ready;
struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES];
struct regmap_field *cmn_refrcv_refclk_plllc1en_preg[SIERRA_NUM_CMN_PLLC];
struct regmap_field *cmn_refrcv_refclk_termen_preg[SIERRA_NUM_CMN_PLLC];
@@ -392,6 +400,17 @@ static int cdns_sierra_phy_on(struct phy *gphy)
return ret;
}
+ /*
+ * Wait for cmn_ready assertion
+ * PHY_PMA_CMN_CTRL[0] == 1
+ */
+ ret = regmap_field_read_poll_timeout(sp->pma_cmn_ready, val, val,
+ 1000, PLL_LOCK_TIME);
+ if (ret) {
+ dev_err(dev, "Timeout waiting for CMN ready\n");
+ return ret;
+ }
+
ret = regmap_field_read_poll_timeout(sp->pllctrl_lock[ins->mlane],
val, val, 1000, PLL_LOCK_TIME);
if (ret < 0)
@@ -632,6 +651,14 @@ static int cdns_regfield_init(struct cdns_sierra_phy *sp)
}
sp->phy_pll_cfg_1 = field;
+ regmap = sp->regmap_phy_pma_common_cdb;
+ field = devm_regmap_field_alloc(dev, regmap, pma_cmn_ready);
+ if (IS_ERR(field)) {
+ dev_err(dev, "PHY_PMA_CMN_CTRL reg field init failed\n");
+ return PTR_ERR(field);
+ }
+ sp->pma_cmn_ready = field;
+
for (i = 0; i < SIERRA_MAX_LANES; i++) {
regmap = sp->regmap_lane_cdb[i];
field = devm_regmap_field_alloc(dev, regmap, pllctrl_lock);
@@ -681,6 +708,14 @@ static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp,
}
sp->regmap_phy_pcs_common_cdb = regmap;
+ regmap = cdns_regmap_init(dev, base, SIERRA_PHY_PMA_COMMON_OFFSET,
+ block_offset_shift, reg_offset_shift);
+ if (IS_ERR(regmap)) {
+ dev_err(dev, "Failed to init PHY PMA common CDB regmap\n");
+ return PTR_ERR(regmap);
+ }
+ sp->regmap_phy_pma_common_cdb = regmap;
+
return 0;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 19/25] phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation
2022-01-28 8:11 [PATCH v2 00/25] SIERRA: Add support for Mulitlink Configuration Aswath Govindraju
` (17 preceding siblings ...)
2022-01-28 8:11 ` [PATCH v2 18/25] phy: cadence: Sierra: Check cmn_ready assertion during PHY power on Aswath Govindraju
@ 2022-01-28 8:11 ` Aswath Govindraju
2022-02-08 17:35 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 20/25] phy: cadence: Sierra: Update single link PCIe register configuration Aswath Govindraju
` (5 subsequent siblings)
24 siblings, 1 reply; 51+ messages in thread
From: Aswath Govindraju @ 2022-01-28 8:11 UTC (permalink / raw)
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra,
Aswath Govindraju
From: Swapnil Jakhade <sjakhade@cadence.com>
PIPE phy status is used to communicate the completion of several PHY
functions. Check if PHY is ready for operation while configured for
PIPE mode during startup.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
---
drivers/phy/cadence/phy-cadence-sierra.c | 41 +++++++++++++++++++++++-
1 file changed, 40 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index df31fb3f19a3..8518594b266b 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -157,6 +157,11 @@
#define SIERRA_PHY_PMA_COMMON_OFFSET 0xe000
#define SIERRA_PHY_PMA_CMN_CTRL 0x0
+/* PHY PCS lane registers */
+#define SIERRA_PHY_PCS_LANE_CDB_OFFSET(ln, offset) \
+ (0xD000 + ((ln) * (0x800 >> (3 - (offset)))))
+#define SIERRA_PHY_ISO_LINK_CTRL 0xB
+
#define SIERRA_MACRO_ID 0x00007364
#define SIERRA_MAX_LANES 16
#define PLL_LOCK_TIME 100
@@ -181,6 +186,8 @@ static const struct reg_field pma_cmn_ready =
REG_FIELD(SIERRA_PHY_PMA_CMN_CTRL, 0, 0);
static const struct reg_field pllctrl_lock =
REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0);
+static const struct reg_field phy_iso_link_ctrl_1 =
+ REG_FIELD(SIERRA_PHY_ISO_LINK_CTRL, 1, 1);
static const char * const clk_names[] = {
[CDNS_SIERRA_PLL_CMNLC] = "pll_cmnlc",
@@ -276,6 +283,7 @@ struct cdns_sierra_phy {
struct reset_control *phy_rst;
struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES];
struct regmap *regmap_phy_pcs_common_cdb;
+ struct regmap *regmap_phy_pcs_lane_cdb[SIERRA_MAX_LANES];
struct regmap *regmap_phy_pma_common_cdb;
struct regmap *regmap_common_cdb;
struct regmap_field *macro_id_type;
@@ -286,6 +294,7 @@ struct cdns_sierra_phy {
struct regmap_field *cmn_refrcv_refclk_termen_preg[SIERRA_NUM_CMN_PLLC];
struct regmap_field *cmn_plllc_pfdclk1_sel_preg[SIERRA_NUM_CMN_PLLC];
struct clk *input_clks[CDNS_SIERRA_INPUT_CLOCKS];
+ struct regmap_field *phy_iso_link_ctrl_1[SIERRA_MAX_LANES];
int nsubnodes;
u32 num_lanes;
bool autoconf;
@@ -400,6 +409,15 @@ static int cdns_sierra_phy_on(struct phy *gphy)
return ret;
}
+ if (ins->phy_type == TYPE_PCIE || ins->phy_type == TYPE_USB) {
+ ret = regmap_field_read_poll_timeout(sp->phy_iso_link_ctrl_1[ins->mlane],
+ val, !val, 1000, PLL_LOCK_TIME);
+ if (ret) {
+ dev_err(dev, "Timeout waiting for PHY status ready\n");
+ return ret;
+ }
+ }
+
/*
* Wait for cmn_ready assertion
* PHY_PMA_CMN_CTRL[0] == 1
@@ -666,7 +684,17 @@ static int cdns_regfield_init(struct cdns_sierra_phy *sp)
dev_err(dev, "P%d_ENABLE reg field init failed\n", i);
return PTR_ERR(field);
}
- sp->pllctrl_lock[i] = field;
+ sp->pllctrl_lock[i] = field;
+ }
+
+ for (i = 0; i < SIERRA_MAX_LANES; i++) {
+ regmap = sp->regmap_phy_pcs_lane_cdb[i];
+ field = devm_regmap_field_alloc(dev, regmap, phy_iso_link_ctrl_1);
+ if (IS_ERR(field)) {
+ dev_err(dev, "PHY_ISO_LINK_CTRL reg field init for lane %d failed\n", i);
+ return PTR_ERR(field);
+ }
+ sp->phy_iso_link_ctrl_1[i] = field;
}
return 0;
@@ -708,6 +736,17 @@ static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp,
}
sp->regmap_phy_pcs_common_cdb = regmap;
+ for (i = 0; i < SIERRA_MAX_LANES; i++) {
+ block_offset = SIERRA_PHY_PCS_LANE_CDB_OFFSET(i, reg_offset_shift);
+ regmap = cdns_regmap_init(dev, base, block_offset,
+ block_offset_shift, reg_offset_shift);
+ if (IS_ERR(regmap)) {
+ dev_err(dev, "Failed to init PHY PCS lane CDB regmap\n");
+ return PTR_ERR(regmap);
+ }
+ sp->regmap_phy_pcs_lane_cdb[i] = regmap;
+ }
+
regmap = cdns_regmap_init(dev, base, SIERRA_PHY_PMA_COMMON_OFFSET,
block_offset_shift, reg_offset_shift);
if (IS_ERR(regmap)) {
--
2.17.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 20/25] phy: cadence: Sierra: Update single link PCIe register configuration
2022-01-28 8:11 [PATCH v2 00/25] SIERRA: Add support for Mulitlink Configuration Aswath Govindraju
` (18 preceding siblings ...)
2022-01-28 8:11 ` [PATCH v2 19/25] phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation Aswath Govindraju
@ 2022-01-28 8:11 ` Aswath Govindraju
2022-02-08 17:35 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 21/25] phy: cadence: Sierra: Add support for PHY multilink configurations Aswath Govindraju
` (4 subsequent siblings)
24 siblings, 1 reply; 51+ messages in thread
From: Aswath Govindraju @ 2022-01-28 8:11 UTC (permalink / raw)
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra,
Aswath Govindraju
From: Swapnil Jakhade <sjakhade@cadence.com>
Add single link PCIe register configurations for no SSC and internal
SSC. Also, add missing PMA lane registers for external SSC.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
---
drivers/phy/cadence/phy-cadence-sierra.c | 218 ++++++++++++++++++++++-
1 file changed, 215 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index 8518594b266b..54d316d4ec41 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -41,10 +41,15 @@
#define SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG 0x4B
#define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG 0x4F
#define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG 0x50
+#define SIERRA_CMN_PLLLC_DSMCORR_PREG 0x51
+#define SIERRA_CMN_PLLLC_SS_PREG 0x52
+#define SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG 0x53
+#define SIERRA_CMN_PLLLC_SSTWOPT_PREG 0x54
#define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG 0x62
#define SIERRA_CMN_REFRCV_PREG 0x98
#define SIERRA_CMN_REFRCV1_PREG 0xB8
#define SIERRA_CMN_PLLLC1_GEN_PREG 0xC2
+#define SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG 0x63
#define SIERRA_LANE_CDB_OFFSET(ln, offset) \
(0x4000 + ((ln) * (0x800 >> (2 - (offset)))))
@@ -56,6 +61,7 @@
#define SIERRA_DET_STANDEC_E_PREG 0x004
#define SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG 0x008
#define SIERRA_PSM_A0IN_TMR_PREG 0x009
+#define SIERRA_PSM_A3IN_TMR_PREG 0x00C
#define SIERRA_PSM_DIAG_PREG 0x015
#define SIERRA_PSC_TX_A0_PREG 0x028
#define SIERRA_PSC_TX_A1_PREG 0x029
@@ -72,12 +78,15 @@
#define SIERRA_CLKPATH_BIASTRIM_PREG 0x04B
#define SIERRA_DFE_BIASTRIM_PREG 0x04C
#define SIERRA_DRVCTRL_ATTEN_PREG 0x06A
+#define SIERRA_DRVCTRL_BOOST_PREG 0x06F
#define SIERRA_CLKPATHCTRL_TMR_PREG 0x081
#define SIERRA_RX_CREQ_FLTR_A_MODE3_PREG 0x085
#define SIERRA_RX_CREQ_FLTR_A_MODE2_PREG 0x086
#define SIERRA_RX_CREQ_FLTR_A_MODE1_PREG 0x087
#define SIERRA_RX_CREQ_FLTR_A_MODE0_PREG 0x088
+#define SIERRA_CREQ_DCBIASATTEN_OVR_PREG 0x08C
#define SIERRA_CREQ_CCLKDET_MODE01_PREG 0x08E
+#define SIERRA_RX_CTLE_CAL_PREG 0x08F
#define SIERRA_RX_CTLE_MAINTENANCE_PREG 0x091
#define SIERRA_CREQ_FSMCLK_SEL_PREG 0x092
#define SIERRA_CREQ_EQ_CTRL_PREG 0x093
@@ -127,15 +136,27 @@
#define SIERRA_DEQ_ALUT12 0x114
#define SIERRA_DEQ_ALUT13 0x115
#define SIERRA_DEQ_DFETAP_CTRL_PREG 0x128
+#define SIERRA_DEQ_DFETAP0 0x129
+#define SIERRA_DEQ_DFETAP1 0x12B
+#define SIERRA_DEQ_DFETAP2 0x12D
+#define SIERRA_DEQ_DFETAP3 0x12F
+#define SIERRA_DEQ_DFETAP4 0x131
#define SIERRA_DFE_EN_1010_IGNORE_PREG 0x134
+#define SIERRA_DEQ_PRECUR_PREG 0x138
+#define SIERRA_DEQ_POSTCUR_PREG 0x140
+#define SIERRA_DEQ_POSTCUR_DECR_PREG 0x142
#define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150
#define SIERRA_DEQ_TAU_CTRL2_PREG 0x151
+#define SIERRA_DEQ_TAU_CTRL3_PREG 0x152
+#define SIERRA_DEQ_OPENEYE_CTRL_PREG 0x158
#define SIERRA_DEQ_PICTRL_PREG 0x161
#define SIERRA_CPICAL_TMRVAL_MODE1_PREG 0x170
#define SIERRA_CPICAL_TMRVAL_MODE0_PREG 0x171
#define SIERRA_CPICAL_PICNT_MODE1_PREG 0x174
#define SIERRA_CPI_OUTBUF_RATESEL_PREG 0x17C
+#define SIERRA_CPI_TRIM_PREG 0x17F
#define SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG 0x183
+#define SIERRA_EPI_CTRL_PREG 0x187
#define SIERRA_LFPSDET_SUPPORT_PREG 0x188
#define SIERRA_LFPSFILT_NS_PREG 0x18A
#define SIERRA_LFPSFILT_RD_PREG 0x18B
@@ -985,6 +1006,146 @@ static struct cdns_sierra_vals pcie_phy_pcs_cmn_vals = {
.num_regs = ARRAY_SIZE(pcie_phy_pcs_cmn_regs),
};
+/* refclk100MHz_32b_PCIe_cmn_pll_no_ssc */
+static const struct cdns_reg_pairs cdns_pcie_cmn_regs_no_ssc[] = {
+ {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
+ {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
+ {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
+ {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}
+};
+
+/* refclk100MHz_32b_PCIe_ln_no_ssc */
+static const struct cdns_reg_pairs cdns_pcie_ln_regs_no_ssc[] = {
+ {0xFC08, SIERRA_DET_STANDEC_A_PREG},
+ {0x001D, SIERRA_PSM_A3IN_TMR_PREG},
+ {0x1555, SIERRA_DFE_BIASTRIM_PREG},
+ {0x9703, SIERRA_DRVCTRL_BOOST_PREG},
+ {0x8055, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
+ {0x80BB, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
+ {0x8351, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
+ {0x8349, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
+ {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
+ {0x9800, SIERRA_RX_CTLE_CAL_PREG},
+ {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
+ {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
+ {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
+ {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
+ {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
+ {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
+ {0x0041, SIERRA_DEQ_GLUT0},
+ {0x0082, SIERRA_DEQ_GLUT1},
+ {0x00C3, SIERRA_DEQ_GLUT2},
+ {0x0145, SIERRA_DEQ_GLUT3},
+ {0x0186, SIERRA_DEQ_GLUT4},
+ {0x09E7, SIERRA_DEQ_ALUT0},
+ {0x09A6, SIERRA_DEQ_ALUT1},
+ {0x0965, SIERRA_DEQ_ALUT2},
+ {0x08E3, SIERRA_DEQ_ALUT3},
+ {0x00FA, SIERRA_DEQ_DFETAP0},
+ {0x00FA, SIERRA_DEQ_DFETAP1},
+ {0x00FA, SIERRA_DEQ_DFETAP2},
+ {0x00FA, SIERRA_DEQ_DFETAP3},
+ {0x00FA, SIERRA_DEQ_DFETAP4},
+ {0x000F, SIERRA_DEQ_PRECUR_PREG},
+ {0x0280, SIERRA_DEQ_POSTCUR_PREG},
+ {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
+ {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
+ {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
+ {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
+ {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
+ {0x002B, SIERRA_CPI_TRIM_PREG},
+ {0x0003, SIERRA_EPI_CTRL_PREG},
+ {0x803F, SIERRA_SDFILT_H2L_A_PREG},
+ {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
+ {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
+ {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}
+};
+
+static struct cdns_sierra_vals pcie_100_no_ssc_cmn_vals = {
+ .reg_pairs = cdns_pcie_cmn_regs_no_ssc,
+ .num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_no_ssc),
+};
+
+static struct cdns_sierra_vals pcie_100_no_ssc_ln_vals = {
+ .reg_pairs = cdns_pcie_ln_regs_no_ssc,
+ .num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_no_ssc),
+};
+
+/* refclk100MHz_32b_PCIe_cmn_pll_int_ssc */
+static const struct cdns_reg_pairs cdns_pcie_cmn_regs_int_ssc[] = {
+ {0x000E, SIERRA_CMN_PLLLC_MODE_PREG},
+ {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
+ {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
+ {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
+ {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
+ {0x0581, SIERRA_CMN_PLLLC_DSMCORR_PREG},
+ {0x7F80, SIERRA_CMN_PLLLC_SS_PREG},
+ {0x0041, SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG},
+ {0x0464, SIERRA_CMN_PLLLC_SSTWOPT_PREG},
+ {0x0D0D, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG},
+ {0x0060, SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG}
+};
+
+/* refclk100MHz_32b_PCIe_ln_int_ssc */
+static const struct cdns_reg_pairs cdns_pcie_ln_regs_int_ssc[] = {
+ {0xFC08, SIERRA_DET_STANDEC_A_PREG},
+ {0x001D, SIERRA_PSM_A3IN_TMR_PREG},
+ {0x1555, SIERRA_DFE_BIASTRIM_PREG},
+ {0x9703, SIERRA_DRVCTRL_BOOST_PREG},
+ {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},
+ {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
+ {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
+ {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
+ {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
+ {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
+ {0x9800, SIERRA_RX_CTLE_CAL_PREG},
+ {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
+ {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
+ {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
+ {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
+ {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
+ {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
+ {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
+ {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
+ {0x0041, SIERRA_DEQ_GLUT0},
+ {0x0082, SIERRA_DEQ_GLUT1},
+ {0x00C3, SIERRA_DEQ_GLUT2},
+ {0x0145, SIERRA_DEQ_GLUT3},
+ {0x0186, SIERRA_DEQ_GLUT4},
+ {0x09E7, SIERRA_DEQ_ALUT0},
+ {0x09A6, SIERRA_DEQ_ALUT1},
+ {0x0965, SIERRA_DEQ_ALUT2},
+ {0x08E3, SIERRA_DEQ_ALUT3},
+ {0x00FA, SIERRA_DEQ_DFETAP0},
+ {0x00FA, SIERRA_DEQ_DFETAP1},
+ {0x00FA, SIERRA_DEQ_DFETAP2},
+ {0x00FA, SIERRA_DEQ_DFETAP3},
+ {0x00FA, SIERRA_DEQ_DFETAP4},
+ {0x000F, SIERRA_DEQ_PRECUR_PREG},
+ {0x0280, SIERRA_DEQ_POSTCUR_PREG},
+ {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
+ {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
+ {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
+ {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
+ {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
+ {0x002B, SIERRA_CPI_TRIM_PREG},
+ {0x0003, SIERRA_EPI_CTRL_PREG},
+ {0x803F, SIERRA_SDFILT_H2L_A_PREG},
+ {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
+ {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
+ {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}
+};
+
+static struct cdns_sierra_vals pcie_100_int_ssc_cmn_vals = {
+ .reg_pairs = cdns_pcie_cmn_regs_int_ssc,
+ .num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_int_ssc),
+};
+
+static struct cdns_sierra_vals pcie_100_int_ssc_ln_vals = {
+ .reg_pairs = cdns_pcie_ln_regs_int_ssc,
+ .num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_int_ssc),
+};
+
/* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc */
static struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = {
{0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
@@ -996,13 +1157,52 @@ static struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = {
/* refclk100MHz_32b_PCIe_ln_ext_ssc */
static struct cdns_reg_pairs cdns_pcie_ln_regs_ext_ssc[] = {
+ {0xFC08, SIERRA_DET_STANDEC_A_PREG},
+ {0x001D, SIERRA_PSM_A3IN_TMR_PREG},
+ {0x1555, SIERRA_DFE_BIASTRIM_PREG},
+ {0x9703, SIERRA_DRVCTRL_BOOST_PREG},
{0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},
{0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
+ {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
+ {0x9800, SIERRA_RX_CTLE_CAL_PREG},
{0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
- {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}
+ {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
+ {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
+ {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
+ {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
+ {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
+ {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
+ {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
+ {0x0041, SIERRA_DEQ_GLUT0},
+ {0x0082, SIERRA_DEQ_GLUT1},
+ {0x00C3, SIERRA_DEQ_GLUT2},
+ {0x0145, SIERRA_DEQ_GLUT3},
+ {0x0186, SIERRA_DEQ_GLUT4},
+ {0x09E7, SIERRA_DEQ_ALUT0},
+ {0x09A6, SIERRA_DEQ_ALUT1},
+ {0x0965, SIERRA_DEQ_ALUT2},
+ {0x08E3, SIERRA_DEQ_ALUT3},
+ {0x00FA, SIERRA_DEQ_DFETAP0},
+ {0x00FA, SIERRA_DEQ_DFETAP1},
+ {0x00FA, SIERRA_DEQ_DFETAP2},
+ {0x00FA, SIERRA_DEQ_DFETAP3},
+ {0x00FA, SIERRA_DEQ_DFETAP4},
+ {0x000F, SIERRA_DEQ_PRECUR_PREG},
+ {0x0280, SIERRA_DEQ_POSTCUR_PREG},
+ {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
+ {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
+ {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
+ {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
+ {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
+ {0x002B, SIERRA_CPI_TRIM_PREG},
+ {0x0003, SIERRA_EPI_CTRL_PREG},
+ {0x803F, SIERRA_SDFILT_H2L_A_PREG},
+ {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
+ {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
+ {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}
};
static struct cdns_sierra_vals pcie_100_ext_ssc_cmn_vals = {
@@ -1139,16 +1339,20 @@ static const struct cdns_sierra_data cdns_map_sierra = {
.pcs_cmn_vals = {
[TYPE_PCIE] = {
[TYPE_NONE] = {
+ [NO_SSC] = &pcie_phy_pcs_cmn_vals,
[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
+ [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
},
},
},
.pma_cmn_vals = {
[TYPE_PCIE] = {
[TYPE_NONE] = {
- [EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals,
- },
+ [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
+ [EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals,
+ [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals
},
+ },
[TYPE_USB] = {
[TYPE_NONE] = {
[EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals,
@@ -1158,7 +1362,9 @@ static const struct cdns_sierra_data cdns_map_sierra = {
.pma_ln_vals = {
[TYPE_PCIE] = {
[TYPE_NONE] = {
+ [NO_SSC] = &pcie_100_no_ssc_ln_vals,
[EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals,
+ [INTERNAL_SSC] = &pcie_100_int_ssc_ln_vals,
},
},
[TYPE_USB] = {
@@ -1176,14 +1382,18 @@ static const struct cdns_sierra_data cdns_ti_map_sierra = {
.pcs_cmn_vals = {
[TYPE_PCIE] = {
[TYPE_NONE] = {
+ [NO_SSC] = &pcie_phy_pcs_cmn_vals,
[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
+ [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
},
},
},
.pma_cmn_vals = {
[TYPE_PCIE] = {
[TYPE_NONE] = {
+ [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
[EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals,
+ [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
},
},
[TYPE_USB] = {
@@ -1195,7 +1405,9 @@ static const struct cdns_sierra_data cdns_ti_map_sierra = {
.pma_ln_vals = {
[TYPE_PCIE] = {
[TYPE_NONE] = {
+ [NO_SSC] = &pcie_100_no_ssc_ln_vals,
[EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals,
+ [INTERNAL_SSC] = &pcie_100_int_ssc_ln_vals,
},
},
[TYPE_USB] = {
--
2.17.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 21/25] phy: cadence: Sierra: Add support for PHY multilink configurations
2022-01-28 8:11 [PATCH v2 00/25] SIERRA: Add support for Mulitlink Configuration Aswath Govindraju
` (19 preceding siblings ...)
2022-01-28 8:11 ` [PATCH v2 20/25] phy: cadence: Sierra: Update single link PCIe register configuration Aswath Govindraju
@ 2022-01-28 8:11 ` Aswath Govindraju
2022-02-08 17:35 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 22/25] phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration Aswath Govindraju
` (3 subsequent siblings)
24 siblings, 1 reply; 51+ messages in thread
From: Aswath Govindraju @ 2022-01-28 8:11 UTC (permalink / raw)
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra,
Aswath Govindraju
From: Swapnil Jakhade <sjakhade@cadence.com>
Add support for multilink configuration of Sierra PHY. Currently,
maximum two links are supported.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
---
drivers/phy/cadence/phy-cadence-sierra.c | 153 +++++++++++++++++++++--
1 file changed, 145 insertions(+), 8 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index 54d316d4ec41..5641c5672806 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -29,7 +29,7 @@
#include <regmap.h>
#define NUM_SSC_MODE 3
-#define NUM_PHY_TYPE 3
+#define NUM_PHY_TYPE 4
/* PHY register offsets */
#define SIERRA_COMMON_CDB_OFFSET 0x0
@@ -183,6 +183,11 @@
(0xD000 + ((ln) * (0x800 >> (3 - (offset)))))
#define SIERRA_PHY_ISO_LINK_CTRL 0xB
+/* PHY PMA lane registers */
+#define SIERRA_PHY_PMA_LANE_CDB_OFFSET(ln, offset) \
+ (0xF000 + ((ln) * (0x800 >> (3 - (offset)))))
+#define SIERRA_PHY_PMA_XCVR_CTRL 0x000
+
#define SIERRA_MACRO_ID 0x00007364
#define SIERRA_MAX_LANES 16
#define PLL_LOCK_TIME 100
@@ -288,6 +293,8 @@ struct cdns_sierra_data {
u8 reg_offset_shift;
struct cdns_sierra_vals *pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
[NUM_SSC_MODE];
+ struct cdns_sierra_vals *phy_pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
+ [NUM_SSC_MODE];
struct cdns_sierra_vals *pma_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
[NUM_SSC_MODE];
struct cdns_sierra_vals *pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
@@ -306,6 +313,7 @@ struct cdns_sierra_phy {
struct regmap *regmap_phy_pcs_common_cdb;
struct regmap *regmap_phy_pcs_lane_cdb[SIERRA_MAX_LANES];
struct regmap *regmap_phy_pma_common_cdb;
+ struct regmap *regmap_phy_pma_lane_cdb[SIERRA_MAX_LANES];
struct regmap *regmap_common_cdb;
struct regmap_field *macro_id_type;
struct regmap_field *phy_pll_cfg_1;
@@ -361,6 +369,7 @@ static int cdns_sierra_phy_init(struct phy *gphy)
struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals;
enum cdns_sierra_phy_type phy_type = ins->phy_type;
enum cdns_sierra_ssc_mode ssc = ins->ssc_mode;
+ struct cdns_sierra_vals *phy_pma_ln_vals;
const struct cdns_reg_pairs *reg_pairs;
struct cdns_sierra_vals *pcs_cmn_vals;
struct regmap *regmap = phy->regmap;
@@ -368,7 +377,7 @@ static int cdns_sierra_phy_init(struct phy *gphy)
int i, j;
/* Initialise the PHY registers, unless auto configured */
- if (phy->autoconf)
+ if (phy->autoconf || phy->nsubnodes > 1)
return 0;
clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 25000000);
@@ -384,6 +393,18 @@ static int cdns_sierra_phy_init(struct phy *gphy)
regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val);
}
+ /* PHY PMA lane registers configurations */
+ phy_pma_ln_vals = init_data->phy_pma_ln_vals[phy_type][TYPE_NONE][ssc];
+ if (phy_pma_ln_vals) {
+ reg_pairs = phy_pma_ln_vals->reg_pairs;
+ num_regs = phy_pma_ln_vals->num_regs;
+ for (i = 0; i < ins->num_lanes; i++) {
+ regmap = phy->regmap_phy_pma_lane_cdb[i + ins->mlane];
+ for (j = 0; j < num_regs; j++)
+ regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val);
+ }
+ }
+
/* PMA common registers configurations */
pma_cmn_vals = init_data->pma_cmn_vals[phy_type][TYPE_NONE][ssc];
if (pma_cmn_vals) {
@@ -417,10 +438,13 @@ static int cdns_sierra_phy_on(struct phy *gphy)
u32 val;
int ret;
- ret = reset_control_deassert(sp->phy_rst);
- if (ret) {
- dev_err(dev, "Failed to take the PHY out of reset\n");
- return ret;
+ if (sp->nsubnodes == 1) {
+ /* Take the PHY out of reset */
+ ret = reset_control_deassert(sp->phy_rst);
+ if (ret) {
+ dev_err(dev, "Failed to take the PHY out of reset\n");
+ return ret;
+ }
}
/* Take the PHY lane group out of reset */
@@ -776,6 +800,116 @@ static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp,
}
sp->regmap_phy_pma_common_cdb = regmap;
+ for (i = 0; i < SIERRA_MAX_LANES; i++) {
+ block_offset = SIERRA_PHY_PMA_LANE_CDB_OFFSET(i, reg_offset_shift);
+ regmap = cdns_regmap_init(dev, base, block_offset,
+ block_offset_shift, reg_offset_shift);
+ if (IS_ERR(regmap)) {
+ dev_err(dev, "Failed to init PHY PMA lane CDB regmap\n");
+ return PTR_ERR(regmap);
+ }
+ sp->regmap_phy_pma_lane_cdb[i] = regmap;
+ }
+
+ return 0;
+}
+
+static int cdns_sierra_phy_configure_multilink(struct cdns_sierra_phy *sp)
+{
+ const struct cdns_sierra_data *init_data = sp->init_data;
+ enum cdns_sierra_phy_type phy_t1, phy_t2, tmp_phy_type;
+ struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals;
+ struct cdns_sierra_vals *phy_pma_ln_vals;
+ const struct cdns_reg_pairs *reg_pairs;
+ struct cdns_sierra_vals *pcs_cmn_vals;
+ int i, j, node, mlane, num_lanes, ret;
+ enum cdns_sierra_ssc_mode ssc;
+ struct regmap *regmap;
+ u32 num_regs;
+
+ /* Maximum 2 links (subnodes) are supported */
+ if (sp->nsubnodes != 2)
+ return -EINVAL;
+
+ clk_set_rate(sp->input_clks[CMN_REFCLK_DIG_DIV], 25000000);
+ clk_set_rate(sp->input_clks[CMN_REFCLK1_DIG_DIV], 25000000);
+
+ /* PHY configured to use both PLL LC and LC1 */
+ regmap_field_write(sp->phy_pll_cfg_1, 0x1);
+
+ phy_t1 = sp->phys[0]->phy_type;
+ phy_t2 = sp->phys[1]->phy_type;
+
+ /*
+ * First configure the PHY for first link with phy_t1. Get the array
+ * values as [phy_t1][phy_t2][ssc].
+ */
+ for (node = 0; node < sp->nsubnodes; node++) {
+ if (node == 1) {
+ /*
+ * If first link with phy_t1 is configured, then
+ * configure the PHY for second link with phy_t2.
+ * Get the array values as [phy_t2][phy_t1][ssc].
+ */
+ tmp_phy_type = phy_t1;
+ phy_t1 = phy_t2;
+ phy_t2 = tmp_phy_type;
+ }
+
+ mlane = sp->phys[node]->mlane;
+ ssc = sp->phys[node]->ssc_mode;
+ num_lanes = sp->phys[node]->num_lanes;
+
+ /* PHY PCS common registers configurations */
+ pcs_cmn_vals = init_data->pcs_cmn_vals[phy_t1][phy_t2][ssc];
+ if (pcs_cmn_vals) {
+ reg_pairs = pcs_cmn_vals->reg_pairs;
+ num_regs = pcs_cmn_vals->num_regs;
+ regmap = sp->regmap_phy_pcs_common_cdb;
+ for (i = 0; i < num_regs; i++)
+ regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val);
+ }
+
+ /* PHY PMA lane registers configurations */
+ phy_pma_ln_vals = init_data->phy_pma_ln_vals[phy_t1][phy_t2][ssc];
+ if (phy_pma_ln_vals) {
+ reg_pairs = phy_pma_ln_vals->reg_pairs;
+ num_regs = phy_pma_ln_vals->num_regs;
+ for (i = 0; i < num_lanes; i++) {
+ regmap = sp->regmap_phy_pma_lane_cdb[i + mlane];
+ for (j = 0; j < num_regs; j++)
+ regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val);
+ }
+ }
+
+ /* PMA common registers configurations */
+ pma_cmn_vals = init_data->pma_cmn_vals[phy_t1][phy_t2][ssc];
+ if (pma_cmn_vals) {
+ reg_pairs = pma_cmn_vals->reg_pairs;
+ num_regs = pma_cmn_vals->num_regs;
+ regmap = sp->regmap_common_cdb;
+ for (i = 0; i < num_regs; i++)
+ regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val);
+ }
+
+ /* PMA TX lane registers configurations */
+ pma_ln_vals = init_data->pma_ln_vals[phy_t1][phy_t2][ssc];
+ if (pma_ln_vals) {
+ reg_pairs = pma_ln_vals->reg_pairs;
+ num_regs = pma_ln_vals->num_regs;
+ for (i = 0; i < num_lanes; i++) {
+ regmap = sp->regmap_lane_cdb[i + mlane];
+ for (j = 0; j < num_regs; j++)
+ regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val);
+ }
+ }
+ }
+
+ /* Take the PHY out of reset */
+ ret = reset_control_deassert(sp->phy_rst);
+ if (ret)
+ return ret;
+
return 0;
}
@@ -896,8 +1030,11 @@ static int cdns_sierra_link_probe(struct udevice *dev)
sp->num_lanes += inst->num_lanes;
/* If more than one subnode, configure the PHY as multilink */
- if (!sp->autoconf && sp->nsubnodes > 1)
- regmap_field_write(sp->phy_pll_cfg_1, 0x1);
+ if (!sp->autoconf && sp->nsubnodes > 1) {
+ ret = cdns_sierra_phy_configure_multilink(sp);
+ if (ret)
+ return ret;
+ }
return 0;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 22/25] phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration
2022-01-28 8:11 [PATCH v2 00/25] SIERRA: Add support for Mulitlink Configuration Aswath Govindraju
` (20 preceding siblings ...)
2022-01-28 8:11 ` [PATCH v2 21/25] phy: cadence: Sierra: Add support for PHY multilink configurations Aswath Govindraju
@ 2022-01-28 8:11 ` Aswath Govindraju
2022-02-08 17:35 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 23/25] phy: cadence: Sierra: Add support for skipping configuration Aswath Govindraju
` (2 subsequent siblings)
24 siblings, 1 reply; 51+ messages in thread
From: Aswath Govindraju @ 2022-01-28 8:11 UTC (permalink / raw)
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra,
Aswath Govindraju
From: Swapnil Jakhade <sjakhade@cadence.com>
Add register sequences for PCIe + QSGMII PHY multilink configuration.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
---
drivers/phy/cadence/phy-cadence-sierra.c | 378 ++++++++++++++++++++++-
1 file changed, 377 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index 5641c5672806..95cdd39cb367 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -50,6 +50,9 @@
#define SIERRA_CMN_REFRCV1_PREG 0xB8
#define SIERRA_CMN_PLLLC1_GEN_PREG 0xC2
#define SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG 0x63
+#define SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG 0xCA
+#define SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG 0xD0
+#define SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG 0xE2
#define SIERRA_LANE_CDB_OFFSET(ln, offset) \
(0x4000 + ((ln) * (0x800 >> (2 - (offset)))))
@@ -63,6 +66,9 @@
#define SIERRA_PSM_A0IN_TMR_PREG 0x009
#define SIERRA_PSM_A3IN_TMR_PREG 0x00C
#define SIERRA_PSM_DIAG_PREG 0x015
+#define SIERRA_PSC_LN_A3_PREG 0x023
+#define SIERRA_PSC_LN_A4_PREG 0x024
+#define SIERRA_PSC_LN_IDLE_PREG 0x026
#define SIERRA_PSC_TX_A0_PREG 0x028
#define SIERRA_PSC_TX_A1_PREG 0x029
#define SIERRA_PSC_TX_A2_PREG 0x02A
@@ -72,6 +78,7 @@
#define SIERRA_PSC_RX_A2_PREG 0x032
#define SIERRA_PSC_RX_A3_PREG 0x033
#define SIERRA_PLLCTRL_SUBRATE_PREG 0x03A
+#define SIERRA_PLLCTRL_GEN_A_PREG 0x03B
#define SIERRA_PLLCTRL_GEN_D_PREG 0x03E
#define SIERRA_PLLCTRL_CPGAIN_MODE_PREG 0x03F
#define SIERRA_PLLCTRL_STATUS_PREG 0x044
@@ -154,6 +161,7 @@
#define SIERRA_CPICAL_TMRVAL_MODE0_PREG 0x171
#define SIERRA_CPICAL_PICNT_MODE1_PREG 0x174
#define SIERRA_CPI_OUTBUF_RATESEL_PREG 0x17C
+#define SIERRA_CPI_RESBIAS_BIN_PREG 0x17E
#define SIERRA_CPI_TRIM_PREG 0x17F
#define SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG 0x183
#define SIERRA_EPI_CTRL_PREG 0x187
@@ -260,7 +268,8 @@ struct cdns_sierra_pll_mux {
enum cdns_sierra_phy_type {
TYPE_NONE,
TYPE_PCIE,
- TYPE_USB
+ TYPE_USB,
+ TYPE_QSGMII
};
enum cdns_sierra_ssc_mode {
@@ -639,6 +648,9 @@ static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst,
case PHY_TYPE_USB3:
inst->phy_type = TYPE_USB;
break;
+ case PHY_TYPE_QSGMII:
+ inst->phy_type = TYPE_QSGMII;
+ break;
default:
return -EINVAL;
}
@@ -903,6 +915,9 @@ static int cdns_sierra_phy_configure_multilink(struct cdns_sierra_phy *sp)
regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val);
}
}
+
+ if (phy_t1 == TYPE_QSGMII)
+ reset_deassert_bulk(sp->phys[node]->lnk_rst);
}
/* Take the PHY out of reset */
@@ -1133,6 +1148,72 @@ static int cdns_sierra_phy_remove(struct udevice *dev)
return 0;
}
+/* QSGMII PHY PMA lane configuration */
+static struct cdns_reg_pairs qsgmii_phy_pma_ln_regs[] = {
+ {0x9010, SIERRA_PHY_PMA_XCVR_CTRL}
+};
+
+static struct cdns_sierra_vals qsgmii_phy_pma_ln_vals = {
+ .reg_pairs = qsgmii_phy_pma_ln_regs,
+ .num_regs = ARRAY_SIZE(qsgmii_phy_pma_ln_regs),
+};
+
+/* QSGMII refclk 100MHz, 20b, opt1, No BW cal, no ssc, PLL LC1 */
+static const struct cdns_reg_pairs qsgmii_100_no_ssc_plllc1_cmn_regs[] = {
+ {0x2085, SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG},
+ {0x0000, SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG},
+ {0x0000, SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG}
+};
+
+static const struct cdns_reg_pairs qsgmii_100_no_ssc_plllc1_ln_regs[] = {
+ {0xFC08, SIERRA_DET_STANDEC_A_PREG},
+ {0x0252, SIERRA_DET_STANDEC_E_PREG},
+ {0x0004, SIERRA_PSC_LN_IDLE_PREG},
+ {0x0FFE, SIERRA_PSC_RX_A0_PREG},
+ {0x0011, SIERRA_PLLCTRL_SUBRATE_PREG},
+ {0x0001, SIERRA_PLLCTRL_GEN_A_PREG},
+ {0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG},
+ {0x0000, SIERRA_DRVCTRL_ATTEN_PREG},
+ {0x0089, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
+ {0x3C3C, SIERRA_CREQ_CCLKDET_MODE01_PREG},
+ {0x3222, SIERRA_CREQ_FSMCLK_SEL_PREG},
+ {0x0000, SIERRA_CREQ_EQ_CTRL_PREG},
+ {0x8422, SIERRA_CTLELUT_CTRL_PREG},
+ {0x4111, SIERRA_DFE_ECMP_RATESEL_PREG},
+ {0x4111, SIERRA_DFE_SMP_RATESEL_PREG},
+ {0x0002, SIERRA_DEQ_PHALIGN_CTRL},
+ {0x9595, SIERRA_DEQ_VGATUNE_CTRL_PREG},
+ {0x0186, SIERRA_DEQ_GLUT0},
+ {0x0186, SIERRA_DEQ_GLUT1},
+ {0x0186, SIERRA_DEQ_GLUT2},
+ {0x0186, SIERRA_DEQ_GLUT3},
+ {0x0186, SIERRA_DEQ_GLUT4},
+ {0x0861, SIERRA_DEQ_ALUT0},
+ {0x07E0, SIERRA_DEQ_ALUT1},
+ {0x079E, SIERRA_DEQ_ALUT2},
+ {0x071D, SIERRA_DEQ_ALUT3},
+ {0x03F5, SIERRA_DEQ_DFETAP_CTRL_PREG},
+ {0x0C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG},
+ {0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
+ {0x1C04, SIERRA_DEQ_TAU_CTRL2_PREG},
+ {0x0033, SIERRA_DEQ_PICTRL_PREG},
+ {0x0660, SIERRA_CPICAL_TMRVAL_MODE0_PREG},
+ {0x00D5, SIERRA_CPI_OUTBUF_RATESEL_PREG},
+ {0x0B6D, SIERRA_CPI_RESBIAS_BIN_PREG},
+ {0x0102, SIERRA_RXBUFFER_CTLECTRL_PREG},
+ {0x0002, SIERRA_RXBUFFER_RCDFECTRL_PREG}
+};
+
+static struct cdns_sierra_vals qsgmii_100_no_ssc_plllc1_cmn_vals = {
+ .reg_pairs = qsgmii_100_no_ssc_plllc1_cmn_regs,
+ .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_plllc1_cmn_regs),
+};
+
+static struct cdns_sierra_vals qsgmii_100_no_ssc_plllc1_ln_vals = {
+ .reg_pairs = qsgmii_100_no_ssc_plllc1_ln_regs,
+ .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_plllc1_ln_regs),
+};
+
/* PCIE PHY PCS common configuration */
static struct cdns_reg_pairs pcie_phy_pcs_cmn_regs[] = {
{0x0430, SIERRA_PHY_PIPE_CMN_CTRL1}
@@ -1143,6 +1224,233 @@ static struct cdns_sierra_vals pcie_phy_pcs_cmn_vals = {
.num_regs = ARRAY_SIZE(pcie_phy_pcs_cmn_regs),
};
+/* refclk100MHz_32b_PCIe_cmn_pll_no_ssc, pcie_links_using_plllc, pipe_bw_3 */
+static const struct cdns_reg_pairs pcie_100_no_ssc_plllc_cmn_regs[] = {
+ {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
+ {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
+ {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
+ {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}
+};
+
+/*
+ * refclk100MHz_32b_PCIe_ln_no_ssc, multilink, using_plllc,
+ * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz
+ */
+static const struct cdns_reg_pairs ml_pcie_100_no_ssc_ln_regs[] = {
+ {0xFC08, SIERRA_DET_STANDEC_A_PREG},
+ {0x001D, SIERRA_PSM_A3IN_TMR_PREG},
+ {0x0004, SIERRA_PSC_LN_A3_PREG},
+ {0x0004, SIERRA_PSC_LN_A4_PREG},
+ {0x0004, SIERRA_PSC_LN_IDLE_PREG},
+ {0x1555, SIERRA_DFE_BIASTRIM_PREG},
+ {0x9703, SIERRA_DRVCTRL_BOOST_PREG},
+ {0x8055, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
+ {0x80BB, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
+ {0x8351, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
+ {0x8349, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
+ {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
+ {0x9800, SIERRA_RX_CTLE_CAL_PREG},
+ {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
+ {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
+ {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
+ {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
+ {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
+ {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
+ {0x0041, SIERRA_DEQ_GLUT0},
+ {0x0082, SIERRA_DEQ_GLUT1},
+ {0x00C3, SIERRA_DEQ_GLUT2},
+ {0x0145, SIERRA_DEQ_GLUT3},
+ {0x0186, SIERRA_DEQ_GLUT4},
+ {0x09E7, SIERRA_DEQ_ALUT0},
+ {0x09A6, SIERRA_DEQ_ALUT1},
+ {0x0965, SIERRA_DEQ_ALUT2},
+ {0x08E3, SIERRA_DEQ_ALUT3},
+ {0x00FA, SIERRA_DEQ_DFETAP0},
+ {0x00FA, SIERRA_DEQ_DFETAP1},
+ {0x00FA, SIERRA_DEQ_DFETAP2},
+ {0x00FA, SIERRA_DEQ_DFETAP3},
+ {0x00FA, SIERRA_DEQ_DFETAP4},
+ {0x000F, SIERRA_DEQ_PRECUR_PREG},
+ {0x0280, SIERRA_DEQ_POSTCUR_PREG},
+ {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
+ {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
+ {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
+ {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
+ {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
+ {0x002B, SIERRA_CPI_TRIM_PREG},
+ {0x0003, SIERRA_EPI_CTRL_PREG},
+ {0x803F, SIERRA_SDFILT_H2L_A_PREG},
+ {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
+ {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
+ {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}
+};
+
+static struct cdns_sierra_vals pcie_100_no_ssc_plllc_cmn_vals = {
+ .reg_pairs = pcie_100_no_ssc_plllc_cmn_regs,
+ .num_regs = ARRAY_SIZE(pcie_100_no_ssc_plllc_cmn_regs),
+};
+
+static struct cdns_sierra_vals ml_pcie_100_no_ssc_ln_vals = {
+ .reg_pairs = ml_pcie_100_no_ssc_ln_regs,
+ .num_regs = ARRAY_SIZE(ml_pcie_100_no_ssc_ln_regs),
+};
+
+/* refclk100MHz_32b_PCIe_cmn_pll_int_ssc, pcie_links_using_plllc, pipe_bw_3 */
+static const struct cdns_reg_pairs pcie_100_int_ssc_plllc_cmn_regs[] = {
+ {0x000E, SIERRA_CMN_PLLLC_MODE_PREG},
+ {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
+ {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
+ {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
+ {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
+ {0x0581, SIERRA_CMN_PLLLC_DSMCORR_PREG},
+ {0x7F80, SIERRA_CMN_PLLLC_SS_PREG},
+ {0x0041, SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG},
+ {0x0464, SIERRA_CMN_PLLLC_SSTWOPT_PREG},
+ {0x0D0D, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG},
+ {0x0060, SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG}
+};
+
+/*
+ * refclk100MHz_32b_PCIe_ln_int_ssc, multilink, using_plllc,
+ * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz
+ */
+static const struct cdns_reg_pairs ml_pcie_100_int_ssc_ln_regs[] = {
+ {0xFC08, SIERRA_DET_STANDEC_A_PREG},
+ {0x001D, SIERRA_PSM_A3IN_TMR_PREG},
+ {0x0004, SIERRA_PSC_LN_A3_PREG},
+ {0x0004, SIERRA_PSC_LN_A4_PREG},
+ {0x0004, SIERRA_PSC_LN_IDLE_PREG},
+ {0x1555, SIERRA_DFE_BIASTRIM_PREG},
+ {0x9703, SIERRA_DRVCTRL_BOOST_PREG},
+ {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},
+ {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
+ {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
+ {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
+ {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
+ {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
+ {0x9800, SIERRA_RX_CTLE_CAL_PREG},
+ {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
+ {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
+ {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
+ {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
+ {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
+ {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
+ {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
+ {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
+ {0x0041, SIERRA_DEQ_GLUT0},
+ {0x0082, SIERRA_DEQ_GLUT1},
+ {0x00C3, SIERRA_DEQ_GLUT2},
+ {0x0145, SIERRA_DEQ_GLUT3},
+ {0x0186, SIERRA_DEQ_GLUT4},
+ {0x09E7, SIERRA_DEQ_ALUT0},
+ {0x09A6, SIERRA_DEQ_ALUT1},
+ {0x0965, SIERRA_DEQ_ALUT2},
+ {0x08E3, SIERRA_DEQ_ALUT3},
+ {0x00FA, SIERRA_DEQ_DFETAP0},
+ {0x00FA, SIERRA_DEQ_DFETAP1},
+ {0x00FA, SIERRA_DEQ_DFETAP2},
+ {0x00FA, SIERRA_DEQ_DFETAP3},
+ {0x00FA, SIERRA_DEQ_DFETAP4},
+ {0x000F, SIERRA_DEQ_PRECUR_PREG},
+ {0x0280, SIERRA_DEQ_POSTCUR_PREG},
+ {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
+ {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
+ {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
+ {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
+ {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
+ {0x002B, SIERRA_CPI_TRIM_PREG},
+ {0x0003, SIERRA_EPI_CTRL_PREG},
+ {0x803F, SIERRA_SDFILT_H2L_A_PREG},
+ {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
+ {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
+ {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}
+};
+
+static struct cdns_sierra_vals pcie_100_int_ssc_plllc_cmn_vals = {
+ .reg_pairs = pcie_100_int_ssc_plllc_cmn_regs,
+ .num_regs = ARRAY_SIZE(pcie_100_int_ssc_plllc_cmn_regs),
+};
+
+static struct cdns_sierra_vals ml_pcie_100_int_ssc_ln_vals = {
+ .reg_pairs = ml_pcie_100_int_ssc_ln_regs,
+ .num_regs = ARRAY_SIZE(ml_pcie_100_int_ssc_ln_regs),
+};
+
+/* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc, pcie_links_using_plllc, pipe_bw_3 */
+static const struct cdns_reg_pairs pcie_100_ext_ssc_plllc_cmn_regs[] = {
+ {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
+ {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
+ {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
+ {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
+ {0x1B1B, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}
+};
+
+/*
+ * refclk100MHz_32b_PCIe_ln_ext_ssc, multilink, using_plllc,
+ * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz
+ */
+static const struct cdns_reg_pairs ml_pcie_100_ext_ssc_ln_regs[] = {
+ {0xFC08, SIERRA_DET_STANDEC_A_PREG},
+ {0x001D, SIERRA_PSM_A3IN_TMR_PREG},
+ {0x0004, SIERRA_PSC_LN_A3_PREG},
+ {0x0004, SIERRA_PSC_LN_A4_PREG},
+ {0x0004, SIERRA_PSC_LN_IDLE_PREG},
+ {0x1555, SIERRA_DFE_BIASTRIM_PREG},
+ {0x9703, SIERRA_DRVCTRL_BOOST_PREG},
+ {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},
+ {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
+ {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
+ {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
+ {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
+ {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},
+ {0x9800, SIERRA_RX_CTLE_CAL_PREG},
+ {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
+ {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
+ {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},
+ {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
+ {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
+ {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},
+ {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},
+ {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},
+ {0x0041, SIERRA_DEQ_GLUT0},
+ {0x0082, SIERRA_DEQ_GLUT1},
+ {0x00C3, SIERRA_DEQ_GLUT2},
+ {0x0145, SIERRA_DEQ_GLUT3},
+ {0x0186, SIERRA_DEQ_GLUT4},
+ {0x09E7, SIERRA_DEQ_ALUT0},
+ {0x09A6, SIERRA_DEQ_ALUT1},
+ {0x0965, SIERRA_DEQ_ALUT2},
+ {0x08E3, SIERRA_DEQ_ALUT3},
+ {0x00FA, SIERRA_DEQ_DFETAP0},
+ {0x00FA, SIERRA_DEQ_DFETAP1},
+ {0x00FA, SIERRA_DEQ_DFETAP2},
+ {0x00FA, SIERRA_DEQ_DFETAP3},
+ {0x00FA, SIERRA_DEQ_DFETAP4},
+ {0x000F, SIERRA_DEQ_PRECUR_PREG},
+ {0x0280, SIERRA_DEQ_POSTCUR_PREG},
+ {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},
+ {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
+ {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},
+ {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},
+ {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},
+ {0x002B, SIERRA_CPI_TRIM_PREG},
+ {0x0003, SIERRA_EPI_CTRL_PREG},
+ {0x803F, SIERRA_SDFILT_H2L_A_PREG},
+ {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},
+ {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},
+ {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}
+};
+
+static struct cdns_sierra_vals pcie_100_ext_ssc_plllc_cmn_vals = {
+ .reg_pairs = pcie_100_ext_ssc_plllc_cmn_regs,
+ .num_regs = ARRAY_SIZE(pcie_100_ext_ssc_plllc_cmn_regs),
+};
+
+static struct cdns_sierra_vals ml_pcie_100_ext_ssc_ln_vals = {
+ .reg_pairs = ml_pcie_100_ext_ssc_ln_regs,
+ .num_regs = ARRAY_SIZE(ml_pcie_100_ext_ssc_ln_regs),
+};
+
/* refclk100MHz_32b_PCIe_cmn_pll_no_ssc */
static const struct cdns_reg_pairs cdns_pcie_cmn_regs_no_ssc[] = {
{0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
@@ -1480,6 +1788,11 @@ static const struct cdns_sierra_data cdns_map_sierra = {
[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
},
+ [TYPE_QSGMII] = {
+ [NO_SSC] = &pcie_phy_pcs_cmn_vals,
+ [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
+ [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
+ },
},
},
.pma_cmn_vals = {
@@ -1489,12 +1802,24 @@ static const struct cdns_sierra_data cdns_map_sierra = {
[EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals,
[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals
},
+ [TYPE_QSGMII] = {
+ [NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals,
+ [EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals,
+ [INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals,
+ },
},
[TYPE_USB] = {
[TYPE_NONE] = {
[EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals,
},
},
+ [TYPE_QSGMII] = {
+ [TYPE_PCIE] = {
+ [NO_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,
+ [EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,
+ [INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,
+ },
+ },
},
.pma_ln_vals = {
[TYPE_PCIE] = {
@@ -1503,12 +1828,25 @@ static const struct cdns_sierra_data cdns_map_sierra = {
[EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals,
[INTERNAL_SSC] = &pcie_100_int_ssc_ln_vals,
},
+ [TYPE_QSGMII] = {
+ [NO_SSC] = &ml_pcie_100_no_ssc_ln_vals,
+ [EXTERNAL_SSC] = &ml_pcie_100_ext_ssc_ln_vals,
+ [INTERNAL_SSC] = &ml_pcie_100_int_ssc_ln_vals,
+ },
},
[TYPE_USB] = {
[TYPE_NONE] = {
[EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals,
},
},
+ [TYPE_QSGMII] = {
+ [TYPE_PCIE] = {
+ [NO_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,
+ [EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,
+ [INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,
+ },
+ },
+
},
};
@@ -1523,6 +1861,20 @@ static const struct cdns_sierra_data cdns_ti_map_sierra = {
[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
},
+ [TYPE_QSGMII] = {
+ [NO_SSC] = &pcie_phy_pcs_cmn_vals,
+ [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
+ [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
+ },
+ },
+ },
+ .phy_pma_ln_vals = {
+ [TYPE_QSGMII] = {
+ [TYPE_PCIE] = {
+ [NO_SSC] = &qsgmii_phy_pma_ln_vals,
+ [EXTERNAL_SSC] = &qsgmii_phy_pma_ln_vals,
+ [INTERNAL_SSC] = &qsgmii_phy_pma_ln_vals,
+ },
},
},
.pma_cmn_vals = {
@@ -1532,12 +1884,24 @@ static const struct cdns_sierra_data cdns_ti_map_sierra = {
[EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals,
[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
},
+ [TYPE_QSGMII] = {
+ [NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals,
+ [EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals,
+ [INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals,
+ },
},
[TYPE_USB] = {
[TYPE_NONE] = {
[EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals,
},
},
+ [TYPE_QSGMII] = {
+ [TYPE_PCIE] = {
+ [NO_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,
+ [EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,
+ [INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,
+ },
+ },
},
.pma_ln_vals = {
[TYPE_PCIE] = {
@@ -1546,12 +1910,24 @@ static const struct cdns_sierra_data cdns_ti_map_sierra = {
[EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals,
[INTERNAL_SSC] = &pcie_100_int_ssc_ln_vals,
},
+ [TYPE_QSGMII] = {
+ [NO_SSC] = &ml_pcie_100_no_ssc_ln_vals,
+ [EXTERNAL_SSC] = &ml_pcie_100_ext_ssc_ln_vals,
+ [INTERNAL_SSC] = &ml_pcie_100_int_ssc_ln_vals,
+ },
},
[TYPE_USB] = {
[TYPE_NONE] = {
[EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals,
},
},
+ [TYPE_QSGMII] = {
+ [TYPE_PCIE] = {
+ [NO_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,
+ [EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,
+ [INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,
+ },
+ },
},
};
--
2.17.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 23/25] phy: cadence: Sierra: Add support for skipping configuration
2022-01-28 8:11 [PATCH v2 00/25] SIERRA: Add support for Mulitlink Configuration Aswath Govindraju
` (21 preceding siblings ...)
2022-01-28 8:11 ` [PATCH v2 22/25] phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration Aswath Govindraju
@ 2022-01-28 8:11 ` Aswath Govindraju
2022-02-08 17:36 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 24/25] arm: dts: k3-j721e: Add support for multilink PCIe + QSGMII Aswath Govindraju
2022-01-28 8:11 ` [PATCH v2 25/25] include: configs: j721e_evm: Add support to boot ethfw core in j721e Aswath Govindraju
24 siblings, 1 reply; 51+ messages in thread
From: Aswath Govindraju @ 2022-01-28 8:11 UTC (permalink / raw)
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra,
Aswath Govindraju
In some cases, a single SerDes instance can be shared between two different
processors, each using a separate link. In these cases, the SerDes
configuration is done in an earlier boot stage. Therefore, add support to
skip reconfiguring, if it is was already configured beforehand.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
---
drivers/phy/cadence/phy-cadence-sierra.c | 58 +++++++++++++++++-------
1 file changed, 42 insertions(+), 16 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index 95cdd39cb367..d95d4b432a98 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -13,6 +13,7 @@
*/
#include <common.h>
#include <clk.h>
+#include <linux/delay.h>
#include <linux/clk-provider.h>
#include <generic-phy.h>
#include <reset.h>
@@ -28,6 +29,8 @@
#include <dt-bindings/phy/phy-cadence.h>
#include <regmap.h>
+#define usleep_range(a, b) udelay((b))
+
#define NUM_SSC_MODE 3
#define NUM_PHY_TYPE 4
@@ -336,6 +339,7 @@ struct cdns_sierra_phy {
int nsubnodes;
u32 num_lanes;
bool autoconf;
+ unsigned int already_configured;
};
static inline int cdns_reset_assert(struct reset_control *rst)
@@ -386,7 +390,7 @@ static int cdns_sierra_phy_init(struct phy *gphy)
int i, j;
/* Initialise the PHY registers, unless auto configured */
- if (phy->autoconf || phy->nsubnodes > 1)
+ if (phy->autoconf || phy->already_configured || phy->nsubnodes > 1)
return 0;
clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 25000000);
@@ -447,6 +451,11 @@ static int cdns_sierra_phy_on(struct phy *gphy)
u32 val;
int ret;
+ if (sp->already_configured) {
+ usleep_range(5000, 10000);
+ return 0;
+ }
+
if (sp->nsubnodes == 1) {
/* Take the PHY out of reset */
ret = reset_control_deassert(sp->phy_rst);
@@ -934,13 +943,6 @@ static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp,
struct clk *clk;
int ret;
- clk = devm_clk_get_optional(dev, "phy_clk");
- if (IS_ERR(clk)) {
- dev_err(dev, "failed to get clock phy_clk\n");
- return PTR_ERR(clk);
- }
- sp->input_clks[PHY_CLK] = clk;
-
clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div");
if (IS_ERR(clk)) {
dev_err(dev, "cmn_refclk_dig_div clock not found\n");
@@ -976,6 +978,25 @@ static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp,
return 0;
}
+static int cdns_sierra_phy_clk(struct cdns_sierra_phy *sp)
+{
+ struct udevice *dev = sp->dev;
+ struct clk *clk;
+ int ret;
+
+ clk = devm_clk_get_optional(dev, "phy_clk");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "failed to get clock phy_clk\n");
+ return PTR_ERR(clk);
+ }
+ sp->input_clks[PHY_CLK] = clk;
+
+ ret = clk_prepare_enable(sp->input_clks[PHY_CLK]);
+ if (ret)
+ return ret;
+
+ return 0;
+}
static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp,
struct udevice *dev)
{
@@ -1045,7 +1066,7 @@ static int cdns_sierra_link_probe(struct udevice *dev)
sp->num_lanes += inst->num_lanes;
/* If more than one subnode, configure the PHY as multilink */
- if (!sp->autoconf && sp->nsubnodes > 1) {
+ if (!sp->autoconf && !sp->already_configured && sp->nsubnodes > 1) {
ret = cdns_sierra_phy_configure_multilink(sp);
if (ret)
return ret;
@@ -1098,13 +1119,17 @@ static int cdns_sierra_phy_probe(struct udevice *dev)
if (ret)
return ret;
- ret = cdns_sierra_phy_get_resets(sp, dev);
- if (ret)
- return ret;
+ regmap_field_read(sp->pma_cmn_ready, &sp->already_configured);
- ret = clk_prepare_enable(sp->input_clks[PHY_CLK]);
- if (ret)
- return ret;
+ if (!sp->already_configured) {
+ ret = cdns_sierra_phy_clk(sp);
+ if (ret)
+ return ret;
+
+ ret = cdns_sierra_phy_get_resets(sp, dev);
+ if (ret)
+ return ret;
+ }
/* Check that PHY is present */
regmap_field_read(sp->macro_id_type, &id_value);
@@ -1125,7 +1150,8 @@ static int cdns_sierra_phy_probe(struct udevice *dev)
return 0;
clk_disable:
- clk_disable_unprepare(sp->input_clks[PHY_CLK]);
+ if (!sp->already_configured)
+ clk_disable_unprepare(sp->input_clks[PHY_CLK]);
return ret;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 24/25] arm: dts: k3-j721e: Add support for multilink PCIe + QSGMII
2022-01-28 8:11 [PATCH v2 00/25] SIERRA: Add support for Mulitlink Configuration Aswath Govindraju
` (22 preceding siblings ...)
2022-01-28 8:11 ` [PATCH v2 23/25] phy: cadence: Sierra: Add support for skipping configuration Aswath Govindraju
@ 2022-01-28 8:11 ` Aswath Govindraju
2022-02-08 17:36 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 25/25] include: configs: j721e_evm: Add support to boot ethfw core in j721e Aswath Govindraju
24 siblings, 1 reply; 51+ messages in thread
From: Aswath Govindraju @ 2022-01-28 8:11 UTC (permalink / raw)
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra,
Aswath Govindraju
Add support for QSGMII multilink configuration.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
---
.../arm/dts/k3-j721e-common-proc-board-u-boot.dtsi | 5 +++++
arch/arm/dts/k3-j721e-common-proc-board.dts | 14 +++++++++++---
arch/arm/dts/k3-j721e-r5-common-proc-board.dts | 12 ++++++++++--
3 files changed, 26 insertions(+), 5 deletions(-)
diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
index 938e978a6b66..677a72d2a241 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
@@ -242,3 +242,8 @@
assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
assigned-clock-parents = <&wiz0_pll1_refclk>;
};
+
+&serdes0_qsgmii_link {
+ assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
+ assigned-clock-parents = <&wiz0_pll1_refclk>;
+};
diff --git a/arch/arm/dts/k3-j721e-common-proc-board.dts b/arch/arm/dts/k3-j721e-common-proc-board.dts
index 8bd02d9e28ad..f3b6302a4317 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-common-proc-board.dts
@@ -345,7 +345,7 @@
};
&serdes_ln_ctrl {
- idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
+ idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_QSGMII_LANE2>,
<J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
<J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
<J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
@@ -671,8 +671,8 @@
};
&serdes0 {
- assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
- assigned-clock-parents = <&wiz0_pll1_refclk>;
+ assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
+ assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>;
serdes0_pcie_link: phy@0 {
reg = <0>;
@@ -681,6 +681,14 @@
cdns,phy-type = <PHY_TYPE_PCIE>;
resets = <&serdes_wiz0 1>;
};
+
+ serdes0_qsgmii_link: phy@1 {
+ reg = <1>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_QSGMII>;
+ resets = <&serdes_wiz0 2>;
+ };
};
&serdes1 {
diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
index 8299463c3e01..5362c528703d 100644
--- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
@@ -374,8 +374,8 @@
};
&serdes0 {
- assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
- assigned-clock-parents = <&wiz0_pll1_refclk>;
+ assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
+ assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>;
serdes0_pcie_link: link@0 {
reg = <0>;
@@ -384,4 +384,12 @@
cdns,phy-type = <PHY_TYPE_PCIE>;
resets = <&serdes_wiz0 1>;
};
+
+ serdes0_qsgmii_link: phy@1 {
+ reg = <1>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_QSGMII>;
+ resets = <&serdes_wiz0 2>;
+ };
};
--
2.17.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 25/25] include: configs: j721e_evm: Add support to boot ethfw core in j721e
2022-01-28 8:11 [PATCH v2 00/25] SIERRA: Add support for Mulitlink Configuration Aswath Govindraju
` (23 preceding siblings ...)
2022-01-28 8:11 ` [PATCH v2 24/25] arm: dts: k3-j721e: Add support for multilink PCIe + QSGMII Aswath Govindraju
@ 2022-01-28 8:11 ` Aswath Govindraju
2022-02-08 17:36 ` Tom Rini
24 siblings, 1 reply; 51+ messages in thread
From: Aswath Govindraju @ 2022-01-28 8:11 UTC (permalink / raw)
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra,
Aswath Govindraju
Add configs to enable booting ethfw core in j721e
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
---
configs/j721e_evm_a72_defconfig | 2 +-
include/configs/j721e_evm.h | 19 ++++++++++---------
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index 2e452739034e..8f412d65a8ac 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -29,7 +29,7 @@ CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
# CONFIG_USE_SPL_FIT_GENERATOR is not set
-CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
+CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run main_cpsw0_qsgmii_phyinit; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
CONFIG_LOGLEVEL=7
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
index abea7517e8b5..627c363ce66e 100644
--- a/include/configs/j721e_evm.h
+++ b/include/configs/j721e_evm.h
@@ -119,6 +119,16 @@
/* Set the default list of remote processors to boot */
#if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
+#define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY \
+ "dorprocboot=1\0" \
+ "do_main_cpsw0_qsgmii_phyinit=1\0" \
+ "init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17;" \
+ "gpio clear gpio@22_16\0" \
+ "main_cpsw0_qsgmii_phyinit=" \
+ "if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1 && test ${dorprocboot} -eq 1 && " \
+ "test ${boot} = mmc; then " \
+ "run init_main_cpsw0_qsgmii_phy;" \
+ "fi;\0"
#ifdef DEFAULT_RPROCS
#undef DEFAULT_RPROCS
#endif
@@ -136,15 +146,6 @@
#endif /* CONFIG_TARGET_J721E_A72_EVM */
#ifdef CONFIG_TARGET_J7200_A72_EVM
-#define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY \
- "do_main_cpsw0_qsgmii_phyinit=1\0" \
- "init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17;" \
- "gpio clear gpio@22_16\0" \
- "main_cpsw0_qsgmii_phyinit=" \
- "if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1 && test ${dorprocboot} -eq 1 && " \
- "test ${boot} = mmc; then " \
- "run init_main_cpsw0_qsgmii_phy;" \
- "fi;\0"
#define DEFAULT_RPROCS "" \
"2 /lib/firmware/j7200-main-r5f0_0-fw " \
"3 /lib/firmware/j7200-main-r5f0_1-fw "
--
2.17.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* Re: [PATCH v2 01/25] phy: cadence: sierra: Fix for USB3 U1/U2 state
2022-01-28 8:11 ` [PATCH v2 01/25] phy: cadence: sierra: Fix for USB3 U1/U2 state Aswath Govindraju
@ 2022-02-08 17:33 ` Tom Rini
0 siblings, 0 replies; 51+ messages in thread
From: Tom Rini @ 2022-02-08 17:33 UTC (permalink / raw)
To: Aswath Govindraju
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra
[-- Attachment #1: Type: text/plain, Size: 430 bytes --]
On Fri, Jan 28, 2022 at 01:41:28PM +0530, Aswath Govindraju wrote:
> From: Sanket Parmar <sparmar@cadence.com>
>
> Updated values of USB3 related Sierra PHY registers.
> This change fixes USB3 device disconnect issue observed
> while enternig U1/U2 state.
>
> Signed-off-by: Sanket Parmar <sparmar@cadence.com>
> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 02/25] phy: cadence: Sierra: Fix PHY power_on sequence
2022-01-28 8:11 ` [PATCH v2 02/25] phy: cadence: Sierra: Fix PHY power_on sequence Aswath Govindraju
@ 2022-02-08 17:33 ` Tom Rini
0 siblings, 0 replies; 51+ messages in thread
From: Tom Rini @ 2022-02-08 17:33 UTC (permalink / raw)
To: Aswath Govindraju
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra
[-- Attachment #1: Type: text/plain, Size: 590 bytes --]
On Fri, Jan 28, 2022 at 01:41:29PM +0530, Aswath Govindraju wrote:
> From: Kishon Vijay Abraham I <kishon@ti.com>
>
> Commit 39b823381d9d ("phy: cadence: Add driver for Sierra PHY")
> de-asserts PHY_RESET even before the configurations are loaded in
> phy_init(). However PHY_RESET should be de-asserted only after
> all the configurations has been initialized, instead of de-asserting
> in probe. Fix it here.
>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 03/25] phy: cadence: Sierra: Create PHY only for "phy" or "link" sub-nodes
2022-01-28 8:11 ` [PATCH v2 03/25] phy: cadence: Sierra: Create PHY only for "phy" or "link" sub-nodes Aswath Govindraju
@ 2022-02-08 17:33 ` Tom Rini
0 siblings, 0 replies; 51+ messages in thread
From: Tom Rini @ 2022-02-08 17:33 UTC (permalink / raw)
To: Aswath Govindraju
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra
[-- Attachment #1: Type: text/plain, Size: 629 bytes --]
On Fri, Jan 28, 2022 at 01:41:30PM +0530, Aswath Govindraju wrote:
> From: Kishon Vijay Abraham I <kishon@ti.com>
>
> Cadence Sierra PHY driver registers PHY using devm_phy_create()
> for all sub-nodes of Sierra device tree node. However Sierra device
> tree node can have sub-nodes for the various clocks in addtion to the
> PHY. Use devm_phy_create() only for nodes with name "phy" (or "link"
> for old device tree) which represent the actual PHY.
>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 04/25] phy: cadence: Sierra: Move all clk_get_*() to a separate function
2022-01-28 8:11 ` [PATCH v2 04/25] phy: cadence: Sierra: Move all clk_get_*() to a separate function Aswath Govindraju
@ 2022-02-08 17:34 ` Tom Rini
0 siblings, 0 replies; 51+ messages in thread
From: Tom Rini @ 2022-02-08 17:34 UTC (permalink / raw)
To: Aswath Govindraju
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra
[-- Attachment #1: Type: text/plain, Size: 376 bytes --]
On Fri, Jan 28, 2022 at 01:41:31PM +0530, Aswath Govindraju wrote:
> From: Kishon Vijay Abraham I <kishon@ti.com>
>
> No functional change. Group all devm_clk_get_optional() to a
> separate function.
>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 05/25] phy: cadence: Sierra: Move all reset_control_get*() to a separate function
2022-01-28 8:11 ` [PATCH v2 05/25] phy: cadence: Sierra: Move all reset_control_get*() " Aswath Govindraju
@ 2022-02-08 17:34 ` Tom Rini
0 siblings, 0 replies; 51+ messages in thread
From: Tom Rini @ 2022-02-08 17:34 UTC (permalink / raw)
To: Aswath Govindraju
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra
[-- Attachment #1: Type: text/plain, Size: 411 bytes --]
On Fri, Jan 28, 2022 at 01:41:32PM +0530, Aswath Govindraju wrote:
> From: Kishon Vijay Abraham I <kishon@ti.com>
>
> No functional change. Group devm_reset_control_get() and
> devm_reset_control_get_optional() to a separate function.
>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 06/25] phy: cadence: Sierra: Add array of input clocks in "struct cdns_sierra_phy"
2022-01-28 8:11 ` [PATCH v2 06/25] phy: cadence: Sierra: Add array of input clocks in "struct cdns_sierra_phy" Aswath Govindraju
@ 2022-02-08 17:34 ` Tom Rini
0 siblings, 0 replies; 51+ messages in thread
From: Tom Rini @ 2022-02-08 17:34 UTC (permalink / raw)
To: Aswath Govindraju
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra
[-- Attachment #1: Type: text/plain, Size: 542 bytes --]
On Fri, Jan 28, 2022 at 01:41:33PM +0530, Aswath Govindraju wrote:
> From: Kishon Vijay Abraham I <kishon@ti.com>
>
> Instead of having separate structure members for each input clock, add
> an array for the input clocks within "struct cdns_sierra_phy". This is
> in preparation for adding more input clocks required for supporting
> additional clock combination.
>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 07/25] phy: cadence: Sierra: Add missing clk_disable_unprepare() in .remove callback
2022-01-28 8:11 ` [PATCH v2 07/25] phy: cadence: Sierra: Add missing clk_disable_unprepare() in .remove callback Aswath Govindraju
@ 2022-02-08 17:34 ` Tom Rini
0 siblings, 0 replies; 51+ messages in thread
From: Tom Rini @ 2022-02-08 17:34 UTC (permalink / raw)
To: Aswath Govindraju
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra
[-- Attachment #1: Type: text/plain, Size: 358 bytes --]
On Fri, Jan 28, 2022 at 01:41:34PM +0530, Aswath Govindraju wrote:
> From: Kishon Vijay Abraham I <kishon@ti.com>
>
> Add missing clk_disable_unprepare() in cdns_sierra_phy_remove().
>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 08/25] phy: cadence: Sierra: Add a UCLASS_PHY device for links
2022-01-28 8:11 ` [PATCH v2 08/25] phy: cadence: Sierra: Add a UCLASS_PHY device for links Aswath Govindraju
@ 2022-02-08 17:34 ` Tom Rini
0 siblings, 0 replies; 51+ messages in thread
From: Tom Rini @ 2022-02-08 17:34 UTC (permalink / raw)
To: Aswath Govindraju
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra
[-- Attachment #1: Type: text/plain, Size: 270 bytes --]
On Fri, Jan 28, 2022 at 01:41:35PM +0530, Aswath Govindraju wrote:
> Add a driver of type UCLASS_PHY for each of the link nodes in the serdes
> instance.
>
> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 09/25] phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as a clock
2022-01-28 8:11 ` [PATCH v2 09/25] phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as a clock Aswath Govindraju
@ 2022-02-08 17:34 ` Tom Rini
0 siblings, 0 replies; 51+ messages in thread
From: Tom Rini @ 2022-02-08 17:34 UTC (permalink / raw)
To: Aswath Govindraju
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra
[-- Attachment #1: Type: text/plain, Size: 469 bytes --]
On Fri, Jan 28, 2022 at 01:41:36PM +0530, Aswath Govindraju wrote:
> Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has
> two inputs, plllc_refclk (input from pll0_refclk) and refrcv (input from
> pll1_refclk). Model PLL_CMNLC and PLL_CMNLC1 as a clock so that it's
> possible to select one of these two inputs from device tree.
>
> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 10/25] phy: ti: phy-j721e-wiz.c: Fix the condition for setting P_ENABLE_FORCE
2022-01-28 8:11 ` [PATCH v2 10/25] phy: ti: phy-j721e-wiz.c: Fix the condition for setting P_ENABLE_FORCE Aswath Govindraju
@ 2022-02-08 17:34 ` Tom Rini
0 siblings, 0 replies; 51+ messages in thread
From: Tom Rini @ 2022-02-08 17:34 UTC (permalink / raw)
To: Aswath Govindraju
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra
[-- Attachment #1: Type: text/plain, Size: 275 bytes --]
On Fri, Jan 28, 2022 at 01:41:37PM +0530, Aswath Govindraju wrote:
> Fix the condition for setting P_ENABLE_FORCE bit, by syncing with the
> driver in kernel.
>
> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 11/25] board: ti: j721e: evm.c: Add support for probing SerDes0
2022-01-28 8:11 ` [PATCH v2 11/25] board: ti: j721e: evm.c: Add support for probing SerDes0 Aswath Govindraju
@ 2022-02-08 17:34 ` Tom Rini
0 siblings, 0 replies; 51+ messages in thread
From: Tom Rini @ 2022-02-08 17:34 UTC (permalink / raw)
To: Aswath Govindraju
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra
[-- Attachment #1: Type: text/plain, Size: 254 bytes --]
On Fri, Jan 28, 2022 at 01:41:38PM +0530, Aswath Govindraju wrote:
> Add support for probing, initializing and powering, SerDes0 instance.
>
> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 12/25] arm: dts: k3-j721e: Add support for PLL_CMNLC clocks in SerDes0
2022-01-28 8:11 ` [PATCH v2 12/25] arm: dts: k3-j721e: Add support for PLL_CMNLC clocks in SerDes0 Aswath Govindraju
@ 2022-02-08 17:34 ` Tom Rini
0 siblings, 0 replies; 51+ messages in thread
From: Tom Rini @ 2022-02-08 17:34 UTC (permalink / raw)
To: Aswath Govindraju
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra
[-- Attachment #1: Type: text/plain, Size: 541 bytes --]
On Fri, Jan 28, 2022 at 01:41:39PM +0530, Aswath Govindraju wrote:
> The PLL_CMNLC clocks are modelled as a child clock device of seirra. In the
> function device_probe, the corresponding clocks are probed before calling
> the device's probe. The PLL_CMNLC mux clock can only be created after the
> device's probe. Therefore, move assigned-clocks and assigned-clock-parents
> to the link nodes in U-Boot device tree file.
>
> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Applied to u-boot/master, thanks!
--
Tom
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[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 13/25] phy: cadence: Sierra: Prepare driver to add support for multilink configurations
2022-01-28 8:11 ` [PATCH v2 13/25] phy: cadence: Sierra: Prepare driver to add support for multilink configurations Aswath Govindraju
@ 2022-02-08 17:35 ` Tom Rini
0 siblings, 0 replies; 51+ messages in thread
From: Tom Rini @ 2022-02-08 17:35 UTC (permalink / raw)
To: Aswath Govindraju
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra
[-- Attachment #1: Type: text/plain, Size: 462 bytes --]
On Fri, Jan 28, 2022 at 01:41:40PM +0530, Aswath Govindraju wrote:
> From: Swapnil Jakhade <sjakhade@cadence.com>
>
> Sierra driver currently supports single link configurations only. Prepare
> driver to support multilink multiprotocol configurations along with
> different SSC modes.
>
> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 14/25] dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode
2022-01-28 8:11 ` [PATCH v2 14/25] dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode Aswath Govindraju
@ 2022-02-08 17:35 ` Tom Rini
0 siblings, 0 replies; 51+ messages in thread
From: Tom Rini @ 2022-02-08 17:35 UTC (permalink / raw)
To: Aswath Govindraju
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra
[-- Attachment #1: Type: text/plain, Size: 351 bytes --]
On Fri, Jan 28, 2022 at 01:41:41PM +0530, Aswath Govindraju wrote:
> From: Swapnil Jakhade <sjakhade@cadence.com>
>
> Add binding to specify Spread Spectrum Clocking mode used
>
> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 15/25] phy: cadence: Sierra: Add support to get SSC type from device tree.
2022-01-28 8:11 ` [PATCH v2 15/25] phy: cadence: Sierra: Add support to get SSC type from device tree Aswath Govindraju
@ 2022-02-08 17:35 ` Tom Rini
0 siblings, 0 replies; 51+ messages in thread
From: Tom Rini @ 2022-02-08 17:35 UTC (permalink / raw)
To: Aswath Govindraju
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra
[-- Attachment #1: Type: text/plain, Size: 330 bytes --]
On Fri, Jan 28, 2022 at 01:41:42PM +0530, Aswath Govindraju wrote:
> From: Swapnil Jakhade <sjakhade@cadence.com>
>
> Add support to get SSC type from DT.
>
> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 16/25] phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra documentation
2022-01-28 8:11 ` [PATCH v2 16/25] phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra documentation Aswath Govindraju
@ 2022-02-08 17:35 ` Tom Rini
0 siblings, 0 replies; 51+ messages in thread
From: Tom Rini @ 2022-02-08 17:35 UTC (permalink / raw)
To: Aswath Govindraju
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra
[-- Attachment #1: Type: text/plain, Size: 406 bytes --]
On Fri, Jan 28, 2022 at 01:41:43PM +0530, Aswath Govindraju wrote:
> From: Swapnil Jakhade <sjakhade@cadence.com>
>
> No functional change. Rename some regmap variables as mentioned in Sierra
> register description documentation.
>
> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 17/25] phy: cadence: Sierra: Add PHY PCS common register configurations
2022-01-28 8:11 ` [PATCH v2 17/25] phy: cadence: Sierra: Add PHY PCS common register configurations Aswath Govindraju
@ 2022-02-08 17:35 ` Tom Rini
0 siblings, 0 replies; 51+ messages in thread
From: Tom Rini @ 2022-02-08 17:35 UTC (permalink / raw)
To: Aswath Govindraju
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra
[-- Attachment #1: Type: text/plain, Size: 420 bytes --]
On Fri, Jan 28, 2022 at 01:41:44PM +0530, Aswath Govindraju wrote:
> From: Swapnil Jakhade <sjakhade@cadence.com>
>
> Add PHY PCS common register configuration sequences for single link.
> Update single link PCIe register sequence accordingly.
>
> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 18/25] phy: cadence: Sierra: Check cmn_ready assertion during PHY power on
2022-01-28 8:11 ` [PATCH v2 18/25] phy: cadence: Sierra: Check cmn_ready assertion during PHY power on Aswath Govindraju
@ 2022-02-08 17:35 ` Tom Rini
0 siblings, 0 replies; 51+ messages in thread
From: Tom Rini @ 2022-02-08 17:35 UTC (permalink / raw)
To: Aswath Govindraju
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra
[-- Attachment #1: Type: text/plain, Size: 367 bytes --]
On Fri, Jan 28, 2022 at 01:41:45PM +0530, Aswath Govindraju wrote:
> From: Swapnil Jakhade <sjakhade@cadence.com>
>
> Check if PMA cmn_ready is set indicating the startup process is complete.
>
> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 19/25] phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation
2022-01-28 8:11 ` [PATCH v2 19/25] phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation Aswath Govindraju
@ 2022-02-08 17:35 ` Tom Rini
0 siblings, 0 replies; 51+ messages in thread
From: Tom Rini @ 2022-02-08 17:35 UTC (permalink / raw)
To: Aswath Govindraju
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra
[-- Attachment #1: Type: text/plain, Size: 462 bytes --]
On Fri, Jan 28, 2022 at 01:41:46PM +0530, Aswath Govindraju wrote:
> From: Swapnil Jakhade <sjakhade@cadence.com>
>
> PIPE phy status is used to communicate the completion of several PHY
> functions. Check if PHY is ready for operation while configured for
> PIPE mode during startup.
>
> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 20/25] phy: cadence: Sierra: Update single link PCIe register configuration
2022-01-28 8:11 ` [PATCH v2 20/25] phy: cadence: Sierra: Update single link PCIe register configuration Aswath Govindraju
@ 2022-02-08 17:35 ` Tom Rini
0 siblings, 0 replies; 51+ messages in thread
From: Tom Rini @ 2022-02-08 17:35 UTC (permalink / raw)
To: Aswath Govindraju
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra
[-- Attachment #1: Type: text/plain, Size: 425 bytes --]
On Fri, Jan 28, 2022 at 01:41:47PM +0530, Aswath Govindraju wrote:
> From: Swapnil Jakhade <sjakhade@cadence.com>
>
> Add single link PCIe register configurations for no SSC and internal
> SSC. Also, add missing PMA lane registers for external SSC.
>
> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 21/25] phy: cadence: Sierra: Add support for PHY multilink configurations
2022-01-28 8:11 ` [PATCH v2 21/25] phy: cadence: Sierra: Add support for PHY multilink configurations Aswath Govindraju
@ 2022-02-08 17:35 ` Tom Rini
0 siblings, 0 replies; 51+ messages in thread
From: Tom Rini @ 2022-02-08 17:35 UTC (permalink / raw)
To: Aswath Govindraju
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra
[-- Attachment #1: Type: text/plain, Size: 395 bytes --]
On Fri, Jan 28, 2022 at 01:41:48PM +0530, Aswath Govindraju wrote:
> From: Swapnil Jakhade <sjakhade@cadence.com>
>
> Add support for multilink configuration of Sierra PHY. Currently,
> maximum two links are supported.
>
> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 22/25] phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration
2022-01-28 8:11 ` [PATCH v2 22/25] phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration Aswath Govindraju
@ 2022-02-08 17:35 ` Tom Rini
0 siblings, 0 replies; 51+ messages in thread
From: Tom Rini @ 2022-02-08 17:35 UTC (permalink / raw)
To: Aswath Govindraju
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra
[-- Attachment #1: Type: text/plain, Size: 363 bytes --]
On Fri, Jan 28, 2022 at 01:41:49PM +0530, Aswath Govindraju wrote:
> From: Swapnil Jakhade <sjakhade@cadence.com>
>
> Add register sequences for PCIe + QSGMII PHY multilink configuration.
>
> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 23/25] phy: cadence: Sierra: Add support for skipping configuration
2022-01-28 8:11 ` [PATCH v2 23/25] phy: cadence: Sierra: Add support for skipping configuration Aswath Govindraju
@ 2022-02-08 17:36 ` Tom Rini
0 siblings, 0 replies; 51+ messages in thread
From: Tom Rini @ 2022-02-08 17:36 UTC (permalink / raw)
To: Aswath Govindraju
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra
[-- Attachment #1: Type: text/plain, Size: 474 bytes --]
On Fri, Jan 28, 2022 at 01:41:50PM +0530, Aswath Govindraju wrote:
> In some cases, a single SerDes instance can be shared between two different
> processors, each using a separate link. In these cases, the SerDes
> configuration is done in an earlier boot stage. Therefore, add support to
> skip reconfiguring, if it is was already configured beforehand.
>
> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 24/25] arm: dts: k3-j721e: Add support for multilink PCIe + QSGMII
2022-01-28 8:11 ` [PATCH v2 24/25] arm: dts: k3-j721e: Add support for multilink PCIe + QSGMII Aswath Govindraju
@ 2022-02-08 17:36 ` Tom Rini
0 siblings, 0 replies; 51+ messages in thread
From: Tom Rini @ 2022-02-08 17:36 UTC (permalink / raw)
To: Aswath Govindraju
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra
[-- Attachment #1: Type: text/plain, Size: 232 bytes --]
On Fri, Jan 28, 2022 at 01:41:51PM +0530, Aswath Govindraju wrote:
> Add support for QSGMII multilink configuration.
>
> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 25/25] include: configs: j721e_evm: Add support to boot ethfw core in j721e
2022-01-28 8:11 ` [PATCH v2 25/25] include: configs: j721e_evm: Add support to boot ethfw core in j721e Aswath Govindraju
@ 2022-02-08 17:36 ` Tom Rini
0 siblings, 0 replies; 51+ messages in thread
From: Tom Rini @ 2022-02-08 17:36 UTC (permalink / raw)
To: Aswath Govindraju
Cc: u-boot, Sanket Parmar, Alan Douglas, Swapnil Jakhade,
Kishon Vijay Abraham I, Tero Kristo, Vignesh Raghavendra
[-- Attachment #1: Type: text/plain, Size: 234 bytes --]
On Fri, Jan 28, 2022 at 01:41:52PM +0530, Aswath Govindraju wrote:
> Add configs to enable booting ethfw core in j721e
>
> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 51+ messages in thread
end of thread, other threads:[~2022-02-08 17:43 UTC | newest]
Thread overview: 51+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-01-28 8:11 [PATCH v2 00/25] SIERRA: Add support for Mulitlink Configuration Aswath Govindraju
2022-01-28 8:11 ` [PATCH v2 01/25] phy: cadence: sierra: Fix for USB3 U1/U2 state Aswath Govindraju
2022-02-08 17:33 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 02/25] phy: cadence: Sierra: Fix PHY power_on sequence Aswath Govindraju
2022-02-08 17:33 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 03/25] phy: cadence: Sierra: Create PHY only for "phy" or "link" sub-nodes Aswath Govindraju
2022-02-08 17:33 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 04/25] phy: cadence: Sierra: Move all clk_get_*() to a separate function Aswath Govindraju
2022-02-08 17:34 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 05/25] phy: cadence: Sierra: Move all reset_control_get*() " Aswath Govindraju
2022-02-08 17:34 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 06/25] phy: cadence: Sierra: Add array of input clocks in "struct cdns_sierra_phy" Aswath Govindraju
2022-02-08 17:34 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 07/25] phy: cadence: Sierra: Add missing clk_disable_unprepare() in .remove callback Aswath Govindraju
2022-02-08 17:34 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 08/25] phy: cadence: Sierra: Add a UCLASS_PHY device for links Aswath Govindraju
2022-02-08 17:34 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 09/25] phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as a clock Aswath Govindraju
2022-02-08 17:34 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 10/25] phy: ti: phy-j721e-wiz.c: Fix the condition for setting P_ENABLE_FORCE Aswath Govindraju
2022-02-08 17:34 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 11/25] board: ti: j721e: evm.c: Add support for probing SerDes0 Aswath Govindraju
2022-02-08 17:34 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 12/25] arm: dts: k3-j721e: Add support for PLL_CMNLC clocks in SerDes0 Aswath Govindraju
2022-02-08 17:34 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 13/25] phy: cadence: Sierra: Prepare driver to add support for multilink configurations Aswath Govindraju
2022-02-08 17:35 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 14/25] dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode Aswath Govindraju
2022-02-08 17:35 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 15/25] phy: cadence: Sierra: Add support to get SSC type from device tree Aswath Govindraju
2022-02-08 17:35 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 16/25] phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra documentation Aswath Govindraju
2022-02-08 17:35 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 17/25] phy: cadence: Sierra: Add PHY PCS common register configurations Aswath Govindraju
2022-02-08 17:35 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 18/25] phy: cadence: Sierra: Check cmn_ready assertion during PHY power on Aswath Govindraju
2022-02-08 17:35 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 19/25] phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation Aswath Govindraju
2022-02-08 17:35 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 20/25] phy: cadence: Sierra: Update single link PCIe register configuration Aswath Govindraju
2022-02-08 17:35 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 21/25] phy: cadence: Sierra: Add support for PHY multilink configurations Aswath Govindraju
2022-02-08 17:35 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 22/25] phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration Aswath Govindraju
2022-02-08 17:35 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 23/25] phy: cadence: Sierra: Add support for skipping configuration Aswath Govindraju
2022-02-08 17:36 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 24/25] arm: dts: k3-j721e: Add support for multilink PCIe + QSGMII Aswath Govindraju
2022-02-08 17:36 ` Tom Rini
2022-01-28 8:11 ` [PATCH v2 25/25] include: configs: j721e_evm: Add support to boot ethfw core in j721e Aswath Govindraju
2022-02-08 17:36 ` Tom Rini
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