* [PATCH 01/11] target/ppc: Introduce powerpc_excp_booke
2022-01-28 22:40 [PATCH 00/11] target/ppc: powerpc_excp improvements [BookE] (6/n) Fabiano Rosas
@ 2022-01-28 22:40 ` Fabiano Rosas
2022-01-28 22:40 ` [PATCH 02/11] target/ppc: Simplify powerpc_excp_booke Fabiano Rosas
` (11 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Fabiano Rosas @ 2022-01-28 22:40 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
Introduce a new powerpc_excp function specific for BookE CPUs. This
commit copies powerpc_excp_legacy verbatim so the next one has a clean
diff.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 474 +++++++++++++++++++++++++++++++++++++++
1 file changed, 474 insertions(+)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index c107953dec..1571ab6496 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -745,6 +745,477 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
powerpc_set_excp_state(cpu, vector, new_msr);
}
+static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
+{
+ CPUState *cs = CPU(cpu);
+ CPUPPCState *env = &cpu->env;
+ int excp_model = env->excp_model;
+ target_ulong msr, new_msr, vector;
+ int srr0, srr1, lev = -1;
+
+ if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
+ cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
+ }
+
+ qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
+ " => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
+ excp, env->error_code);
+
+ /* new srr1 value excluding must-be-zero bits */
+ if (excp_model == POWERPC_EXCP_BOOKE) {
+ msr = env->msr;
+ } else {
+ msr = env->msr & ~0x783f0000ULL;
+ }
+
+ /*
+ * new interrupt handler msr preserves existing HV and ME unless
+ * explicitly overriden
+ */
+ new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
+
+ /* target registers */
+ srr0 = SPR_SRR0;
+ srr1 = SPR_SRR1;
+
+ /*
+ * check for special resume at 0x100 from doze/nap/sleep/winkle on
+ * P7/P8/P9
+ */
+ if (env->resume_as_sreset) {
+ excp = powerpc_reset_wakeup(cs, env, excp, &msr);
+ }
+
+ /*
+ * Hypervisor emulation assistance interrupt only exists on server
+ * arch 2.05 server or later. We also don't want to generate it if
+ * we don't have HVB in msr_mask (PAPR mode).
+ */
+ if (excp == POWERPC_EXCP_HV_EMU
+#if defined(TARGET_PPC64)
+ && !(mmu_is_64bit(env->mmu_model) && (env->msr_mask & MSR_HVB))
+#endif /* defined(TARGET_PPC64) */
+
+ ) {
+ excp = POWERPC_EXCP_PROGRAM;
+ }
+
+#ifdef TARGET_PPC64
+ /*
+ * SPEU and VPU share the same IVOR but they exist in different
+ * processors. SPEU is e500v1/2 only and VPU is e6500 only.
+ */
+ if (excp_model == POWERPC_EXCP_BOOKE && excp == POWERPC_EXCP_VPU) {
+ excp = POWERPC_EXCP_SPEU;
+ }
+#endif
+
+ vector = env->excp_vectors[excp];
+ if (vector == (target_ulong)-1ULL) {
+ cpu_abort(cs, "Raised an exception without defined vector %d\n",
+ excp);
+ }
+
+ vector |= env->excp_prefix;
+
+ switch (excp) {
+ case POWERPC_EXCP_CRITICAL: /* Critical input */
+ switch (excp_model) {
+ case POWERPC_EXCP_40x:
+ srr0 = SPR_40x_SRR2;
+ srr1 = SPR_40x_SRR3;
+ break;
+ case POWERPC_EXCP_BOOKE:
+ srr0 = SPR_BOOKE_CSRR0;
+ srr1 = SPR_BOOKE_CSRR1;
+ break;
+ case POWERPC_EXCP_G2:
+ break;
+ default:
+ goto excp_invalid;
+ }
+ break;
+ case POWERPC_EXCP_MCHECK: /* Machine check exception */
+ if (msr_me == 0) {
+ /*
+ * Machine check exception is not enabled. Enter
+ * checkstop state.
+ */
+ fprintf(stderr, "Machine check while not allowed. "
+ "Entering checkstop state\n");
+ if (qemu_log_separate()) {
+ qemu_log("Machine check while not allowed. "
+ "Entering checkstop state\n");
+ }
+ cs->halted = 1;
+ cpu_interrupt_exittb(cs);
+ }
+ if (env->msr_mask & MSR_HVB) {
+ /*
+ * ISA specifies HV, but can be delivered to guest with HV
+ * clear (e.g., see FWNMI in PAPR).
+ */
+ new_msr |= (target_ulong)MSR_HVB;
+ }
+
+ /* machine check exceptions don't have ME set */
+ new_msr &= ~((target_ulong)1 << MSR_ME);
+
+ /* XXX: should also have something loaded in DAR / DSISR */
+ switch (excp_model) {
+ case POWERPC_EXCP_40x:
+ srr0 = SPR_40x_SRR2;
+ srr1 = SPR_40x_SRR3;
+ break;
+ case POWERPC_EXCP_BOOKE:
+ /* FIXME: choose one or the other based on CPU type */
+ srr0 = SPR_BOOKE_MCSRR0;
+ srr1 = SPR_BOOKE_MCSRR1;
+
+ env->spr[SPR_BOOKE_CSRR0] = env->nip;
+ env->spr[SPR_BOOKE_CSRR1] = msr;
+ break;
+ default:
+ break;
+ }
+ break;
+ case POWERPC_EXCP_DSI: /* Data storage exception */
+ trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
+ break;
+ case POWERPC_EXCP_ISI: /* Instruction storage exception */
+ trace_ppc_excp_isi(msr, env->nip);
+ msr |= env->error_code;
+ break;
+ case POWERPC_EXCP_EXTERNAL: /* External input */
+ {
+ bool lpes0;
+
+ cs = CPU(cpu);
+
+ /*
+ * Exception targeting modifiers
+ *
+ * LPES0 is supported on POWER7/8/9
+ * LPES1 is not supported (old iSeries mode)
+ *
+ * On anything else, we behave as if LPES0 is 1
+ * (externals don't alter MSR:HV)
+ */
+#if defined(TARGET_PPC64)
+ if (excp_model == POWERPC_EXCP_POWER7 ||
+ excp_model == POWERPC_EXCP_POWER8 ||
+ excp_model == POWERPC_EXCP_POWER9 ||
+ excp_model == POWERPC_EXCP_POWER10) {
+ lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
+ } else
+#endif /* defined(TARGET_PPC64) */
+ {
+ lpes0 = true;
+ }
+
+ if (!lpes0) {
+ new_msr |= (target_ulong)MSR_HVB;
+ new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
+ srr0 = SPR_HSRR0;
+ srr1 = SPR_HSRR1;
+ }
+ if (env->mpic_proxy) {
+ /* IACK the IRQ on delivery */
+ env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
+ }
+ break;
+ }
+ case POWERPC_EXCP_ALIGN: /* Alignment exception */
+ /* Get rS/rD and rA from faulting opcode */
+ /*
+ * Note: the opcode fields will not be set properly for a
+ * direct store load/store, but nobody cares as nobody
+ * actually uses direct store segments.
+ */
+ env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
+ break;
+ case POWERPC_EXCP_PROGRAM: /* Program exception */
+ switch (env->error_code & ~0xF) {
+ case POWERPC_EXCP_FP:
+ if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
+ trace_ppc_excp_fp_ignore();
+ cs->exception_index = POWERPC_EXCP_NONE;
+ env->error_code = 0;
+ return;
+ }
+
+ /*
+ * FP exceptions always have NIP pointing to the faulting
+ * instruction, so always use store_next and claim we are
+ * precise in the MSR.
+ */
+ msr |= 0x00100000;
+ env->spr[SPR_BOOKE_ESR] = ESR_FP;
+ break;
+ case POWERPC_EXCP_INVAL:
+ trace_ppc_excp_inval(env->nip);
+ msr |= 0x00080000;
+ env->spr[SPR_BOOKE_ESR] = ESR_PIL;
+ break;
+ case POWERPC_EXCP_PRIV:
+ msr |= 0x00040000;
+ env->spr[SPR_BOOKE_ESR] = ESR_PPR;
+ break;
+ case POWERPC_EXCP_TRAP:
+ msr |= 0x00020000;
+ env->spr[SPR_BOOKE_ESR] = ESR_PTR;
+ break;
+ default:
+ /* Should never occur */
+ cpu_abort(cs, "Invalid program exception %d. Aborting\n",
+ env->error_code);
+ break;
+ }
+ break;
+ case POWERPC_EXCP_SYSCALL: /* System call exception */
+ lev = env->error_code;
+
+ if ((lev == 1) && cpu->vhyp) {
+ dump_hcall(env);
+ } else {
+ dump_syscall(env);
+ }
+
+ /*
+ * We need to correct the NIP which in this case is supposed
+ * to point to the next instruction
+ */
+ env->nip += 4;
+
+ /* "PAPR mode" built-in hypercall emulation */
+ if ((lev == 1) && cpu->vhyp) {
+ PPCVirtualHypervisorClass *vhc =
+ PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
+ vhc->hypercall(cpu->vhyp, cpu);
+ return;
+ }
+ if (lev == 1) {
+ new_msr |= (target_ulong)MSR_HVB;
+ }
+ break;
+ case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception */
+ lev = env->error_code;
+ dump_syscall(env);
+ env->nip += 4;
+ new_msr |= env->msr & ((target_ulong)1 << MSR_EE);
+ new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
+
+ vector += lev * 0x20;
+
+ env->lr = env->nip;
+ env->ctr = msr;
+ break;
+ case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
+ case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
+ case POWERPC_EXCP_DECR: /* Decrementer exception */
+ break;
+ case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
+ /* FIT on 4xx */
+ trace_ppc_excp_print("FIT");
+ break;
+ case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
+ trace_ppc_excp_print("WDT");
+ switch (excp_model) {
+ case POWERPC_EXCP_BOOKE:
+ srr0 = SPR_BOOKE_CSRR0;
+ srr1 = SPR_BOOKE_CSRR1;
+ break;
+ default:
+ break;
+ }
+ break;
+ case POWERPC_EXCP_DTLB: /* Data TLB error */
+ case POWERPC_EXCP_ITLB: /* Instruction TLB error */
+ break;
+ case POWERPC_EXCP_DEBUG: /* Debug interrupt */
+ if (env->flags & POWERPC_FLAG_DE) {
+ /* FIXME: choose one or the other based on CPU type */
+ srr0 = SPR_BOOKE_DSRR0;
+ srr1 = SPR_BOOKE_DSRR1;
+
+ env->spr[SPR_BOOKE_CSRR0] = env->nip;
+ env->spr[SPR_BOOKE_CSRR1] = msr;
+
+ /* DBSR already modified by caller */
+ } else {
+ cpu_abort(cs, "Debug exception triggered on unsupported model\n");
+ }
+ break;
+ case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/VPU */
+ env->spr[SPR_BOOKE_ESR] = ESR_SPV;
+ break;
+ case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
+ break;
+ case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
+ srr0 = SPR_BOOKE_CSRR0;
+ srr1 = SPR_BOOKE_CSRR1;
+ break;
+ case POWERPC_EXCP_RESET: /* System reset exception */
+ /* A power-saving exception sets ME, otherwise it is unchanged */
+ if (msr_pow) {
+ /* indicate that we resumed from power save mode */
+ msr |= 0x10000;
+ new_msr |= ((target_ulong)1 << MSR_ME);
+ }
+ if (env->msr_mask & MSR_HVB) {
+ /*
+ * ISA specifies HV, but can be delivered to guest with HV
+ * clear (e.g., see FWNMI in PAPR, NMI injection in QEMU).
+ */
+ new_msr |= (target_ulong)MSR_HVB;
+ } else {
+ if (msr_pow) {
+ cpu_abort(cs, "Trying to deliver power-saving system reset "
+ "exception %d with no HV support\n", excp);
+ }
+ }
+ break;
+ case POWERPC_EXCP_DSEG: /* Data segment exception */
+ case POWERPC_EXCP_ISEG: /* Instruction segment exception */
+ case POWERPC_EXCP_TRACE: /* Trace exception */
+ break;
+ case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
+ msr |= env->error_code;
+ /* fall through */
+ case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
+ case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
+ case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
+ case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
+ case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt */
+ case POWERPC_EXCP_HV_EMU:
+ case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization */
+ srr0 = SPR_HSRR0;
+ srr1 = SPR_HSRR1;
+ new_msr |= (target_ulong)MSR_HVB;
+ new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
+ break;
+ case POWERPC_EXCP_VPU: /* Vector unavailable exception */
+ case POWERPC_EXCP_VSXU: /* VSX unavailable exception */
+ case POWERPC_EXCP_FU: /* Facility unavailable exception */
+#ifdef TARGET_PPC64
+ env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56);
+#endif
+ break;
+ case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Exception */
+#ifdef TARGET_PPC64
+ env->spr[SPR_HFSCR] |= ((target_ulong)env->error_code << FSCR_IC_POS);
+ srr0 = SPR_HSRR0;
+ srr1 = SPR_HSRR1;
+ new_msr |= (target_ulong)MSR_HVB;
+ new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
+#endif
+ break;
+ case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
+ trace_ppc_excp_print("PIT");
+ break;
+ case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
+ case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
+ case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
+ switch (excp_model) {
+ case POWERPC_EXCP_602:
+ case POWERPC_EXCP_603:
+ case POWERPC_EXCP_G2:
+ /* Swap temporary saved registers with GPRs */
+ if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
+ new_msr |= (target_ulong)1 << MSR_TGPR;
+ hreg_swap_gpr_tgpr(env);
+ }
+ /* fall through */
+ case POWERPC_EXCP_7x5:
+ ppc_excp_debug_sw_tlb(env, excp);
+
+ msr |= env->crf[0] << 28;
+ msr |= env->error_code; /* key, D/I, S/L bits */
+ /* Set way using a LRU mechanism */
+ msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
+ break;
+ default:
+ cpu_abort(cs, "Invalid TLB miss exception\n");
+ break;
+ }
+ break;
+ case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
+ case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
+ case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
+ case POWERPC_EXCP_IO: /* IO error exception */
+ case POWERPC_EXCP_RUNM: /* Run mode exception */
+ case POWERPC_EXCP_EMUL: /* Emulation trap exception */
+ case POWERPC_EXCP_FPA: /* Floating-point assist exception */
+ case POWERPC_EXCP_DABR: /* Data address breakpoint */
+ case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
+ case POWERPC_EXCP_SMI: /* System management interrupt */
+ case POWERPC_EXCP_THERM: /* Thermal interrupt */
+ case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
+ case POWERPC_EXCP_VPUA: /* Vector assist exception */
+ case POWERPC_EXCP_SOFTP: /* Soft patch exception */
+ case POWERPC_EXCP_MAINT: /* Maintenance exception */
+ case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
+ case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
+ cpu_abort(cs, "%s exception not implemented\n",
+ powerpc_excp_name(excp));
+ break;
+ default:
+ excp_invalid:
+ cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
+ break;
+ }
+
+ /* Sanity check */
+ if (!(env->msr_mask & MSR_HVB)) {
+ if (new_msr & MSR_HVB) {
+ cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
+ "no HV support\n", excp);
+ }
+ if (srr0 == SPR_HSRR0) {
+ cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
+ "no HV support\n", excp);
+ }
+ }
+
+ /*
+ * Sort out endianness of interrupt, this differs depending on the
+ * CPU, the HV mode, etc...
+ */
+ if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) {
+ new_msr |= (target_ulong)1 << MSR_LE;
+ }
+
+#if defined(TARGET_PPC64)
+ if (excp_model == POWERPC_EXCP_BOOKE) {
+ if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
+ /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
+ new_msr |= (target_ulong)1 << MSR_CM;
+ } else {
+ vector = (uint32_t)vector;
+ }
+ } else {
+ if (!msr_isf && !mmu_is_64bit(env->mmu_model)) {
+ vector = (uint32_t)vector;
+ } else {
+ new_msr |= (target_ulong)1 << MSR_SF;
+ }
+ }
+#endif
+
+ if (excp != POWERPC_EXCP_SYSCALL_VECTORED) {
+ /* Save PC */
+ env->spr[srr0] = env->nip;
+
+ /* Save MSR */
+ env->spr[srr1] = msr;
+ }
+
+ /* This can update new_msr and vector if AIL applies */
+ ppc_excp_apply_ail(cpu, excp_model, excp, msr, &new_msr, &vector);
+
+ powerpc_set_excp_state(cpu, vector, new_msr);
+}
+
#ifdef TARGET_PPC64
static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
{
@@ -1531,6 +2002,9 @@ static void powerpc_excp(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_74xx:
powerpc_excp_74xx(cpu, excp);
break;
+ case POWERPC_EXCP_BOOKE:
+ powerpc_excp_booke(cpu, excp);
+ break;
case POWERPC_EXCP_970:
case POWERPC_EXCP_POWER7:
case POWERPC_EXCP_POWER8:
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 02/11] target/ppc: Simplify powerpc_excp_booke
2022-01-28 22:40 [PATCH 00/11] target/ppc: powerpc_excp improvements [BookE] (6/n) Fabiano Rosas
2022-01-28 22:40 ` [PATCH 01/11] target/ppc: Introduce powerpc_excp_booke Fabiano Rosas
@ 2022-01-28 22:40 ` Fabiano Rosas
2022-01-28 22:40 ` [PATCH 03/11] target/ppc: booke: Critical exception cleanup Fabiano Rosas
` (10 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Fabiano Rosas @ 2022-01-28 22:40 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
Differences from the generic powerpc_excp code:
- No MSR bits are cleared at interrupt dispatch;
- No MSR_HV;
- No power saving states;
- No Hypervisor Emulation Assistance;
- SPEU needs special handling;
- Big endian only;
- Both 64 and 32 bits;
- No System call vectored;
- No Alternate Interrupt Location.
Exceptions used:
POWERPC_EXCP_ALIGN
POWERPC_EXCP_APU
POWERPC_EXCP_CRITICAL
POWERPC_EXCP_DEBUG
POWERPC_EXCP_DECR
POWERPC_EXCP_DSI
POWERPC_EXCP_DTLB
POWERPC_EXCP_EFPDI
POWERPC_EXCP_EFPRI
POWERPC_EXCP_EXTERNAL
POWERPC_EXCP_FIT
POWERPC_EXCP_FPU
POWERPC_EXCP_ISI
POWERPC_EXCP_ITLB
POWERPC_EXCP_MCHECK
POWERPC_EXCP_PROGRAM
POWERPC_EXCP_RESET
POWERPC_EXCP_SPEU
POWERPC_EXCP_SYSCALL
POWERPC_EXCP_WDT
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 165 ++++-----------------------------------
1 file changed, 14 insertions(+), 151 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 1571ab6496..596c16a678 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -761,42 +761,23 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
" => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
excp, env->error_code);
- /* new srr1 value excluding must-be-zero bits */
- if (excp_model == POWERPC_EXCP_BOOKE) {
- msr = env->msr;
- } else {
- msr = env->msr & ~0x783f0000ULL;
- }
+ msr = env->msr;
/*
- * new interrupt handler msr preserves existing HV and ME unless
+ * new interrupt handler msr preserves existing ME unless
* explicitly overriden
*/
- new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
+ new_msr = env->msr & ((target_ulong)1 << MSR_ME);
/* target registers */
srr0 = SPR_SRR0;
srr1 = SPR_SRR1;
- /*
- * check for special resume at 0x100 from doze/nap/sleep/winkle on
- * P7/P8/P9
- */
- if (env->resume_as_sreset) {
- excp = powerpc_reset_wakeup(cs, env, excp, &msr);
- }
-
/*
* Hypervisor emulation assistance interrupt only exists on server
- * arch 2.05 server or later. We also don't want to generate it if
- * we don't have HVB in msr_mask (PAPR mode).
+ * arch 2.05 server or later.
*/
- if (excp == POWERPC_EXCP_HV_EMU
-#if defined(TARGET_PPC64)
- && !(mmu_is_64bit(env->mmu_model) && (env->msr_mask & MSR_HVB))
-#endif /* defined(TARGET_PPC64) */
-
- ) {
+ if (excp == POWERPC_EXCP_HV_EMU) {
excp = POWERPC_EXCP_PROGRAM;
}
@@ -805,7 +786,7 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
* SPEU and VPU share the same IVOR but they exist in different
* processors. SPEU is e500v1/2 only and VPU is e6500 only.
*/
- if (excp_model == POWERPC_EXCP_BOOKE && excp == POWERPC_EXCP_VPU) {
+ if (excp == POWERPC_EXCP_VPU) {
excp = POWERPC_EXCP_SPEU;
}
#endif
@@ -998,18 +979,6 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
new_msr |= (target_ulong)MSR_HVB;
}
break;
- case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception */
- lev = env->error_code;
- dump_syscall(env);
- env->nip += 4;
- new_msr |= env->msr & ((target_ulong)1 << MSR_EE);
- new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
-
- vector += lev * 0x20;
-
- env->lr = env->nip;
- env->ctr = msr;
- break;
case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
case POWERPC_EXCP_DECR: /* Decrementer exception */
@@ -1049,12 +1018,6 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/VPU */
env->spr[SPR_BOOKE_ESR] = ESR_SPV;
break;
- case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
- break;
- case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
- srr0 = SPR_BOOKE_CSRR0;
- srr1 = SPR_BOOKE_CSRR1;
- break;
case POWERPC_EXCP_RESET: /* System reset exception */
/* A power-saving exception sets ME, otherwise it is unchanged */
if (msr_pow) {
@@ -1075,87 +1038,8 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
}
}
break;
- case POWERPC_EXCP_DSEG: /* Data segment exception */
- case POWERPC_EXCP_ISEG: /* Instruction segment exception */
- case POWERPC_EXCP_TRACE: /* Trace exception */
- break;
- case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
- msr |= env->error_code;
- /* fall through */
- case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
- case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
- case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
- case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
- case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt */
- case POWERPC_EXCP_HV_EMU:
- case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization */
- srr0 = SPR_HSRR0;
- srr1 = SPR_HSRR1;
- new_msr |= (target_ulong)MSR_HVB;
- new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
- break;
- case POWERPC_EXCP_VPU: /* Vector unavailable exception */
- case POWERPC_EXCP_VSXU: /* VSX unavailable exception */
- case POWERPC_EXCP_FU: /* Facility unavailable exception */
-#ifdef TARGET_PPC64
- env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56);
-#endif
- break;
- case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Exception */
-#ifdef TARGET_PPC64
- env->spr[SPR_HFSCR] |= ((target_ulong)env->error_code << FSCR_IC_POS);
- srr0 = SPR_HSRR0;
- srr1 = SPR_HSRR1;
- new_msr |= (target_ulong)MSR_HVB;
- new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
-#endif
- break;
- case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
- trace_ppc_excp_print("PIT");
- break;
- case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
- case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
- case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
- switch (excp_model) {
- case POWERPC_EXCP_602:
- case POWERPC_EXCP_603:
- case POWERPC_EXCP_G2:
- /* Swap temporary saved registers with GPRs */
- if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
- new_msr |= (target_ulong)1 << MSR_TGPR;
- hreg_swap_gpr_tgpr(env);
- }
- /* fall through */
- case POWERPC_EXCP_7x5:
- ppc_excp_debug_sw_tlb(env, excp);
-
- msr |= env->crf[0] << 28;
- msr |= env->error_code; /* key, D/I, S/L bits */
- /* Set way using a LRU mechanism */
- msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
- break;
- default:
- cpu_abort(cs, "Invalid TLB miss exception\n");
- break;
- }
- break;
case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
- case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
- case POWERPC_EXCP_IO: /* IO error exception */
- case POWERPC_EXCP_RUNM: /* Run mode exception */
- case POWERPC_EXCP_EMUL: /* Emulation trap exception */
- case POWERPC_EXCP_FPA: /* Floating-point assist exception */
- case POWERPC_EXCP_DABR: /* Data address breakpoint */
- case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
- case POWERPC_EXCP_SMI: /* System management interrupt */
- case POWERPC_EXCP_THERM: /* Thermal interrupt */
- case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
- case POWERPC_EXCP_VPUA: /* Vector assist exception */
- case POWERPC_EXCP_SOFTP: /* Soft patch exception */
- case POWERPC_EXCP_MAINT: /* Maintenance exception */
- case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
- case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
cpu_abort(cs, "%s exception not implemented\n",
powerpc_excp_name(excp));
break;
@@ -1177,41 +1061,20 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
}
}
- /*
- * Sort out endianness of interrupt, this differs depending on the
- * CPU, the HV mode, etc...
- */
- if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) {
- new_msr |= (target_ulong)1 << MSR_LE;
- }
-
#if defined(TARGET_PPC64)
- if (excp_model == POWERPC_EXCP_BOOKE) {
- if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
- /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
- new_msr |= (target_ulong)1 << MSR_CM;
- } else {
- vector = (uint32_t)vector;
- }
+ if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
+ /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
+ new_msr |= (target_ulong)1 << MSR_CM;
} else {
- if (!msr_isf && !mmu_is_64bit(env->mmu_model)) {
- vector = (uint32_t)vector;
- } else {
- new_msr |= (target_ulong)1 << MSR_SF;
- }
+ vector = (uint32_t)vector;
}
#endif
- if (excp != POWERPC_EXCP_SYSCALL_VECTORED) {
- /* Save PC */
- env->spr[srr0] = env->nip;
+ /* Save PC */
+ env->spr[srr0] = env->nip;
- /* Save MSR */
- env->spr[srr1] = msr;
- }
-
- /* This can update new_msr and vector if AIL applies */
- ppc_excp_apply_ail(cpu, excp_model, excp, msr, &new_msr, &vector);
+ /* Save MSR */
+ env->spr[srr1] = msr;
powerpc_set_excp_state(cpu, vector, new_msr);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 03/11] target/ppc: booke: Critical exception cleanup
2022-01-28 22:40 [PATCH 00/11] target/ppc: powerpc_excp improvements [BookE] (6/n) Fabiano Rosas
2022-01-28 22:40 ` [PATCH 01/11] target/ppc: Introduce powerpc_excp_booke Fabiano Rosas
2022-01-28 22:40 ` [PATCH 02/11] target/ppc: Simplify powerpc_excp_booke Fabiano Rosas
@ 2022-01-28 22:40 ` Fabiano Rosas
2022-01-28 22:40 ` [PATCH 04/11] target/ppc: booke: Machine Check cleanups Fabiano Rosas
` (9 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Fabiano Rosas @ 2022-01-28 22:40 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
Remove 40x and G2 code.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 17 ++---------------
1 file changed, 2 insertions(+), 15 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 596c16a678..8a656ace6f 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -801,20 +801,8 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
switch (excp) {
case POWERPC_EXCP_CRITICAL: /* Critical input */
- switch (excp_model) {
- case POWERPC_EXCP_40x:
- srr0 = SPR_40x_SRR2;
- srr1 = SPR_40x_SRR3;
- break;
- case POWERPC_EXCP_BOOKE:
- srr0 = SPR_BOOKE_CSRR0;
- srr1 = SPR_BOOKE_CSRR1;
- break;
- case POWERPC_EXCP_G2:
- break;
- default:
- goto excp_invalid;
- }
+ srr0 = SPR_BOOKE_CSRR0;
+ srr1 = SPR_BOOKE_CSRR1;
break;
case POWERPC_EXCP_MCHECK: /* Machine check exception */
if (msr_me == 0) {
@@ -1044,7 +1032,6 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
powerpc_excp_name(excp));
break;
default:
- excp_invalid:
cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
break;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 04/11] target/ppc: booke: Machine Check cleanups
2022-01-28 22:40 [PATCH 00/11] target/ppc: powerpc_excp improvements [BookE] (6/n) Fabiano Rosas
` (2 preceding siblings ...)
2022-01-28 22:40 ` [PATCH 03/11] target/ppc: booke: Critical exception cleanup Fabiano Rosas
@ 2022-01-28 22:40 ` Fabiano Rosas
2022-01-28 22:40 ` [PATCH 05/11] target/ppc: booke: Data Storage exception cleanup Fabiano Rosas
` (8 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Fabiano Rosas @ 2022-01-28 22:40 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
There's no MSR_HV in BookE.
Also remove 40x code.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 29 ++++++-----------------------
1 file changed, 6 insertions(+), 23 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 8a656ace6f..4753b81527 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -819,34 +819,17 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
cs->halted = 1;
cpu_interrupt_exittb(cs);
}
- if (env->msr_mask & MSR_HVB) {
- /*
- * ISA specifies HV, but can be delivered to guest with HV
- * clear (e.g., see FWNMI in PAPR).
- */
- new_msr |= (target_ulong)MSR_HVB;
- }
/* machine check exceptions don't have ME set */
new_msr &= ~((target_ulong)1 << MSR_ME);
- /* XXX: should also have something loaded in DAR / DSISR */
- switch (excp_model) {
- case POWERPC_EXCP_40x:
- srr0 = SPR_40x_SRR2;
- srr1 = SPR_40x_SRR3;
- break;
- case POWERPC_EXCP_BOOKE:
- /* FIXME: choose one or the other based on CPU type */
- srr0 = SPR_BOOKE_MCSRR0;
- srr1 = SPR_BOOKE_MCSRR1;
+ /* FIXME: choose one or the other based on CPU type */
+ srr0 = SPR_BOOKE_MCSRR0;
+ srr1 = SPR_BOOKE_MCSRR1;
+
+ env->spr[SPR_BOOKE_CSRR0] = env->nip;
+ env->spr[SPR_BOOKE_CSRR1] = msr;
- env->spr[SPR_BOOKE_CSRR0] = env->nip;
- env->spr[SPR_BOOKE_CSRR1] = msr;
- break;
- default:
- break;
- }
break;
case POWERPC_EXCP_DSI: /* Data storage exception */
trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 05/11] target/ppc: booke: Data Storage exception cleanup
2022-01-28 22:40 [PATCH 00/11] target/ppc: powerpc_excp improvements [BookE] (6/n) Fabiano Rosas
` (3 preceding siblings ...)
2022-01-28 22:40 ` [PATCH 04/11] target/ppc: booke: Machine Check cleanups Fabiano Rosas
@ 2022-01-28 22:40 ` Fabiano Rosas
2022-01-28 22:40 ` [PATCH 06/11] target/ppc: booke: Instruction storage " Fabiano Rosas
` (7 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Fabiano Rosas @ 2022-01-28 22:40 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
There is no DSISR or DAR in BookE. Change to ESR and DEAR.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 4753b81527..c8bd78d5cb 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -832,7 +832,7 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
break;
case POWERPC_EXCP_DSI: /* Data storage exception */
- trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
+ trace_ppc_excp_dsi(env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
break;
case POWERPC_EXCP_ISI: /* Instruction storage exception */
trace_ppc_excp_isi(msr, env->nip);
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 06/11] target/ppc: booke: Instruction storage exception cleanup
2022-01-28 22:40 [PATCH 00/11] target/ppc: powerpc_excp improvements [BookE] (6/n) Fabiano Rosas
` (4 preceding siblings ...)
2022-01-28 22:40 ` [PATCH 05/11] target/ppc: booke: Data Storage exception cleanup Fabiano Rosas
@ 2022-01-28 22:40 ` Fabiano Rosas
2022-01-28 22:40 ` [PATCH 07/11] target/ppc: booke: External interrupt cleanup Fabiano Rosas
` (6 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Fabiano Rosas @ 2022-01-28 22:40 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
The SRR1 should be set to the MSR value. There are no diagnostic bits
in the SRR1 for BookE.
Note that this fixes a bug where MSR_GS would be set and Linux would
go into KVM code when there's no KVM guest.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index c8bd78d5cb..8340146902 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -836,7 +836,6 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
break;
case POWERPC_EXCP_ISI: /* Instruction storage exception */
trace_ppc_excp_isi(msr, env->nip);
- msr |= env->error_code;
break;
case POWERPC_EXCP_EXTERNAL: /* External input */
{
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 07/11] target/ppc: booke: External interrupt cleanup
2022-01-28 22:40 [PATCH 00/11] target/ppc: powerpc_excp improvements [BookE] (6/n) Fabiano Rosas
` (5 preceding siblings ...)
2022-01-28 22:40 ` [PATCH 06/11] target/ppc: booke: Instruction storage " Fabiano Rosas
@ 2022-01-28 22:40 ` Fabiano Rosas
2022-01-28 22:40 ` [PATCH 08/11] target/ppc: booke: Alignment " Fabiano Rosas
` (5 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Fabiano Rosas @ 2022-01-28 22:40 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
There is no LPES0 in BookE and no MSR_HV.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 33 ---------------------------------
1 file changed, 33 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 8340146902..6d86ae04eb 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -838,44 +838,11 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
trace_ppc_excp_isi(msr, env->nip);
break;
case POWERPC_EXCP_EXTERNAL: /* External input */
- {
- bool lpes0;
-
- cs = CPU(cpu);
-
- /*
- * Exception targeting modifiers
- *
- * LPES0 is supported on POWER7/8/9
- * LPES1 is not supported (old iSeries mode)
- *
- * On anything else, we behave as if LPES0 is 1
- * (externals don't alter MSR:HV)
- */
-#if defined(TARGET_PPC64)
- if (excp_model == POWERPC_EXCP_POWER7 ||
- excp_model == POWERPC_EXCP_POWER8 ||
- excp_model == POWERPC_EXCP_POWER9 ||
- excp_model == POWERPC_EXCP_POWER10) {
- lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
- } else
-#endif /* defined(TARGET_PPC64) */
- {
- lpes0 = true;
- }
-
- if (!lpes0) {
- new_msr |= (target_ulong)MSR_HVB;
- new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
- srr0 = SPR_HSRR0;
- srr1 = SPR_HSRR1;
- }
if (env->mpic_proxy) {
/* IACK the IRQ on delivery */
env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
}
break;
- }
case POWERPC_EXCP_ALIGN: /* Alignment exception */
/* Get rS/rD and rA from faulting opcode */
/*
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 08/11] target/ppc: booke: Alignment interrupt cleanup
2022-01-28 22:40 [PATCH 00/11] target/ppc: powerpc_excp improvements [BookE] (6/n) Fabiano Rosas
` (6 preceding siblings ...)
2022-01-28 22:40 ` [PATCH 07/11] target/ppc: booke: External interrupt cleanup Fabiano Rosas
@ 2022-01-28 22:40 ` Fabiano Rosas
2022-01-28 22:40 ` [PATCH 09/11] target/ppc: booke: System Call exception cleanup Fabiano Rosas
` (4 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Fabiano Rosas @ 2022-01-28 22:40 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
BookE has no DSISR or DAR. The proper registers ESR and DEAR were
already set at this point.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 7 -------
1 file changed, 7 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 6d86ae04eb..dfcb9995b8 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -844,13 +844,6 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
}
break;
case POWERPC_EXCP_ALIGN: /* Alignment exception */
- /* Get rS/rD and rA from faulting opcode */
- /*
- * Note: the opcode fields will not be set properly for a
- * direct store load/store, but nobody cares as nobody
- * actually uses direct store segments.
- */
- env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
break;
case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 09/11] target/ppc: booke: System Call exception cleanup
2022-01-28 22:40 [PATCH 00/11] target/ppc: powerpc_excp improvements [BookE] (6/n) Fabiano Rosas
` (7 preceding siblings ...)
2022-01-28 22:40 ` [PATCH 08/11] target/ppc: booke: Alignment " Fabiano Rosas
@ 2022-01-28 22:40 ` Fabiano Rosas
2022-01-28 22:40 ` [PATCH 10/11] target/ppc: booke: Watchdog Timer interrupt Fabiano Rosas
` (3 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Fabiano Rosas @ 2022-01-28 22:40 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
QEMU does not support BookE as a hypervisor.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 21 ++-------------------
1 file changed, 2 insertions(+), 19 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index dfcb9995b8..a5134e360c 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -751,7 +751,7 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
CPUPPCState *env = &cpu->env;
int excp_model = env->excp_model;
target_ulong msr, new_msr, vector;
- int srr0, srr1, lev = -1;
+ int srr0, srr1;
if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
@@ -884,30 +884,13 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
}
break;
case POWERPC_EXCP_SYSCALL: /* System call exception */
- lev = env->error_code;
-
- if ((lev == 1) && cpu->vhyp) {
- dump_hcall(env);
- } else {
- dump_syscall(env);
- }
+ dump_syscall(env);
/*
* We need to correct the NIP which in this case is supposed
* to point to the next instruction
*/
env->nip += 4;
-
- /* "PAPR mode" built-in hypercall emulation */
- if ((lev == 1) && cpu->vhyp) {
- PPCVirtualHypervisorClass *vhc =
- PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
- vhc->hypercall(cpu->vhyp, cpu);
- return;
- }
- if (lev == 1) {
- new_msr |= (target_ulong)MSR_HVB;
- }
break;
case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 10/11] target/ppc: booke: Watchdog Timer interrupt
2022-01-28 22:40 [PATCH 00/11] target/ppc: powerpc_excp improvements [BookE] (6/n) Fabiano Rosas
` (8 preceding siblings ...)
2022-01-28 22:40 ` [PATCH 09/11] target/ppc: booke: System Call exception cleanup Fabiano Rosas
@ 2022-01-28 22:40 ` Fabiano Rosas
2022-01-28 22:40 ` [PATCH 11/11] target/ppc: booke: System Reset exception cleanup Fabiano Rosas
` (2 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Fabiano Rosas @ 2022-01-28 22:40 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
Remove the switch as this function applies to BookE only.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 11 ++---------
1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index a5134e360c..7c228dac58 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -749,7 +749,6 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
{
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
- int excp_model = env->excp_model;
target_ulong msr, new_msr, vector;
int srr0, srr1;
@@ -902,14 +901,8 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
break;
case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
trace_ppc_excp_print("WDT");
- switch (excp_model) {
- case POWERPC_EXCP_BOOKE:
- srr0 = SPR_BOOKE_CSRR0;
- srr1 = SPR_BOOKE_CSRR1;
- break;
- default:
- break;
- }
+ srr0 = SPR_BOOKE_CSRR0;
+ srr1 = SPR_BOOKE_CSRR1;
break;
case POWERPC_EXCP_DTLB: /* Data TLB error */
case POWERPC_EXCP_ITLB: /* Instruction TLB error */
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 11/11] target/ppc: booke: System Reset exception cleanup
2022-01-28 22:40 [PATCH 00/11] target/ppc: powerpc_excp improvements [BookE] (6/n) Fabiano Rosas
` (9 preceding siblings ...)
2022-01-28 22:40 ` [PATCH 10/11] target/ppc: booke: Watchdog Timer interrupt Fabiano Rosas
@ 2022-01-28 22:40 ` Fabiano Rosas
2022-01-29 0:07 ` [PATCH 00/11] target/ppc: powerpc_excp improvements [BookE] (6/n) BALATON Zoltan
2022-02-09 7:43 ` Cédric Le Goater
12 siblings, 0 replies; 17+ messages in thread
From: Fabiano Rosas @ 2022-01-28 22:40 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
There is no MSR_HV in BookE, so remove all of the HV logic.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 18 ++----------------
1 file changed, 2 insertions(+), 16 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 7c228dac58..7d7d0a08b5 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -925,23 +925,9 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
env->spr[SPR_BOOKE_ESR] = ESR_SPV;
break;
case POWERPC_EXCP_RESET: /* System reset exception */
- /* A power-saving exception sets ME, otherwise it is unchanged */
if (msr_pow) {
- /* indicate that we resumed from power save mode */
- msr |= 0x10000;
- new_msr |= ((target_ulong)1 << MSR_ME);
- }
- if (env->msr_mask & MSR_HVB) {
- /*
- * ISA specifies HV, but can be delivered to guest with HV
- * clear (e.g., see FWNMI in PAPR, NMI injection in QEMU).
- */
- new_msr |= (target_ulong)MSR_HVB;
- } else {
- if (msr_pow) {
- cpu_abort(cs, "Trying to deliver power-saving system reset "
- "exception %d with no HV support\n", excp);
- }
+ cpu_abort(cs, "Trying to deliver power-saving system reset "
+ "exception %d with no HV support\n", excp);
}
break;
case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 00/11] target/ppc: powerpc_excp improvements [BookE] (6/n)
2022-01-28 22:40 [PATCH 00/11] target/ppc: powerpc_excp improvements [BookE] (6/n) Fabiano Rosas
` (10 preceding siblings ...)
2022-01-28 22:40 ` [PATCH 11/11] target/ppc: booke: System Reset exception cleanup Fabiano Rosas
@ 2022-01-29 0:07 ` BALATON Zoltan
2022-02-01 8:10 ` Cédric Le Goater
2022-02-09 7:43 ` Cédric Le Goater
12 siblings, 1 reply; 17+ messages in thread
From: BALATON Zoltan @ 2022-01-29 0:07 UTC (permalink / raw)
To: Fabiano Rosas; +Cc: danielhb413, qemu-ppc, qemu-devel, david, clg
On Fri, 28 Jan 2022, Fabiano Rosas wrote:
> This series handles the BookE exception code.
>
> Tested the following machines/CPUs:
>
> == bamboo ==
> 440ep, 460ex, 440-xilinx-w-dfpu
>
> == sam460ex ==
> 440ep, 460ex, 440-xilinx-w-dfpu
What OS did you test with? Other than the 460ex may not make much sense
on this board but checking it never hurts. If you only tried Linux kernel
then something else to give more coverage could be the same MorphOS iso
that used for pegasos2 which should also boot on sam460ex as shown here:
http://zero.eik.bme.hu/~balaton/qemu/amiga/#morphos
or the AROS iso further up that page that should also boot on sam460ex.
Regards,
BALATON Zoltan
> == mpc8544ds ==
> e500v1, e500v2
>
> == ppce500 ==
> e500mc, e5500, e6500
>
> About the remaining CPUs:
>
> - The 440x4 have been partially removed in the past. I sent a separate
> patch removing what's left of it.
>
> - The 440x5 (440-xilinx) boots with the bamboo machine but it
> segfaults in userspace (also in master).
>
> - The e200 is broken in master due to an assert in _spr_register (the
> DSRR0/1 registers are being registered twice). After fixing that
> QEMU crashes due to lack of IRQ controller (there's a TODO in the
> init_proc_e200).
>
> Fabiano Rosas (11):
> target/ppc: Introduce powerpc_excp_booke
> target/ppc: Simplify powerpc_excp_booke
> target/ppc: booke: Critical exception cleanup
> target/ppc: booke: Machine Check cleanups
> target/ppc: booke: Data Storage exception cleanup
> target/ppc: booke: Instruction storage exception cleanup
> target/ppc: booke: External interrupt cleanup
> target/ppc: booke: Alignment interrupt cleanup
> target/ppc: booke: System Call exception cleanup
> target/ppc: booke: Watchdog Timer interrupt
> target/ppc: booke: System Reset exception cleanup
>
> target/ppc/excp_helper.c | 228 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 228 insertions(+)
>
>
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 00/11] target/ppc: powerpc_excp improvements [BookE] (6/n)
2022-01-29 0:07 ` [PATCH 00/11] target/ppc: powerpc_excp improvements [BookE] (6/n) BALATON Zoltan
@ 2022-02-01 8:10 ` Cédric Le Goater
2022-02-01 11:32 ` BALATON Zoltan
0 siblings, 1 reply; 17+ messages in thread
From: Cédric Le Goater @ 2022-02-01 8:10 UTC (permalink / raw)
To: BALATON Zoltan, Fabiano Rosas; +Cc: danielhb413, qemu-ppc, qemu-devel, david
Hello Zoltan,
On 1/29/22 01:07, BALATON Zoltan wrote:
> On Fri, 28 Jan 2022, Fabiano Rosas wrote:
>> This series handles the BookE exception code.
>>
>> Tested the following machines/CPUs:
>>
>> == bamboo ==
>> 440ep, 460ex, 440-xilinx-w-dfpu
>>
>> == sam460ex ==
>> 440ep, 460ex, 440-xilinx-w-dfpu
>
> What OS did you test with? Other than the 460ex may not make much sense on this board but checking it never hurts. If you only tried Linux kernel then something else to give more coverage could be the same MorphOS iso that used for pegasos2 which should also boot on sam460ex as shown here:
>
> http://zero.eik.bme.hu/~balaton/qemu/amiga/#morphos
>
> or the AROS iso further up that page that should also boot on sam460ex.
>
I didn't see any issue.
Could you please give a try to this branch :
https://gitlab.com/legoater/qemu/-/tree/ppc-7.0
Thanks,
C.
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 00/11] target/ppc: powerpc_excp improvements [BookE] (6/n)
2022-02-01 8:10 ` Cédric Le Goater
@ 2022-02-01 11:32 ` BALATON Zoltan
2022-02-01 12:54 ` Fabiano Rosas
0 siblings, 1 reply; 17+ messages in thread
From: BALATON Zoltan @ 2022-02-01 11:32 UTC (permalink / raw)
To: Cédric Le Goater
Cc: danielhb413, qemu-ppc, qemu-devel, david, Fabiano Rosas
[-- Attachment #1: Type: text/plain, Size: 1235 bytes --]
On Tue, 1 Feb 2022, Cédric Le Goater wrote:
> On 1/29/22 01:07, BALATON Zoltan wrote:
>> On Fri, 28 Jan 2022, Fabiano Rosas wrote:
>>> This series handles the BookE exception code.
>>>
>>> Tested the following machines/CPUs:
>>>
>>> == bamboo ==
>>> 440ep, 460ex, 440-xilinx-w-dfpu
>>>
>>> == sam460ex ==
>>> 440ep, 460ex, 440-xilinx-w-dfpu
>>
>> What OS did you test with? Other than the 460ex may not make much sense on
>> this board but checking it never hurts. If you only tried Linux kernel then
>> something else to give more coverage could be the same MorphOS iso that
>> used for pegasos2 which should also boot on sam460ex as shown here:
>>
>> http://zero.eik.bme.hu/~balaton/qemu/amiga/#morphos
>>
>> or the AROS iso further up that page that should also boot on sam460ex.
>
> I didn't see any issue.
>
> Could you please give a try to this branch :
>
> https://gitlab.com/legoater/qemu/-/tree/ppc-7.0
Thanks for testing. It should be fine if it still boots so just go ahead
and put the series in the next pull request. If I find anything I'll
report when it's in master, I don't have the resources to follow branches
but we have a long freeze time to find any bugs so ir should be OK.
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 00/11] target/ppc: powerpc_excp improvements [BookE] (6/n)
2022-02-01 11:32 ` BALATON Zoltan
@ 2022-02-01 12:54 ` Fabiano Rosas
0 siblings, 0 replies; 17+ messages in thread
From: Fabiano Rosas @ 2022-02-01 12:54 UTC (permalink / raw)
To: BALATON Zoltan, Cédric Le Goater
Cc: danielhb413, qemu-ppc, qemu-devel, david
BALATON Zoltan <balaton@eik.bme.hu> writes:
> On Tue, 1 Feb 2022, Cédric Le Goater wrote:
>> On 1/29/22 01:07, BALATON Zoltan wrote:
>>> On Fri, 28 Jan 2022, Fabiano Rosas wrote:
>>>> This series handles the BookE exception code.
>>>>
>>>> Tested the following machines/CPUs:
>>>>
>>>> == bamboo ==
>>>> 440ep, 460ex, 440-xilinx-w-dfpu
>>>>
>>>> == sam460ex ==
>>>> 440ep, 460ex, 440-xilinx-w-dfpu
>>>
>>> What OS did you test with? Other than the 460ex may not make much sense on
>>> this board but checking it never hurts. If you only tried Linux kernel then
>>> something else to give more coverage could be the same MorphOS iso that
>>> used for pegasos2 which should also boot on sam460ex as shown here:
>>>
>>> http://zero.eik.bme.hu/~balaton/qemu/amiga/#morphos
>>>
>>> or the AROS iso further up that page that should also boot on sam460ex.
>>
>> I didn't see any issue.
>>
>> Could you please give a try to this branch :
>>
>> https://gitlab.com/legoater/qemu/-/tree/ppc-7.0
>
> Thanks for testing. It should be fine if it still boots so just go ahead
> and put the series in the next pull request. If I find anything I'll
> report when it's in master, I don't have the resources to follow branches
> but we have a long freeze time to find any bugs so ir should be OK.
I tested it but forgot to post here. It boots fine until the little
ballons screen and I can click around. So I'd say were good. =)
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 00/11] target/ppc: powerpc_excp improvements [BookE] (6/n)
2022-01-28 22:40 [PATCH 00/11] target/ppc: powerpc_excp improvements [BookE] (6/n) Fabiano Rosas
` (11 preceding siblings ...)
2022-01-29 0:07 ` [PATCH 00/11] target/ppc: powerpc_excp improvements [BookE] (6/n) BALATON Zoltan
@ 2022-02-09 7:43 ` Cédric Le Goater
12 siblings, 0 replies; 17+ messages in thread
From: Cédric Le Goater @ 2022-02-09 7:43 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel; +Cc: danielhb413, qemu-ppc, david
On 1/28/22 23:40, Fabiano Rosas wrote:
> This series handles the BookE exception code.
>
> Tested the following machines/CPUs:
>
> == bamboo ==
> 440ep, 460ex, 440-xilinx-w-dfpu
>
> == sam460ex ==
> 440ep, 460ex, 440-xilinx-w-dfpu
>
> == mpc8544ds ==
> e500v1, e500v2
>
> == ppce500 ==
> e500mc, e5500, e6500
>
> About the remaining CPUs:
>
> - The 440x4 have been partially removed in the past. I sent a separate
> patch removing what's left of it.
>
> - The 440x5 (440-xilinx) boots with the bamboo machine but it
> segfaults in userspace (also in master).
>
> - The e200 is broken in master due to an assert in _spr_register (the
> DSRR0/1 registers are being registered twice). After fixing that
> QEMU crashes due to lack of IRQ controller (there's a TODO in the
> init_proc_e200).
>
> Fabiano Rosas (11):
> target/ppc: Introduce powerpc_excp_booke
> target/ppc: Simplify powerpc_excp_booke
> target/ppc: booke: Critical exception cleanup
> target/ppc: booke: Machine Check cleanups
> target/ppc: booke: Data Storage exception cleanup
> target/ppc: booke: Instruction storage exception cleanup
> target/ppc: booke: External interrupt cleanup
> target/ppc: booke: Alignment interrupt cleanup
> target/ppc: booke: System Call exception cleanup
> target/ppc: booke: Watchdog Timer interrupt
> target/ppc: booke: System Reset exception cleanup
>
> target/ppc/excp_helper.c | 228 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 228 insertions(+)
>
Applied to ppc-7.0.
Thanks,
C.
^ permalink raw reply [flat|nested] 17+ messages in thread