* [PATCH 1/3] sunxi: prcm: Add a few registers
2022-01-30 14:27 [PATCH 0/3] sunxi: H6/H616: PRCM updates Jernej Skrabec
@ 2022-01-30 14:27 ` Jernej Skrabec
2022-01-30 16:29 ` Samuel Holland
2022-01-30 14:27 ` [PATCH 2/3] sunxi: clock: H6/H616: Add resistor calibration Jernej Skrabec
` (2 subsequent siblings)
3 siblings, 1 reply; 6+ messages in thread
From: Jernej Skrabec @ 2022-01-30 14:27 UTC (permalink / raw)
To: jagan, andre.przywara; +Cc: samuel, u-boot, linux-sunxi, Jernej Skrabec
H6 and H616 SPL code has a few writes to unknown PRCM registers. Now
that we know what they are, let's replace magic offsets with proper
register names.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
---
arch/arm/include/asm/arch-sunxi/prcm_sun50i.h | 10 ++++++++++
arch/arm/mach-sunxi/clock_sun50i_h6.c | 4 +++-
arch/arm/mach-sunxi/dram_sun50i_h6.c | 8 +++++---
arch/arm/mach-sunxi/dram_sun50i_h616.c | 7 +++++--
4 files changed, 23 insertions(+), 6 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h b/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h
index 5f636e83845a..fd63d3aad839 100644
--- a/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h
+++ b/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h
@@ -37,8 +37,18 @@ struct sunxi_prcm_reg {
u32 w1_gate_reset; /* 0x1ec */
u8 res10[0x1c]; /* 0x1f0 */
u32 rtc_gate_reset; /* 0x20c */
+ u8 res11[0x34]; /* 0x210 */
+ u32 pll_ldo_cfg; /* 0x244 */
+ u8 res12[0x8]; /* 0x248 */
+ u32 sys_pwroff_gating; /* 0x250 */
+ u8 res13[0xbc]; /* 0x254 */
+ u32 res_cal_ctrl; /* 0x310 */
+ u32 ohms200; /* 0x314 */
+ u32 ohms240; /* 0x318 */
+ u32 res_cal_status; /* 0x31c */
};
check_member(sunxi_prcm_reg, rtc_gate_reset, 0x20c);
+check_member(sunxi_prcm_reg, res_cal_status, 0x31c);
#define PRCM_TWI_GATE (1 << 0)
#define PRCM_TWI_RESET (1 << 16)
diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c
index a947463e0a53..e5846e6381ff 100644
--- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
@@ -9,10 +9,12 @@ void clock_init_safe(void)
{
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ struct sunxi_prcm_reg *const prcm =
+ (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
/* this seems to enable PLLs on H616 */
if (IS_ENABLED(CONFIG_MACH_SUN50I_H616))
- setbits_le32(SUNXI_PRCM_BASE + 0x250, 0x10);
+ setbits_le32(&prcm->sys_pwroff_gating, 0x10);
clock_set_pll1(408000000);
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c
index d05375c90277..b332f3a3e4aa 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c
@@ -12,6 +12,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/dram.h>
#include <asm/arch/cpu.h>
+#include <asm/arch/prcm.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/kconfig.h>
@@ -665,6 +666,8 @@ unsigned long sunxi_dram_init(void)
{
struct sunxi_mctl_com_reg * const mctl_com =
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+ struct sunxi_prcm_reg *const prcm =
+ (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
struct dram_para para = {
.clk = CONFIG_DRAM_CLK,
#ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3
@@ -680,9 +683,8 @@ unsigned long sunxi_dram_init(void)
unsigned long size;
- /* RES_CAL_CTRL_REG in BSP U-boot*/
- setbits_le32(0x7010310, BIT(8));
- clrbits_le32(0x7010318, 0x3f);
+ setbits_le32(&prcm->res_cal_ctrl, BIT(8));
+ clrbits_le32(&prcm->ohms240, 0x3f);
mctl_auto_detect_rank_width(¶);
mctl_auto_detect_dram_size(¶);
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index 83e8abc2f8d8..454c845a0010 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -19,6 +19,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/dram.h>
#include <asm/arch/cpu.h>
+#include <asm/arch/prcm.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/kconfig.h>
@@ -1001,14 +1002,16 @@ static unsigned long mctl_calc_size(struct dram_para *para)
unsigned long sunxi_dram_init(void)
{
+ struct sunxi_prcm_reg *const prcm =
+ (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
struct dram_para para = {
.clk = CONFIG_DRAM_CLK,
.type = SUNXI_DRAM_TYPE_DDR3,
};
unsigned long size;
- setbits_le32(0x7010310, BIT(8));
- clrbits_le32(0x7010318, 0x3f);
+ setbits_le32(&prcm->res_cal_ctrl, BIT(8));
+ clrbits_le32(&prcm->ohms240, 0x3f);
mctl_auto_detect_rank_width(¶);
mctl_auto_detect_dram_size(¶);
--
2.35.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 2/3] sunxi: clock: H6/H616: Add resistor calibration
2022-01-30 14:27 [PATCH 0/3] sunxi: H6/H616: PRCM updates Jernej Skrabec
2022-01-30 14:27 ` [PATCH 1/3] sunxi: prcm: Add a few registers Jernej Skrabec
@ 2022-01-30 14:27 ` Jernej Skrabec
2022-01-30 14:27 ` [PATCH 3/3] sunxi: clock: H6: Adjust PLL LDO before clock setup Jernej Skrabec
2022-04-05 22:42 ` [PATCH 0/3] sunxi: H6/H616: PRCM updates Andre Przywara
3 siblings, 0 replies; 6+ messages in thread
From: Jernej Skrabec @ 2022-01-30 14:27 UTC (permalink / raw)
To: jagan, andre.przywara; +Cc: samuel, u-boot, linux-sunxi, Jernej Skrabec
BSP boot0 executes resistor calibration before clocks are initialized.
Let's do that.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
---
arch/arm/mach-sunxi/clock_sun50i_h6.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c
index e5846e6381ff..32119ad16555 100644
--- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
@@ -12,9 +12,14 @@ void clock_init_safe(void)
struct sunxi_prcm_reg *const prcm =
(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
- /* this seems to enable PLLs on H616 */
- if (IS_ENABLED(CONFIG_MACH_SUN50I_H616))
+ if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) {
+ /* this seems to enable PLLs on H616 */
setbits_le32(&prcm->sys_pwroff_gating, 0x10);
+ setbits_le32(&prcm->res_cal_ctrl, 2);
+ }
+
+ clrbits_le32(&prcm->res_cal_ctrl, 1);
+ setbits_le32(&prcm->res_cal_ctrl, 1);
clock_set_pll1(408000000);
--
2.35.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 3/3] sunxi: clock: H6: Adjust PLL LDO before clock setup
2022-01-30 14:27 [PATCH 0/3] sunxi: H6/H616: PRCM updates Jernej Skrabec
2022-01-30 14:27 ` [PATCH 1/3] sunxi: prcm: Add a few registers Jernej Skrabec
2022-01-30 14:27 ` [PATCH 2/3] sunxi: clock: H6/H616: Add resistor calibration Jernej Skrabec
@ 2022-01-30 14:27 ` Jernej Skrabec
2022-04-05 22:42 ` [PATCH 0/3] sunxi: H6/H616: PRCM updates Andre Przywara
3 siblings, 0 replies; 6+ messages in thread
From: Jernej Skrabec @ 2022-01-30 14:27 UTC (permalink / raw)
To: jagan, andre.przywara; +Cc: samuel, u-boot, linux-sunxi, Jernej Skrabec
BSP boot0 adjust PLL LDO regulator before clocks are initialized.
Let's do that.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
---
arch/arm/mach-sunxi/clock_sun50i_h6.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c
index 32119ad16555..7926394cf762 100644
--- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
@@ -21,6 +21,13 @@ void clock_init_safe(void)
clrbits_le32(&prcm->res_cal_ctrl, 1);
setbits_le32(&prcm->res_cal_ctrl, 1);
+ if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) {
+ /* set key field for ldo enable */
+ setbits_le32(&prcm->pll_ldo_cfg, 0xA7000000);
+ /* set PLL VDD LDO output to 1.14 V */
+ setbits_le32(&prcm->pll_ldo_cfg, 0x60000);
+ }
+
clock_set_pll1(408000000);
writel(CCM_PLL6_DEFAULT, &ccm->pll6_cfg);
--
2.35.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH 0/3] sunxi: H6/H616: PRCM updates
2022-01-30 14:27 [PATCH 0/3] sunxi: H6/H616: PRCM updates Jernej Skrabec
` (2 preceding siblings ...)
2022-01-30 14:27 ` [PATCH 3/3] sunxi: clock: H6: Adjust PLL LDO before clock setup Jernej Skrabec
@ 2022-04-05 22:42 ` Andre Przywara
3 siblings, 0 replies; 6+ messages in thread
From: Andre Przywara @ 2022-04-05 22:42 UTC (permalink / raw)
To: Jernej Skrabec; +Cc: jagan, samuel, u-boot, linux-sunxi
On Sun, 30 Jan 2022 15:27:12 +0100
Jernej Skrabec <jernej.skrabec@gmail.com> wrote:
> During H616 boot0 blob and H6 boot0 sources analysis, I noticed that
> SPL doesn't set resistor calibration and PLL LDO on H6. Tests didn't
> show any observable difference, but nevertheless it's better to mimick
> boot0 behaviour.
>
> In the process I also added names for few PRCM registers so it's
> clearer what code does.
>
> Please take a look.
All merged into sunxi/master, which already landed in mainline.
Thanks!
Andre
>
> Best regards,
> Jernej
>
> Jernej Skrabec (3):
> sunxi: prcm: Add a few registers
> sunxi: clock: H6/H616: Add resistor calibration
> sunxi: clock: H6: Adjust PLL LDO before clock setup
>
> arch/arm/include/asm/arch-sunxi/prcm_sun50i.h | 10 ++++++++++
> arch/arm/mach-sunxi/clock_sun50i_h6.c | 20 ++++++++++++++++---
> arch/arm/mach-sunxi/dram_sun50i_h6.c | 8 +++++---
> arch/arm/mach-sunxi/dram_sun50i_h616.c | 7 +++++--
> 4 files changed, 37 insertions(+), 8 deletions(-)
>
^ permalink raw reply [flat|nested] 6+ messages in thread