* [PATCH v1 0/6] hw/arm: zynqmp: Add CRF and APU control to support PSCI
@ 2022-01-30 23:12 Edgar E. Iglesias
2022-01-30 23:12 ` [PATCH v1 1/6] hw/arm/xlnx-zynqmp: Add unimplemented SERDES area Edgar E. Iglesias
` (5 more replies)
0 siblings, 6 replies; 26+ messages in thread
From: Edgar E. Iglesias @ 2022-01-30 23:12 UTC (permalink / raw)
To: qemu-devel
Cc: edgar.iglesias, peter.maydell, luc, sai.pavan.boddu,
frasse.iglesias, alistair, richard.henderson, francisco.iglesias,
frederic.konrad, qemu-arm
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
This adds the necessary modeling to support some of our firmware
tests at EL3 implementing PSCI (TBM). These are the test-cases
that were previously relying on QEMU's builtin PSCI emulation.
I've only tested this on top of Peter's recent PSCI emulation fixes.
Cheers,
Edgar
Edgar E. Iglesias (6):
hw/arm/xlnx-zynqmp: Add unimplemented SERDES area
target/arm: Make rvbar settable after realize
hw/misc: Add a model of the Xilinx ZynqMP CRF
hw/arm/xlnx-zynqmp: Connect the ZynqMP CRF
hw/misc: Add a model of the Xilinx ZynqMP APU Control
hw/arm/xlnx-zynqmp: Connect the ZynqMP APU Control
include/hw/arm/xlnx-zynqmp.h | 4 +
include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 91 +++++++++
include/hw/misc/xlnx-zynqmp-crf.h | 209 +++++++++++++++++++
hw/arm/xlnx-zynqmp.c | 45 ++++-
hw/misc/xlnx-zynqmp-apu-ctrl.c | 257 +++++++++++++++++++++++
hw/misc/xlnx-zynqmp-crf.c | 270 +++++++++++++++++++++++++
target/arm/cpu.c | 7 +-
hw/misc/meson.build | 2 +
8 files changed, 879 insertions(+), 6 deletions(-)
create mode 100644 include/hw/misc/xlnx-zynqmp-apu-ctrl.h
create mode 100644 include/hw/misc/xlnx-zynqmp-crf.h
create mode 100644 hw/misc/xlnx-zynqmp-apu-ctrl.c
create mode 100644 hw/misc/xlnx-zynqmp-crf.c
--
2.25.1
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v1 1/6] hw/arm/xlnx-zynqmp: Add unimplemented SERDES area
2022-01-30 23:12 [PATCH v1 0/6] hw/arm: zynqmp: Add CRF and APU control to support PSCI Edgar E. Iglesias
@ 2022-01-30 23:12 ` Edgar E. Iglesias
2022-01-30 23:37 ` Philippe Mathieu-Daudé via
` (2 more replies)
2022-01-30 23:12 ` [PATCH v1 2/6] target/arm: Make rvbar settable after realize Edgar E. Iglesias
` (4 subsequent siblings)
5 siblings, 3 replies; 26+ messages in thread
From: Edgar E. Iglesias @ 2022-01-30 23:12 UTC (permalink / raw)
To: qemu-devel
Cc: edgar.iglesias, peter.maydell, luc, sai.pavan.boddu,
frasse.iglesias, alistair, richard.henderson, francisco.iglesias,
frederic.konrad, qemu-arm
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Add unimplemented SERDES area.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
include/hw/arm/xlnx-zynqmp.h | 2 +-
hw/arm/xlnx-zynqmp.c | 4 ++++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index 062e637fe4..99ceb8a609 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -84,7 +84,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
/*
* Unimplemented mmio regions needed to boot some images.
*/
-#define XLNX_ZYNQMP_NUM_UNIMP_AREAS 1
+#define XLNX_ZYNQMP_NUM_UNIMP_AREAS 2
struct XlnxZynqMPState {
/*< private >*/
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 17305fe7b7..ba44e95899 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -51,6 +51,9 @@
#define QSPI_IRQ 15
#define QSPI_DMA_ADDR 0xff0f0800
+#define SERDES_ADDR 0xfd400000
+#define SERDES_SIZE 0x20000
+
#define DP_ADDR 0xfd4a0000
#define DP_IRQ 113
@@ -284,6 +287,7 @@ static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
hwaddr size;
} unimp_areas[ARRAY_SIZE(s->mr_unimp)] = {
{ .name = "apu", APU_ADDR, APU_SIZE },
+ { .name = "serdes", SERDES_ADDR, SERDES_SIZE },
};
unsigned int nr;
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v1 2/6] target/arm: Make rvbar settable after realize
2022-01-30 23:12 [PATCH v1 0/6] hw/arm: zynqmp: Add CRF and APU control to support PSCI Edgar E. Iglesias
2022-01-30 23:12 ` [PATCH v1 1/6] hw/arm/xlnx-zynqmp: Add unimplemented SERDES area Edgar E. Iglesias
@ 2022-01-30 23:12 ` Edgar E. Iglesias
2022-02-03 20:21 ` Luc Michel
2022-01-30 23:12 ` [PATCH v1 3/6] hw/misc: Add a model of the Xilinx ZynqMP CRF Edgar E. Iglesias
` (3 subsequent siblings)
5 siblings, 1 reply; 26+ messages in thread
From: Edgar E. Iglesias @ 2022-01-30 23:12 UTC (permalink / raw)
To: qemu-devel
Cc: edgar.iglesias, peter.maydell, luc, sai.pavan.boddu,
frasse.iglesias, alistair, richard.henderson, francisco.iglesias,
frederic.konrad, qemu-arm
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Make the rvbar property settable after realize. This is done
in preparation to model the ZynqMP's runtime configurable rvbar.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
target/arm/cpu.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 5a9c02a256..e30ae088fe 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1128,9 +1128,6 @@ static Property arm_cpu_reset_cbar_property =
static Property arm_cpu_reset_hivecs_property =
DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
-static Property arm_cpu_rvbar_property =
- DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
-
#ifndef CONFIG_USER_ONLY
static Property arm_cpu_has_el2_property =
DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true);
@@ -1233,7 +1230,9 @@ void arm_cpu_post_init(Object *obj)
}
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
- qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property);
+ object_property_add_uint64_ptr(obj, "rvbar",
+ &cpu->rvbar,
+ OBJ_PROP_FLAG_READWRITE);
}
#ifndef CONFIG_USER_ONLY
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v1 3/6] hw/misc: Add a model of the Xilinx ZynqMP CRF
2022-01-30 23:12 [PATCH v1 0/6] hw/arm: zynqmp: Add CRF and APU control to support PSCI Edgar E. Iglesias
2022-01-30 23:12 ` [PATCH v1 1/6] hw/arm/xlnx-zynqmp: Add unimplemented SERDES area Edgar E. Iglesias
2022-01-30 23:12 ` [PATCH v1 2/6] target/arm: Make rvbar settable after realize Edgar E. Iglesias
@ 2022-01-30 23:12 ` Edgar E. Iglesias
2022-01-30 23:32 ` Philippe Mathieu-Daudé via
2022-01-31 15:35 ` Francisco Iglesias
2022-01-30 23:12 ` [PATCH v1 4/6] hw/arm/xlnx-zynqmp: Connect the " Edgar E. Iglesias
` (2 subsequent siblings)
5 siblings, 2 replies; 26+ messages in thread
From: Edgar E. Iglesias @ 2022-01-30 23:12 UTC (permalink / raw)
To: qemu-devel
Cc: edgar.iglesias, peter.maydell, luc, sai.pavan.boddu,
frasse.iglesias, alistair, richard.henderson, francisco.iglesias,
frederic.konrad, qemu-arm
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Add a model of the Xilinx ZynqMP CRF. At the moment this
is mostly a stub model.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
include/hw/misc/xlnx-zynqmp-crf.h | 209 +++++++++++++++++++++++
hw/misc/xlnx-zynqmp-crf.c | 270 ++++++++++++++++++++++++++++++
hw/misc/meson.build | 1 +
3 files changed, 480 insertions(+)
create mode 100644 include/hw/misc/xlnx-zynqmp-crf.h
create mode 100644 hw/misc/xlnx-zynqmp-crf.c
diff --git a/include/hw/misc/xlnx-zynqmp-crf.h b/include/hw/misc/xlnx-zynqmp-crf.h
new file mode 100644
index 0000000000..b173ea4a08
--- /dev/null
+++ b/include/hw/misc/xlnx-zynqmp-crf.h
@@ -0,0 +1,209 @@
+/*
+ * QEMU model of the CRF - Clock Reset FPD.
+ *
+ * Copyright (c) 2022 Xilinx Inc.
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+ */
+
+#include "hw/sysbus.h"
+#include "hw/register.h"
+
+#define TYPE_XLNX_ZYNQMP_CRF "xlnx.zynqmp_crf"
+
+#define XILINX_CRF(obj) \
+ OBJECT_CHECK(XlnxZynqMPCRF, (obj), TYPE_XLNX_ZYNQMP_CRF)
+
+REG32(ERR_CTRL, 0x0)
+ FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1)
+REG32(IR_STATUS, 0x4)
+ FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1)
+REG32(IR_MASK, 0x8)
+ FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1)
+REG32(IR_ENABLE, 0xc)
+ FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1)
+REG32(IR_DISABLE, 0x10)
+ FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1)
+REG32(CRF_WPROT, 0x1c)
+ FIELD(CRF_WPROT, ACTIVE, 0, 1)
+REG32(APLL_CTRL, 0x20)
+ FIELD(APLL_CTRL, POST_SRC, 24, 3)
+ FIELD(APLL_CTRL, PRE_SRC, 20, 3)
+ FIELD(APLL_CTRL, CLKOUTDIV, 17, 1)
+ FIELD(APLL_CTRL, DIV2, 16, 1)
+ FIELD(APLL_CTRL, FBDIV, 8, 7)
+ FIELD(APLL_CTRL, BYPASS, 3, 1)
+ FIELD(APLL_CTRL, RESET, 0, 1)
+REG32(APLL_CFG, 0x24)
+ FIELD(APLL_CFG, LOCK_DLY, 25, 7)
+ FIELD(APLL_CFG, LOCK_CNT, 13, 10)
+ FIELD(APLL_CFG, LFHF, 10, 2)
+ FIELD(APLL_CFG, CP, 5, 4)
+ FIELD(APLL_CFG, RES, 0, 4)
+REG32(APLL_FRAC_CFG, 0x28)
+ FIELD(APLL_FRAC_CFG, ENABLED, 31, 1)
+ FIELD(APLL_FRAC_CFG, SEED, 22, 3)
+ FIELD(APLL_FRAC_CFG, ALGRTHM, 19, 1)
+ FIELD(APLL_FRAC_CFG, ORDER, 18, 1)
+ FIELD(APLL_FRAC_CFG, DATA, 0, 16)
+REG32(DPLL_CTRL, 0x2c)
+ FIELD(DPLL_CTRL, POST_SRC, 24, 3)
+ FIELD(DPLL_CTRL, PRE_SRC, 20, 3)
+ FIELD(DPLL_CTRL, CLKOUTDIV, 17, 1)
+ FIELD(DPLL_CTRL, DIV2, 16, 1)
+ FIELD(DPLL_CTRL, FBDIV, 8, 7)
+ FIELD(DPLL_CTRL, BYPASS, 3, 1)
+ FIELD(DPLL_CTRL, RESET, 0, 1)
+REG32(DPLL_CFG, 0x30)
+ FIELD(DPLL_CFG, LOCK_DLY, 25, 7)
+ FIELD(DPLL_CFG, LOCK_CNT, 13, 10)
+ FIELD(DPLL_CFG, LFHF, 10, 2)
+ FIELD(DPLL_CFG, CP, 5, 4)
+ FIELD(DPLL_CFG, RES, 0, 4)
+REG32(DPLL_FRAC_CFG, 0x34)
+ FIELD(DPLL_FRAC_CFG, ENABLED, 31, 1)
+ FIELD(DPLL_FRAC_CFG, SEED, 22, 3)
+ FIELD(DPLL_FRAC_CFG, ALGRTHM, 19, 1)
+ FIELD(DPLL_FRAC_CFG, ORDER, 18, 1)
+ FIELD(DPLL_FRAC_CFG, DATA, 0, 16)
+REG32(VPLL_CTRL, 0x38)
+ FIELD(VPLL_CTRL, POST_SRC, 24, 3)
+ FIELD(VPLL_CTRL, PRE_SRC, 20, 3)
+ FIELD(VPLL_CTRL, CLKOUTDIV, 17, 1)
+ FIELD(VPLL_CTRL, DIV2, 16, 1)
+ FIELD(VPLL_CTRL, FBDIV, 8, 7)
+ FIELD(VPLL_CTRL, BYPASS, 3, 1)
+ FIELD(VPLL_CTRL, RESET, 0, 1)
+REG32(VPLL_CFG, 0x3c)
+ FIELD(VPLL_CFG, LOCK_DLY, 25, 7)
+ FIELD(VPLL_CFG, LOCK_CNT, 13, 10)
+ FIELD(VPLL_CFG, LFHF, 10, 2)
+ FIELD(VPLL_CFG, CP, 5, 4)
+ FIELD(VPLL_CFG, RES, 0, 4)
+REG32(VPLL_FRAC_CFG, 0x40)
+ FIELD(VPLL_FRAC_CFG, ENABLED, 31, 1)
+ FIELD(VPLL_FRAC_CFG, SEED, 22, 3)
+ FIELD(VPLL_FRAC_CFG, ALGRTHM, 19, 1)
+ FIELD(VPLL_FRAC_CFG, ORDER, 18, 1)
+ FIELD(VPLL_FRAC_CFG, DATA, 0, 16)
+REG32(PLL_STATUS, 0x44)
+ FIELD(PLL_STATUS, VPLL_STABLE, 5, 1)
+ FIELD(PLL_STATUS, DPLL_STABLE, 4, 1)
+ FIELD(PLL_STATUS, APLL_STABLE, 3, 1)
+ FIELD(PLL_STATUS, VPLL_LOCK, 2, 1)
+ FIELD(PLL_STATUS, DPLL_LOCK, 1, 1)
+ FIELD(PLL_STATUS, APLL_LOCK, 0, 1)
+REG32(APLL_TO_LPD_CTRL, 0x48)
+ FIELD(APLL_TO_LPD_CTRL, DIVISOR0, 8, 6)
+REG32(DPLL_TO_LPD_CTRL, 0x4c)
+ FIELD(DPLL_TO_LPD_CTRL, DIVISOR0, 8, 6)
+REG32(VPLL_TO_LPD_CTRL, 0x50)
+ FIELD(VPLL_TO_LPD_CTRL, DIVISOR0, 8, 6)
+REG32(ACPU_CTRL, 0x60)
+ FIELD(ACPU_CTRL, CLKACT_HALF, 25, 1)
+ FIELD(ACPU_CTRL, CLKACT_FULL, 24, 1)
+ FIELD(ACPU_CTRL, DIVISOR0, 8, 6)
+ FIELD(ACPU_CTRL, SRCSEL, 0, 3)
+REG32(DBG_TRACE_CTRL, 0x64)
+ FIELD(DBG_TRACE_CTRL, CLKACT, 24, 1)
+ FIELD(DBG_TRACE_CTRL, DIVISOR0, 8, 6)
+ FIELD(DBG_TRACE_CTRL, SRCSEL, 0, 3)
+REG32(DBG_FPD_CTRL, 0x68)
+ FIELD(DBG_FPD_CTRL, CLKACT, 24, 1)
+ FIELD(DBG_FPD_CTRL, DIVISOR0, 8, 6)
+ FIELD(DBG_FPD_CTRL, SRCSEL, 0, 3)
+REG32(DP_VIDEO_REF_CTRL, 0x70)
+ FIELD(DP_VIDEO_REF_CTRL, CLKACT, 24, 1)
+ FIELD(DP_VIDEO_REF_CTRL, DIVISOR1, 16, 6)
+ FIELD(DP_VIDEO_REF_CTRL, DIVISOR0, 8, 6)
+ FIELD(DP_VIDEO_REF_CTRL, SRCSEL, 0, 3)
+REG32(DP_AUDIO_REF_CTRL, 0x74)
+ FIELD(DP_AUDIO_REF_CTRL, CLKACT, 24, 1)
+ FIELD(DP_AUDIO_REF_CTRL, DIVISOR1, 16, 6)
+ FIELD(DP_AUDIO_REF_CTRL, DIVISOR0, 8, 6)
+ FIELD(DP_AUDIO_REF_CTRL, SRCSEL, 0, 3)
+REG32(DP_STC_REF_CTRL, 0x7c)
+ FIELD(DP_STC_REF_CTRL, CLKACT, 24, 1)
+ FIELD(DP_STC_REF_CTRL, DIVISOR1, 16, 6)
+ FIELD(DP_STC_REF_CTRL, DIVISOR0, 8, 6)
+ FIELD(DP_STC_REF_CTRL, SRCSEL, 0, 3)
+REG32(DDR_CTRL, 0x80)
+ FIELD(DDR_CTRL, CLKACT, 24, 1)
+ FIELD(DDR_CTRL, DIVISOR0, 8, 6)
+ FIELD(DDR_CTRL, SRCSEL, 0, 3)
+REG32(GPU_REF_CTRL, 0x84)
+ FIELD(GPU_REF_CTRL, PP1_CLKACT, 26, 1)
+ FIELD(GPU_REF_CTRL, PP0_CLKACT, 25, 1)
+ FIELD(GPU_REF_CTRL, CLKACT, 24, 1)
+ FIELD(GPU_REF_CTRL, DIVISOR0, 8, 6)
+ FIELD(GPU_REF_CTRL, SRCSEL, 0, 3)
+REG32(SATA_REF_CTRL, 0xa0)
+ FIELD(SATA_REF_CTRL, CLKACT, 24, 1)
+ FIELD(SATA_REF_CTRL, DIVISOR0, 8, 6)
+ FIELD(SATA_REF_CTRL, SRCSEL, 0, 3)
+REG32(PCIE_REF_CTRL, 0xb4)
+ FIELD(PCIE_REF_CTRL, CLKACT, 24, 1)
+ FIELD(PCIE_REF_CTRL, DIVISOR0, 8, 6)
+ FIELD(PCIE_REF_CTRL, SRCSEL, 0, 3)
+REG32(GDMA_REF_CTRL, 0xb8)
+ FIELD(GDMA_REF_CTRL, CLKACT, 24, 1)
+ FIELD(GDMA_REF_CTRL, DIVISOR0, 8, 6)
+ FIELD(GDMA_REF_CTRL, SRCSEL, 0, 3)
+REG32(DPDMA_REF_CTRL, 0xbc)
+ FIELD(DPDMA_REF_CTRL, CLKACT, 24, 1)
+ FIELD(DPDMA_REF_CTRL, DIVISOR0, 8, 6)
+ FIELD(DPDMA_REF_CTRL, SRCSEL, 0, 3)
+REG32(TOPSW_MAIN_CTRL, 0xc0)
+ FIELD(TOPSW_MAIN_CTRL, CLKACT, 24, 1)
+ FIELD(TOPSW_MAIN_CTRL, DIVISOR0, 8, 6)
+ FIELD(TOPSW_MAIN_CTRL, SRCSEL, 0, 3)
+REG32(TOPSW_LSBUS_CTRL, 0xc4)
+ FIELD(TOPSW_LSBUS_CTRL, CLKACT, 24, 1)
+ FIELD(TOPSW_LSBUS_CTRL, DIVISOR0, 8, 6)
+ FIELD(TOPSW_LSBUS_CTRL, SRCSEL, 0, 3)
+REG32(DBG_TSTMP_CTRL, 0xf8)
+ FIELD(DBG_TSTMP_CTRL, DIVISOR0, 8, 6)
+ FIELD(DBG_TSTMP_CTRL, SRCSEL, 0, 3)
+REG32(RST_FPD_TOP, 0x100)
+ FIELD(RST_FPD_TOP, PCIE_CFG_RESET, 19, 1)
+ FIELD(RST_FPD_TOP, PCIE_BRIDGE_RESET, 18, 1)
+ FIELD(RST_FPD_TOP, PCIE_CTRL_RESET, 17, 1)
+ FIELD(RST_FPD_TOP, DP_RESET, 16, 1)
+ FIELD(RST_FPD_TOP, SWDT_RESET, 15, 1)
+ FIELD(RST_FPD_TOP, AFI_FM5_RESET, 12, 1)
+ FIELD(RST_FPD_TOP, AFI_FM4_RESET, 11, 1)
+ FIELD(RST_FPD_TOP, AFI_FM3_RESET, 10, 1)
+ FIELD(RST_FPD_TOP, AFI_FM2_RESET, 9, 1)
+ FIELD(RST_FPD_TOP, AFI_FM1_RESET, 8, 1)
+ FIELD(RST_FPD_TOP, AFI_FM0_RESET, 7, 1)
+ FIELD(RST_FPD_TOP, GDMA_RESET, 6, 1)
+ FIELD(RST_FPD_TOP, GPU_PP1_RESET, 5, 1)
+ FIELD(RST_FPD_TOP, GPU_PP0_RESET, 4, 1)
+ FIELD(RST_FPD_TOP, GPU_RESET, 3, 1)
+ FIELD(RST_FPD_TOP, GT_RESET, 2, 1)
+ FIELD(RST_FPD_TOP, SATA_RESET, 1, 1)
+REG32(RST_FPD_APU, 0x104)
+ FIELD(RST_FPD_APU, ACPU3_PWRON_RESET, 13, 1)
+ FIELD(RST_FPD_APU, ACPU2_PWRON_RESET, 12, 1)
+ FIELD(RST_FPD_APU, ACPU1_PWRON_RESET, 11, 1)
+ FIELD(RST_FPD_APU, ACPU0_PWRON_RESET, 10, 1)
+ FIELD(RST_FPD_APU, APU_L2_RESET, 8, 1)
+ FIELD(RST_FPD_APU, ACPU3_RESET, 3, 1)
+ FIELD(RST_FPD_APU, ACPU2_RESET, 2, 1)
+ FIELD(RST_FPD_APU, ACPU1_RESET, 1, 1)
+ FIELD(RST_FPD_APU, ACPU0_RESET, 0, 1)
+REG32(RST_DDR_SS, 0x108)
+ FIELD(RST_DDR_SS, DDR_RESET, 3, 1)
+ FIELD(RST_DDR_SS, APM_RESET, 2, 1)
+
+#define CRF_R_MAX (R_RST_DDR_SS + 1)
+
+typedef struct XlnxZynqMPCRF {
+ SysBusDevice parent_obj;
+ MemoryRegion iomem;
+ qemu_irq irq_ir;
+
+ RegisterInfoArray *reg_array;
+ uint32_t regs[CRF_R_MAX];
+ RegisterInfo regs_info[CRF_R_MAX];
+} XlnxZynqMPCRF;
diff --git a/hw/misc/xlnx-zynqmp-crf.c b/hw/misc/xlnx-zynqmp-crf.c
new file mode 100644
index 0000000000..7b3a955a42
--- /dev/null
+++ b/hw/misc/xlnx-zynqmp-crf.c
@@ -0,0 +1,270 @@
+/*
+ * QEMU model of the CRF - Clock Reset FPD.
+ *
+ * Copyright (c) 2022 Xilinx Inc.
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "hw/register.h"
+#include "qemu/bitops.h"
+#include "qemu/log.h"
+#include "migration/vmstate.h"
+#include "hw/irq.h"
+#include "hw/misc/xlnx-zynqmp-crf.h"
+#include "target/arm/arm-powerctl.h"
+
+#ifndef XILINX_CRF_ERR_DEBUG
+#define XILINX_CRF_ERR_DEBUG 1
+#endif
+
+#define APU_MAX_CPU 4
+
+static void ir_update_irq(XlnxZynqMPCRF *s)
+{
+ bool pending = s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK];
+ qemu_set_irq(s->irq_ir, pending);
+}
+
+static void ir_status_postw(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxZynqMPCRF *s = XILINX_CRF(reg->opaque);
+ ir_update_irq(s);
+}
+
+static uint64_t ir_enable_prew(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxZynqMPCRF *s = XILINX_CRF(reg->opaque);
+ uint32_t val = val64;
+
+ s->regs[R_IR_MASK] &= ~val;
+ ir_update_irq(s);
+ return 0;
+}
+
+static uint64_t ir_disable_prew(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxZynqMPCRF *s = XILINX_CRF(reg->opaque);
+ uint32_t val = val64;
+
+ s->regs[R_IR_MASK] |= val;
+ ir_update_irq(s);
+ return 0;
+}
+
+static uint64_t rst_fpd_apu_prew(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxZynqMPCRF *s = XILINX_CRF(reg->opaque);
+ uint32_t val = val64;
+ uint32_t val_old = s->regs[R_RST_FPD_APU];
+ unsigned int i;
+
+ for (i = 0; i < APU_MAX_CPU; i++) {
+ uint32_t mask = (1 << (R_RST_FPD_APU_ACPU0_RESET_SHIFT + i));
+
+ if ((val ^ val_old) & mask) {
+ if (val & mask) {
+ arm_set_cpu_off(i);
+ } else {
+ arm_set_cpu_on_and_reset(i);
+ }
+ }
+ }
+ return val64;
+}
+
+static const RegisterAccessInfo crf_regs_info[] = {
+ { .name = "ERR_CTRL", .addr = A_ERR_CTRL,
+ },{ .name = "IR_STATUS", .addr = A_IR_STATUS,
+ .w1c = 0x1,
+ .post_write = ir_status_postw,
+ },{ .name = "IR_MASK", .addr = A_IR_MASK,
+ .reset = 0x1,
+ .ro = 0x1,
+ },{ .name = "IR_ENABLE", .addr = A_IR_ENABLE,
+ .pre_write = ir_enable_prew,
+ },{ .name = "IR_DISABLE", .addr = A_IR_DISABLE,
+ .pre_write = ir_disable_prew,
+ },{ .name = "CRF_WPROT", .addr = A_CRF_WPROT,
+ },{ .name = "APLL_CTRL", .addr = A_APLL_CTRL,
+ .reset = 0x12c09,
+ .rsvd = 0xf88c80f6,
+ },{ .name = "APLL_CFG", .addr = A_APLL_CFG,
+ .rsvd = 0x1801210,
+ },{ .name = "APLL_FRAC_CFG", .addr = A_APLL_FRAC_CFG,
+ .rsvd = 0x7e330000,
+ },{ .name = "DPLL_CTRL", .addr = A_DPLL_CTRL,
+ .reset = 0x2c09,
+ .rsvd = 0xf88c80f6,
+ },{ .name = "DPLL_CFG", .addr = A_DPLL_CFG,
+ .rsvd = 0x1801210,
+ },{ .name = "DPLL_FRAC_CFG", .addr = A_DPLL_FRAC_CFG,
+ .rsvd = 0x7e330000,
+ },{ .name = "VPLL_CTRL", .addr = A_VPLL_CTRL,
+ .reset = 0x12809,
+ .rsvd = 0xf88c80f6,
+ },{ .name = "VPLL_CFG", .addr = A_VPLL_CFG,
+ .rsvd = 0x1801210,
+ },{ .name = "VPLL_FRAC_CFG", .addr = A_VPLL_FRAC_CFG,
+ .rsvd = 0x7e330000,
+ },{ .name = "PLL_STATUS", .addr = A_PLL_STATUS,
+ .reset = 0x3f,
+ .rsvd = 0xc0,
+ .ro = 0x3f,
+ },{ .name = "APLL_TO_LPD_CTRL", .addr = A_APLL_TO_LPD_CTRL,
+ .reset = 0x400,
+ .rsvd = 0xc0ff,
+ },{ .name = "DPLL_TO_LPD_CTRL", .addr = A_DPLL_TO_LPD_CTRL,
+ .reset = 0x400,
+ .rsvd = 0xc0ff,
+ },{ .name = "VPLL_TO_LPD_CTRL", .addr = A_VPLL_TO_LPD_CTRL,
+ .reset = 0x400,
+ .rsvd = 0xc0ff,
+ },{ .name = "ACPU_CTRL", .addr = A_ACPU_CTRL,
+ .reset = 0x3000400,
+ .rsvd = 0xfcffc0f8,
+ },{ .name = "DBG_TRACE_CTRL", .addr = A_DBG_TRACE_CTRL,
+ .reset = 0x2500,
+ .rsvd = 0xfeffc0f8,
+ },{ .name = "DBG_FPD_CTRL", .addr = A_DBG_FPD_CTRL,
+ .reset = 0x1002500,
+ .rsvd = 0xfeffc0f8,
+ },{ .name = "DP_VIDEO_REF_CTRL", .addr = A_DP_VIDEO_REF_CTRL,
+ .reset = 0x1002300,
+ .rsvd = 0xfec0c0f8,
+ },{ .name = "DP_AUDIO_REF_CTRL", .addr = A_DP_AUDIO_REF_CTRL,
+ .reset = 0x1032300,
+ .rsvd = 0xfec0c0f8,
+ },{ .name = "DP_STC_REF_CTRL", .addr = A_DP_STC_REF_CTRL,
+ .reset = 0x1203200,
+ .rsvd = 0xfec0c0f8,
+ },{ .name = "DDR_CTRL", .addr = A_DDR_CTRL,
+ .reset = 0x1000500,
+ .rsvd = 0xfeffc0f8,
+ },{ .name = "GPU_REF_CTRL", .addr = A_GPU_REF_CTRL,
+ .reset = 0x1500,
+ .rsvd = 0xf8ffc0f8,
+ },{ .name = "SATA_REF_CTRL", .addr = A_SATA_REF_CTRL,
+ .reset = 0x1001600,
+ .rsvd = 0xfeffc0f8,
+ },{ .name = "PCIE_REF_CTRL", .addr = A_PCIE_REF_CTRL,
+ .reset = 0x1500,
+ .rsvd = 0xfeffc0f8,
+ },{ .name = "GDMA_REF_CTRL", .addr = A_GDMA_REF_CTRL,
+ .reset = 0x1000500,
+ .rsvd = 0xfeffc0f8,
+ },{ .name = "DPDMA_REF_CTRL", .addr = A_DPDMA_REF_CTRL,
+ .reset = 0x1000500,
+ .rsvd = 0xfeffc0f8,
+ },{ .name = "TOPSW_MAIN_CTRL", .addr = A_TOPSW_MAIN_CTRL,
+ .reset = 0x1000400,
+ .rsvd = 0xfeffc0f8,
+ },{ .name = "TOPSW_LSBUS_CTRL", .addr = A_TOPSW_LSBUS_CTRL,
+ .reset = 0x1000800,
+ .rsvd = 0xfeffc0f8,
+ },{ .name = "DBG_TSTMP_CTRL", .addr = A_DBG_TSTMP_CTRL,
+ .reset = 0xa00,
+ .rsvd = 0xffffc0f8,
+ },
+ { .name = "RST_FPD_TOP", .addr = A_RST_FPD_TOP,
+ .reset = 0xf9ffe,
+ .rsvd = 0xf06001,
+ },{ .name = "RST_FPD_APU", .addr = A_RST_FPD_APU,
+ .reset = 0x3d0f,
+ .rsvd = 0xc2f0,
+ .pre_write = rst_fpd_apu_prew,
+ },{ .name = "RST_DDR_SS", .addr = A_RST_DDR_SS,
+ .reset = 0xf,
+ .rsvd = 0xf3,
+ }
+};
+
+static void crf_reset_enter(Object *obj, ResetType type)
+{
+ XlnxZynqMPCRF *s = XILINX_CRF(obj);
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
+ register_reset(&s->regs_info[i]);
+ }
+}
+
+static void crf_reset_hold(Object *obj)
+{
+ XlnxZynqMPCRF *s = XILINX_CRF(obj);
+ ir_update_irq(s);
+}
+
+static const MemoryRegionOps crf_ops = {
+ .read = register_read_memory,
+ .write = register_write_memory,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+};
+
+static void crf_init(Object *obj)
+{
+ XlnxZynqMPCRF *s = XILINX_CRF(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+
+ s->reg_array =
+ register_init_block32(DEVICE(obj), crf_regs_info,
+ ARRAY_SIZE(crf_regs_info),
+ s->regs_info, s->regs,
+ &crf_ops,
+ XILINX_CRF_ERR_DEBUG,
+ CRF_R_MAX * 4);
+ sysbus_init_mmio(sbd, &s->reg_array->mem);
+ sysbus_init_irq(sbd, &s->irq_ir);
+}
+
+static void crf_finalize(Object *obj)
+{
+ XlnxZynqMPCRF *s = XILINX_CRF(obj);
+ register_finalize_block(s->reg_array);
+}
+
+static const VMStateDescription vmstate_crf = {
+ .name = TYPE_XLNX_ZYNQMP_CRF,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPCRF, CRF_R_MAX),
+ VMSTATE_END_OF_LIST(),
+ }
+};
+
+static void crf_class_init(ObjectClass *klass, void *data)
+{
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->vmsd = &vmstate_crf;
+ rc->phases.enter = crf_reset_enter;
+ rc->phases.hold = crf_reset_hold;
+}
+
+static const TypeInfo crf_info = {
+ .name = TYPE_XLNX_ZYNQMP_CRF,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(XlnxZynqMPCRF),
+ .class_init = crf_class_init,
+ .instance_init = crf_init,
+ .instance_finalize = crf_finalize,
+ .interfaces = (InterfaceInfo[]) {
+ { }
+ },
+};
+
+static void crf_register_types(void)
+{
+ type_register_static(&crf_info);
+}
+
+type_init(crf_register_types)
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index 6dcbe044f3..1927f13a5e 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -84,6 +84,7 @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
))
softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c'))
+specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c'))
softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files(
'xlnx-versal-xramc.c',
'xlnx-versal-pmc-iou-slcr.c',
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v1 4/6] hw/arm/xlnx-zynqmp: Connect the ZynqMP CRF
2022-01-30 23:12 [PATCH v1 0/6] hw/arm: zynqmp: Add CRF and APU control to support PSCI Edgar E. Iglesias
` (2 preceding siblings ...)
2022-01-30 23:12 ` [PATCH v1 3/6] hw/misc: Add a model of the Xilinx ZynqMP CRF Edgar E. Iglesias
@ 2022-01-30 23:12 ` Edgar E. Iglesias
2022-01-30 23:33 ` Philippe Mathieu-Daudé via
` (2 more replies)
2022-01-30 23:12 ` [PATCH v1 5/6] hw/misc: Add a model of the Xilinx ZynqMP APU Control Edgar E. Iglesias
2022-01-30 23:12 ` [PATCH v1 6/6] hw/arm/xlnx-zynqmp: Connect the " Edgar E. Iglesias
5 siblings, 3 replies; 26+ messages in thread
From: Edgar E. Iglesias @ 2022-01-30 23:12 UTC (permalink / raw)
To: qemu-devel
Cc: edgar.iglesias, peter.maydell, luc, sai.pavan.boddu,
frasse.iglesias, alistair, richard.henderson, francisco.iglesias,
frederic.konrad, qemu-arm
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Connect the ZynqMP CRF - Clock Reset FPD device.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
include/hw/arm/xlnx-zynqmp.h | 2 ++
hw/arm/xlnx-zynqmp.c | 16 ++++++++++++++++
2 files changed, 18 insertions(+)
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index 99ceb8a609..d5a3ad3df2 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -38,6 +38,7 @@
#include "hw/dma/xlnx_csu_dma.h"
#include "hw/nvram/xlnx-bbram.h"
#include "hw/nvram/xlnx-zynqmp-efuse.h"
+#include "hw/misc/xlnx-zynqmp-crf.h"
#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
@@ -122,6 +123,7 @@ struct XlnxZynqMPState {
XlnxZDMA gdma[XLNX_ZYNQMP_NUM_GDMA_CH];
XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH];
XlnxCSUDMA qspi_dma;
+ XlnxZynqMPCRF crf;
char *boot_cpu;
ARMCPU *boot_cpu_ptr;
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index ba44e95899..857d3c9636 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -51,6 +51,9 @@
#define QSPI_IRQ 15
#define QSPI_DMA_ADDR 0xff0f0800
+#define CRF_ADDR 0xfd1a0000
+#define CRF_IRQ 120
+
#define SERDES_ADDR 0xfd400000
#define SERDES_SIZE 0x20000
@@ -279,6 +282,18 @@ static void xlnx_zynqmp_create_efuse(XlnxZynqMPState *s, qemu_irq *gic)
sysbus_connect_irq(sbd, 0, gic[EFUSE_IRQ]);
}
+static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic)
+{
+ SysBusDevice *sbd;
+
+ object_initialize_child(OBJECT(s), "crf", &s->crf, TYPE_XLNX_ZYNQMP_CRF);
+ sbd = SYS_BUS_DEVICE(&s->crf);
+
+ sysbus_realize(sbd, &error_fatal);
+ sysbus_mmio_map(sbd, 0, CRF_ADDR);
+ sysbus_connect_irq(sbd, 0, gic[CRF_IRQ]);
+}
+
static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
{
static const struct UnimpInfo {
@@ -682,6 +697,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
xlnx_zynqmp_create_bbram(s, gic_spi);
xlnx_zynqmp_create_efuse(s, gic_spi);
+ xlnx_zynqmp_create_crf(s, gic_spi);
xlnx_zynqmp_create_unimp_mmio(s);
for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v1 5/6] hw/misc: Add a model of the Xilinx ZynqMP APU Control
2022-01-30 23:12 [PATCH v1 0/6] hw/arm: zynqmp: Add CRF and APU control to support PSCI Edgar E. Iglesias
` (3 preceding siblings ...)
2022-01-30 23:12 ` [PATCH v1 4/6] hw/arm/xlnx-zynqmp: Connect the " Edgar E. Iglesias
@ 2022-01-30 23:12 ` Edgar E. Iglesias
2022-01-30 23:35 ` Philippe Mathieu-Daudé via
2022-01-31 15:46 ` Francisco Iglesias
2022-01-30 23:12 ` [PATCH v1 6/6] hw/arm/xlnx-zynqmp: Connect the " Edgar E. Iglesias
5 siblings, 2 replies; 26+ messages in thread
From: Edgar E. Iglesias @ 2022-01-30 23:12 UTC (permalink / raw)
To: qemu-devel
Cc: edgar.iglesias, peter.maydell, luc, sai.pavan.boddu,
frasse.iglesias, alistair, richard.henderson, francisco.iglesias,
frederic.konrad, qemu-arm
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Add a model of the Xilinx ZynqMP APU Control.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 91 +++++++++
hw/misc/xlnx-zynqmp-apu-ctrl.c | 257 +++++++++++++++++++++++++
hw/misc/meson.build | 1 +
3 files changed, 349 insertions(+)
create mode 100644 include/hw/misc/xlnx-zynqmp-apu-ctrl.h
create mode 100644 hw/misc/xlnx-zynqmp-apu-ctrl.c
diff --git a/include/hw/misc/xlnx-zynqmp-apu-ctrl.h b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h
new file mode 100644
index 0000000000..44bf264cef
--- /dev/null
+++ b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h
@@ -0,0 +1,91 @@
+/*
+ * QEMU model of ZynqMP APU Control.
+ *
+ * Copyright (c) 2013-2022 Xilinx Inc
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> and
+ * Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+ *
+ */
+
+#include "hw/sysbus.h"
+#include "hw/register.h"
+#include "target/arm/cpu.h"
+
+#define TYPE_XLNX_ZYNQMP_APU_CTRL "xlnx.apu-ctrl"
+
+#define XLNX_ZYNQMP_APU(obj) \
+ OBJECT_CHECK(XlnxZynqMPAPUCtrl, (obj), TYPE_XLNX_ZYNQMP_APU_CTRL)
+
+REG32(APU_ERR_CTRL, 0x0)
+ FIELD(APU_ERR_CTRL, PSLVERR, 0, 1)
+REG32(ISR, 0x10)
+ FIELD(ISR, INV_APB, 0, 1)
+REG32(IMR, 0x14)
+ FIELD(IMR, INV_APB, 0, 1)
+REG32(IEN, 0x18)
+ FIELD(IEN, INV_APB, 0, 1)
+REG32(IDS, 0x1c)
+ FIELD(IDS, INV_APB, 0, 1)
+REG32(CONFIG_0, 0x20)
+ FIELD(CONFIG_0, CFGTE, 24, 4)
+ FIELD(CONFIG_0, CFGEND, 16, 4)
+ FIELD(CONFIG_0, VINITHI, 8, 4)
+ FIELD(CONFIG_0, AA64NAA32, 0, 4)
+REG32(CONFIG_1, 0x24)
+ FIELD(CONFIG_1, L2RSTDISABLE, 29, 1)
+ FIELD(CONFIG_1, L1RSTDISABLE, 28, 1)
+ FIELD(CONFIG_1, CP15DISABLE, 0, 4)
+REG32(RVBARADDR0L, 0x40)
+ FIELD(RVBARADDR0L, ADDR, 2, 30)
+REG32(RVBARADDR0H, 0x44)
+ FIELD(RVBARADDR0H, ADDR, 0, 8)
+REG32(RVBARADDR1L, 0x48)
+ FIELD(RVBARADDR1L, ADDR, 2, 30)
+REG32(RVBARADDR1H, 0x4c)
+ FIELD(RVBARADDR1H, ADDR, 0, 8)
+REG32(RVBARADDR2L, 0x50)
+ FIELD(RVBARADDR2L, ADDR, 2, 30)
+REG32(RVBARADDR2H, 0x54)
+ FIELD(RVBARADDR2H, ADDR, 0, 8)
+REG32(RVBARADDR3L, 0x58)
+ FIELD(RVBARADDR3L, ADDR, 2, 30)
+REG32(RVBARADDR3H, 0x5c)
+ FIELD(RVBARADDR3H, ADDR, 0, 8)
+REG32(ACE_CTRL, 0x60)
+ FIELD(ACE_CTRL, AWQOS, 16, 4)
+ FIELD(ACE_CTRL, ARQOS, 0, 4)
+REG32(SNOOP_CTRL, 0x80)
+ FIELD(SNOOP_CTRL, ACE_INACT, 4, 1)
+ FIELD(SNOOP_CTRL, ACP_INACT, 0, 1)
+REG32(PWRCTL, 0x90)
+ FIELD(PWRCTL, CLREXMONREQ, 17, 1)
+ FIELD(PWRCTL, L2FLUSHREQ, 16, 1)
+ FIELD(PWRCTL, CPUPWRDWNREQ, 0, 4)
+REG32(PWRSTAT, 0x94)
+ FIELD(PWRSTAT, CLREXMONACK, 17, 1)
+ FIELD(PWRSTAT, L2FLUSHDONE, 16, 1)
+ FIELD(PWRSTAT, DBGNOPWRDWN, 0, 4)
+
+#define APU_R_MAX ((R_PWRSTAT) + 1)
+
+#define NUM_CPUS 4
+
+typedef struct XlnxZynqMPAPUCtrl {
+ SysBusDevice busdev;
+
+ ARMCPU *cpus[NUM_CPUS];
+ /* WFIs towards PMU. */
+ qemu_irq wfi_out[4];
+ /* CPU Power status towards INTC Redirect. */
+ qemu_irq cpu_power_status[4];
+ qemu_irq irq_imr;
+
+ uint8_t cpu_pwrdwn_req;
+ uint8_t cpu_in_wfi;
+
+ RegisterInfoArray *reg_array;
+ uint32_t regs[APU_R_MAX];
+ RegisterInfo regs_info[APU_R_MAX];
+} XlnxZynqMPAPUCtrl;
diff --git a/hw/misc/xlnx-zynqmp-apu-ctrl.c b/hw/misc/xlnx-zynqmp-apu-ctrl.c
new file mode 100644
index 0000000000..c27b8b9253
--- /dev/null
+++ b/hw/misc/xlnx-zynqmp-apu-ctrl.c
@@ -0,0 +1,257 @@
+/*
+ * QEMU model of the ZynqMP APU Control.
+ *
+ * Copyright (c) 2013-2022 Xilinx Inc
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> and
+ * Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu/log.h"
+#include "migration/vmstate.h"
+#include "hw/qdev-properties.h"
+#include "hw/sysbus.h"
+#include "hw/irq.h"
+#include "hw/register.h"
+
+#include "qemu/bitops.h"
+#include "qapi/qmp/qerror.h"
+
+#include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
+
+#ifndef XILINX_ZYNQMP_APU_ERR_DEBUG
+#define XILINX_ZYNQMP_APU_ERR_DEBUG 1
+#endif
+
+static void update_wfi_out(void *opaque)
+{
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU(opaque);
+ unsigned int i, wfi_pending;
+
+ wfi_pending = s->cpu_pwrdwn_req & s->cpu_in_wfi;
+ for (i = 0; i < NUM_CPUS; i++) {
+ qemu_set_irq(s->wfi_out[i], !!(wfi_pending & (1 << i)));
+ }
+}
+
+static void zynqmp_apu_rvbar_post_write(RegisterInfo *reg, uint64_t val)
+{
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU(reg->opaque);
+ int i;
+
+ for (i = 0; i < NUM_CPUS; ++i) {
+ uint64_t rvbar = s->regs[R_RVBARADDR0L + 2 * i] +
+ ((uint64_t)s->regs[R_RVBARADDR0H + 2 * i] << 32);
+ if (s->cpus[i]) {
+ object_property_set_int(OBJECT(s->cpus[i]), "rvbar", rvbar,
+ &error_abort);
+ }
+ }
+}
+
+static void zynqmp_apu_pwrctl_post_write(RegisterInfo *reg, uint64_t val)
+{
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU(reg->opaque);
+ unsigned int i, new;
+
+ for (i = 0; i < NUM_CPUS; i++) {
+ new = val & (1 << i);
+ /* Check if CPU's CPUPWRDNREQ has changed. If yes, update GPIOs. */
+ if (new != (s->cpu_pwrdwn_req & (1 << i))) {
+ qemu_set_irq(s->cpu_power_status[i], !!new);
+ }
+ s->cpu_pwrdwn_req &= ~(1 << i);
+ s->cpu_pwrdwn_req |= new;
+ }
+ update_wfi_out(s);
+}
+
+static void imr_update_irq(XlnxZynqMPAPUCtrl *s)
+{
+ bool pending = s->regs[R_ISR] & ~s->regs[R_IMR];
+ qemu_set_irq(s->irq_imr, pending);
+}
+
+static void isr_postw(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU(reg->opaque);
+ imr_update_irq(s);
+}
+
+static uint64_t ien_prew(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU(reg->opaque);
+ uint32_t val = val64;
+
+ s->regs[R_IMR] &= ~val;
+ imr_update_irq(s);
+ return 0;
+}
+
+static uint64_t ids_prew(RegisterInfo *reg, uint64_t val64)
+{
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU(reg->opaque);
+ uint32_t val = val64;
+
+ s->regs[R_IMR] |= val;
+ imr_update_irq(s);
+ return 0;
+}
+
+static const RegisterAccessInfo zynqmp_apu_regs_info[] = {
+#define RVBAR_REGDEF(n) \
+ { .name = "RVBAR CPU " #n " Low", .addr = A_RVBARADDR ## n ## L, \
+ .reset = 0xffff0000ul, \
+ .post_write = zynqmp_apu_rvbar_post_write, \
+ },{ .name = "RVBAR CPU " #n " High", .addr = A_RVBARADDR ## n ## H, \
+ .post_write = zynqmp_apu_rvbar_post_write, \
+ }
+ { .name = "ERR_CTRL", .addr = A_APU_ERR_CTRL,
+ },{ .name = "ISR", .addr = A_ISR,
+ .w1c = 0x1,
+ .post_write = isr_postw,
+ },{ .name = "IMR", .addr = A_IMR,
+ .reset = 0x1,
+ .ro = 0x1,
+ },{ .name = "IEN", .addr = A_IEN,
+ .pre_write = ien_prew,
+ },{ .name = "IDS", .addr = A_IDS,
+ .pre_write = ids_prew,
+ },{ .name = "CONFIG_0", .addr = A_CONFIG_0,
+ .reset = 0xf0f,
+ },{ .name = "CONFIG_1", .addr = A_CONFIG_1,
+ },
+ RVBAR_REGDEF(0),
+ RVBAR_REGDEF(1),
+ RVBAR_REGDEF(2),
+ RVBAR_REGDEF(3),
+ { .name = "ACE_CTRL", .addr = A_ACE_CTRL,
+ .reset = 0xf000f,
+ },{ .name = "SNOOP_CTRL", .addr = A_SNOOP_CTRL,
+ },{ .name = "PWRCTL", .addr = A_PWRCTL,
+ .post_write = zynqmp_apu_pwrctl_post_write,
+ },{ .name = "PWRSTAT", .addr = A_PWRSTAT,
+ .ro = 0x3000f,
+ }
+};
+
+static void zynqmp_apu_reset_enter(Object *obj, ResetType type)
+{
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU(obj);
+ int i;
+
+ for (i = 0; i < APU_R_MAX; ++i) {
+ register_reset(&s->regs_info[i]);
+ }
+
+ s->cpu_pwrdwn_req = 0;
+ s->cpu_in_wfi = 0;
+}
+
+static void zynqmp_apu_reset_hold(Object *obj)
+{
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU(obj);
+
+ update_wfi_out(s);
+ imr_update_irq(s);
+}
+
+static const MemoryRegionOps zynqmp_apu_ops = {
+ .read = register_read_memory,
+ .write = register_write_memory,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ }
+};
+
+static void zynqmp_apu_handle_wfi(void *opaque, int irq, int level)
+{
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU(opaque);
+
+ s->cpu_in_wfi = deposit32(s->cpu_in_wfi, irq, 1, level);
+ update_wfi_out(s);
+}
+
+static void zynqmp_apu_init(Object *obj)
+{
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU(obj);
+ int i;
+
+ s->reg_array =
+ register_init_block32(DEVICE(obj), zynqmp_apu_regs_info,
+ ARRAY_SIZE(zynqmp_apu_regs_info),
+ s->regs_info, s->regs,
+ &zynqmp_apu_ops,
+ XILINX_ZYNQMP_APU_ERR_DEBUG,
+ APU_R_MAX * 4);
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->reg_array->mem);
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq_imr);
+
+ for (i = 0; i < NUM_CPUS; ++i) {
+ g_autofree gchar *prop_name = g_strdup_printf("cpu%d", i);
+ object_property_add_link(obj, prop_name, TYPE_ARM_CPU,
+ (Object **)&s->cpus[i],
+ qdev_prop_allow_set_link_before_realize,
+ OBJ_PROP_LINK_STRONG);
+ }
+
+ /* wfi_out is used to connect to PMU GPIs. */
+ qdev_init_gpio_out_named(DEVICE(obj), s->wfi_out, "wfi_out", 4);
+ /* CPU_POWER_STATUS is used to connect to INTC redirect. */
+ qdev_init_gpio_out_named(DEVICE(obj), s->cpu_power_status,
+ "CPU_POWER_STATUS", 4);
+ /* wfi_in is used as input from CPUs as wfi request. */
+ qdev_init_gpio_in_named(DEVICE(obj), zynqmp_apu_handle_wfi, "wfi_in", 4);
+}
+
+static void zynqmp_apu_finalize(Object *obj)
+{
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU(obj);
+ register_finalize_block(s->reg_array);
+}
+
+static const VMStateDescription vmstate_zynqmp_apu = {
+ .name = TYPE_XLNX_ZYNQMP_APU_CTRL,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPAPUCtrl, APU_R_MAX),
+ VMSTATE_END_OF_LIST(),
+ }
+};
+
+static void zynqmp_apu_class_init(ObjectClass *klass, void *data)
+{
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->vmsd = &vmstate_zynqmp_apu;
+
+ rc->phases.enter = zynqmp_apu_reset_enter;
+ rc->phases.hold = zynqmp_apu_reset_hold;
+}
+
+static const TypeInfo zynqmp_apu_info = {
+ .name = TYPE_XLNX_ZYNQMP_APU_CTRL,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(XlnxZynqMPAPUCtrl),
+ .class_init = zynqmp_apu_class_init,
+ .instance_init = zynqmp_apu_init,
+ .instance_finalize = zynqmp_apu_finalize,
+ .interfaces = (InterfaceInfo[]) {
+ { }
+ },
+};
+
+static void zynqmp_apu_register_types(void)
+{
+ type_register_static(&zynqmp_apu_info);
+}
+
+type_init(zynqmp_apu_register_types)
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index 1927f13a5e..cf9d4cc618 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -85,6 +85,7 @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c'))
specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c'))
+specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c'))
softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files(
'xlnx-versal-xramc.c',
'xlnx-versal-pmc-iou-slcr.c',
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v1 6/6] hw/arm/xlnx-zynqmp: Connect the ZynqMP APU Control
2022-01-30 23:12 [PATCH v1 0/6] hw/arm: zynqmp: Add CRF and APU control to support PSCI Edgar E. Iglesias
` (4 preceding siblings ...)
2022-01-30 23:12 ` [PATCH v1 5/6] hw/misc: Add a model of the Xilinx ZynqMP APU Control Edgar E. Iglesias
@ 2022-01-30 23:12 ` Edgar E. Iglesias
2022-01-30 23:37 ` Philippe Mathieu-Daudé via
` (2 more replies)
5 siblings, 3 replies; 26+ messages in thread
From: Edgar E. Iglesias @ 2022-01-30 23:12 UTC (permalink / raw)
To: qemu-devel
Cc: edgar.iglesias, peter.maydell, luc, sai.pavan.boddu,
frasse.iglesias, alistair, richard.henderson, francisco.iglesias,
frederic.konrad, qemu-arm
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Connect the ZynqMP APU Control device.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
include/hw/arm/xlnx-zynqmp.h | 4 +++-
hw/arm/xlnx-zynqmp.c | 25 +++++++++++++++++++++++--
2 files changed, 26 insertions(+), 3 deletions(-)
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index d5a3ad3df2..05cd2128f3 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -38,6 +38,7 @@
#include "hw/dma/xlnx_csu_dma.h"
#include "hw/nvram/xlnx-bbram.h"
#include "hw/nvram/xlnx-zynqmp-efuse.h"
+#include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
#include "hw/misc/xlnx-zynqmp-crf.h"
#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
@@ -85,7 +86,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
/*
* Unimplemented mmio regions needed to boot some images.
*/
-#define XLNX_ZYNQMP_NUM_UNIMP_AREAS 2
+#define XLNX_ZYNQMP_NUM_UNIMP_AREAS 1
struct XlnxZynqMPState {
/*< private >*/
@@ -123,6 +124,7 @@ struct XlnxZynqMPState {
XlnxZDMA gdma[XLNX_ZYNQMP_NUM_GDMA_CH];
XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH];
XlnxCSUDMA qspi_dma;
+ XlnxZynqMPAPUCtrl apu_ctrl;
XlnxZynqMPCRF crf;
char *boot_cpu;
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 857d3c9636..21c411cd77 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -64,7 +64,7 @@
#define DPDMA_IRQ 116
#define APU_ADDR 0xfd5c0000
-#define APU_SIZE 0x100
+#define APU_IRQ 153
#define IPI_ADDR 0xFF300000
#define IPI_IRQ 64
@@ -282,6 +282,27 @@ static void xlnx_zynqmp_create_efuse(XlnxZynqMPState *s, qemu_irq *gic)
sysbus_connect_irq(sbd, 0, gic[EFUSE_IRQ]);
}
+static void xlnx_zynqmp_create_apu_ctrl(XlnxZynqMPState *s, qemu_irq *gic)
+{
+ SysBusDevice *sbd;
+ int i;
+
+ object_initialize_child(OBJECT(s), "apu-ctrl", &s->apu_ctrl,
+ TYPE_XLNX_ZYNQMP_APU_CTRL);
+ sbd = SYS_BUS_DEVICE(&s->apu_ctrl);
+
+ for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
+ g_autofree gchar *name = g_strdup_printf("cpu%d", i);
+
+ object_property_set_link(OBJECT(&s->apu_ctrl), name,
+ OBJECT(&s->apu_cpu[i]), &error_abort);
+ }
+
+ sysbus_realize(sbd, &error_fatal);
+ sysbus_mmio_map(sbd, 0, APU_ADDR);
+ sysbus_connect_irq(sbd, 0, gic[APU_IRQ]);
+}
+
static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic)
{
SysBusDevice *sbd;
@@ -301,7 +322,6 @@ static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
hwaddr base;
hwaddr size;
} unimp_areas[ARRAY_SIZE(s->mr_unimp)] = {
- { .name = "apu", APU_ADDR, APU_SIZE },
{ .name = "serdes", SERDES_ADDR, SERDES_SIZE },
};
unsigned int nr;
@@ -697,6 +717,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
xlnx_zynqmp_create_bbram(s, gic_spi);
xlnx_zynqmp_create_efuse(s, gic_spi);
+ xlnx_zynqmp_create_apu_ctrl(s, gic_spi);
xlnx_zynqmp_create_crf(s, gic_spi);
xlnx_zynqmp_create_unimp_mmio(s);
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH v1 3/6] hw/misc: Add a model of the Xilinx ZynqMP CRF
2022-01-30 23:12 ` [PATCH v1 3/6] hw/misc: Add a model of the Xilinx ZynqMP CRF Edgar E. Iglesias
@ 2022-01-30 23:32 ` Philippe Mathieu-Daudé via
2022-01-31 15:35 ` Francisco Iglesias
1 sibling, 0 replies; 26+ messages in thread
From: Philippe Mathieu-Daudé via @ 2022-01-30 23:32 UTC (permalink / raw)
To: Edgar E. Iglesias, qemu-devel
Cc: edgar.iglesias, peter.maydell, luc, sai.pavan.boddu,
frasse.iglesias, alistair, richard.henderson, francisco.iglesias,
frederic.konrad, qemu-arm
On 31/1/22 00:12, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Add a model of the Xilinx ZynqMP CRF. At the moment this
> is mostly a stub model.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
> include/hw/misc/xlnx-zynqmp-crf.h | 209 +++++++++++++++++++++++
> hw/misc/xlnx-zynqmp-crf.c | 270 ++++++++++++++++++++++++++++++
> hw/misc/meson.build | 1 +
> 3 files changed, 480 insertions(+)
> create mode 100644 include/hw/misc/xlnx-zynqmp-crf.h
> create mode 100644 hw/misc/xlnx-zynqmp-crf.c
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v1 4/6] hw/arm/xlnx-zynqmp: Connect the ZynqMP CRF
2022-01-30 23:12 ` [PATCH v1 4/6] hw/arm/xlnx-zynqmp: Connect the " Edgar E. Iglesias
@ 2022-01-30 23:33 ` Philippe Mathieu-Daudé via
2022-01-31 15:37 ` Francisco Iglesias
2022-02-03 20:23 ` Luc Michel
2 siblings, 0 replies; 26+ messages in thread
From: Philippe Mathieu-Daudé via @ 2022-01-30 23:33 UTC (permalink / raw)
To: Edgar E. Iglesias, qemu-devel
Cc: edgar.iglesias, peter.maydell, luc, sai.pavan.boddu,
frasse.iglesias, alistair, richard.henderson, francisco.iglesias,
frederic.konrad, qemu-arm
On 31/1/22 00:12, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Connect the ZynqMP CRF - Clock Reset FPD device.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
> include/hw/arm/xlnx-zynqmp.h | 2 ++
> hw/arm/xlnx-zynqmp.c | 16 ++++++++++++++++
> 2 files changed, 18 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v1 5/6] hw/misc: Add a model of the Xilinx ZynqMP APU Control
2022-01-30 23:12 ` [PATCH v1 5/6] hw/misc: Add a model of the Xilinx ZynqMP APU Control Edgar E. Iglesias
@ 2022-01-30 23:35 ` Philippe Mathieu-Daudé via
2022-01-31 12:17 ` Edgar E. Iglesias
2022-01-31 15:46 ` Francisco Iglesias
1 sibling, 1 reply; 26+ messages in thread
From: Philippe Mathieu-Daudé via @ 2022-01-30 23:35 UTC (permalink / raw)
To: Edgar E. Iglesias, qemu-devel
Cc: edgar.iglesias, peter.maydell, luc, sai.pavan.boddu,
frasse.iglesias, alistair, richard.henderson, francisco.iglesias,
frederic.konrad, qemu-arm
On 31/1/22 00:12, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Add a model of the Xilinx ZynqMP APU Control.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
> include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 91 +++++++++
> hw/misc/xlnx-zynqmp-apu-ctrl.c | 257 +++++++++++++++++++++++++
> hw/misc/meson.build | 1 +
> 3 files changed, 349 insertions(+)
> create mode 100644 include/hw/misc/xlnx-zynqmp-apu-ctrl.h
> create mode 100644 hw/misc/xlnx-zynqmp-apu-ctrl.c
>
> diff --git a/include/hw/misc/xlnx-zynqmp-apu-ctrl.h b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h
> new file mode 100644
> index 0000000000..44bf264cef
> --- /dev/null
> +++ b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h
> @@ -0,0 +1,91 @@
> +/*
> + * QEMU model of ZynqMP APU Control.
> + *
> + * Copyright (c) 2013-2022 Xilinx Inc
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + *
> + * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> and
> + * Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> + *
> + */
> +
> +#include "hw/sysbus.h"
> +#include "hw/register.h"
> +#include "target/arm/cpu.h"
> +
> +#define TYPE_XLNX_ZYNQMP_APU_CTRL "xlnx.apu-ctrl"
> +
> +#define XLNX_ZYNQMP_APU(obj) \
> + OBJECT_CHECK(XlnxZynqMPAPUCtrl, (obj), TYPE_XLNX_ZYNQMP_APU_CTRL)
...
> +#define APU_R_MAX ((R_PWRSTAT) + 1)
> +
> +#define NUM_CPUS 4
Hmm isn't it APU_MAX_CPU?
> +typedef struct XlnxZynqMPAPUCtrl {
> + SysBusDevice busdev;
> +
> + ARMCPU *cpus[NUM_CPUS];
> + /* WFIs towards PMU. */
> + qemu_irq wfi_out[4];
> + /* CPU Power status towards INTC Redirect. */
> + qemu_irq cpu_power_status[4];
> + qemu_irq irq_imr;
> +
> + uint8_t cpu_pwrdwn_req;
> + uint8_t cpu_in_wfi;
> +
> + RegisterInfoArray *reg_array;
> + uint32_t regs[APU_R_MAX];
> + RegisterInfo regs_info[APU_R_MAX];
> +} XlnxZynqMPAPUCtrl;
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v1 6/6] hw/arm/xlnx-zynqmp: Connect the ZynqMP APU Control
2022-01-30 23:12 ` [PATCH v1 6/6] hw/arm/xlnx-zynqmp: Connect the " Edgar E. Iglesias
@ 2022-01-30 23:37 ` Philippe Mathieu-Daudé via
2022-01-31 15:48 ` Francisco Iglesias
2022-02-03 20:26 ` Luc Michel
2 siblings, 0 replies; 26+ messages in thread
From: Philippe Mathieu-Daudé via @ 2022-01-30 23:37 UTC (permalink / raw)
To: Edgar E. Iglesias, qemu-devel
Cc: edgar.iglesias, peter.maydell, luc, sai.pavan.boddu,
frasse.iglesias, alistair, richard.henderson, francisco.iglesias,
frederic.konrad, qemu-arm
On 31/1/22 00:12, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Connect the ZynqMP APU Control device.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
> include/hw/arm/xlnx-zynqmp.h | 4 +++-
> hw/arm/xlnx-zynqmp.c | 25 +++++++++++++++++++++++--
> 2 files changed, 26 insertions(+), 3 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v1 1/6] hw/arm/xlnx-zynqmp: Add unimplemented SERDES area
2022-01-30 23:12 ` [PATCH v1 1/6] hw/arm/xlnx-zynqmp: Add unimplemented SERDES area Edgar E. Iglesias
@ 2022-01-30 23:37 ` Philippe Mathieu-Daudé via
2022-01-31 15:21 ` Francisco Iglesias
2022-01-31 15:32 ` Peter Maydell
2 siblings, 0 replies; 26+ messages in thread
From: Philippe Mathieu-Daudé via @ 2022-01-30 23:37 UTC (permalink / raw)
To: Edgar E. Iglesias, qemu-devel
Cc: edgar.iglesias, peter.maydell, luc, sai.pavan.boddu,
frasse.iglesias, alistair, richard.henderson, francisco.iglesias,
frederic.konrad, qemu-arm
On 31/1/22 00:12, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Add unimplemented SERDES area.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
> include/hw/arm/xlnx-zynqmp.h | 2 +-
> hw/arm/xlnx-zynqmp.c | 4 ++++
> 2 files changed, 5 insertions(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v1 5/6] hw/misc: Add a model of the Xilinx ZynqMP APU Control
2022-01-30 23:35 ` Philippe Mathieu-Daudé via
@ 2022-01-31 12:17 ` Edgar E. Iglesias
2022-01-31 23:21 ` Philippe Mathieu-Daudé via
0 siblings, 1 reply; 26+ messages in thread
From: Edgar E. Iglesias @ 2022-01-31 12:17 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: edgar.iglesias, peter.maydell, luc, sai.pavan.boddu,
frasse.iglesias, alistair, richard.henderson, qemu-devel,
francisco.iglesias, frederic.konrad, qemu-arm
On Mon, Jan 31, 2022 at 12:35:54AM +0100, Philippe Mathieu-Daudé wrote:
> On 31/1/22 00:12, Edgar E. Iglesias wrote:
> > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> >
> > Add a model of the Xilinx ZynqMP APU Control.
> >
> > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> > ---
> > include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 91 +++++++++
> > hw/misc/xlnx-zynqmp-apu-ctrl.c | 257 +++++++++++++++++++++++++
> > hw/misc/meson.build | 1 +
> > 3 files changed, 349 insertions(+)
> > create mode 100644 include/hw/misc/xlnx-zynqmp-apu-ctrl.h
> > create mode 100644 hw/misc/xlnx-zynqmp-apu-ctrl.c
> >
> > diff --git a/include/hw/misc/xlnx-zynqmp-apu-ctrl.h b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h
> > new file mode 100644
> > index 0000000000..44bf264cef
> > --- /dev/null
> > +++ b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h
> > @@ -0,0 +1,91 @@
> > +/*
> > + * QEMU model of ZynqMP APU Control.
> > + *
> > + * Copyright (c) 2013-2022 Xilinx Inc
> > + * SPDX-License-Identifier: GPL-2.0-or-later
> > + *
> > + * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> and
> > + * Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> > + *
> > + */
> > +
> > +#include "hw/sysbus.h"
> > +#include "hw/register.h"
> > +#include "target/arm/cpu.h"
> > +
> > +#define TYPE_XLNX_ZYNQMP_APU_CTRL "xlnx.apu-ctrl"
> > +
> > +#define XLNX_ZYNQMP_APU(obj) \
> > + OBJECT_CHECK(XlnxZynqMPAPUCtrl, (obj), TYPE_XLNX_ZYNQMP_APU_CTRL)
> ...
>
> > +#define APU_R_MAX ((R_PWRSTAT) + 1)
> > +
> > +#define NUM_CPUS 4
>
> Hmm isn't it APU_MAX_CPU?
>
Thanks Philippe. Yes, this was a little confusing. The values happen to be the
same but they belong to different models. For example, the apu-ctrl model will be
reused in Versal.
Anyways, for v2 I've renamed the macros to CRF_MAX_CPU and APU_MAX_CPU respectevly.
I hope that makes things clearer.
Thanks,
Edgar
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v1 1/6] hw/arm/xlnx-zynqmp: Add unimplemented SERDES area
2022-01-30 23:12 ` [PATCH v1 1/6] hw/arm/xlnx-zynqmp: Add unimplemented SERDES area Edgar E. Iglesias
2022-01-30 23:37 ` Philippe Mathieu-Daudé via
@ 2022-01-31 15:21 ` Francisco Iglesias
2022-01-31 15:32 ` Peter Maydell
2 siblings, 0 replies; 26+ messages in thread
From: Francisco Iglesias @ 2022-01-31 15:21 UTC (permalink / raw)
To: Edgar E. Iglesias
Cc: edgar.iglesias, peter.maydell, luc, sai.pavan.boddu,
frasse.iglesias, alistair, richard.henderson, qemu-devel,
frederic.konrad, qemu-arm
On Mon, Jan 31, 2022 at 12:12:01AM +0100, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Add unimplemented SERDES area.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
> ---
> include/hw/arm/xlnx-zynqmp.h | 2 +-
> hw/arm/xlnx-zynqmp.c | 4 ++++
> 2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
> index 062e637fe4..99ceb8a609 100644
> --- a/include/hw/arm/xlnx-zynqmp.h
> +++ b/include/hw/arm/xlnx-zynqmp.h
> @@ -84,7 +84,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
> /*
> * Unimplemented mmio regions needed to boot some images.
> */
> -#define XLNX_ZYNQMP_NUM_UNIMP_AREAS 1
> +#define XLNX_ZYNQMP_NUM_UNIMP_AREAS 2
>
> struct XlnxZynqMPState {
> /*< private >*/
> diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
> index 17305fe7b7..ba44e95899 100644
> --- a/hw/arm/xlnx-zynqmp.c
> +++ b/hw/arm/xlnx-zynqmp.c
> @@ -51,6 +51,9 @@
> #define QSPI_IRQ 15
> #define QSPI_DMA_ADDR 0xff0f0800
>
> +#define SERDES_ADDR 0xfd400000
> +#define SERDES_SIZE 0x20000
> +
> #define DP_ADDR 0xfd4a0000
> #define DP_IRQ 113
>
> @@ -284,6 +287,7 @@ static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
> hwaddr size;
> } unimp_areas[ARRAY_SIZE(s->mr_unimp)] = {
> { .name = "apu", APU_ADDR, APU_SIZE },
> + { .name = "serdes", SERDES_ADDR, SERDES_SIZE },
> };
> unsigned int nr;
>
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v1 1/6] hw/arm/xlnx-zynqmp: Add unimplemented SERDES area
2022-01-30 23:12 ` [PATCH v1 1/6] hw/arm/xlnx-zynqmp: Add unimplemented SERDES area Edgar E. Iglesias
2022-01-30 23:37 ` Philippe Mathieu-Daudé via
2022-01-31 15:21 ` Francisco Iglesias
@ 2022-01-31 15:32 ` Peter Maydell
2022-01-31 17:30 ` Edgar E. Iglesias
2 siblings, 1 reply; 26+ messages in thread
From: Peter Maydell @ 2022-01-31 15:32 UTC (permalink / raw)
To: Edgar E. Iglesias
Cc: edgar.iglesias, luc, sai.pavan.boddu, frasse.iglesias, alistair,
richard.henderson, qemu-devel, francisco.iglesias,
frederic.konrad, qemu-arm
On Sun, 30 Jan 2022 at 23:12, Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
>
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Add unimplemented SERDES area.
What's a SERDES ? A brief description might be helpful in
the commit message or a comment.
thanks
-- PMM
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v1 3/6] hw/misc: Add a model of the Xilinx ZynqMP CRF
2022-01-30 23:12 ` [PATCH v1 3/6] hw/misc: Add a model of the Xilinx ZynqMP CRF Edgar E. Iglesias
2022-01-30 23:32 ` Philippe Mathieu-Daudé via
@ 2022-01-31 15:35 ` Francisco Iglesias
2022-01-31 17:27 ` Edgar E. Iglesias
1 sibling, 1 reply; 26+ messages in thread
From: Francisco Iglesias @ 2022-01-31 15:35 UTC (permalink / raw)
To: Edgar E. Iglesias
Cc: edgar.iglesias, peter.maydell, luc, sai.pavan.boddu,
frasse.iglesias, alistair, richard.henderson, qemu-devel,
frederic.konrad, qemu-arm
Hi Edgar,
A couple of minor comments below, looks good to me otherwise!
On Mon, Jan 31, 2022 at 12:12:03AM +0100, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Add a model of the Xilinx ZynqMP CRF. At the moment this
> is mostly a stub model.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
> include/hw/misc/xlnx-zynqmp-crf.h | 209 +++++++++++++++++++++++
> hw/misc/xlnx-zynqmp-crf.c | 270 ++++++++++++++++++++++++++++++
> hw/misc/meson.build | 1 +
> 3 files changed, 480 insertions(+)
> create mode 100644 include/hw/misc/xlnx-zynqmp-crf.h
> create mode 100644 hw/misc/xlnx-zynqmp-crf.c
>
> diff --git a/include/hw/misc/xlnx-zynqmp-crf.h b/include/hw/misc/xlnx-zynqmp-crf.h
> new file mode 100644
> index 0000000000..b173ea4a08
> --- /dev/null
> +++ b/include/hw/misc/xlnx-zynqmp-crf.h
> @@ -0,0 +1,209 @@
> +/*
> + * QEMU model of the CRF - Clock Reset FPD.
> + *
> + * Copyright (c) 2022 Xilinx Inc.
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> + */
> +
Include guard seem to be missing:
#ifndef XLNX_ZYNQMP_CRF_H
#define XLNX_ZYNQMP_CRF_H
> +#include "hw/sysbus.h"
> +#include "hw/register.h"
> +
> +#define TYPE_XLNX_ZYNQMP_CRF "xlnx.zynqmp_crf"
> +
> +#define XILINX_CRF(obj) \
> + OBJECT_CHECK(XlnxZynqMPCRF, (obj), TYPE_XLNX_ZYNQMP_CRF)
> +
> +REG32(ERR_CTRL, 0x0)
(Optional but in case the these ones wont be used outside
xlnx-zynqmp-crf.c we could consider placing them there).
> + FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1)
> +REG32(IR_STATUS, 0x4)
> + FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1)
> +REG32(IR_MASK, 0x8)
> + FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1)
> +REG32(IR_ENABLE, 0xc)
> + FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1)
> +REG32(IR_DISABLE, 0x10)
> + FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1)
> +REG32(CRF_WPROT, 0x1c)
> + FIELD(CRF_WPROT, ACTIVE, 0, 1)
> +REG32(APLL_CTRL, 0x20)
> + FIELD(APLL_CTRL, POST_SRC, 24, 3)
> + FIELD(APLL_CTRL, PRE_SRC, 20, 3)
> + FIELD(APLL_CTRL, CLKOUTDIV, 17, 1)
> + FIELD(APLL_CTRL, DIV2, 16, 1)
> + FIELD(APLL_CTRL, FBDIV, 8, 7)
> + FIELD(APLL_CTRL, BYPASS, 3, 1)
> + FIELD(APLL_CTRL, RESET, 0, 1)
> +REG32(APLL_CFG, 0x24)
> + FIELD(APLL_CFG, LOCK_DLY, 25, 7)
> + FIELD(APLL_CFG, LOCK_CNT, 13, 10)
> + FIELD(APLL_CFG, LFHF, 10, 2)
> + FIELD(APLL_CFG, CP, 5, 4)
> + FIELD(APLL_CFG, RES, 0, 4)
> +REG32(APLL_FRAC_CFG, 0x28)
> + FIELD(APLL_FRAC_CFG, ENABLED, 31, 1)
> + FIELD(APLL_FRAC_CFG, SEED, 22, 3)
> + FIELD(APLL_FRAC_CFG, ALGRTHM, 19, 1)
> + FIELD(APLL_FRAC_CFG, ORDER, 18, 1)
> + FIELD(APLL_FRAC_CFG, DATA, 0, 16)
> +REG32(DPLL_CTRL, 0x2c)
> + FIELD(DPLL_CTRL, POST_SRC, 24, 3)
> + FIELD(DPLL_CTRL, PRE_SRC, 20, 3)
> + FIELD(DPLL_CTRL, CLKOUTDIV, 17, 1)
> + FIELD(DPLL_CTRL, DIV2, 16, 1)
> + FIELD(DPLL_CTRL, FBDIV, 8, 7)
> + FIELD(DPLL_CTRL, BYPASS, 3, 1)
> + FIELD(DPLL_CTRL, RESET, 0, 1)
> +REG32(DPLL_CFG, 0x30)
> + FIELD(DPLL_CFG, LOCK_DLY, 25, 7)
> + FIELD(DPLL_CFG, LOCK_CNT, 13, 10)
> + FIELD(DPLL_CFG, LFHF, 10, 2)
> + FIELD(DPLL_CFG, CP, 5, 4)
> + FIELD(DPLL_CFG, RES, 0, 4)
> +REG32(DPLL_FRAC_CFG, 0x34)
> + FIELD(DPLL_FRAC_CFG, ENABLED, 31, 1)
> + FIELD(DPLL_FRAC_CFG, SEED, 22, 3)
> + FIELD(DPLL_FRAC_CFG, ALGRTHM, 19, 1)
> + FIELD(DPLL_FRAC_CFG, ORDER, 18, 1)
> + FIELD(DPLL_FRAC_CFG, DATA, 0, 16)
> +REG32(VPLL_CTRL, 0x38)
> + FIELD(VPLL_CTRL, POST_SRC, 24, 3)
> + FIELD(VPLL_CTRL, PRE_SRC, 20, 3)
> + FIELD(VPLL_CTRL, CLKOUTDIV, 17, 1)
> + FIELD(VPLL_CTRL, DIV2, 16, 1)
> + FIELD(VPLL_CTRL, FBDIV, 8, 7)
> + FIELD(VPLL_CTRL, BYPASS, 3, 1)
> + FIELD(VPLL_CTRL, RESET, 0, 1)
> +REG32(VPLL_CFG, 0x3c)
> + FIELD(VPLL_CFG, LOCK_DLY, 25, 7)
> + FIELD(VPLL_CFG, LOCK_CNT, 13, 10)
> + FIELD(VPLL_CFG, LFHF, 10, 2)
> + FIELD(VPLL_CFG, CP, 5, 4)
> + FIELD(VPLL_CFG, RES, 0, 4)
> +REG32(VPLL_FRAC_CFG, 0x40)
> + FIELD(VPLL_FRAC_CFG, ENABLED, 31, 1)
> + FIELD(VPLL_FRAC_CFG, SEED, 22, 3)
> + FIELD(VPLL_FRAC_CFG, ALGRTHM, 19, 1)
> + FIELD(VPLL_FRAC_CFG, ORDER, 18, 1)
> + FIELD(VPLL_FRAC_CFG, DATA, 0, 16)
> +REG32(PLL_STATUS, 0x44)
> + FIELD(PLL_STATUS, VPLL_STABLE, 5, 1)
> + FIELD(PLL_STATUS, DPLL_STABLE, 4, 1)
> + FIELD(PLL_STATUS, APLL_STABLE, 3, 1)
> + FIELD(PLL_STATUS, VPLL_LOCK, 2, 1)
> + FIELD(PLL_STATUS, DPLL_LOCK, 1, 1)
> + FIELD(PLL_STATUS, APLL_LOCK, 0, 1)
> +REG32(APLL_TO_LPD_CTRL, 0x48)
> + FIELD(APLL_TO_LPD_CTRL, DIVISOR0, 8, 6)
> +REG32(DPLL_TO_LPD_CTRL, 0x4c)
> + FIELD(DPLL_TO_LPD_CTRL, DIVISOR0, 8, 6)
> +REG32(VPLL_TO_LPD_CTRL, 0x50)
> + FIELD(VPLL_TO_LPD_CTRL, DIVISOR0, 8, 6)
> +REG32(ACPU_CTRL, 0x60)
> + FIELD(ACPU_CTRL, CLKACT_HALF, 25, 1)
> + FIELD(ACPU_CTRL, CLKACT_FULL, 24, 1)
> + FIELD(ACPU_CTRL, DIVISOR0, 8, 6)
> + FIELD(ACPU_CTRL, SRCSEL, 0, 3)
> +REG32(DBG_TRACE_CTRL, 0x64)
> + FIELD(DBG_TRACE_CTRL, CLKACT, 24, 1)
> + FIELD(DBG_TRACE_CTRL, DIVISOR0, 8, 6)
> + FIELD(DBG_TRACE_CTRL, SRCSEL, 0, 3)
> +REG32(DBG_FPD_CTRL, 0x68)
> + FIELD(DBG_FPD_CTRL, CLKACT, 24, 1)
> + FIELD(DBG_FPD_CTRL, DIVISOR0, 8, 6)
> + FIELD(DBG_FPD_CTRL, SRCSEL, 0, 3)
> +REG32(DP_VIDEO_REF_CTRL, 0x70)
> + FIELD(DP_VIDEO_REF_CTRL, CLKACT, 24, 1)
> + FIELD(DP_VIDEO_REF_CTRL, DIVISOR1, 16, 6)
> + FIELD(DP_VIDEO_REF_CTRL, DIVISOR0, 8, 6)
> + FIELD(DP_VIDEO_REF_CTRL, SRCSEL, 0, 3)
> +REG32(DP_AUDIO_REF_CTRL, 0x74)
> + FIELD(DP_AUDIO_REF_CTRL, CLKACT, 24, 1)
> + FIELD(DP_AUDIO_REF_CTRL, DIVISOR1, 16, 6)
> + FIELD(DP_AUDIO_REF_CTRL, DIVISOR0, 8, 6)
> + FIELD(DP_AUDIO_REF_CTRL, SRCSEL, 0, 3)
> +REG32(DP_STC_REF_CTRL, 0x7c)
> + FIELD(DP_STC_REF_CTRL, CLKACT, 24, 1)
> + FIELD(DP_STC_REF_CTRL, DIVISOR1, 16, 6)
> + FIELD(DP_STC_REF_CTRL, DIVISOR0, 8, 6)
> + FIELD(DP_STC_REF_CTRL, SRCSEL, 0, 3)
> +REG32(DDR_CTRL, 0x80)
> + FIELD(DDR_CTRL, CLKACT, 24, 1)
> + FIELD(DDR_CTRL, DIVISOR0, 8, 6)
> + FIELD(DDR_CTRL, SRCSEL, 0, 3)
> +REG32(GPU_REF_CTRL, 0x84)
> + FIELD(GPU_REF_CTRL, PP1_CLKACT, 26, 1)
> + FIELD(GPU_REF_CTRL, PP0_CLKACT, 25, 1)
> + FIELD(GPU_REF_CTRL, CLKACT, 24, 1)
> + FIELD(GPU_REF_CTRL, DIVISOR0, 8, 6)
> + FIELD(GPU_REF_CTRL, SRCSEL, 0, 3)
> +REG32(SATA_REF_CTRL, 0xa0)
> + FIELD(SATA_REF_CTRL, CLKACT, 24, 1)
> + FIELD(SATA_REF_CTRL, DIVISOR0, 8, 6)
> + FIELD(SATA_REF_CTRL, SRCSEL, 0, 3)
> +REG32(PCIE_REF_CTRL, 0xb4)
> + FIELD(PCIE_REF_CTRL, CLKACT, 24, 1)
> + FIELD(PCIE_REF_CTRL, DIVISOR0, 8, 6)
> + FIELD(PCIE_REF_CTRL, SRCSEL, 0, 3)
> +REG32(GDMA_REF_CTRL, 0xb8)
> + FIELD(GDMA_REF_CTRL, CLKACT, 24, 1)
> + FIELD(GDMA_REF_CTRL, DIVISOR0, 8, 6)
> + FIELD(GDMA_REF_CTRL, SRCSEL, 0, 3)
> +REG32(DPDMA_REF_CTRL, 0xbc)
> + FIELD(DPDMA_REF_CTRL, CLKACT, 24, 1)
> + FIELD(DPDMA_REF_CTRL, DIVISOR0, 8, 6)
> + FIELD(DPDMA_REF_CTRL, SRCSEL, 0, 3)
> +REG32(TOPSW_MAIN_CTRL, 0xc0)
> + FIELD(TOPSW_MAIN_CTRL, CLKACT, 24, 1)
> + FIELD(TOPSW_MAIN_CTRL, DIVISOR0, 8, 6)
> + FIELD(TOPSW_MAIN_CTRL, SRCSEL, 0, 3)
> +REG32(TOPSW_LSBUS_CTRL, 0xc4)
> + FIELD(TOPSW_LSBUS_CTRL, CLKACT, 24, 1)
> + FIELD(TOPSW_LSBUS_CTRL, DIVISOR0, 8, 6)
> + FIELD(TOPSW_LSBUS_CTRL, SRCSEL, 0, 3)
> +REG32(DBG_TSTMP_CTRL, 0xf8)
> + FIELD(DBG_TSTMP_CTRL, DIVISOR0, 8, 6)
> + FIELD(DBG_TSTMP_CTRL, SRCSEL, 0, 3)
> +REG32(RST_FPD_TOP, 0x100)
> + FIELD(RST_FPD_TOP, PCIE_CFG_RESET, 19, 1)
> + FIELD(RST_FPD_TOP, PCIE_BRIDGE_RESET, 18, 1)
> + FIELD(RST_FPD_TOP, PCIE_CTRL_RESET, 17, 1)
> + FIELD(RST_FPD_TOP, DP_RESET, 16, 1)
> + FIELD(RST_FPD_TOP, SWDT_RESET, 15, 1)
> + FIELD(RST_FPD_TOP, AFI_FM5_RESET, 12, 1)
> + FIELD(RST_FPD_TOP, AFI_FM4_RESET, 11, 1)
> + FIELD(RST_FPD_TOP, AFI_FM3_RESET, 10, 1)
> + FIELD(RST_FPD_TOP, AFI_FM2_RESET, 9, 1)
> + FIELD(RST_FPD_TOP, AFI_FM1_RESET, 8, 1)
> + FIELD(RST_FPD_TOP, AFI_FM0_RESET, 7, 1)
> + FIELD(RST_FPD_TOP, GDMA_RESET, 6, 1)
> + FIELD(RST_FPD_TOP, GPU_PP1_RESET, 5, 1)
> + FIELD(RST_FPD_TOP, GPU_PP0_RESET, 4, 1)
> + FIELD(RST_FPD_TOP, GPU_RESET, 3, 1)
> + FIELD(RST_FPD_TOP, GT_RESET, 2, 1)
> + FIELD(RST_FPD_TOP, SATA_RESET, 1, 1)
> +REG32(RST_FPD_APU, 0x104)
> + FIELD(RST_FPD_APU, ACPU3_PWRON_RESET, 13, 1)
> + FIELD(RST_FPD_APU, ACPU2_PWRON_RESET, 12, 1)
> + FIELD(RST_FPD_APU, ACPU1_PWRON_RESET, 11, 1)
> + FIELD(RST_FPD_APU, ACPU0_PWRON_RESET, 10, 1)
> + FIELD(RST_FPD_APU, APU_L2_RESET, 8, 1)
> + FIELD(RST_FPD_APU, ACPU3_RESET, 3, 1)
> + FIELD(RST_FPD_APU, ACPU2_RESET, 2, 1)
> + FIELD(RST_FPD_APU, ACPU1_RESET, 1, 1)
> + FIELD(RST_FPD_APU, ACPU0_RESET, 0, 1)
> +REG32(RST_DDR_SS, 0x108)
> + FIELD(RST_DDR_SS, DDR_RESET, 3, 1)
> + FIELD(RST_DDR_SS, APM_RESET, 2, 1)
> +
> +#define CRF_R_MAX (R_RST_DDR_SS + 1)
> +
> +typedef struct XlnxZynqMPCRF {
> + SysBusDevice parent_obj;
> + MemoryRegion iomem;
> + qemu_irq irq_ir;
> +
> + RegisterInfoArray *reg_array;
> + uint32_t regs[CRF_R_MAX];
> + RegisterInfo regs_info[CRF_R_MAX];
> +} XlnxZynqMPCRF;
> diff --git a/hw/misc/xlnx-zynqmp-crf.c b/hw/misc/xlnx-zynqmp-crf.c
> new file mode 100644
> index 0000000000..7b3a955a42
> --- /dev/null
> +++ b/hw/misc/xlnx-zynqmp-crf.c
> @@ -0,0 +1,270 @@
> +/*
> + * QEMU model of the CRF - Clock Reset FPD.
> + *
> + * Copyright (c) 2022 Xilinx Inc.
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/sysbus.h"
> +#include "hw/register.h"
> +#include "qemu/bitops.h"
> +#include "qemu/log.h"
> +#include "migration/vmstate.h"
> +#include "hw/irq.h"
> +#include "hw/misc/xlnx-zynqmp-crf.h"
> +#include "target/arm/arm-powerctl.h"
> +
> +#ifndef XILINX_CRF_ERR_DEBUG
> +#define XILINX_CRF_ERR_DEBUG 1
> +#endif
> +
> +#define APU_MAX_CPU 4
> +
> +static void ir_update_irq(XlnxZynqMPCRF *s)
> +{
> + bool pending = s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK];
> + qemu_set_irq(s->irq_ir, pending);
> +}
> +
> +static void ir_status_postw(RegisterInfo *reg, uint64_t val64)
> +{
> + XlnxZynqMPCRF *s = XILINX_CRF(reg->opaque);
> + ir_update_irq(s);
> +}
> +
> +static uint64_t ir_enable_prew(RegisterInfo *reg, uint64_t val64)
> +{
> + XlnxZynqMPCRF *s = XILINX_CRF(reg->opaque);
> + uint32_t val = val64;
> +
> + s->regs[R_IR_MASK] &= ~val;
> + ir_update_irq(s);
> + return 0;
> +}
> +
> +static uint64_t ir_disable_prew(RegisterInfo *reg, uint64_t val64)
> +{
> + XlnxZynqMPCRF *s = XILINX_CRF(reg->opaque);
> + uint32_t val = val64;
> +
> + s->regs[R_IR_MASK] |= val;
> + ir_update_irq(s);
> + return 0;
> +}
> +
> +static uint64_t rst_fpd_apu_prew(RegisterInfo *reg, uint64_t val64)
> +{
> + XlnxZynqMPCRF *s = XILINX_CRF(reg->opaque);
> + uint32_t val = val64;
> + uint32_t val_old = s->regs[R_RST_FPD_APU];
> + unsigned int i;
> +
> + for (i = 0; i < APU_MAX_CPU; i++) {
> + uint32_t mask = (1 << (R_RST_FPD_APU_ACPU0_RESET_SHIFT + i));
> +
> + if ((val ^ val_old) & mask) {
> + if (val & mask) {
> + arm_set_cpu_off(i);
> + } else {
> + arm_set_cpu_on_and_reset(i);
> + }
> + }
> + }
> + return val64;
> +}
> +
> +static const RegisterAccessInfo crf_regs_info[] = {
> + { .name = "ERR_CTRL", .addr = A_ERR_CTRL,
> + },{ .name = "IR_STATUS", .addr = A_IR_STATUS,
> + .w1c = 0x1,
> + .post_write = ir_status_postw,
> + },{ .name = "IR_MASK", .addr = A_IR_MASK,
> + .reset = 0x1,
> + .ro = 0x1,
> + },{ .name = "IR_ENABLE", .addr = A_IR_ENABLE,
> + .pre_write = ir_enable_prew,
> + },{ .name = "IR_DISABLE", .addr = A_IR_DISABLE,
> + .pre_write = ir_disable_prew,
> + },{ .name = "CRF_WPROT", .addr = A_CRF_WPROT,
> + },{ .name = "APLL_CTRL", .addr = A_APLL_CTRL,
> + .reset = 0x12c09,
> + .rsvd = 0xf88c80f6,
> + },{ .name = "APLL_CFG", .addr = A_APLL_CFG,
> + .rsvd = 0x1801210,
> + },{ .name = "APLL_FRAC_CFG", .addr = A_APLL_FRAC_CFG,
> + .rsvd = 0x7e330000,
> + },{ .name = "DPLL_CTRL", .addr = A_DPLL_CTRL,
> + .reset = 0x2c09,
> + .rsvd = 0xf88c80f6,
> + },{ .name = "DPLL_CFG", .addr = A_DPLL_CFG,
> + .rsvd = 0x1801210,
> + },{ .name = "DPLL_FRAC_CFG", .addr = A_DPLL_FRAC_CFG,
> + .rsvd = 0x7e330000,
> + },{ .name = "VPLL_CTRL", .addr = A_VPLL_CTRL,
> + .reset = 0x12809,
> + .rsvd = 0xf88c80f6,
> + },{ .name = "VPLL_CFG", .addr = A_VPLL_CFG,
> + .rsvd = 0x1801210,
> + },{ .name = "VPLL_FRAC_CFG", .addr = A_VPLL_FRAC_CFG,
> + .rsvd = 0x7e330000,
> + },{ .name = "PLL_STATUS", .addr = A_PLL_STATUS,
> + .reset = 0x3f,
> + .rsvd = 0xc0,
> + .ro = 0x3f,
> + },{ .name = "APLL_TO_LPD_CTRL", .addr = A_APLL_TO_LPD_CTRL,
> + .reset = 0x400,
> + .rsvd = 0xc0ff,
> + },{ .name = "DPLL_TO_LPD_CTRL", .addr = A_DPLL_TO_LPD_CTRL,
> + .reset = 0x400,
> + .rsvd = 0xc0ff,
> + },{ .name = "VPLL_TO_LPD_CTRL", .addr = A_VPLL_TO_LPD_CTRL,
> + .reset = 0x400,
> + .rsvd = 0xc0ff,
> + },{ .name = "ACPU_CTRL", .addr = A_ACPU_CTRL,
> + .reset = 0x3000400,
> + .rsvd = 0xfcffc0f8,
> + },{ .name = "DBG_TRACE_CTRL", .addr = A_DBG_TRACE_CTRL,
> + .reset = 0x2500,
> + .rsvd = 0xfeffc0f8,
> + },{ .name = "DBG_FPD_CTRL", .addr = A_DBG_FPD_CTRL,
> + .reset = 0x1002500,
> + .rsvd = 0xfeffc0f8,
> + },{ .name = "DP_VIDEO_REF_CTRL", .addr = A_DP_VIDEO_REF_CTRL,
> + .reset = 0x1002300,
> + .rsvd = 0xfec0c0f8,
> + },{ .name = "DP_AUDIO_REF_CTRL", .addr = A_DP_AUDIO_REF_CTRL,
> + .reset = 0x1032300,
> + .rsvd = 0xfec0c0f8,
> + },{ .name = "DP_STC_REF_CTRL", .addr = A_DP_STC_REF_CTRL,
> + .reset = 0x1203200,
> + .rsvd = 0xfec0c0f8,
> + },{ .name = "DDR_CTRL", .addr = A_DDR_CTRL,
> + .reset = 0x1000500,
> + .rsvd = 0xfeffc0f8,
> + },{ .name = "GPU_REF_CTRL", .addr = A_GPU_REF_CTRL,
> + .reset = 0x1500,
> + .rsvd = 0xf8ffc0f8,
> + },{ .name = "SATA_REF_CTRL", .addr = A_SATA_REF_CTRL,
> + .reset = 0x1001600,
> + .rsvd = 0xfeffc0f8,
> + },{ .name = "PCIE_REF_CTRL", .addr = A_PCIE_REF_CTRL,
> + .reset = 0x1500,
> + .rsvd = 0xfeffc0f8,
> + },{ .name = "GDMA_REF_CTRL", .addr = A_GDMA_REF_CTRL,
> + .reset = 0x1000500,
> + .rsvd = 0xfeffc0f8,
> + },{ .name = "DPDMA_REF_CTRL", .addr = A_DPDMA_REF_CTRL,
> + .reset = 0x1000500,
> + .rsvd = 0xfeffc0f8,
> + },{ .name = "TOPSW_MAIN_CTRL", .addr = A_TOPSW_MAIN_CTRL,
> + .reset = 0x1000400,
> + .rsvd = 0xfeffc0f8,
> + },{ .name = "TOPSW_LSBUS_CTRL", .addr = A_TOPSW_LSBUS_CTRL,
> + .reset = 0x1000800,
> + .rsvd = 0xfeffc0f8,
> + },{ .name = "DBG_TSTMP_CTRL", .addr = A_DBG_TSTMP_CTRL,
> + .reset = 0xa00,
> + .rsvd = 0xffffc0f8,
> + },
> + { .name = "RST_FPD_TOP", .addr = A_RST_FPD_TOP,
> + .reset = 0xf9ffe,
> + .rsvd = 0xf06001,
> + },{ .name = "RST_FPD_APU", .addr = A_RST_FPD_APU,
> + .reset = 0x3d0f,
> + .rsvd = 0xc2f0,
> + .pre_write = rst_fpd_apu_prew,
> + },{ .name = "RST_DDR_SS", .addr = A_RST_DDR_SS,
> + .reset = 0xf,
> + .rsvd = 0xf3,
> + }
> +};
> +
> +static void crf_reset_enter(Object *obj, ResetType type)
> +{
> + XlnxZynqMPCRF *s = XILINX_CRF(obj);
> + unsigned int i;
> +
> + for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
> + register_reset(&s->regs_info[i]);
> + }
> +}
> +
> +static void crf_reset_hold(Object *obj)
> +{
> + XlnxZynqMPCRF *s = XILINX_CRF(obj);
> + ir_update_irq(s);
> +}
> +
> +static const MemoryRegionOps crf_ops = {
> + .read = register_read_memory,
> + .write = register_write_memory,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> + .valid = {
> + .min_access_size = 4,
> + .max_access_size = 4,
> + },
> +};
> +
> +static void crf_init(Object *obj)
> +{
> + XlnxZynqMPCRF *s = XILINX_CRF(obj);
> + SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
> +
> + s->reg_array =
> + register_init_block32(DEVICE(obj), crf_regs_info,
> + ARRAY_SIZE(crf_regs_info),
> + s->regs_info, s->regs,
> + &crf_ops,
> + XILINX_CRF_ERR_DEBUG,
> + CRF_R_MAX * 4);
> + sysbus_init_mmio(sbd, &s->reg_array->mem);
> + sysbus_init_irq(sbd, &s->irq_ir);
> +}
> +
> +static void crf_finalize(Object *obj)
> +{
> + XlnxZynqMPCRF *s = XILINX_CRF(obj);
> + register_finalize_block(s->reg_array);
> +}
> +
> +static const VMStateDescription vmstate_crf = {
> + .name = TYPE_XLNX_ZYNQMP_CRF,
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .minimum_version_id_old = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPCRF, CRF_R_MAX),
> + VMSTATE_END_OF_LIST(),
> + }
> +};
> +
> +static void crf_class_init(ObjectClass *klass, void *data)
> +{
> + ResettableClass *rc = RESETTABLE_CLASS(klass);
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->vmsd = &vmstate_crf;
> + rc->phases.enter = crf_reset_enter;
> + rc->phases.hold = crf_reset_hold;
> +}
> +
> +static const TypeInfo crf_info = {
> + .name = TYPE_XLNX_ZYNQMP_CRF,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(XlnxZynqMPCRF),
> + .class_init = crf_class_init,
> + .instance_init = crf_init,
> + .instance_finalize = crf_finalize,
> + .interfaces = (InterfaceInfo[]) {
> + { }
We can remove above 'interfaces'. With above removed and include guards
added:
Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Best regards,
Francisco Iglesias
> + },
> +};
> +
> +static void crf_register_types(void)
> +{
> + type_register_static(&crf_info);
> +}
> +
> +type_init(crf_register_types)
> diff --git a/hw/misc/meson.build b/hw/misc/meson.build
> index 6dcbe044f3..1927f13a5e 100644
> --- a/hw/misc/meson.build
> +++ b/hw/misc/meson.build
> @@ -84,6 +84,7 @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
> ))
> softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
> softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c'))
> +specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c'))
> softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files(
> 'xlnx-versal-xramc.c',
> 'xlnx-versal-pmc-iou-slcr.c',
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v1 4/6] hw/arm/xlnx-zynqmp: Connect the ZynqMP CRF
2022-01-30 23:12 ` [PATCH v1 4/6] hw/arm/xlnx-zynqmp: Connect the " Edgar E. Iglesias
2022-01-30 23:33 ` Philippe Mathieu-Daudé via
@ 2022-01-31 15:37 ` Francisco Iglesias
2022-02-03 20:23 ` Luc Michel
2 siblings, 0 replies; 26+ messages in thread
From: Francisco Iglesias @ 2022-01-31 15:37 UTC (permalink / raw)
To: Edgar E. Iglesias
Cc: edgar.iglesias, peter.maydell, luc, sai.pavan.boddu,
frasse.iglesias, alistair, richard.henderson, qemu-devel,
frederic.konrad, qemu-arm
On Mon, Jan 31, 2022 at 12:12:04AM +0100, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Connect the ZynqMP CRF - Clock Reset FPD device.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
> ---
> include/hw/arm/xlnx-zynqmp.h | 2 ++
> hw/arm/xlnx-zynqmp.c | 16 ++++++++++++++++
> 2 files changed, 18 insertions(+)
>
> diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
> index 99ceb8a609..d5a3ad3df2 100644
> --- a/include/hw/arm/xlnx-zynqmp.h
> +++ b/include/hw/arm/xlnx-zynqmp.h
> @@ -38,6 +38,7 @@
> #include "hw/dma/xlnx_csu_dma.h"
> #include "hw/nvram/xlnx-bbram.h"
> #include "hw/nvram/xlnx-zynqmp-efuse.h"
> +#include "hw/misc/xlnx-zynqmp-crf.h"
>
> #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
> OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
> @@ -122,6 +123,7 @@ struct XlnxZynqMPState {
> XlnxZDMA gdma[XLNX_ZYNQMP_NUM_GDMA_CH];
> XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH];
> XlnxCSUDMA qspi_dma;
> + XlnxZynqMPCRF crf;
>
> char *boot_cpu;
> ARMCPU *boot_cpu_ptr;
> diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
> index ba44e95899..857d3c9636 100644
> --- a/hw/arm/xlnx-zynqmp.c
> +++ b/hw/arm/xlnx-zynqmp.c
> @@ -51,6 +51,9 @@
> #define QSPI_IRQ 15
> #define QSPI_DMA_ADDR 0xff0f0800
>
> +#define CRF_ADDR 0xfd1a0000
> +#define CRF_IRQ 120
> +
> #define SERDES_ADDR 0xfd400000
> #define SERDES_SIZE 0x20000
>
> @@ -279,6 +282,18 @@ static void xlnx_zynqmp_create_efuse(XlnxZynqMPState *s, qemu_irq *gic)
> sysbus_connect_irq(sbd, 0, gic[EFUSE_IRQ]);
> }
>
> +static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic)
> +{
> + SysBusDevice *sbd;
> +
> + object_initialize_child(OBJECT(s), "crf", &s->crf, TYPE_XLNX_ZYNQMP_CRF);
> + sbd = SYS_BUS_DEVICE(&s->crf);
> +
> + sysbus_realize(sbd, &error_fatal);
> + sysbus_mmio_map(sbd, 0, CRF_ADDR);
> + sysbus_connect_irq(sbd, 0, gic[CRF_IRQ]);
> +}
> +
> static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
> {
> static const struct UnimpInfo {
> @@ -682,6 +697,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
>
> xlnx_zynqmp_create_bbram(s, gic_spi);
> xlnx_zynqmp_create_efuse(s, gic_spi);
> + xlnx_zynqmp_create_crf(s, gic_spi);
> xlnx_zynqmp_create_unimp_mmio(s);
>
> for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v1 5/6] hw/misc: Add a model of the Xilinx ZynqMP APU Control
2022-01-30 23:12 ` [PATCH v1 5/6] hw/misc: Add a model of the Xilinx ZynqMP APU Control Edgar E. Iglesias
2022-01-30 23:35 ` Philippe Mathieu-Daudé via
@ 2022-01-31 15:46 ` Francisco Iglesias
1 sibling, 0 replies; 26+ messages in thread
From: Francisco Iglesias @ 2022-01-31 15:46 UTC (permalink / raw)
To: Edgar E. Iglesias
Cc: edgar.iglesias, peter.maydell, luc, sai.pavan.boddu,
frasse.iglesias, alistair, richard.henderson, qemu-devel,
frederic.konrad, qemu-arm
Hi Edgar,
Some minor comments again, otherwise it looks good to me!
On Mon, Jan 31, 2022 at 12:12:05AM +0100, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Add a model of the Xilinx ZynqMP APU Control.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
> include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 91 +++++++++
> hw/misc/xlnx-zynqmp-apu-ctrl.c | 257 +++++++++++++++++++++++++
> hw/misc/meson.build | 1 +
> 3 files changed, 349 insertions(+)
> create mode 100644 include/hw/misc/xlnx-zynqmp-apu-ctrl.h
> create mode 100644 hw/misc/xlnx-zynqmp-apu-ctrl.c
>
> diff --git a/include/hw/misc/xlnx-zynqmp-apu-ctrl.h b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h
> new file mode 100644
> index 0000000000..44bf264cef
> --- /dev/null
> +++ b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h
> @@ -0,0 +1,91 @@
> +/*
> + * QEMU model of ZynqMP APU Control.
> + *
> + * Copyright (c) 2013-2022 Xilinx Inc
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + *
> + * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> and
> + * Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> + *
> + */
> +
Include guards are missing here again.
> +#include "hw/sysbus.h"
> +#include "hw/register.h"
> +#include "target/arm/cpu.h"
> +
> +#define TYPE_XLNX_ZYNQMP_APU_CTRL "xlnx.apu-ctrl"
> +
> +#define XLNX_ZYNQMP_APU(obj) \
> + OBJECT_CHECK(XlnxZynqMPAPUCtrl, (obj), TYPE_XLNX_ZYNQMP_APU_CTRL)
> +
> +REG32(APU_ERR_CTRL, 0x0)
> + FIELD(APU_ERR_CTRL, PSLVERR, 0, 1)
> +REG32(ISR, 0x10)
> + FIELD(ISR, INV_APB, 0, 1)
> +REG32(IMR, 0x14)
> + FIELD(IMR, INV_APB, 0, 1)
> +REG32(IEN, 0x18)
> + FIELD(IEN, INV_APB, 0, 1)
> +REG32(IDS, 0x1c)
> + FIELD(IDS, INV_APB, 0, 1)
> +REG32(CONFIG_0, 0x20)
> + FIELD(CONFIG_0, CFGTE, 24, 4)
> + FIELD(CONFIG_0, CFGEND, 16, 4)
> + FIELD(CONFIG_0, VINITHI, 8, 4)
> + FIELD(CONFIG_0, AA64NAA32, 0, 4)
> +REG32(CONFIG_1, 0x24)
> + FIELD(CONFIG_1, L2RSTDISABLE, 29, 1)
> + FIELD(CONFIG_1, L1RSTDISABLE, 28, 1)
> + FIELD(CONFIG_1, CP15DISABLE, 0, 4)
> +REG32(RVBARADDR0L, 0x40)
> + FIELD(RVBARADDR0L, ADDR, 2, 30)
> +REG32(RVBARADDR0H, 0x44)
> + FIELD(RVBARADDR0H, ADDR, 0, 8)
> +REG32(RVBARADDR1L, 0x48)
> + FIELD(RVBARADDR1L, ADDR, 2, 30)
> +REG32(RVBARADDR1H, 0x4c)
> + FIELD(RVBARADDR1H, ADDR, 0, 8)
> +REG32(RVBARADDR2L, 0x50)
> + FIELD(RVBARADDR2L, ADDR, 2, 30)
> +REG32(RVBARADDR2H, 0x54)
> + FIELD(RVBARADDR2H, ADDR, 0, 8)
> +REG32(RVBARADDR3L, 0x58)
> + FIELD(RVBARADDR3L, ADDR, 2, 30)
> +REG32(RVBARADDR3H, 0x5c)
> + FIELD(RVBARADDR3H, ADDR, 0, 8)
> +REG32(ACE_CTRL, 0x60)
> + FIELD(ACE_CTRL, AWQOS, 16, 4)
> + FIELD(ACE_CTRL, ARQOS, 0, 4)
> +REG32(SNOOP_CTRL, 0x80)
> + FIELD(SNOOP_CTRL, ACE_INACT, 4, 1)
> + FIELD(SNOOP_CTRL, ACP_INACT, 0, 1)
> +REG32(PWRCTL, 0x90)
> + FIELD(PWRCTL, CLREXMONREQ, 17, 1)
> + FIELD(PWRCTL, L2FLUSHREQ, 16, 1)
> + FIELD(PWRCTL, CPUPWRDWNREQ, 0, 4)
> +REG32(PWRSTAT, 0x94)
> + FIELD(PWRSTAT, CLREXMONACK, 17, 1)
> + FIELD(PWRSTAT, L2FLUSHDONE, 16, 1)
> + FIELD(PWRSTAT, DBGNOPWRDWN, 0, 4)
> +
> +#define APU_R_MAX ((R_PWRSTAT) + 1)
> +
> +#define NUM_CPUS 4
> +
> +typedef struct XlnxZynqMPAPUCtrl {
> + SysBusDevice busdev;
> +
> + ARMCPU *cpus[NUM_CPUS];
> + /* WFIs towards PMU. */
> + qemu_irq wfi_out[4];
> + /* CPU Power status towards INTC Redirect. */
> + qemu_irq cpu_power_status[4];
> + qemu_irq irq_imr;
> +
> + uint8_t cpu_pwrdwn_req;
> + uint8_t cpu_in_wfi;
> +
> + RegisterInfoArray *reg_array;
> + uint32_t regs[APU_R_MAX];
> + RegisterInfo regs_info[APU_R_MAX];
> +} XlnxZynqMPAPUCtrl;
> diff --git a/hw/misc/xlnx-zynqmp-apu-ctrl.c b/hw/misc/xlnx-zynqmp-apu-ctrl.c
> new file mode 100644
> index 0000000000..c27b8b9253
> --- /dev/null
> +++ b/hw/misc/xlnx-zynqmp-apu-ctrl.c
> @@ -0,0 +1,257 @@
> +/*
> + * QEMU model of the ZynqMP APU Control.
> + *
> + * Copyright (c) 2013-2022 Xilinx Inc
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + *
> + * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> and
> + * Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qapi/error.h"
> +#include "qemu/log.h"
> +#include "migration/vmstate.h"
> +#include "hw/qdev-properties.h"
> +#include "hw/sysbus.h"
> +#include "hw/irq.h"
> +#include "hw/register.h"
> +
> +#include "qemu/bitops.h"
> +#include "qapi/qmp/qerror.h"
> +
> +#include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
> +
> +#ifndef XILINX_ZYNQMP_APU_ERR_DEBUG
> +#define XILINX_ZYNQMP_APU_ERR_DEBUG 1
> +#endif
> +
> +static void update_wfi_out(void *opaque)
> +{
> + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU(opaque);
> + unsigned int i, wfi_pending;
> +
> + wfi_pending = s->cpu_pwrdwn_req & s->cpu_in_wfi;
> + for (i = 0; i < NUM_CPUS; i++) {
> + qemu_set_irq(s->wfi_out[i], !!(wfi_pending & (1 << i)));
> + }
> +}
> +
> +static void zynqmp_apu_rvbar_post_write(RegisterInfo *reg, uint64_t val)
> +{
> + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU(reg->opaque);
> + int i;
> +
> + for (i = 0; i < NUM_CPUS; ++i) {
> + uint64_t rvbar = s->regs[R_RVBARADDR0L + 2 * i] +
> + ((uint64_t)s->regs[R_RVBARADDR0H + 2 * i] << 32);
> + if (s->cpus[i]) {
> + object_property_set_int(OBJECT(s->cpus[i]), "rvbar", rvbar,
> + &error_abort);
> + }
> + }
> +}
> +
> +static void zynqmp_apu_pwrctl_post_write(RegisterInfo *reg, uint64_t val)
> +{
> + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU(reg->opaque);
> + unsigned int i, new;
> +
> + for (i = 0; i < NUM_CPUS; i++) {
> + new = val & (1 << i);
> + /* Check if CPU's CPUPWRDNREQ has changed. If yes, update GPIOs. */
> + if (new != (s->cpu_pwrdwn_req & (1 << i))) {
> + qemu_set_irq(s->cpu_power_status[i], !!new);
> + }
> + s->cpu_pwrdwn_req &= ~(1 << i);
> + s->cpu_pwrdwn_req |= new;
> + }
> + update_wfi_out(s);
> +}
> +
> +static void imr_update_irq(XlnxZynqMPAPUCtrl *s)
> +{
> + bool pending = s->regs[R_ISR] & ~s->regs[R_IMR];
> + qemu_set_irq(s->irq_imr, pending);
> +}
> +
> +static void isr_postw(RegisterInfo *reg, uint64_t val64)
> +{
> + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU(reg->opaque);
> + imr_update_irq(s);
> +}
> +
> +static uint64_t ien_prew(RegisterInfo *reg, uint64_t val64)
> +{
> + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU(reg->opaque);
> + uint32_t val = val64;
> +
> + s->regs[R_IMR] &= ~val;
> + imr_update_irq(s);
> + return 0;
> +}
> +
> +static uint64_t ids_prew(RegisterInfo *reg, uint64_t val64)
> +{
> + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU(reg->opaque);
> + uint32_t val = val64;
> +
> + s->regs[R_IMR] |= val;
> + imr_update_irq(s);
> + return 0;
> +}
> +
> +static const RegisterAccessInfo zynqmp_apu_regs_info[] = {
> +#define RVBAR_REGDEF(n) \
> + { .name = "RVBAR CPU " #n " Low", .addr = A_RVBARADDR ## n ## L, \
> + .reset = 0xffff0000ul, \
> + .post_write = zynqmp_apu_rvbar_post_write, \
> + },{ .name = "RVBAR CPU " #n " High", .addr = A_RVBARADDR ## n ## H, \
> + .post_write = zynqmp_apu_rvbar_post_write, \
> + }
> + { .name = "ERR_CTRL", .addr = A_APU_ERR_CTRL,
> + },{ .name = "ISR", .addr = A_ISR,
> + .w1c = 0x1,
> + .post_write = isr_postw,
> + },{ .name = "IMR", .addr = A_IMR,
> + .reset = 0x1,
> + .ro = 0x1,
> + },{ .name = "IEN", .addr = A_IEN,
> + .pre_write = ien_prew,
> + },{ .name = "IDS", .addr = A_IDS,
> + .pre_write = ids_prew,
> + },{ .name = "CONFIG_0", .addr = A_CONFIG_0,
> + .reset = 0xf0f,
> + },{ .name = "CONFIG_1", .addr = A_CONFIG_1,
> + },
> + RVBAR_REGDEF(0),
> + RVBAR_REGDEF(1),
> + RVBAR_REGDEF(2),
> + RVBAR_REGDEF(3),
> + { .name = "ACE_CTRL", .addr = A_ACE_CTRL,
> + .reset = 0xf000f,
> + },{ .name = "SNOOP_CTRL", .addr = A_SNOOP_CTRL,
> + },{ .name = "PWRCTL", .addr = A_PWRCTL,
> + .post_write = zynqmp_apu_pwrctl_post_write,
> + },{ .name = "PWRSTAT", .addr = A_PWRSTAT,
> + .ro = 0x3000f,
> + }
> +};
> +
> +static void zynqmp_apu_reset_enter(Object *obj, ResetType type)
> +{
> + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU(obj);
> + int i;
> +
> + for (i = 0; i < APU_R_MAX; ++i) {
> + register_reset(&s->regs_info[i]);
> + }
> +
> + s->cpu_pwrdwn_req = 0;
> + s->cpu_in_wfi = 0;
> +}
> +
> +static void zynqmp_apu_reset_hold(Object *obj)
> +{
> + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU(obj);
> +
> + update_wfi_out(s);
> + imr_update_irq(s);
> +}
> +
> +static const MemoryRegionOps zynqmp_apu_ops = {
> + .read = register_read_memory,
> + .write = register_write_memory,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> + .valid = {
> + .min_access_size = 4,
> + .max_access_size = 4,
> + }
> +};
> +
> +static void zynqmp_apu_handle_wfi(void *opaque, int irq, int level)
> +{
> + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU(opaque);
> +
> + s->cpu_in_wfi = deposit32(s->cpu_in_wfi, irq, 1, level);
> + update_wfi_out(s);
> +}
> +
> +static void zynqmp_apu_init(Object *obj)
> +{
> + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU(obj);
> + int i;
> +
> + s->reg_array =
> + register_init_block32(DEVICE(obj), zynqmp_apu_regs_info,
> + ARRAY_SIZE(zynqmp_apu_regs_info),
> + s->regs_info, s->regs,
> + &zynqmp_apu_ops,
> + XILINX_ZYNQMP_APU_ERR_DEBUG,
> + APU_R_MAX * 4);
> + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->reg_array->mem);
> + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq_imr);
> +
> + for (i = 0; i < NUM_CPUS; ++i) {
> + g_autofree gchar *prop_name = g_strdup_printf("cpu%d", i);
> + object_property_add_link(obj, prop_name, TYPE_ARM_CPU,
Indentation needs a minor correction on the lines below.
> + (Object **)&s->cpus[i],
> + qdev_prop_allow_set_link_before_realize,
> + OBJ_PROP_LINK_STRONG);
> + }
> +
> + /* wfi_out is used to connect to PMU GPIs. */
> + qdev_init_gpio_out_named(DEVICE(obj), s->wfi_out, "wfi_out", 4);
> + /* CPU_POWER_STATUS is used to connect to INTC redirect. */
> + qdev_init_gpio_out_named(DEVICE(obj), s->cpu_power_status,
> + "CPU_POWER_STATUS", 4);
> + /* wfi_in is used as input from CPUs as wfi request. */
> + qdev_init_gpio_in_named(DEVICE(obj), zynqmp_apu_handle_wfi, "wfi_in", 4);
> +}
> +
> +static void zynqmp_apu_finalize(Object *obj)
> +{
> + XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU(obj);
> + register_finalize_block(s->reg_array);
> +}
> +
> +static const VMStateDescription vmstate_zynqmp_apu = {
> + .name = TYPE_XLNX_ZYNQMP_APU_CTRL,
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .minimum_version_id_old = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPAPUCtrl, APU_R_MAX),
> + VMSTATE_END_OF_LIST(),
> + }
> +};
> +
> +static void zynqmp_apu_class_init(ObjectClass *klass, void *data)
> +{
> + ResettableClass *rc = RESETTABLE_CLASS(klass);
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->vmsd = &vmstate_zynqmp_apu;
> +
> + rc->phases.enter = zynqmp_apu_reset_enter;
> + rc->phases.hold = zynqmp_apu_reset_hold;
> +}
> +
> +static const TypeInfo zynqmp_apu_info = {
> + .name = TYPE_XLNX_ZYNQMP_APU_CTRL,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(XlnxZynqMPAPUCtrl),
> + .class_init = zynqmp_apu_class_init,
> + .instance_init = zynqmp_apu_init,
> + .instance_finalize = zynqmp_apu_finalize,
> + .interfaces = (InterfaceInfo[]) {
> + { }
Interfaces can be removed above.
Best regards,
Francisco Iglesias
> + },
> +};
> +
> +static void zynqmp_apu_register_types(void)
> +{
> + type_register_static(&zynqmp_apu_info);
> +}
> +
> +type_init(zynqmp_apu_register_types)
> diff --git a/hw/misc/meson.build b/hw/misc/meson.build
> index 1927f13a5e..cf9d4cc618 100644
> --- a/hw/misc/meson.build
> +++ b/hw/misc/meson.build
> @@ -85,6 +85,7 @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
> softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
> softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c'))
> specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c'))
> +specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c'))
> softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files(
> 'xlnx-versal-xramc.c',
> 'xlnx-versal-pmc-iou-slcr.c',
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v1 6/6] hw/arm/xlnx-zynqmp: Connect the ZynqMP APU Control
2022-01-30 23:12 ` [PATCH v1 6/6] hw/arm/xlnx-zynqmp: Connect the " Edgar E. Iglesias
2022-01-30 23:37 ` Philippe Mathieu-Daudé via
@ 2022-01-31 15:48 ` Francisco Iglesias
2022-02-03 20:26 ` Luc Michel
2 siblings, 0 replies; 26+ messages in thread
From: Francisco Iglesias @ 2022-01-31 15:48 UTC (permalink / raw)
To: Edgar E. Iglesias
Cc: edgar.iglesias, peter.maydell, luc, sai.pavan.boddu,
frasse.iglesias, alistair, richard.henderson, qemu-devel,
frederic.konrad, qemu-arm
On Mon, Jan 31, 2022 at 12:12:06AM +0100, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Connect the ZynqMP APU Control device.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
> ---
> include/hw/arm/xlnx-zynqmp.h | 4 +++-
> hw/arm/xlnx-zynqmp.c | 25 +++++++++++++++++++++++--
> 2 files changed, 26 insertions(+), 3 deletions(-)
>
> diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
> index d5a3ad3df2..05cd2128f3 100644
> --- a/include/hw/arm/xlnx-zynqmp.h
> +++ b/include/hw/arm/xlnx-zynqmp.h
> @@ -38,6 +38,7 @@
> #include "hw/dma/xlnx_csu_dma.h"
> #include "hw/nvram/xlnx-bbram.h"
> #include "hw/nvram/xlnx-zynqmp-efuse.h"
> +#include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
> #include "hw/misc/xlnx-zynqmp-crf.h"
>
> #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
> @@ -85,7 +86,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
> /*
> * Unimplemented mmio regions needed to boot some images.
> */
> -#define XLNX_ZYNQMP_NUM_UNIMP_AREAS 2
> +#define XLNX_ZYNQMP_NUM_UNIMP_AREAS 1
>
> struct XlnxZynqMPState {
> /*< private >*/
> @@ -123,6 +124,7 @@ struct XlnxZynqMPState {
> XlnxZDMA gdma[XLNX_ZYNQMP_NUM_GDMA_CH];
> XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH];
> XlnxCSUDMA qspi_dma;
> + XlnxZynqMPAPUCtrl apu_ctrl;
> XlnxZynqMPCRF crf;
>
> char *boot_cpu;
> diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
> index 857d3c9636..21c411cd77 100644
> --- a/hw/arm/xlnx-zynqmp.c
> +++ b/hw/arm/xlnx-zynqmp.c
> @@ -64,7 +64,7 @@
> #define DPDMA_IRQ 116
>
> #define APU_ADDR 0xfd5c0000
> -#define APU_SIZE 0x100
> +#define APU_IRQ 153
>
> #define IPI_ADDR 0xFF300000
> #define IPI_IRQ 64
> @@ -282,6 +282,27 @@ static void xlnx_zynqmp_create_efuse(XlnxZynqMPState *s, qemu_irq *gic)
> sysbus_connect_irq(sbd, 0, gic[EFUSE_IRQ]);
> }
>
> +static void xlnx_zynqmp_create_apu_ctrl(XlnxZynqMPState *s, qemu_irq *gic)
> +{
> + SysBusDevice *sbd;
> + int i;
> +
> + object_initialize_child(OBJECT(s), "apu-ctrl", &s->apu_ctrl,
> + TYPE_XLNX_ZYNQMP_APU_CTRL);
> + sbd = SYS_BUS_DEVICE(&s->apu_ctrl);
> +
> + for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
> + g_autofree gchar *name = g_strdup_printf("cpu%d", i);
> +
> + object_property_set_link(OBJECT(&s->apu_ctrl), name,
> + OBJECT(&s->apu_cpu[i]), &error_abort);
> + }
> +
> + sysbus_realize(sbd, &error_fatal);
> + sysbus_mmio_map(sbd, 0, APU_ADDR);
> + sysbus_connect_irq(sbd, 0, gic[APU_IRQ]);
> +}
> +
> static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic)
> {
> SysBusDevice *sbd;
> @@ -301,7 +322,6 @@ static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
> hwaddr base;
> hwaddr size;
> } unimp_areas[ARRAY_SIZE(s->mr_unimp)] = {
> - { .name = "apu", APU_ADDR, APU_SIZE },
> { .name = "serdes", SERDES_ADDR, SERDES_SIZE },
> };
> unsigned int nr;
> @@ -697,6 +717,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
>
> xlnx_zynqmp_create_bbram(s, gic_spi);
> xlnx_zynqmp_create_efuse(s, gic_spi);
> + xlnx_zynqmp_create_apu_ctrl(s, gic_spi);
> xlnx_zynqmp_create_crf(s, gic_spi);
> xlnx_zynqmp_create_unimp_mmio(s);
>
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v1 3/6] hw/misc: Add a model of the Xilinx ZynqMP CRF
2022-01-31 15:35 ` Francisco Iglesias
@ 2022-01-31 17:27 ` Edgar E. Iglesias
2022-01-31 17:51 ` Edgar E. Iglesias
0 siblings, 1 reply; 26+ messages in thread
From: Edgar E. Iglesias @ 2022-01-31 17:27 UTC (permalink / raw)
To: Francisco Iglesias
Cc: peter.maydell, luc, sai.pavan.boddu, frasse.iglesias, alistair,
richard.henderson, qemu-devel, frederic.konrad, qemu-arm,
Edgar E. Iglesias
On Mon, Jan 31, 2022 at 03:35:57PM +0000, Francisco Iglesias wrote:
> Hi Edgar,
>
> A couple of minor comments below, looks good to me otherwise!
>
> On Mon, Jan 31, 2022 at 12:12:03AM +0100, Edgar E. Iglesias wrote:
> > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> >
> > Add a model of the Xilinx ZynqMP CRF. At the moment this
> > is mostly a stub model.
> >
> > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> > ---
> > include/hw/misc/xlnx-zynqmp-crf.h | 209 +++++++++++++++++++++++
> > hw/misc/xlnx-zynqmp-crf.c | 270 ++++++++++++++++++++++++++++++
> > hw/misc/meson.build | 1 +
> > 3 files changed, 480 insertions(+)
> > create mode 100644 include/hw/misc/xlnx-zynqmp-crf.h
> > create mode 100644 hw/misc/xlnx-zynqmp-crf.c
> >
> > diff --git a/include/hw/misc/xlnx-zynqmp-crf.h b/include/hw/misc/xlnx-zynqmp-crf.h
> > new file mode 100644
> > index 0000000000..b173ea4a08
> > --- /dev/null
> > +++ b/include/hw/misc/xlnx-zynqmp-crf.h
> > @@ -0,0 +1,209 @@
> > +/*
> > + * QEMU model of the CRF - Clock Reset FPD.
> > + *
> > + * Copyright (c) 2022 Xilinx Inc.
> > + * SPDX-License-Identifier: GPL-2.0-or-later
> > + * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> > + */
> > +
>
> Include guard seem to be missing:
>
> #ifndef XLNX_ZYNQMP_CRF_H
> #define XLNX_ZYNQMP_CRF_H
>
>
> > +#include "hw/sysbus.h"
> > +#include "hw/register.h"
> > +
> > +#define TYPE_XLNX_ZYNQMP_CRF "xlnx.zynqmp_crf"
> > +
> > +#define XILINX_CRF(obj) \
> > + OBJECT_CHECK(XlnxZynqMPCRF, (obj), TYPE_XLNX_ZYNQMP_CRF)
> > +
> > +REG32(ERR_CTRL, 0x0)
>
> (Optional but in case the these ones wont be used outside
> xlnx-zynqmp-crf.c we could consider placing them there).
Hi,
Yeah, I thought about that but the issue is with defining:
#define CRF_R_MAX (R_RST_DDR_SS + 1)
We could move these regdefs out and hardcode CRF_R_MAX, e.g:
#define CRF_R_MAX (0x108 / 4)
But that seems error-phrone.
The trade-off is keeping them here and pollute the name-space.
I already to rename one of these macros to avoid conflict...
Does someone have other ideas or preferences?
Cheers,
Edgar
....
> > +REG32(RST_DDR_SS, 0x108)
> > + FIELD(RST_DDR_SS, DDR_RESET, 3, 1)
> > + FIELD(RST_DDR_SS, APM_RESET, 2, 1)
> > +
> > +#define CRF_R_MAX (R_RST_DDR_SS + 1)
> > +
> > +typedef struct XlnxZynqMPCRF {
> > + SysBusDevice parent_obj;
> > + MemoryRegion iomem;
> > + qemu_irq irq_ir;
> > +
> > + RegisterInfoArray *reg_array;
> > + uint32_t regs[CRF_R_MAX];
> > + RegisterInfo regs_info[CRF_R_MAX];
> > +} XlnxZynqMPCRF;
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v1 1/6] hw/arm/xlnx-zynqmp: Add unimplemented SERDES area
2022-01-31 15:32 ` Peter Maydell
@ 2022-01-31 17:30 ` Edgar E. Iglesias
0 siblings, 0 replies; 26+ messages in thread
From: Edgar E. Iglesias @ 2022-01-31 17:30 UTC (permalink / raw)
To: Peter Maydell
Cc: luc, sai.pavan.boddu, frasse.iglesias, alistair,
richard.henderson, qemu-devel, francisco.iglesias,
frederic.konrad, qemu-arm, Edgar E. Iglesias
On Mon, Jan 31, 2022 at 03:32:25PM +0000, Peter Maydell wrote:
> On Sun, 30 Jan 2022 at 23:12, Edgar E. Iglesias
> <edgar.iglesias@gmail.com> wrote:
> >
> > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> >
> > Add unimplemented SERDES area.
>
> What's a SERDES ? A brief description might be helpful in
> the commit message or a comment.
These are config registers for the SER/DESerializers (for high-speed IO).
This patch was not strictly needed to pass the test-case but it came up I'm guessing due to some SW dependency in the test-case itself...
I'll add a comment and mention it in the commit message.
Thanks,
Edgar
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v1 3/6] hw/misc: Add a model of the Xilinx ZynqMP CRF
2022-01-31 17:27 ` Edgar E. Iglesias
@ 2022-01-31 17:51 ` Edgar E. Iglesias
0 siblings, 0 replies; 26+ messages in thread
From: Edgar E. Iglesias @ 2022-01-31 17:51 UTC (permalink / raw)
To: Edgar E. Iglesias
Cc: peter.maydell, luc, sai.pavan.boddu, frasse.iglesias, alistair,
richard.henderson, qemu-devel, Francisco Iglesias,
frederic.konrad, qemu-arm
On Mon, Jan 31, 2022 at 06:27:09PM +0100, Edgar E. Iglesias wrote:
> On Mon, Jan 31, 2022 at 03:35:57PM +0000, Francisco Iglesias wrote:
> > Hi Edgar,
> >
> > A couple of minor comments below, looks good to me otherwise!
> >
> > On Mon, Jan 31, 2022 at 12:12:03AM +0100, Edgar E. Iglesias wrote:
> > > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> > >
> > > Add a model of the Xilinx ZynqMP CRF. At the moment this
> > > is mostly a stub model.
> > >
> > > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> > > ---
> > > include/hw/misc/xlnx-zynqmp-crf.h | 209 +++++++++++++++++++++++
> > > hw/misc/xlnx-zynqmp-crf.c | 270 ++++++++++++++++++++++++++++++
> > > hw/misc/meson.build | 1 +
> > > 3 files changed, 480 insertions(+)
> > > create mode 100644 include/hw/misc/xlnx-zynqmp-crf.h
> > > create mode 100644 hw/misc/xlnx-zynqmp-crf.c
> > >
> > > diff --git a/include/hw/misc/xlnx-zynqmp-crf.h b/include/hw/misc/xlnx-zynqmp-crf.h
> > > new file mode 100644
> > > index 0000000000..b173ea4a08
> > > --- /dev/null
> > > +++ b/include/hw/misc/xlnx-zynqmp-crf.h
> > > @@ -0,0 +1,209 @@
> > > +/*
> > > + * QEMU model of the CRF - Clock Reset FPD.
> > > + *
> > > + * Copyright (c) 2022 Xilinx Inc.
> > > + * SPDX-License-Identifier: GPL-2.0-or-later
> > > + * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> > > + */
> > > +
> >
> > Include guard seem to be missing:
> >
> > #ifndef XLNX_ZYNQMP_CRF_H
> > #define XLNX_ZYNQMP_CRF_H
> >
> >
> > > +#include "hw/sysbus.h"
> > > +#include "hw/register.h"
> > > +
> > > +#define TYPE_XLNX_ZYNQMP_CRF "xlnx.zynqmp_crf"
> > > +
> > > +#define XILINX_CRF(obj) \
> > > + OBJECT_CHECK(XlnxZynqMPCRF, (obj), TYPE_XLNX_ZYNQMP_CRF)
> > > +
> > > +REG32(ERR_CTRL, 0x0)
> >
> > (Optional but in case the these ones wont be used outside
> > xlnx-zynqmp-crf.c we could consider placing them there).
>
>
> Hi,
>
> Yeah, I thought about that but the issue is with defining:
>
> #define CRF_R_MAX (R_RST_DDR_SS + 1)
>
> We could move these regdefs out and hardcode CRF_R_MAX, e.g:
> #define CRF_R_MAX (0x108 / 4)
>
> But that seems error-phrone.
> The trade-off is keeping them here and pollute the name-space.
> I already to rename one of these macros to avoid conflict...
>
> Does someone have other ideas or preferences?
I guess we could xlnx-zynqmp-crf.h:
#define CRF_R_MAX ((0x108 / 4) + 1)
and in xlnx-zynqmp-crf.c crf_init():
assert((R_RST_DDR_SS + 1) == CRF_R_MAX);
Or something along those lines...
>
> Cheers,
> Edgar
>
> ....
>
> > > +REG32(RST_DDR_SS, 0x108)
> > > + FIELD(RST_DDR_SS, DDR_RESET, 3, 1)
> > > + FIELD(RST_DDR_SS, APM_RESET, 2, 1)
> > > +
> > > +#define CRF_R_MAX (R_RST_DDR_SS + 1)
> > > +
> > > +typedef struct XlnxZynqMPCRF {
> > > + SysBusDevice parent_obj;
> > > + MemoryRegion iomem;
> > > + qemu_irq irq_ir;
> > > +
> > > + RegisterInfoArray *reg_array;
> > > + uint32_t regs[CRF_R_MAX];
> > > + RegisterInfo regs_info[CRF_R_MAX];
> > > +} XlnxZynqMPCRF;
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v1 5/6] hw/misc: Add a model of the Xilinx ZynqMP APU Control
2022-01-31 12:17 ` Edgar E. Iglesias
@ 2022-01-31 23:21 ` Philippe Mathieu-Daudé via
0 siblings, 0 replies; 26+ messages in thread
From: Philippe Mathieu-Daudé via @ 2022-01-31 23:21 UTC (permalink / raw)
To: Edgar E. Iglesias
Cc: qemu-devel, edgar.iglesias, peter.maydell, luc, sai.pavan.boddu,
frasse.iglesias, alistair, richard.henderson, francisco.iglesias,
frederic.konrad, qemu-arm
On 31/1/22 13:17, Edgar E. Iglesias wrote:
> On Mon, Jan 31, 2022 at 12:35:54AM +0100, Philippe Mathieu-Daudé wrote:
>> On 31/1/22 00:12, Edgar E. Iglesias wrote:
>>> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>>>
>>> Add a model of the Xilinx ZynqMP APU Control.
>>>
>>> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
>>> ---
>>> include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 91 +++++++++
>>> hw/misc/xlnx-zynqmp-apu-ctrl.c | 257 +++++++++++++++++++++++++
>>> hw/misc/meson.build | 1 +
>>> 3 files changed, 349 insertions(+)
>>> create mode 100644 include/hw/misc/xlnx-zynqmp-apu-ctrl.h
>>> create mode 100644 hw/misc/xlnx-zynqmp-apu-ctrl.c
>>> +
>>> +#define NUM_CPUS 4
>>
>> Hmm isn't it APU_MAX_CPU?
>>
>
>
> Thanks Philippe. Yes, this was a little confusing. The values happen to be the
> same but they belong to different models. For example, the apu-ctrl model will be
> reused in Versal.
>
> Anyways, for v2 I've renamed the macros to CRF_MAX_CPU and APU_MAX_CPU respectevly.
> I hope that makes things clearer.
Thanks!
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v1 2/6] target/arm: Make rvbar settable after realize
2022-01-30 23:12 ` [PATCH v1 2/6] target/arm: Make rvbar settable after realize Edgar E. Iglesias
@ 2022-02-03 20:21 ` Luc Michel
0 siblings, 0 replies; 26+ messages in thread
From: Luc Michel @ 2022-02-03 20:21 UTC (permalink / raw)
To: Edgar E. Iglesias
Cc: edgar.iglesias, peter.maydell, sai.pavan.boddu, frasse.iglesias,
alistair, richard.henderson, qemu-devel, francisco.iglesias,
frederic.konrad, qemu-arm
Hi Edgar,
On 00:12 Mon 31 Jan , Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Make the rvbar property settable after realize. This is done
> in preparation to model the ZynqMP's runtime configurable rvbar.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
> target/arm/cpu.c | 7 +++----
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 5a9c02a256..e30ae088fe 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -1128,9 +1128,6 @@ static Property arm_cpu_reset_cbar_property =
> static Property arm_cpu_reset_hivecs_property =
> DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
>
> -static Property arm_cpu_rvbar_property =
> - DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
> -
> #ifndef CONFIG_USER_ONLY
> static Property arm_cpu_has_el2_property =
> DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true);
> @@ -1233,7 +1230,9 @@ void arm_cpu_post_init(Object *obj)
> }
>
> if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
> - qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property);
> + object_property_add_uint64_ptr(obj, "rvbar",
> + &cpu->rvbar,
> + OBJ_PROP_FLAG_READWRITE);
I think you may have a problem here. cpu->rvbar is used to define the
reset value of the rvbar_elx registers in register_cp_regs_for_features.
This is done at realize time. Changing the rvbar property after realize
would fail to update the rvbar_elx register values.
I guess you should also switch to a .readfn instead of a .resetvalue for
those registers.
--
Luc
> }
>
> #ifndef CONFIG_USER_ONLY
> --
> 2.25.1
>
--
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v1 4/6] hw/arm/xlnx-zynqmp: Connect the ZynqMP CRF
2022-01-30 23:12 ` [PATCH v1 4/6] hw/arm/xlnx-zynqmp: Connect the " Edgar E. Iglesias
2022-01-30 23:33 ` Philippe Mathieu-Daudé via
2022-01-31 15:37 ` Francisco Iglesias
@ 2022-02-03 20:23 ` Luc Michel
2 siblings, 0 replies; 26+ messages in thread
From: Luc Michel @ 2022-02-03 20:23 UTC (permalink / raw)
To: Edgar E. Iglesias
Cc: edgar.iglesias, peter.maydell, sai.pavan.boddu, frasse.iglesias,
alistair, richard.henderson, qemu-devel, francisco.iglesias,
frederic.konrad, qemu-arm
On 00:12 Mon 31 Jan , Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Connect the ZynqMP CRF - Clock Reset FPD device.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> include/hw/arm/xlnx-zynqmp.h | 2 ++
> hw/arm/xlnx-zynqmp.c | 16 ++++++++++++++++
> 2 files changed, 18 insertions(+)
>
> diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
> index 99ceb8a609..d5a3ad3df2 100644
> --- a/include/hw/arm/xlnx-zynqmp.h
> +++ b/include/hw/arm/xlnx-zynqmp.h
> @@ -38,6 +38,7 @@
> #include "hw/dma/xlnx_csu_dma.h"
> #include "hw/nvram/xlnx-bbram.h"
> #include "hw/nvram/xlnx-zynqmp-efuse.h"
> +#include "hw/misc/xlnx-zynqmp-crf.h"
>
> #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
> OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
> @@ -122,6 +123,7 @@ struct XlnxZynqMPState {
> XlnxZDMA gdma[XLNX_ZYNQMP_NUM_GDMA_CH];
> XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH];
> XlnxCSUDMA qspi_dma;
> + XlnxZynqMPCRF crf;
>
> char *boot_cpu;
> ARMCPU *boot_cpu_ptr;
> diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
> index ba44e95899..857d3c9636 100644
> --- a/hw/arm/xlnx-zynqmp.c
> +++ b/hw/arm/xlnx-zynqmp.c
> @@ -51,6 +51,9 @@
> #define QSPI_IRQ 15
> #define QSPI_DMA_ADDR 0xff0f0800
>
> +#define CRF_ADDR 0xfd1a0000
> +#define CRF_IRQ 120
> +
> #define SERDES_ADDR 0xfd400000
> #define SERDES_SIZE 0x20000
>
> @@ -279,6 +282,18 @@ static void xlnx_zynqmp_create_efuse(XlnxZynqMPState *s, qemu_irq *gic)
> sysbus_connect_irq(sbd, 0, gic[EFUSE_IRQ]);
> }
>
> +static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic)
> +{
> + SysBusDevice *sbd;
> +
> + object_initialize_child(OBJECT(s), "crf", &s->crf, TYPE_XLNX_ZYNQMP_CRF);
> + sbd = SYS_BUS_DEVICE(&s->crf);
> +
> + sysbus_realize(sbd, &error_fatal);
> + sysbus_mmio_map(sbd, 0, CRF_ADDR);
> + sysbus_connect_irq(sbd, 0, gic[CRF_IRQ]);
> +}
> +
> static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
> {
> static const struct UnimpInfo {
> @@ -682,6 +697,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
>
> xlnx_zynqmp_create_bbram(s, gic_spi);
> xlnx_zynqmp_create_efuse(s, gic_spi);
> + xlnx_zynqmp_create_crf(s, gic_spi);
> xlnx_zynqmp_create_unimp_mmio(s);
>
> for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
> --
> 2.25.1
>
--
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v1 6/6] hw/arm/xlnx-zynqmp: Connect the ZynqMP APU Control
2022-01-30 23:12 ` [PATCH v1 6/6] hw/arm/xlnx-zynqmp: Connect the " Edgar E. Iglesias
2022-01-30 23:37 ` Philippe Mathieu-Daudé via
2022-01-31 15:48 ` Francisco Iglesias
@ 2022-02-03 20:26 ` Luc Michel
2 siblings, 0 replies; 26+ messages in thread
From: Luc Michel @ 2022-02-03 20:26 UTC (permalink / raw)
To: Edgar E. Iglesias
Cc: edgar.iglesias, peter.maydell, sai.pavan.boddu, frasse.iglesias,
alistair, richard.henderson, qemu-devel, francisco.iglesias,
frederic.konrad, qemu-arm
On 00:12 Mon 31 Jan , Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Connect the ZynqMP APU Control device.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> include/hw/arm/xlnx-zynqmp.h | 4 +++-
> hw/arm/xlnx-zynqmp.c | 25 +++++++++++++++++++++++--
> 2 files changed, 26 insertions(+), 3 deletions(-)
>
> diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
> index d5a3ad3df2..05cd2128f3 100644
> --- a/include/hw/arm/xlnx-zynqmp.h
> +++ b/include/hw/arm/xlnx-zynqmp.h
> @@ -38,6 +38,7 @@
> #include "hw/dma/xlnx_csu_dma.h"
> #include "hw/nvram/xlnx-bbram.h"
> #include "hw/nvram/xlnx-zynqmp-efuse.h"
> +#include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
> #include "hw/misc/xlnx-zynqmp-crf.h"
>
> #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
> @@ -85,7 +86,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
> /*
> * Unimplemented mmio regions needed to boot some images.
> */
> -#define XLNX_ZYNQMP_NUM_UNIMP_AREAS 2
> +#define XLNX_ZYNQMP_NUM_UNIMP_AREAS 1
>
> struct XlnxZynqMPState {
> /*< private >*/
> @@ -123,6 +124,7 @@ struct XlnxZynqMPState {
> XlnxZDMA gdma[XLNX_ZYNQMP_NUM_GDMA_CH];
> XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH];
> XlnxCSUDMA qspi_dma;
> + XlnxZynqMPAPUCtrl apu_ctrl;
> XlnxZynqMPCRF crf;
>
> char *boot_cpu;
> diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
> index 857d3c9636..21c411cd77 100644
> --- a/hw/arm/xlnx-zynqmp.c
> +++ b/hw/arm/xlnx-zynqmp.c
> @@ -64,7 +64,7 @@
> #define DPDMA_IRQ 116
>
> #define APU_ADDR 0xfd5c0000
> -#define APU_SIZE 0x100
> +#define APU_IRQ 153
>
> #define IPI_ADDR 0xFF300000
> #define IPI_IRQ 64
> @@ -282,6 +282,27 @@ static void xlnx_zynqmp_create_efuse(XlnxZynqMPState *s, qemu_irq *gic)
> sysbus_connect_irq(sbd, 0, gic[EFUSE_IRQ]);
> }
>
> +static void xlnx_zynqmp_create_apu_ctrl(XlnxZynqMPState *s, qemu_irq *gic)
> +{
> + SysBusDevice *sbd;
> + int i;
> +
> + object_initialize_child(OBJECT(s), "apu-ctrl", &s->apu_ctrl,
> + TYPE_XLNX_ZYNQMP_APU_CTRL);
> + sbd = SYS_BUS_DEVICE(&s->apu_ctrl);
> +
> + for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
> + g_autofree gchar *name = g_strdup_printf("cpu%d", i);
> +
> + object_property_set_link(OBJECT(&s->apu_ctrl), name,
> + OBJECT(&s->apu_cpu[i]), &error_abort);
> + }
> +
> + sysbus_realize(sbd, &error_fatal);
> + sysbus_mmio_map(sbd, 0, APU_ADDR);
> + sysbus_connect_irq(sbd, 0, gic[APU_IRQ]);
> +}
> +
> static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic)
> {
> SysBusDevice *sbd;
> @@ -301,7 +322,6 @@ static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
> hwaddr base;
> hwaddr size;
> } unimp_areas[ARRAY_SIZE(s->mr_unimp)] = {
> - { .name = "apu", APU_ADDR, APU_SIZE },
> { .name = "serdes", SERDES_ADDR, SERDES_SIZE },
> };
> unsigned int nr;
> @@ -697,6 +717,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
>
> xlnx_zynqmp_create_bbram(s, gic_spi);
> xlnx_zynqmp_create_efuse(s, gic_spi);
> + xlnx_zynqmp_create_apu_ctrl(s, gic_spi);
> xlnx_zynqmp_create_crf(s, gic_spi);
> xlnx_zynqmp_create_unimp_mmio(s);
>
> --
> 2.25.1
>
--
^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2022-02-03 21:33 UTC | newest]
Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-01-30 23:12 [PATCH v1 0/6] hw/arm: zynqmp: Add CRF and APU control to support PSCI Edgar E. Iglesias
2022-01-30 23:12 ` [PATCH v1 1/6] hw/arm/xlnx-zynqmp: Add unimplemented SERDES area Edgar E. Iglesias
2022-01-30 23:37 ` Philippe Mathieu-Daudé via
2022-01-31 15:21 ` Francisco Iglesias
2022-01-31 15:32 ` Peter Maydell
2022-01-31 17:30 ` Edgar E. Iglesias
2022-01-30 23:12 ` [PATCH v1 2/6] target/arm: Make rvbar settable after realize Edgar E. Iglesias
2022-02-03 20:21 ` Luc Michel
2022-01-30 23:12 ` [PATCH v1 3/6] hw/misc: Add a model of the Xilinx ZynqMP CRF Edgar E. Iglesias
2022-01-30 23:32 ` Philippe Mathieu-Daudé via
2022-01-31 15:35 ` Francisco Iglesias
2022-01-31 17:27 ` Edgar E. Iglesias
2022-01-31 17:51 ` Edgar E. Iglesias
2022-01-30 23:12 ` [PATCH v1 4/6] hw/arm/xlnx-zynqmp: Connect the " Edgar E. Iglesias
2022-01-30 23:33 ` Philippe Mathieu-Daudé via
2022-01-31 15:37 ` Francisco Iglesias
2022-02-03 20:23 ` Luc Michel
2022-01-30 23:12 ` [PATCH v1 5/6] hw/misc: Add a model of the Xilinx ZynqMP APU Control Edgar E. Iglesias
2022-01-30 23:35 ` Philippe Mathieu-Daudé via
2022-01-31 12:17 ` Edgar E. Iglesias
2022-01-31 23:21 ` Philippe Mathieu-Daudé via
2022-01-31 15:46 ` Francisco Iglesias
2022-01-30 23:12 ` [PATCH v1 6/6] hw/arm/xlnx-zynqmp: Connect the " Edgar E. Iglesias
2022-01-30 23:37 ` Philippe Mathieu-Daudé via
2022-01-31 15:48 ` Francisco Iglesias
2022-02-03 20:26 ` Luc Michel
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