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From: Philipp Tomsich <philipp.tomsich@vrull.eu>
To: qemu-devel@nongnu.org
Cc: Richard Henderson <richard.henderson@linaro.org>,
	Kito Cheng <kito.cheng@sifive.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	Greg Favor <gfavor@ventanamicro.com>,
	Philipp Tomsich <philipp.tomsich@vrull.eu>
Subject: [PATCH v6 4/7] target/riscv: access cfg structure through DisasContext
Date: Wed,  2 Feb 2022 01:52:46 +0100	[thread overview]
Message-ID: <20220202005249.3566542-5-philipp.tomsich@vrull.eu> (raw)
In-Reply-To: <20220202005249.3566542-1-philipp.tomsich@vrull.eu>

The Zb[abcs] support code still uses the RISCV_CPU macros to access
the configuration information (i.e., check whether an extension is
available/enabled).  Now that we provide this information directly
from DisasContext, we can access this directly via the cfg_ptr field.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

---

(no changes since v3)

Changes in v3:
- (new patch) change Zb[abcs] implementation to use cfg_ptr (copied
  into DisasContext) instead of going throuhg RISCV_CPU

 target/riscv/insn_trans/trans_rvb.c.inc | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 810431a1d6..f9bd3b7ec4 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -19,25 +19,25 @@
  */
 
 #define REQUIRE_ZBA(ctx) do {                    \
-    if (!RISCV_CPU(ctx->cs)->cfg.ext_zba) {      \
+    if (ctx->cfg_ptr->ext_zba) {                 \
         return false;                            \
     }                                            \
 } while (0)
 
 #define REQUIRE_ZBB(ctx) do {                    \
-    if (!RISCV_CPU(ctx->cs)->cfg.ext_zbb) {      \
+    if (ctx->cfg_ptr->ext_zbb) {                 \
         return false;                            \
     }                                            \
 } while (0)
 
 #define REQUIRE_ZBC(ctx) do {                    \
-    if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) {      \
+    if (ctx->cfg_ptr->ext_zbc) {                 \
         return false;                            \
     }                                            \
 } while (0)
 
 #define REQUIRE_ZBS(ctx) do {                    \
-    if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) {      \
+    if (ctx->cfg_ptr->ext_zbs) {                 \
         return false;                            \
     }                                            \
 } while (0)
-- 
2.33.1



  parent reply	other threads:[~2022-02-02  4:18 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-02  0:52 [PATCH v6 0/7] target/riscv: Add XVentanaCondOps and supporting infrastructure changes Philipp Tomsich
2022-02-02  0:52 ` [PATCH v6 1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' Philipp Tomsich
2022-02-02  0:52 ` [PATCH v6 2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr Philipp Tomsich
2022-02-02  0:52 ` [PATCH v6 3/7] target/riscv: access configuration through cfg_ptr in DisasContext Philipp Tomsich
2022-02-08  6:07   ` Alistair Francis
2022-02-08  6:28     ` Alistair Francis
2022-02-02  0:52 ` Philipp Tomsich [this message]
2022-02-02  0:52 ` [PATCH v6 5/7] target/riscv: iterate over a table of decoders Philipp Tomsich
2022-02-02  0:52 ` [PATCH v6 6/7] target/riscv: Add XVentanaCondOps custom extension Philipp Tomsich
2022-02-02  0:52 ` [PATCH v6 7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps Philipp Tomsich
2022-02-02  6:36 ` [PATCH v6 0/7] target/riscv: Add XVentanaCondOps and supporting infrastructure changes Alistair Francis
2022-02-03 15:30   ` Philipp Tomsich

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