From: Philipp Tomsich <philipp.tomsich@vrull.eu>
To: qemu-devel@nongnu.org
Cc: Richard Henderson <richard.henderson@linaro.org>,
Kito Cheng <kito.cheng@sifive.com>,
Alistair Francis <alistair.francis@wdc.com>,
Greg Favor <gfavor@ventanamicro.com>,
Philipp Tomsich <philipp.tomsich@vrull.eu>
Subject: [PATCH v6 7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps
Date: Wed, 2 Feb 2022 01:52:49 +0100 [thread overview]
Message-ID: <20220202005249.3566542-8-philipp.tomsich@vrull.eu> (raw)
In-Reply-To: <20220202005249.3566542-1-philipp.tomsich@vrull.eu>
The XVentanaCondOps extension is supported by VRULL on behalf of the
Ventana Micro. Add myself as a point-of-contact.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v3)
Changes in v3:
- add a MAINTAINERS entry for XVentanaCondOps
MAINTAINERS | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index b43344fa98..2e0b2ae947 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -286,6 +286,13 @@ F: include/hw/riscv/
F: linux-user/host/riscv32/
F: linux-user/host/riscv64/
+RISC-V XVentanaCondOps extension
+M: Philipp Tomsich <philipp.tomsich@vrull.eu>
+L: qemu-riscv@nongnu.org
+S: Supported
+F: target/riscv/XVentanaCondOps.decode
+F: target/riscv/insn_trans/trans_xventanacondops.c.inc
+
RENESAS RX CPUs
R: Yoshinori Sato <ysato@users.sourceforge.jp>
S: Orphan
--
2.33.1
next prev parent reply other threads:[~2022-02-02 2:50 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-02 0:52 [PATCH v6 0/7] target/riscv: Add XVentanaCondOps and supporting infrastructure changes Philipp Tomsich
2022-02-02 0:52 ` [PATCH v6 1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' Philipp Tomsich
2022-02-02 0:52 ` [PATCH v6 2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr Philipp Tomsich
2022-02-02 0:52 ` [PATCH v6 3/7] target/riscv: access configuration through cfg_ptr in DisasContext Philipp Tomsich
2022-02-08 6:07 ` Alistair Francis
2022-02-08 6:28 ` Alistair Francis
2022-02-02 0:52 ` [PATCH v6 4/7] target/riscv: access cfg structure through DisasContext Philipp Tomsich
2022-02-02 0:52 ` [PATCH v6 5/7] target/riscv: iterate over a table of decoders Philipp Tomsich
2022-02-02 0:52 ` [PATCH v6 6/7] target/riscv: Add XVentanaCondOps custom extension Philipp Tomsich
2022-02-02 0:52 ` Philipp Tomsich [this message]
2022-02-02 6:36 ` [PATCH v6 0/7] target/riscv: Add XVentanaCondOps and supporting infrastructure changes Alistair Francis
2022-02-03 15:30 ` Philipp Tomsich
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