* [PATCH v4 0/4] Use drm_clflush* instead of clflush
@ 2022-02-03 17:29 Michael Cheng
2022-02-03 17:29 ` [PATCH v4 1/4] drm/i915/gt: Re-work intel_write_status_page Michael Cheng
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Michael Cheng @ 2022-02-03 17:29 UTC (permalink / raw)
To: gfx-internal-devel
Cc: tvrtko.ursulin, michael.cheng, wayne.boyer, casey.g.bowman,
lucas.demarchi, dri-devel
This patch series re-work a few i915 functions to use drm_clflush_virt_range
instead of calling clflush or clflushopt directly. This will prevent errors
when building for non-x86 architectures.
v2: s/PAGE_SIZE/sizeof(value) for Re-work intel_write_status_page and added
more patches to convert additional clflush/clflushopt to use drm_clflush*.
(Michael Cheng)
v3: Drop invalidate_csb_entries and directly invoke drm_clflush_virt_ran
v4: Remove extra memory barriers
Michael Cheng (4):
drm/i915/gt: Re-work intel_write_status_page
drm/i915/gt: Drop invalidate_csb_entries
drm/i915/gt: Re-work reset_csb
drm/i915/: Re-work clflush_write32
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-----
drivers/gpu/drm/i915/gt/intel_engine.h | 13 ++++---------
.../drm/i915/gt/intel_execlists_submission.c | 17 +++++------------
3 files changed, 12 insertions(+), 26 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v4 1/4] drm/i915/gt: Re-work intel_write_status_page
2022-02-03 17:29 [PATCH v4 0/4] Use drm_clflush* instead of clflush Michael Cheng
@ 2022-02-03 17:29 ` Michael Cheng
2022-02-03 17:29 ` [PATCH v4 2/4] drm/i915/gt: Drop invalidate_csb_entries Michael Cheng
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Michael Cheng @ 2022-02-03 17:29 UTC (permalink / raw)
To: gfx-internal-devel
Cc: tvrtko.ursulin, michael.cheng, wayne.boyer, casey.g.bowman,
lucas.demarchi, dri-devel
Re-work intel_write_status_page to use drm_clflush_virt_range. This
will prevent compiler errors when building for non-x86 architectures.
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine.h | 13 ++++---------
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index 0e353d8c2bc8..986777c2430d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -4,6 +4,7 @@
#include <asm/cacheflush.h>
#include <drm/drm_util.h>
+#include <drm/drm_cache.h>
#include <linux/hashtable.h>
#include <linux/irq_work.h>
@@ -143,15 +144,9 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
* of extra paranoia to try and ensure that the HWS takes the value
* we give and that it doesn't end up trapped inside the CPU!
*/
- if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
- mb();
- clflush(&engine->status_page.addr[reg]);
- engine->status_page.addr[reg] = value;
- clflush(&engine->status_page.addr[reg]);
- mb();
- } else {
- WRITE_ONCE(engine->status_page.addr[reg], value);
- }
+ drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value));
+ WRITE_ONCE(engine->status_page.addr[reg], value);
+ drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value));
}
/*
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v4 2/4] drm/i915/gt: Drop invalidate_csb_entries
2022-02-03 17:29 [PATCH v4 0/4] Use drm_clflush* instead of clflush Michael Cheng
2022-02-03 17:29 ` [PATCH v4 1/4] drm/i915/gt: Re-work intel_write_status_page Michael Cheng
@ 2022-02-03 17:29 ` Michael Cheng
2022-02-03 17:29 ` [PATCH v4 3/4] drm/i915/gt: Re-work reset_csb Michael Cheng
2022-02-03 17:29 ` [PATCH v4 4/4] drm/i915/: Re-work clflush_write32 Michael Cheng
3 siblings, 0 replies; 6+ messages in thread
From: Michael Cheng @ 2022-02-03 17:29 UTC (permalink / raw)
To: gfx-internal-devel
Cc: tvrtko.ursulin, michael.cheng, wayne.boyer, casey.g.bowman,
lucas.demarchi, dri-devel
Drop invalidate_csb_entries and directly call drm_clflush_virt_range.
This allows for one less function call, and prevent complier errors when
building for non-x86 architectures.
v2(Michael Cheng): Drop invalidate_csb_entries function and directly
invoke drm_clflush_virt_range. Thanks to Tvrtko for the
sugguestion.
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 12 +++---------
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 9bb7c863172f..7500c06562da 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1646,12 +1646,6 @@ cancel_port_requests(struct intel_engine_execlists * const execlists,
return inactive;
}
-static void invalidate_csb_entries(const u64 *first, const u64 *last)
-{
- clflush((void *)first);
- clflush((void *)last);
-}
-
/*
* Starting with Gen12, the status has a new format:
*
@@ -1999,7 +1993,7 @@ process_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
* the wash as hardware, working or not, will need to do the
* invalidation before.
*/
- invalidate_csb_entries(&buf[0], &buf[num_entries - 1]);
+ drm_clflush_virt_range(&buf[0], num_entries * sizeof(buf[0]));
/*
* We assume that any event reflects a change in context flow
@@ -2783,8 +2777,8 @@ static void reset_csb_pointers(struct intel_engine_cs *engine)
/* Check that the GPU does indeed update the CSB entries! */
memset(execlists->csb_status, -1, (reset_value + 1) * sizeof(u64));
- invalidate_csb_entries(&execlists->csb_status[0],
- &execlists->csb_status[reset_value]);
+ drm_clflush_virt_range(&execlists->csb_status[0],
+ sizeof(&execlists->csb_status[reset_value]));
/* Once more for luck and our trusty paranoia */
ENGINE_WRITE(engine, RING_CONTEXT_STATUS_PTR,
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v4 3/4] drm/i915/gt: Re-work reset_csb
2022-02-03 17:29 [PATCH v4 0/4] Use drm_clflush* instead of clflush Michael Cheng
2022-02-03 17:29 ` [PATCH v4 1/4] drm/i915/gt: Re-work intel_write_status_page Michael Cheng
2022-02-03 17:29 ` [PATCH v4 2/4] drm/i915/gt: Drop invalidate_csb_entries Michael Cheng
@ 2022-02-03 17:29 ` Michael Cheng
2022-02-03 17:29 ` [PATCH v4 4/4] drm/i915/: Re-work clflush_write32 Michael Cheng
3 siblings, 0 replies; 6+ messages in thread
From: Michael Cheng @ 2022-02-03 17:29 UTC (permalink / raw)
To: gfx-internal-devel
Cc: tvrtko.ursulin, michael.cheng, wayne.boyer, casey.g.bowman,
lucas.demarchi, dri-devel
Use drm_clflush_virt_range instead of directly invoking clflush. This
will prevent compiler errors when building for non-x86 architectures.
v2(Michael Cheng): Remove extra clflush
v3(Michael Cheng): Remove memory barrier since drm_clflush_virt_range
takes care of it.
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 7500c06562da..22505aa428d9 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2944,9 +2944,8 @@ reset_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
- mb(); /* paranoia: read the CSB pointers from after the reset */
- clflush(execlists->csb_write);
- mb();
+ drm_clflush_virt_range(execlists->csb_write,
+ sizeof(execlists->csb_write));
inactive = process_csb(engine, inactive); /* drain preemption events */
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v4 4/4] drm/i915/: Re-work clflush_write32
2022-02-03 17:29 [PATCH v4 0/4] Use drm_clflush* instead of clflush Michael Cheng
` (2 preceding siblings ...)
2022-02-03 17:29 ` [PATCH v4 3/4] drm/i915/gt: Re-work reset_csb Michael Cheng
@ 2022-02-03 17:29 ` Michael Cheng
3 siblings, 0 replies; 6+ messages in thread
From: Michael Cheng @ 2022-02-03 17:29 UTC (permalink / raw)
To: gfx-internal-devel
Cc: tvrtko.ursulin, michael.cheng, wayne.boyer, casey.g.bowman,
lucas.demarchi, dri-devel
Use drm_clflush_virt_range instead of clflushopt and remove the memory
barrier, since drm_clflush_virt_range takes care of that.
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 498b458fd784..0854276ff7ba 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1332,10 +1332,8 @@ static void *reloc_vaddr(struct i915_vma *vma,
static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
{
if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
- if (flushes & CLFLUSH_BEFORE) {
- clflushopt(addr);
- mb();
- }
+ if (flushes & CLFLUSH_BEFORE)
+ drm_clflush_virt_range(addr, sizeof(addr));
*addr = value;
@@ -1347,7 +1345,7 @@ static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
* to ensure ordering of clflush wrt to the system.
*/
if (flushes & CLFLUSH_AFTER)
- clflushopt(addr);
+ drm_clflush_virt_range(addr, sizeof(addr));
} else
*addr = value;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v4 4/4] drm/i915/: Re-work clflush_write32
2022-02-03 20:03 [PATCH v4 0/4] Use drm_clflush* instead of clflush Michael Cheng
@ 2022-02-03 20:04 ` Michael Cheng
0 siblings, 0 replies; 6+ messages in thread
From: Michael Cheng @ 2022-02-03 20:04 UTC (permalink / raw)
To: intel-gfx
Cc: tvrtko.ursulin, michael.cheng, wayne.boyer, casey.g.bowman,
lucas.demarchi, dri-devel
Use drm_clflush_virt_range instead of clflushopt and remove the memory
barrier, since drm_clflush_virt_range takes care of that.
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 498b458fd784..0854276ff7ba 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1332,10 +1332,8 @@ static void *reloc_vaddr(struct i915_vma *vma,
static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
{
if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
- if (flushes & CLFLUSH_BEFORE) {
- clflushopt(addr);
- mb();
- }
+ if (flushes & CLFLUSH_BEFORE)
+ drm_clflush_virt_range(addr, sizeof(addr));
*addr = value;
@@ -1347,7 +1345,7 @@ static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
* to ensure ordering of clflush wrt to the system.
*/
if (flushes & CLFLUSH_AFTER)
- clflushopt(addr);
+ drm_clflush_virt_range(addr, sizeof(addr));
} else
*addr = value;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-02-03 20:04 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-02-03 17:29 [PATCH v4 0/4] Use drm_clflush* instead of clflush Michael Cheng
2022-02-03 17:29 ` [PATCH v4 1/4] drm/i915/gt: Re-work intel_write_status_page Michael Cheng
2022-02-03 17:29 ` [PATCH v4 2/4] drm/i915/gt: Drop invalidate_csb_entries Michael Cheng
2022-02-03 17:29 ` [PATCH v4 3/4] drm/i915/gt: Re-work reset_csb Michael Cheng
2022-02-03 17:29 ` [PATCH v4 4/4] drm/i915/: Re-work clflush_write32 Michael Cheng
2022-02-03 20:03 [PATCH v4 0/4] Use drm_clflush* instead of clflush Michael Cheng
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