* [PATCH] ARM: dts: imx7: Move PCIe out of AIPS3
@ 2022-02-07 15:25 Marek Vasut
2022-02-13 1:50 ` Shawn Guo
0 siblings, 1 reply; 2+ messages in thread
From: Marek Vasut @ 2022-02-07 15:25 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Marek Vasut, Fabio Estevam, Peng Fan, Richard Zhu, Shawn Guo, linux-imx
The AIPS3 on iMX7 is at 0x30800000 and is 0x400000 long, the PCIe IP
is not part of this AIPS range. Move it to /soc node.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: linux-imx@nxp.com
---
arch/arm/boot/dts/imx7d.dtsi | 86 ++++++++++++++++++------------------
1 file changed, 43 insertions(+), 43 deletions(-)
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi
index b7735979b7e4c..f8cba47536a0e 100644
--- a/arch/arm/boot/dts/imx7d.dtsi
+++ b/arch/arm/boot/dts/imx7d.dtsi
@@ -113,6 +113,49 @@ intc: interrupt-controller@31001000 {
<0x31004000 0x2000>,
<0x31006000 0x2000>;
};
+
+ pcie: pcie@33800000 {
+ compatible = "fsl,imx7d-pcie";
+ reg = <0x33800000 0x4000>,
+ <0x4ff00000 0x80000>;
+ reg-names = "dbi", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x00 0xff>;
+ ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000>, /* downstream I/O */
+ <0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
+ num-lanes = <1>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ /*
+ * Reference manual lists pci irqs incorrectly
+ * Real hardware ordering is same as imx6: D+MSI, C, B, A
+ */
+ interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>,
+ <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,
+ <&clks IMX7D_PCIE_PHY_ROOT_CLK>;
+ clock-names = "pcie", "pcie_bus", "pcie_phy";
+ assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>,
+ <&clks IMX7D_PCIE_PHY_ROOT_SRC>;
+ assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
+ <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+
+ fsl,max-link-speed = <2>;
+ power-domains = <&pgc_pcie_phy>;
+ resets = <&src IMX7_RESET_PCIEPHY>,
+ <&src IMX7_RESET_PCIE_CTRL_APPS_EN>,
+ <&src IMX7_RESET_PCIE_CTRL_APPS_TURNOFF>;
+ reset-names = "pciephy", "apps", "turnoff";
+ fsl,imx7d-pcie-phy = <&pcie_phy>;
+ status = "disabled";
+ };
};
};
@@ -162,49 +205,6 @@ fec2: ethernet@30bf0000 {
fsl,stop-mode = <&gpr 0x10 4>;
status = "disabled";
};
-
- pcie: pcie@33800000 {
- compatible = "fsl,imx7d-pcie";
- reg = <0x33800000 0x4000>,
- <0x4ff00000 0x80000>;
- reg-names = "dbi", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- bus-range = <0x00 0xff>;
- ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000>, /* downstream I/O */
- <0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
- num-lanes = <1>;
- interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0x7>;
- /*
- * Reference manual lists pci irqs incorrectly
- * Real hardware ordering is same as imx6: D+MSI, C, B, A
- */
- interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>,
- <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,
- <&clks IMX7D_PCIE_PHY_ROOT_CLK>;
- clock-names = "pcie", "pcie_bus", "pcie_phy";
- assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>,
- <&clks IMX7D_PCIE_PHY_ROOT_SRC>;
- assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
- <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
-
- fsl,max-link-speed = <2>;
- power-domains = <&pgc_pcie_phy>;
- resets = <&src IMX7_RESET_PCIEPHY>,
- <&src IMX7_RESET_PCIE_CTRL_APPS_EN>,
- <&src IMX7_RESET_PCIE_CTRL_APPS_TURNOFF>;
- reset-names = "pciephy", "apps", "turnoff";
- fsl,imx7d-pcie-phy = <&pcie_phy>;
- status = "disabled";
- };
};
&ca_funnel_in_ports {
--
2.34.1
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^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] ARM: dts: imx7: Move PCIe out of AIPS3
2022-02-07 15:25 [PATCH] ARM: dts: imx7: Move PCIe out of AIPS3 Marek Vasut
@ 2022-02-13 1:50 ` Shawn Guo
0 siblings, 0 replies; 2+ messages in thread
From: Shawn Guo @ 2022-02-13 1:50 UTC (permalink / raw)
To: Marek Vasut
Cc: linux-arm-kernel, Fabio Estevam, Peng Fan, Richard Zhu, linux-imx
On Mon, Feb 07, 2022 at 04:25:08PM +0100, Marek Vasut wrote:
> The AIPS3 on iMX7 is at 0x30800000 and is 0x400000 long, the PCIe IP
> is not part of this AIPS range. Move it to /soc node.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Richard Zhu <hongxing.zhu@nxp.com>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: linux-imx@nxp.com
Applied, thanks!
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 2+ messages in thread
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2022-02-13 1:50 ` Shawn Guo
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