[PATCH v8 0/4] Add Naneng combo PHY support for RK3568

[PATCH v8 0/4] Add Naneng combo PHY support for RK3568

[Yifeng Zhao]

This phy can be used as pcie-phy, usb3-phy, sata-phy or sgmii-phy.

Changes in v8:
- rename 'mode' to 'type'
- using devm_reset_control_array_get_exclusive
- move rockchip_combphy_set_mode into rockchip_combphy_init

Changes in v7:
- remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel
- rename regs

Changes in v5:
- modify description for ssc and ext-refclk
- remove apb reset
- add rockchip_combphy_updatel()
- restyle

Changes in v4:
- restyle
- remove some minItems
- add more properties
- remove reset-names
- move #phy-cells
- add rockchip,rk3568-pipe-grf
- add rockchip,rk3568-pipe-phy-grf
- add devm_reset_control_array_get()
- remove clk structure
- change refclk DT parse
- change dev_err message
- add dot to phrase
- add ext_refclk variable
- add enable_ssc variable
- rename rockchip_combphy_param_write
- remove param_read
- replace rockchip-naneng-combphy driver name
- rename node name

Changes in v3:
- Using api devm_reset_control_get_optional_exclusive and dev_err_probe.
- Remove apb_rst.
- Redefine registers address.
- Move pipe_phy_grf0 to rk3568.dtsi

Changes in v2:
- Fix dtschema/dtc warnings/errors
- Using api devm_platform_get_and_ioremap_resource.
- Modify rockchip_combphy_set_Mode.
- Add some PHY registers definition.
- Move phy0 to rk3568.dtsi

Johan Jonker (1):
  dt-bindings: soc: grf: add naneng combo phy register compatible

Yifeng Zhao (3):
  dt-bindings: phy: rockchip: Add Naneng combo PHY bindings
  phy: rockchip: add naneng combo phy for RK3568
  arm64: dts: rockchip: add naneng combo phy nodes for rk3568

 .../phy/phy-rockchip-naneng-combphy.yaml      | 109 ++++
 .../devicetree/bindings/soc/rockchip/grf.yaml |   2 +
 arch/arm64/boot/dts/rockchip/rk3568.dtsi      |  21 +
 arch/arm64/boot/dts/rockchip/rk356x.dtsi      |  47 ++
 drivers/phy/rockchip/Kconfig                  |   8 +
 drivers/phy/rockchip/Makefile                 |   1 +
 .../rockchip/phy-rockchip-naneng-combphy.c    | 581 ++++++++++++++++++
 7 files changed, 769 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
 create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c

-- 
2.17.1


_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

[PATCH v8 0/4] Add Naneng combo PHY support for RK3568

[Yifeng Zhao]

This phy can be used as pcie-phy, usb3-phy, sata-phy or sgmii-phy.

Changes in v8:
- rename 'mode' to 'type'
- using devm_reset_control_array_get_exclusive
- move rockchip_combphy_set_mode into rockchip_combphy_init

Changes in v7:
- remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel
- rename regs

Changes in v5:
- modify description for ssc and ext-refclk
- remove apb reset
- add rockchip_combphy_updatel()
- restyle

Changes in v4:
- restyle
- remove some minItems
- add more properties
- remove reset-names
- move #phy-cells
- add rockchip,rk3568-pipe-grf
- add rockchip,rk3568-pipe-phy-grf
- add devm_reset_control_array_get()
- remove clk structure
- change refclk DT parse
- change dev_err message
- add dot to phrase
- add ext_refclk variable
- add enable_ssc variable
- rename rockchip_combphy_param_write
- remove param_read
- replace rockchip-naneng-combphy driver name
- rename node name

Changes in v3:
- Using api devm_reset_control_get_optional_exclusive and dev_err_probe.
- Remove apb_rst.
- Redefine registers address.
- Move pipe_phy_grf0 to rk3568.dtsi

Changes in v2:
- Fix dtschema/dtc warnings/errors
- Using api devm_platform_get_and_ioremap_resource.
- Modify rockchip_combphy_set_Mode.
- Add some PHY registers definition.
- Move phy0 to rk3568.dtsi

Johan Jonker (1):
  dt-bindings: soc: grf: add naneng combo phy register compatible

Yifeng Zhao (3):
  dt-bindings: phy: rockchip: Add Naneng combo PHY bindings
  phy: rockchip: add naneng combo phy for RK3568
  arm64: dts: rockchip: add naneng combo phy nodes for rk3568

 .../phy/phy-rockchip-naneng-combphy.yaml      | 109 ++++
 .../devicetree/bindings/soc/rockchip/grf.yaml |   2 +
 arch/arm64/boot/dts/rockchip/rk3568.dtsi      |  21 +
 arch/arm64/boot/dts/rockchip/rk356x.dtsi      |  47 ++
 drivers/phy/rockchip/Kconfig                  |   8 +
 drivers/phy/rockchip/Makefile                 |   1 +
 .../rockchip/phy-rockchip-naneng-combphy.c    | 581 ++++++++++++++++++
 7 files changed, 769 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
 create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c

-- 
2.17.1

[PATCH v8 0/4] Add Naneng combo PHY support for RK3568

[Yifeng Zhao]

This phy can be used as pcie-phy, usb3-phy, sata-phy or sgmii-phy.

Changes in v8:
- rename 'mode' to 'type'
- using devm_reset_control_array_get_exclusive
- move rockchip_combphy_set_mode into rockchip_combphy_init

Changes in v7:
- remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel
- rename regs

Changes in v5:
- modify description for ssc and ext-refclk
- remove apb reset
- add rockchip_combphy_updatel()
- restyle

Changes in v4:
- restyle
- remove some minItems
- add more properties
- remove reset-names
- move #phy-cells
- add rockchip,rk3568-pipe-grf
- add rockchip,rk3568-pipe-phy-grf
- add devm_reset_control_array_get()
- remove clk structure
- change refclk DT parse
- change dev_err message
- add dot to phrase
- add ext_refclk variable
- add enable_ssc variable
- rename rockchip_combphy_param_write
- remove param_read
- replace rockchip-naneng-combphy driver name
- rename node name

Changes in v3:
- Using api devm_reset_control_get_optional_exclusive and dev_err_probe.
- Remove apb_rst.
- Redefine registers address.
- Move pipe_phy_grf0 to rk3568.dtsi

Changes in v2:
- Fix dtschema/dtc warnings/errors
- Using api devm_platform_get_and_ioremap_resource.
- Modify rockchip_combphy_set_Mode.
- Add some PHY registers definition.
- Move phy0 to rk3568.dtsi

Johan Jonker (1):
  dt-bindings: soc: grf: add naneng combo phy register compatible

Yifeng Zhao (3):
  dt-bindings: phy: rockchip: Add Naneng combo PHY bindings
  phy: rockchip: add naneng combo phy for RK3568
  arm64: dts: rockchip: add naneng combo phy nodes for rk3568

 .../phy/phy-rockchip-naneng-combphy.yaml      | 109 ++++
 .../devicetree/bindings/soc/rockchip/grf.yaml |   2 +
 arch/arm64/boot/dts/rockchip/rk3568.dtsi      |  21 +
 arch/arm64/boot/dts/rockchip/rk356x.dtsi      |  47 ++
 drivers/phy/rockchip/Kconfig                  |   8 +
 drivers/phy/rockchip/Makefile                 |   1 +
 .../rockchip/phy-rockchip-naneng-combphy.c    | 581 ++++++++++++++++++
 7 files changed, 769 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
 create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c

-- 
2.17.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v8 0/4] Add Naneng combo PHY support for RK3568

[Yifeng Zhao]

This phy can be used as pcie-phy, usb3-phy, sata-phy or sgmii-phy.

Changes in v8:
- rename 'mode' to 'type'
- using devm_reset_control_array_get_exclusive
- move rockchip_combphy_set_mode into rockchip_combphy_init

Changes in v7:
- remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel
- rename regs

Changes in v5:
- modify description for ssc and ext-refclk
- remove apb reset
- add rockchip_combphy_updatel()
- restyle

Changes in v4:
- restyle
- remove some minItems
- add more properties
- remove reset-names
- move #phy-cells
- add rockchip,rk3568-pipe-grf
- add rockchip,rk3568-pipe-phy-grf
- add devm_reset_control_array_get()
- remove clk structure
- change refclk DT parse
- change dev_err message
- add dot to phrase
- add ext_refclk variable
- add enable_ssc variable
- rename rockchip_combphy_param_write
- remove param_read
- replace rockchip-naneng-combphy driver name
- rename node name

Changes in v3:
- Using api devm_reset_control_get_optional_exclusive and dev_err_probe.
- Remove apb_rst.
- Redefine registers address.
- Move pipe_phy_grf0 to rk3568.dtsi

Changes in v2:
- Fix dtschema/dtc warnings/errors
- Using api devm_platform_get_and_ioremap_resource.
- Modify rockchip_combphy_set_Mode.
- Add some PHY registers definition.
- Move phy0 to rk3568.dtsi

Johan Jonker (1):
  dt-bindings: soc: grf: add naneng combo phy register compatible

Yifeng Zhao (3):
  dt-bindings: phy: rockchip: Add Naneng combo PHY bindings
  phy: rockchip: add naneng combo phy for RK3568
  arm64: dts: rockchip: add naneng combo phy nodes for rk3568

 .../phy/phy-rockchip-naneng-combphy.yaml      | 109 ++++
 .../devicetree/bindings/soc/rockchip/grf.yaml |   2 +
 arch/arm64/boot/dts/rockchip/rk3568.dtsi      |  21 +
 arch/arm64/boot/dts/rockchip/rk356x.dtsi      |  47 ++
 drivers/phy/rockchip/Kconfig                  |   8 +
 drivers/phy/rockchip/Makefile                 |   1 +
 .../rockchip/phy-rockchip-naneng-combphy.c    | 581 ++++++++++++++++++
 7 files changed, 769 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
 create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c

-- 
2.17.1


-- 
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

[PATCH v8 1/4] dt-bindings: soc: grf: add naneng combo phy register compatible

[Yifeng Zhao]

From: Johan Jonker <jbx6244@gmail.com>

Add Naneng combo phy register compatible.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
---

Changes in v8: None
Changes in v7: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
index b2ba7bed89b2..5079e9d24af6 100644
--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
@@ -15,6 +15,8 @@ properties:
       - items:
           - enum:
               - rockchip,rk3288-sgrf
+              - rockchip,rk3568-pipe-grf
+              - rockchip,rk3568-pipe-phy-grf
               - rockchip,rk3568-usb2phy-grf
               - rockchip,rv1108-usbgrf
           - const: syscon
-- 
2.17.1


_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

[PATCH v8 1/4] dt-bindings: soc: grf: add naneng combo phy register compatible

[Yifeng Zhao]

From: Johan Jonker <jbx6244@gmail.com>

Add Naneng combo phy register compatible.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
---

Changes in v8: None
Changes in v7: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
index b2ba7bed89b2..5079e9d24af6 100644
--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
@@ -15,6 +15,8 @@ properties:
       - items:
           - enum:
               - rockchip,rk3288-sgrf
+              - rockchip,rk3568-pipe-grf
+              - rockchip,rk3568-pipe-phy-grf
               - rockchip,rk3568-usb2phy-grf
               - rockchip,rv1108-usbgrf
           - const: syscon
-- 
2.17.1

[PATCH v8 1/4] dt-bindings: soc: grf: add naneng combo phy register compatible

[Yifeng Zhao]

From: Johan Jonker <jbx6244@gmail.com>

Add Naneng combo phy register compatible.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
---

Changes in v8: None
Changes in v7: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
index b2ba7bed89b2..5079e9d24af6 100644
--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
@@ -15,6 +15,8 @@ properties:
       - items:
           - enum:
               - rockchip,rk3288-sgrf
+              - rockchip,rk3568-pipe-grf
+              - rockchip,rk3568-pipe-phy-grf
               - rockchip,rk3568-usb2phy-grf
               - rockchip,rv1108-usbgrf
           - const: syscon
-- 
2.17.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v8 1/4] dt-bindings: soc: grf: add naneng combo phy register compatible

[Yifeng Zhao]

From: Johan Jonker <jbx6244@gmail.com>

Add Naneng combo phy register compatible.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
---

Changes in v8: None
Changes in v7: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
index b2ba7bed89b2..5079e9d24af6 100644
--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
@@ -15,6 +15,8 @@ properties:
       - items:
           - enum:
               - rockchip,rk3288-sgrf
+              - rockchip,rk3568-pipe-grf
+              - rockchip,rk3568-pipe-phy-grf
               - rockchip,rk3568-usb2phy-grf
               - rockchip,rv1108-usbgrf
           - const: syscon
-- 
2.17.1


-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

[PATCH v8 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings

[Yifeng Zhao]

Add the compatible strings for the Naneng combo PHY found on rockchip SoC.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---

Changes in v8: None
Changes in v7:
- remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel

Changes in v5:
- modify description for ssc and ext-refclk
- remove apb reset

Changes in v4:
- restyle
- remove some minItems
- add more properties
- remove reset-names
- move #phy-cells
- add rockchip,rk3568-pipe-grf
- add rockchip,rk3568-pipe-phy-grf

Changes in v3: None
Changes in v2:
- Fix dtschema/dtc warnings/errors

 .../phy/phy-rockchip-naneng-combphy.yaml      | 109 ++++++++++++++++++
 1 file changed, 109 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml

diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
new file mode 100644
index 000000000000..f14454401419
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
@@ -0,0 +1,109 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip SoC Naneng Combo Phy Device Tree Bindings
+
+maintainers:
+  - Heiko Stuebner <heiko@sntech.de>
+
+properties:
+  compatible:
+    enum:
+      - rockchip,rk3568-naneng-combphy
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: reference clock
+      - description: apb clock
+      - description: pipe clock
+
+  clock-names:
+    items:
+      - const: ref
+      - const: apb
+      - const: pipe
+
+  resets:
+    items:
+      - description: exclusive PHY reset line
+
+  rockchip,enable-ssc:
+    type: boolean
+    description:
+      The option SSC can be enabled for U3, SATA and PCIE.
+      Most commercially available platforms use SSC to reduce EMI.
+
+  rockchip,ext-refclk:
+    type: boolean
+    description:
+      Many PCIe connections, especially backplane connections,
+      require a synchronous reference clock between the two link partners.
+      To achieve this a common clock source, referred to as REFCLK in
+      the PCI Express Card Electromechanical Specification,
+      should be used by both ends of the PCIe link.
+      In PCIe mode one can choose to use an internal or an external reference
+      clock.
+      By default the internal clock is selected. The PCIe PHY provides a 100MHz
+      differential clock output(optional with SSC) for system applications.
+      When selecting this option an externally 100MHz differential
+      reference clock needs to be provided to the PCIe PHY.
+
+  rockchip,pipe-grf:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      Some additional phy settings are accessed through GRF regs.
+
+  rockchip,pipe-phy-grf:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      Some additional pipe settings are accessed through GRF regs.
+
+  "#phy-cells":
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - resets
+  - rockchip,pipe-grf
+  - rockchip,pipe-phy-grf
+  - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/rk3568-cru.h>
+
+    pipegrf: syscon@fdc50000 {
+      compatible = "rockchip,rk3568-pipe-grf", "syscon";
+      reg = <0xfdc50000 0x1000>;
+    };
+
+    pipe_phy_grf0: syscon@fdc70000 {
+      compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
+      reg = <0xfdc70000 0x1000>;
+    };
+
+    combphy0: phy@fe820000 {
+      compatible = "rockchip,rk3568-naneng-combphy";
+      reg = <0xfe820000 0x100>;
+      clocks = <&pmucru CLK_PCIEPHY0_REF>,
+               <&cru PCLK_PIPEPHY0>,
+               <&cru PCLK_PIPE>;
+      clock-names = "ref", "apb", "pipe";
+      assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
+      assigned-clock-rates = <100000000>;
+      resets = <&cru SRST_PIPEPHY0>;
+      rockchip,pipe-grf = <&pipegrf>;
+      rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
+      #phy-cells = <1>;
+    };
-- 
2.17.1


_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

[PATCH v8 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings

[Yifeng Zhao]

Add the compatible strings for the Naneng combo PHY found on rockchip SoC.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---

Changes in v8: None
Changes in v7:
- remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel

Changes in v5:
- modify description for ssc and ext-refclk
- remove apb reset

Changes in v4:
- restyle
- remove some minItems
- add more properties
- remove reset-names
- move #phy-cells
- add rockchip,rk3568-pipe-grf
- add rockchip,rk3568-pipe-phy-grf

Changes in v3: None
Changes in v2:
- Fix dtschema/dtc warnings/errors

 .../phy/phy-rockchip-naneng-combphy.yaml      | 109 ++++++++++++++++++
 1 file changed, 109 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml

diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
new file mode 100644
index 000000000000..f14454401419
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
@@ -0,0 +1,109 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip SoC Naneng Combo Phy Device Tree Bindings
+
+maintainers:
+  - Heiko Stuebner <heiko@sntech.de>
+
+properties:
+  compatible:
+    enum:
+      - rockchip,rk3568-naneng-combphy
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: reference clock
+      - description: apb clock
+      - description: pipe clock
+
+  clock-names:
+    items:
+      - const: ref
+      - const: apb
+      - const: pipe
+
+  resets:
+    items:
+      - description: exclusive PHY reset line
+
+  rockchip,enable-ssc:
+    type: boolean
+    description:
+      The option SSC can be enabled for U3, SATA and PCIE.
+      Most commercially available platforms use SSC to reduce EMI.
+
+  rockchip,ext-refclk:
+    type: boolean
+    description:
+      Many PCIe connections, especially backplane connections,
+      require a synchronous reference clock between the two link partners.
+      To achieve this a common clock source, referred to as REFCLK in
+      the PCI Express Card Electromechanical Specification,
+      should be used by both ends of the PCIe link.
+      In PCIe mode one can choose to use an internal or an external reference
+      clock.
+      By default the internal clock is selected. The PCIe PHY provides a 100MHz
+      differential clock output(optional with SSC) for system applications.
+      When selecting this option an externally 100MHz differential
+      reference clock needs to be provided to the PCIe PHY.
+
+  rockchip,pipe-grf:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      Some additional phy settings are accessed through GRF regs.
+
+  rockchip,pipe-phy-grf:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      Some additional pipe settings are accessed through GRF regs.
+
+  "#phy-cells":
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - resets
+  - rockchip,pipe-grf
+  - rockchip,pipe-phy-grf
+  - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/rk3568-cru.h>
+
+    pipegrf: syscon@fdc50000 {
+      compatible = "rockchip,rk3568-pipe-grf", "syscon";
+      reg = <0xfdc50000 0x1000>;
+    };
+
+    pipe_phy_grf0: syscon@fdc70000 {
+      compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
+      reg = <0xfdc70000 0x1000>;
+    };
+
+    combphy0: phy@fe820000 {
+      compatible = "rockchip,rk3568-naneng-combphy";
+      reg = <0xfe820000 0x100>;
+      clocks = <&pmucru CLK_PCIEPHY0_REF>,
+               <&cru PCLK_PIPEPHY0>,
+               <&cru PCLK_PIPE>;
+      clock-names = "ref", "apb", "pipe";
+      assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
+      assigned-clock-rates = <100000000>;
+      resets = <&cru SRST_PIPEPHY0>;
+      rockchip,pipe-grf = <&pipegrf>;
+      rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
+      #phy-cells = <1>;
+    };
-- 
2.17.1

[PATCH v8 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings

[Yifeng Zhao]

Add the compatible strings for the Naneng combo PHY found on rockchip SoC.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---

Changes in v8: None
Changes in v7:
- remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel

Changes in v5:
- modify description for ssc and ext-refclk
- remove apb reset

Changes in v4:
- restyle
- remove some minItems
- add more properties
- remove reset-names
- move #phy-cells
- add rockchip,rk3568-pipe-grf
- add rockchip,rk3568-pipe-phy-grf

Changes in v3: None
Changes in v2:
- Fix dtschema/dtc warnings/errors

 .../phy/phy-rockchip-naneng-combphy.yaml      | 109 ++++++++++++++++++
 1 file changed, 109 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml

diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
new file mode 100644
index 000000000000..f14454401419
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
@@ -0,0 +1,109 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip SoC Naneng Combo Phy Device Tree Bindings
+
+maintainers:
+  - Heiko Stuebner <heiko@sntech.de>
+
+properties:
+  compatible:
+    enum:
+      - rockchip,rk3568-naneng-combphy
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: reference clock
+      - description: apb clock
+      - description: pipe clock
+
+  clock-names:
+    items:
+      - const: ref
+      - const: apb
+      - const: pipe
+
+  resets:
+    items:
+      - description: exclusive PHY reset line
+
+  rockchip,enable-ssc:
+    type: boolean
+    description:
+      The option SSC can be enabled for U3, SATA and PCIE.
+      Most commercially available platforms use SSC to reduce EMI.
+
+  rockchip,ext-refclk:
+    type: boolean
+    description:
+      Many PCIe connections, especially backplane connections,
+      require a synchronous reference clock between the two link partners.
+      To achieve this a common clock source, referred to as REFCLK in
+      the PCI Express Card Electromechanical Specification,
+      should be used by both ends of the PCIe link.
+      In PCIe mode one can choose to use an internal or an external reference
+      clock.
+      By default the internal clock is selected. The PCIe PHY provides a 100MHz
+      differential clock output(optional with SSC) for system applications.
+      When selecting this option an externally 100MHz differential
+      reference clock needs to be provided to the PCIe PHY.
+
+  rockchip,pipe-grf:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      Some additional phy settings are accessed through GRF regs.
+
+  rockchip,pipe-phy-grf:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      Some additional pipe settings are accessed through GRF regs.
+
+  "#phy-cells":
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - resets
+  - rockchip,pipe-grf
+  - rockchip,pipe-phy-grf
+  - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/rk3568-cru.h>
+
+    pipegrf: syscon@fdc50000 {
+      compatible = "rockchip,rk3568-pipe-grf", "syscon";
+      reg = <0xfdc50000 0x1000>;
+    };
+
+    pipe_phy_grf0: syscon@fdc70000 {
+      compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
+      reg = <0xfdc70000 0x1000>;
+    };
+
+    combphy0: phy@fe820000 {
+      compatible = "rockchip,rk3568-naneng-combphy";
+      reg = <0xfe820000 0x100>;
+      clocks = <&pmucru CLK_PCIEPHY0_REF>,
+               <&cru PCLK_PIPEPHY0>,
+               <&cru PCLK_PIPE>;
+      clock-names = "ref", "apb", "pipe";
+      assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
+      assigned-clock-rates = <100000000>;
+      resets = <&cru SRST_PIPEPHY0>;
+      rockchip,pipe-grf = <&pipegrf>;
+      rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
+      #phy-cells = <1>;
+    };
-- 
2.17.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v8 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings

[Yifeng Zhao]

Add the compatible strings for the Naneng combo PHY found on rockchip SoC.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---

Changes in v8: None
Changes in v7:
- remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel

Changes in v5:
- modify description for ssc and ext-refclk
- remove apb reset

Changes in v4:
- restyle
- remove some minItems
- add more properties
- remove reset-names
- move #phy-cells
- add rockchip,rk3568-pipe-grf
- add rockchip,rk3568-pipe-phy-grf

Changes in v3: None
Changes in v2:
- Fix dtschema/dtc warnings/errors

 .../phy/phy-rockchip-naneng-combphy.yaml      | 109 ++++++++++++++++++
 1 file changed, 109 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml

diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
new file mode 100644
index 000000000000..f14454401419
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
@@ -0,0 +1,109 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip SoC Naneng Combo Phy Device Tree Bindings
+
+maintainers:
+  - Heiko Stuebner <heiko@sntech.de>
+
+properties:
+  compatible:
+    enum:
+      - rockchip,rk3568-naneng-combphy
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: reference clock
+      - description: apb clock
+      - description: pipe clock
+
+  clock-names:
+    items:
+      - const: ref
+      - const: apb
+      - const: pipe
+
+  resets:
+    items:
+      - description: exclusive PHY reset line
+
+  rockchip,enable-ssc:
+    type: boolean
+    description:
+      The option SSC can be enabled for U3, SATA and PCIE.
+      Most commercially available platforms use SSC to reduce EMI.
+
+  rockchip,ext-refclk:
+    type: boolean
+    description:
+      Many PCIe connections, especially backplane connections,
+      require a synchronous reference clock between the two link partners.
+      To achieve this a common clock source, referred to as REFCLK in
+      the PCI Express Card Electromechanical Specification,
+      should be used by both ends of the PCIe link.
+      In PCIe mode one can choose to use an internal or an external reference
+      clock.
+      By default the internal clock is selected. The PCIe PHY provides a 100MHz
+      differential clock output(optional with SSC) for system applications.
+      When selecting this option an externally 100MHz differential
+      reference clock needs to be provided to the PCIe PHY.
+
+  rockchip,pipe-grf:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      Some additional phy settings are accessed through GRF regs.
+
+  rockchip,pipe-phy-grf:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      Some additional pipe settings are accessed through GRF regs.
+
+  "#phy-cells":
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - resets
+  - rockchip,pipe-grf
+  - rockchip,pipe-phy-grf
+  - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/rk3568-cru.h>
+
+    pipegrf: syscon@fdc50000 {
+      compatible = "rockchip,rk3568-pipe-grf", "syscon";
+      reg = <0xfdc50000 0x1000>;
+    };
+
+    pipe_phy_grf0: syscon@fdc70000 {
+      compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
+      reg = <0xfdc70000 0x1000>;
+    };
+
+    combphy0: phy@fe820000 {
+      compatible = "rockchip,rk3568-naneng-combphy";
+      reg = <0xfe820000 0x100>;
+      clocks = <&pmucru CLK_PCIEPHY0_REF>,
+               <&cru PCLK_PIPEPHY0>,
+               <&cru PCLK_PIPE>;
+      clock-names = "ref", "apb", "pipe";
+      assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
+      assigned-clock-rates = <100000000>;
+      resets = <&cru SRST_PIPEPHY0>;
+      rockchip,pipe-grf = <&pipegrf>;
+      rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
+      #phy-cells = <1>;
+    };
-- 
2.17.1


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Re: [PATCH v8 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings

[Rob Herring]

On Tue, 08 Feb 2022 17:13:24 +0800, Yifeng Zhao wrote:
> Add the compatible strings for the Naneng combo PHY found on rockchip SoC.
> 
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> ---
> 
> Changes in v8: None
> Changes in v7:
> - remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel
> 
> Changes in v5:
> - modify description for ssc and ext-refclk
> - remove apb reset
> 
> Changes in v4:
> - restyle
> - remove some minItems
> - add more properties
> - remove reset-names
> - move #phy-cells
> - add rockchip,rk3568-pipe-grf
> - add rockchip,rk3568-pipe-phy-grf
> 
> Changes in v3: None
> Changes in v2:
> - Fix dtschema/dtc warnings/errors
> 
>  .../phy/phy-rockchip-naneng-combphy.yaml      | 109 ++++++++++++++++++
>  1 file changed, 109 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:0:0: /example-0/syscon@fdc50000: failed to match any schema with compatible: ['rockchip,rk3568-pipe-grf', 'syscon']
Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:0:0: /example-0/syscon@fdc70000: failed to match any schema with compatible: ['rockchip,rk3568-pipe-phy-grf', 'syscon']

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/1589719

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.


_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

Re: [PATCH v8 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings

[Rob Herring]

On Tue, 08 Feb 2022 17:13:24 +0800, Yifeng Zhao wrote:
> Add the compatible strings for the Naneng combo PHY found on rockchip SoC.
> 
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> ---
> 
> Changes in v8: None
> Changes in v7:
> - remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel
> 
> Changes in v5:
> - modify description for ssc and ext-refclk
> - remove apb reset
> 
> Changes in v4:
> - restyle
> - remove some minItems
> - add more properties
> - remove reset-names
> - move #phy-cells
> - add rockchip,rk3568-pipe-grf
> - add rockchip,rk3568-pipe-phy-grf
> 
> Changes in v3: None
> Changes in v2:
> - Fix dtschema/dtc warnings/errors
> 
>  .../phy/phy-rockchip-naneng-combphy.yaml      | 109 ++++++++++++++++++
>  1 file changed, 109 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:0:0: /example-0/syscon@fdc50000: failed to match any schema with compatible: ['rockchip,rk3568-pipe-grf', 'syscon']
Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:0:0: /example-0/syscon@fdc70000: failed to match any schema with compatible: ['rockchip,rk3568-pipe-phy-grf', 'syscon']

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/1589719

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.

Re: [PATCH v8 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings

[Rob Herring]

On Tue, 08 Feb 2022 17:13:24 +0800, Yifeng Zhao wrote:
> Add the compatible strings for the Naneng combo PHY found on rockchip SoC.
> 
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> ---
> 
> Changes in v8: None
> Changes in v7:
> - remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel
> 
> Changes in v5:
> - modify description for ssc and ext-refclk
> - remove apb reset
> 
> Changes in v4:
> - restyle
> - remove some minItems
> - add more properties
> - remove reset-names
> - move #phy-cells
> - add rockchip,rk3568-pipe-grf
> - add rockchip,rk3568-pipe-phy-grf
> 
> Changes in v3: None
> Changes in v2:
> - Fix dtschema/dtc warnings/errors
> 
>  .../phy/phy-rockchip-naneng-combphy.yaml      | 109 ++++++++++++++++++
>  1 file changed, 109 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:0:0: /example-0/syscon@fdc50000: failed to match any schema with compatible: ['rockchip,rk3568-pipe-grf', 'syscon']
Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:0:0: /example-0/syscon@fdc70000: failed to match any schema with compatible: ['rockchip,rk3568-pipe-phy-grf', 'syscon']

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/1589719

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v8 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings

[Rob Herring]

On Tue, 08 Feb 2022 17:13:24 +0800, Yifeng Zhao wrote:
> Add the compatible strings for the Naneng combo PHY found on rockchip SoC.
> 
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> ---
> 
> Changes in v8: None
> Changes in v7:
> - remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel
> 
> Changes in v5:
> - modify description for ssc and ext-refclk
> - remove apb reset
> 
> Changes in v4:
> - restyle
> - remove some minItems
> - add more properties
> - remove reset-names
> - move #phy-cells
> - add rockchip,rk3568-pipe-grf
> - add rockchip,rk3568-pipe-phy-grf
> 
> Changes in v3: None
> Changes in v2:
> - Fix dtschema/dtc warnings/errors
> 
>  .../phy/phy-rockchip-naneng-combphy.yaml      | 109 ++++++++++++++++++
>  1 file changed, 109 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:0:0: /example-0/syscon@fdc50000: failed to match any schema with compatible: ['rockchip,rk3568-pipe-grf', 'syscon']
Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:0:0: /example-0/syscon@fdc70000: failed to match any schema with compatible: ['rockchip,rk3568-pipe-phy-grf', 'syscon']

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/1589719

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.


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Re: Re: [PATCH v8 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings

[zyf]

Hi Rob,

We move "rockchip,rk3568-pipe-grf" from syscon.yaml to grf.yaml.
How to fix this compilation failed?

diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
index fdd96e378df0..e9bb96ab9446 100644
--- a/Documentation/devicetree/bindings/mfd/syscon.yaml
+++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
@@ -52,6 +52,8 @@ properties:
               - rockchip,rk3288-qos
               - rockchip,rk3368-qos
               - rockchip,rk3399-qos
+              - rockchip,rk3568-pipe-grf
+              - rockchip,rk3568-pipe-phy-grf


>On Tue, 08 Feb 2022 17:13:24 +0800, Yifeng Zhao wrote:
>> Add the compatible strings for the Naneng combo PHY found on rockchip SoC.
>>
>> Reviewed-by: Rob Herring <robh@kernel.org>
>> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
>> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
>> ---
>>
>> Changes in v8: None
>> Changes in v7:
>> - remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel
>>
>> Changes in v5:
>> - modify description for ssc and ext-refclk
>> - remove apb reset
>>
>> Changes in v4:
>> - restyle
>> - remove some minItems
>> - add more properties
>> - remove reset-names
>> - move #phy-cells
>> - add rockchip,rk3568-pipe-grf
>> - add rockchip,rk3568-pipe-phy-grf
>>
>> Changes in v3: None
>> Changes in v2:
>> - Fix dtschema/dtc warnings/errors
>>
>>  .../phy/phy-rockchip-naneng-combphy.yaml      | 109 ++++++++++++++++++
>>  1 file changed, 109 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
>>
> 
>My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
>on your patch (DT_CHECKER_FLAGS is new in v5.13):
> 
>yamllint warnings/errors:
> 
>dtschema/dtc warnings/errors:
>Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:0:0: /example-0/syscon@fdc50000: failed to match any schema with compatible: ['rockchip,rk3568-pipe-grf', 'syscon']
>Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:0:0: /example-0/syscon@fdc70000: failed to match any schema with compatible: ['rockchip,rk3568-pipe-phy-grf', 'syscon']
> 
>doc reference errors (make refcheckdocs):
> 
>See https://patchwork.ozlabs.org/patch/1589719
> 
>This check can fail if there are any dependencies. The base for a patch
>series is generally the most recent rc1.
> 
>If you already ran 'make dt_binding_check' and didn't see the above
>error(s), then make sure 'yamllint' is installed and dt-schema is up to
>date:
> 
>pip3 install dtschema --upgrade
> 
>Please check and re-submit.
 
 
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

Re: Re: [PATCH v8 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings

[zyf]

Hi Rob,

We move "rockchip,rk3568-pipe-grf" from syscon.yaml to grf.yaml.
How to fix this compilation failed?

diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
index fdd96e378df0..e9bb96ab9446 100644
--- a/Documentation/devicetree/bindings/mfd/syscon.yaml
+++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
@@ -52,6 +52,8 @@ properties:
               - rockchip,rk3288-qos
               - rockchip,rk3368-qos
               - rockchip,rk3399-qos
+              - rockchip,rk3568-pipe-grf
+              - rockchip,rk3568-pipe-phy-grf


>On Tue, 08 Feb 2022 17:13:24 +0800, Yifeng Zhao wrote:
>> Add the compatible strings for the Naneng combo PHY found on rockchip SoC.
>>
>> Reviewed-by: Rob Herring <robh@kernel.org>
>> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
>> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
>> ---
>>
>> Changes in v8: None
>> Changes in v7:
>> - remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel
>>
>> Changes in v5:
>> - modify description for ssc and ext-refclk
>> - remove apb reset
>>
>> Changes in v4:
>> - restyle
>> - remove some minItems
>> - add more properties
>> - remove reset-names
>> - move #phy-cells
>> - add rockchip,rk3568-pipe-grf
>> - add rockchip,rk3568-pipe-phy-grf
>>
>> Changes in v3: None
>> Changes in v2:
>> - Fix dtschema/dtc warnings/errors
>>
>>  .../phy/phy-rockchip-naneng-combphy.yaml      | 109 ++++++++++++++++++
>>  1 file changed, 109 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
>>
> 
>My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
>on your patch (DT_CHECKER_FLAGS is new in v5.13):
> 
>yamllint warnings/errors:
> 
>dtschema/dtc warnings/errors:
>Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:0:0: /example-0/syscon@fdc50000: failed to match any schema with compatible: ['rockchip,rk3568-pipe-grf', 'syscon']
>Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:0:0: /example-0/syscon@fdc70000: failed to match any schema with compatible: ['rockchip,rk3568-pipe-phy-grf', 'syscon']
> 
>doc reference errors (make refcheckdocs):
> 
>See https://patchwork.ozlabs.org/patch/1589719
> 
>This check can fail if there are any dependencies. The base for a patch
>series is generally the most recent rc1.
> 
>If you already ran 'make dt_binding_check' and didn't see the above
>error(s), then make sure 'yamllint' is installed and dt-schema is up to
>date:
> 
>pip3 install dtschema --upgrade
> 
>Please check and re-submit.
 
 
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: Re: [PATCH v8 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings

[zyf]

Hi Rob,

We move "rockchip,rk3568-pipe-grf" from syscon.yaml to grf.yaml.
How to fix this compilation failed?

diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
index fdd96e378df0..e9bb96ab9446 100644
--- a/Documentation/devicetree/bindings/mfd/syscon.yaml
+++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
@@ -52,6 +52,8 @@ properties:
               - rockchip,rk3288-qos
               - rockchip,rk3368-qos
               - rockchip,rk3399-qos
+              - rockchip,rk3568-pipe-grf
+              - rockchip,rk3568-pipe-phy-grf


>On Tue, 08 Feb 2022 17:13:24 +0800, Yifeng Zhao wrote:
>> Add the compatible strings for the Naneng combo PHY found on rockchip SoC.
>>
>> Reviewed-by: Rob Herring <robh@kernel.org>
>> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
>> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
>> ---
>>
>> Changes in v8: None
>> Changes in v7:
>> - remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel
>>
>> Changes in v5:
>> - modify description for ssc and ext-refclk
>> - remove apb reset
>>
>> Changes in v4:
>> - restyle
>> - remove some minItems
>> - add more properties
>> - remove reset-names
>> - move #phy-cells
>> - add rockchip,rk3568-pipe-grf
>> - add rockchip,rk3568-pipe-phy-grf
>>
>> Changes in v3: None
>> Changes in v2:
>> - Fix dtschema/dtc warnings/errors
>>
>>  .../phy/phy-rockchip-naneng-combphy.yaml      | 109 ++++++++++++++++++
>>  1 file changed, 109 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
>>
> 
>My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
>on your patch (DT_CHECKER_FLAGS is new in v5.13):
> 
>yamllint warnings/errors:
> 
>dtschema/dtc warnings/errors:
>Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:0:0: /example-0/syscon@fdc50000: failed to match any schema with compatible: ['rockchip,rk3568-pipe-grf', 'syscon']
>Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:0:0: /example-0/syscon@fdc70000: failed to match any schema with compatible: ['rockchip,rk3568-pipe-phy-grf', 'syscon']
> 
>doc reference errors (make refcheckdocs):
> 
>See https://patchwork.ozlabs.org/patch/1589719
> 
>This check can fail if there are any dependencies. The base for a patch
>series is generally the most recent rc1.
> 
>If you already ran 'make dt_binding_check' and didn't see the above
>error(s), then make sure 'yamllint' is installed and dt-schema is up to
>date:
> 
>pip3 install dtschema --upgrade
> 
>Please check and re-submit.
 
 
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Re: [PATCH v8 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings

[Heiko Stübner]

Hi,

Am Mittwoch, 9. Februar 2022, 04:38:15 CET schrieb zyf@rock-chips.com:
> Hi Rob,
> 
> We move "rockchip,rk3568-pipe-grf" from syscon.yaml to grf.yaml.
> How to fix this compilation failed?

as you can see in the example, there is already a
	#include <dt-bindings/clock/rk3568-cru.h>
so you probably just need to add another include for the grf.yaml


Heiko

> 
> diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
> index fdd96e378df0..e9bb96ab9446 100644
> --- a/Documentation/devicetree/bindings/mfd/syscon.yaml
> +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
> @@ -52,6 +52,8 @@ properties:
>                - rockchip,rk3288-qos
>                - rockchip,rk3368-qos
>                - rockchip,rk3399-qos
> +              - rockchip,rk3568-pipe-grf
> +              - rockchip,rk3568-pipe-phy-grf
> 
> 
> >On Tue, 08 Feb 2022 17:13:24 +0800, Yifeng Zhao wrote:
> >> Add the compatible strings for the Naneng combo PHY found on rockchip SoC.
> >>
> >> Reviewed-by: Rob Herring <robh@kernel.org>
> >> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
> >> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> >> ---
> >>
> >> Changes in v8: None
> >> Changes in v7:
> >> - remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel
> >>
> >> Changes in v5:
> >> - modify description for ssc and ext-refclk
> >> - remove apb reset
> >>
> >> Changes in v4:
> >> - restyle
> >> - remove some minItems
> >> - add more properties
> >> - remove reset-names
> >> - move #phy-cells
> >> - add rockchip,rk3568-pipe-grf
> >> - add rockchip,rk3568-pipe-phy-grf
> >>
> >> Changes in v3: None
> >> Changes in v2:
> >> - Fix dtschema/dtc warnings/errors
> >>
> >>  .../phy/phy-rockchip-naneng-combphy.yaml      | 109 ++++++++++++++++++
> >>  1 file changed, 109 insertions(+)
> >>  create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
> >>
> > 
> >My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> >on your patch (DT_CHECKER_FLAGS is new in v5.13):
> > 
> >yamllint warnings/errors:
> > 
> >dtschema/dtc warnings/errors:
> >Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:0:0: /example-0/syscon@fdc50000: failed to match any schema with compatible: ['rockchip,rk3568-pipe-grf', 'syscon']
> >Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:0:0: /example-0/syscon@fdc70000: failed to match any schema with compatible: ['rockchip,rk3568-pipe-phy-grf', 'syscon']
> > 
> >doc reference errors (make refcheckdocs):
> > 
> >See https://patchwork.ozlabs.org/patch/1589719
> > 
> >This check can fail if there are any dependencies. The base for a patch
> >series is generally the most recent rc1.
> > 
> >If you already ran 'make dt_binding_check' and didn't see the above
> >error(s), then make sure 'yamllint' is installed and dt-schema is up to
> >date:
> > 
> >pip3 install dtschema --upgrade
> > 
> >Please check and re-submit.
>  
>  
> 





_______________________________________________
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Linux-rockchip@lists.infradead.org
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Re: [PATCH v8 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings

[Heiko Stübner]

Hi,

Am Mittwoch, 9. Februar 2022, 04:38:15 CET schrieb zyf@rock-chips.com:
> Hi Rob,
> 
> We move "rockchip,rk3568-pipe-grf" from syscon.yaml to grf.yaml.
> How to fix this compilation failed?

as you can see in the example, there is already a
	#include <dt-bindings/clock/rk3568-cru.h>
so you probably just need to add another include for the grf.yaml


Heiko

> 
> diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
> index fdd96e378df0..e9bb96ab9446 100644
> --- a/Documentation/devicetree/bindings/mfd/syscon.yaml
> +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
> @@ -52,6 +52,8 @@ properties:
>                - rockchip,rk3288-qos
>                - rockchip,rk3368-qos
>                - rockchip,rk3399-qos
> +              - rockchip,rk3568-pipe-grf
> +              - rockchip,rk3568-pipe-phy-grf
> 
> 
> >On Tue, 08 Feb 2022 17:13:24 +0800, Yifeng Zhao wrote:
> >> Add the compatible strings for the Naneng combo PHY found on rockchip SoC.
> >>
> >> Reviewed-by: Rob Herring <robh@kernel.org>
> >> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
> >> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> >> ---
> >>
> >> Changes in v8: None
> >> Changes in v7:
> >> - remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel
> >>
> >> Changes in v5:
> >> - modify description for ssc and ext-refclk
> >> - remove apb reset
> >>
> >> Changes in v4:
> >> - restyle
> >> - remove some minItems
> >> - add more properties
> >> - remove reset-names
> >> - move #phy-cells
> >> - add rockchip,rk3568-pipe-grf
> >> - add rockchip,rk3568-pipe-phy-grf
> >>
> >> Changes in v3: None
> >> Changes in v2:
> >> - Fix dtschema/dtc warnings/errors
> >>
> >>  .../phy/phy-rockchip-naneng-combphy.yaml      | 109 ++++++++++++++++++
> >>  1 file changed, 109 insertions(+)
> >>  create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
> >>
> > 
> >My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> >on your patch (DT_CHECKER_FLAGS is new in v5.13):
> > 
> >yamllint warnings/errors:
> > 
> >dtschema/dtc warnings/errors:
> >Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:0:0: /example-0/syscon@fdc50000: failed to match any schema with compatible: ['rockchip,rk3568-pipe-grf', 'syscon']
> >Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:0:0: /example-0/syscon@fdc70000: failed to match any schema with compatible: ['rockchip,rk3568-pipe-phy-grf', 'syscon']
> > 
> >doc reference errors (make refcheckdocs):
> > 
> >See https://patchwork.ozlabs.org/patch/1589719
> > 
> >This check can fail if there are any dependencies. The base for a patch
> >series is generally the most recent rc1.
> > 
> >If you already ran 'make dt_binding_check' and didn't see the above
> >error(s), then make sure 'yamllint' is installed and dt-schema is up to
> >date:
> > 
> >pip3 install dtschema --upgrade
> > 
> >Please check and re-submit.
>  
>  
> 

Re: [PATCH v8 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings

[Heiko Stübner]

Hi,

Am Mittwoch, 9. Februar 2022, 04:38:15 CET schrieb zyf@rock-chips.com:
> Hi Rob,
> 
> We move "rockchip,rk3568-pipe-grf" from syscon.yaml to grf.yaml.
> How to fix this compilation failed?

as you can see in the example, there is already a
	#include <dt-bindings/clock/rk3568-cru.h>
so you probably just need to add another include for the grf.yaml


Heiko

> 
> diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
> index fdd96e378df0..e9bb96ab9446 100644
> --- a/Documentation/devicetree/bindings/mfd/syscon.yaml
> +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
> @@ -52,6 +52,8 @@ properties:
>                - rockchip,rk3288-qos
>                - rockchip,rk3368-qos
>                - rockchip,rk3399-qos
> +              - rockchip,rk3568-pipe-grf
> +              - rockchip,rk3568-pipe-phy-grf
> 
> 
> >On Tue, 08 Feb 2022 17:13:24 +0800, Yifeng Zhao wrote:
> >> Add the compatible strings for the Naneng combo PHY found on rockchip SoC.
> >>
> >> Reviewed-by: Rob Herring <robh@kernel.org>
> >> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
> >> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> >> ---
> >>
> >> Changes in v8: None
> >> Changes in v7:
> >> - remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel
> >>
> >> Changes in v5:
> >> - modify description for ssc and ext-refclk
> >> - remove apb reset
> >>
> >> Changes in v4:
> >> - restyle
> >> - remove some minItems
> >> - add more properties
> >> - remove reset-names
> >> - move #phy-cells
> >> - add rockchip,rk3568-pipe-grf
> >> - add rockchip,rk3568-pipe-phy-grf
> >>
> >> Changes in v3: None
> >> Changes in v2:
> >> - Fix dtschema/dtc warnings/errors
> >>
> >>  .../phy/phy-rockchip-naneng-combphy.yaml      | 109 ++++++++++++++++++
> >>  1 file changed, 109 insertions(+)
> >>  create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
> >>
> > 
> >My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> >on your patch (DT_CHECKER_FLAGS is new in v5.13):
> > 
> >yamllint warnings/errors:
> > 
> >dtschema/dtc warnings/errors:
> >Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:0:0: /example-0/syscon@fdc50000: failed to match any schema with compatible: ['rockchip,rk3568-pipe-grf', 'syscon']
> >Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:0:0: /example-0/syscon@fdc70000: failed to match any schema with compatible: ['rockchip,rk3568-pipe-phy-grf', 'syscon']
> > 
> >doc reference errors (make refcheckdocs):
> > 
> >See https://patchwork.ozlabs.org/patch/1589719
> > 
> >This check can fail if there are any dependencies. The base for a patch
> >series is generally the most recent rc1.
> > 
> >If you already ran 'make dt_binding_check' and didn't see the above
> >error(s), then make sure 'yamllint' is installed and dt-schema is up to
> >date:
> > 
> >pip3 install dtschema --upgrade
> > 
> >Please check and re-submit.
>  
>  
> 





_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v8 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings

[Heiko Stübner]

Hi,

Am Mittwoch, 9. Februar 2022, 04:38:15 CET schrieb zyf@rock-chips.com:
> Hi Rob,
> 
> We move "rockchip,rk3568-pipe-grf" from syscon.yaml to grf.yaml.
> How to fix this compilation failed?

as you can see in the example, there is already a
	#include <dt-bindings/clock/rk3568-cru.h>
so you probably just need to add another include for the grf.yaml


Heiko

> 
> diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
> index fdd96e378df0..e9bb96ab9446 100644
> --- a/Documentation/devicetree/bindings/mfd/syscon.yaml
> +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
> @@ -52,6 +52,8 @@ properties:
>                - rockchip,rk3288-qos
>                - rockchip,rk3368-qos
>                - rockchip,rk3399-qos
> +              - rockchip,rk3568-pipe-grf
> +              - rockchip,rk3568-pipe-phy-grf
> 
> 
> >On Tue, 08 Feb 2022 17:13:24 +0800, Yifeng Zhao wrote:
> >> Add the compatible strings for the Naneng combo PHY found on rockchip SoC.
> >>
> >> Reviewed-by: Rob Herring <robh@kernel.org>
> >> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
> >> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> >> ---
> >>
> >> Changes in v8: None
> >> Changes in v7:
> >> - remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel
> >>
> >> Changes in v5:
> >> - modify description for ssc and ext-refclk
> >> - remove apb reset
> >>
> >> Changes in v4:
> >> - restyle
> >> - remove some minItems
> >> - add more properties
> >> - remove reset-names
> >> - move #phy-cells
> >> - add rockchip,rk3568-pipe-grf
> >> - add rockchip,rk3568-pipe-phy-grf
> >>
> >> Changes in v3: None
> >> Changes in v2:
> >> - Fix dtschema/dtc warnings/errors
> >>
> >>  .../phy/phy-rockchip-naneng-combphy.yaml      | 109 ++++++++++++++++++
> >>  1 file changed, 109 insertions(+)
> >>  create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
> >>
> > 
> >My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> >on your patch (DT_CHECKER_FLAGS is new in v5.13):
> > 
> >yamllint warnings/errors:
> > 
> >dtschema/dtc warnings/errors:
> >Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:0:0: /example-0/syscon@fdc50000: failed to match any schema with compatible: ['rockchip,rk3568-pipe-grf', 'syscon']
> >Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:0:0: /example-0/syscon@fdc70000: failed to match any schema with compatible: ['rockchip,rk3568-pipe-phy-grf', 'syscon']
> > 
> >doc reference errors (make refcheckdocs):
> > 
> >See https://patchwork.ozlabs.org/patch/1589719
> > 
> >This check can fail if there are any dependencies. The base for a patch
> >series is generally the most recent rc1.
> > 
> >If you already ran 'make dt_binding_check' and didn't see the above
> >error(s), then make sure 'yamllint' is installed and dt-schema is up to
> >date:
> > 
> >pip3 install dtschema --upgrade
> > 
> >Please check and re-submit.
>  
>  
> 





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Re: [PATCH v8 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings

[Rob Herring]

On Tue, Feb 8, 2022 at 3:15 AM Yifeng Zhao <yifeng.zhao@rock-chips.com> wrote:
>
> Add the compatible strings for the Naneng combo PHY found on rockchip SoC.
>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> ---
>
> Changes in v8: None
> Changes in v7:
> - remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel
>
> Changes in v5:
> - modify description for ssc and ext-refclk
> - remove apb reset
>
> Changes in v4:
> - restyle
> - remove some minItems
> - add more properties
> - remove reset-names
> - move #phy-cells
> - add rockchip,rk3568-pipe-grf
> - add rockchip,rk3568-pipe-phy-grf
>
> Changes in v3: None
> Changes in v2:
> - Fix dtschema/dtc warnings/errors
>
>  .../phy/phy-rockchip-naneng-combphy.yaml      | 109 ++++++++++++++++++
>  1 file changed, 109 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml

This now fails in linux-next:

/builds/robherring/linux-dt/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:
syscon@fdc50000: compatible: 'oneOf' conditional failed, one must be
fixed:
 ['rockchip,rk3568-pipe-grf', 'syscon'] is too short
 'rockchip,rk3568-pipe-grf' is not one of ['rockchip,rk3288-sgrf',
'rockchip,rk3568-usb2phy-grf', 'rockchip,rv1108-usbgrf']
From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
/builds/robherring/linux-dt/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:
syscon@fdc70000: compatible: 'oneOf' conditional failed, one must be
fixed:
 ['rockchip,rk3568-pipe-phy-grf', 'syscon'] is too short
 'rockchip,rk3568-pipe-phy-grf' is not one of ['rockchip,rk3288-sgrf',
'rockchip,rk3568-usb2phy-grf', 'rockchip,rv1108-usbgrf']
From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/rockchip/grf.yaml


The problem appears to be that patch 1 was applied incorrectly and the
compatibles ended up in the wrong section (the one requiring
'simple-mfd'). Patch 1 probably conflicts as my bot will just skip the
patch if it conflicts which is why this had a different error report.

Rob

Re: [PATCH v8 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings

[Rob Herring]

On Tue, Feb 8, 2022 at 3:15 AM Yifeng Zhao <yifeng.zhao@rock-chips.com> wrote:
>
> Add the compatible strings for the Naneng combo PHY found on rockchip SoC.
>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> ---
>
> Changes in v8: None
> Changes in v7:
> - remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel
>
> Changes in v5:
> - modify description for ssc and ext-refclk
> - remove apb reset
>
> Changes in v4:
> - restyle
> - remove some minItems
> - add more properties
> - remove reset-names
> - move #phy-cells
> - add rockchip,rk3568-pipe-grf
> - add rockchip,rk3568-pipe-phy-grf
>
> Changes in v3: None
> Changes in v2:
> - Fix dtschema/dtc warnings/errors
>
>  .../phy/phy-rockchip-naneng-combphy.yaml      | 109 ++++++++++++++++++
>  1 file changed, 109 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml

This now fails in linux-next:

/builds/robherring/linux-dt/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:
syscon@fdc50000: compatible: 'oneOf' conditional failed, one must be
fixed:
 ['rockchip,rk3568-pipe-grf', 'syscon'] is too short
 'rockchip,rk3568-pipe-grf' is not one of ['rockchip,rk3288-sgrf',
'rockchip,rk3568-usb2phy-grf', 'rockchip,rv1108-usbgrf']
From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
/builds/robherring/linux-dt/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:
syscon@fdc70000: compatible: 'oneOf' conditional failed, one must be
fixed:
 ['rockchip,rk3568-pipe-phy-grf', 'syscon'] is too short
 'rockchip,rk3568-pipe-phy-grf' is not one of ['rockchip,rk3288-sgrf',
'rockchip,rk3568-usb2phy-grf', 'rockchip,rv1108-usbgrf']
From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/rockchip/grf.yaml


The problem appears to be that patch 1 was applied incorrectly and the
compatibles ended up in the wrong section (the one requiring
'simple-mfd'). Patch 1 probably conflicts as my bot will just skip the
patch if it conflicts which is why this had a different error report.

Rob

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v8 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings

[Rob Herring]

On Tue, Feb 8, 2022 at 3:15 AM Yifeng Zhao <yifeng.zhao@rock-chips.com> wrote:
>
> Add the compatible strings for the Naneng combo PHY found on rockchip SoC.
>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> ---
>
> Changes in v8: None
> Changes in v7:
> - remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel
>
> Changes in v5:
> - modify description for ssc and ext-refclk
> - remove apb reset
>
> Changes in v4:
> - restyle
> - remove some minItems
> - add more properties
> - remove reset-names
> - move #phy-cells
> - add rockchip,rk3568-pipe-grf
> - add rockchip,rk3568-pipe-phy-grf
>
> Changes in v3: None
> Changes in v2:
> - Fix dtschema/dtc warnings/errors
>
>  .../phy/phy-rockchip-naneng-combphy.yaml      | 109 ++++++++++++++++++
>  1 file changed, 109 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml

This now fails in linux-next:

/builds/robherring/linux-dt/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:
syscon@fdc50000: compatible: 'oneOf' conditional failed, one must be
fixed:
 ['rockchip,rk3568-pipe-grf', 'syscon'] is too short
 'rockchip,rk3568-pipe-grf' is not one of ['rockchip,rk3288-sgrf',
'rockchip,rk3568-usb2phy-grf', 'rockchip,rv1108-usbgrf']
From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
/builds/robherring/linux-dt/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:
syscon@fdc70000: compatible: 'oneOf' conditional failed, one must be
fixed:
 ['rockchip,rk3568-pipe-phy-grf', 'syscon'] is too short
 'rockchip,rk3568-pipe-phy-grf' is not one of ['rockchip,rk3288-sgrf',
'rockchip,rk3568-usb2phy-grf', 'rockchip,rv1108-usbgrf']
From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/rockchip/grf.yaml


The problem appears to be that patch 1 was applied incorrectly and the
compatibles ended up in the wrong section (the one requiring
'simple-mfd'). Patch 1 probably conflicts as my bot will just skip the
patch if it conflicts which is why this had a different error report.

Rob

-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

Re: [PATCH v8 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings

[Rob Herring]

On Tue, Feb 8, 2022 at 3:15 AM Yifeng Zhao <yifeng.zhao@rock-chips.com> wrote:
>
> Add the compatible strings for the Naneng combo PHY found on rockchip SoC.
>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> ---
>
> Changes in v8: None
> Changes in v7:
> - remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel
>
> Changes in v5:
> - modify description for ssc and ext-refclk
> - remove apb reset
>
> Changes in v4:
> - restyle
> - remove some minItems
> - add more properties
> - remove reset-names
> - move #phy-cells
> - add rockchip,rk3568-pipe-grf
> - add rockchip,rk3568-pipe-phy-grf
>
> Changes in v3: None
> Changes in v2:
> - Fix dtschema/dtc warnings/errors
>
>  .../phy/phy-rockchip-naneng-combphy.yaml      | 109 ++++++++++++++++++
>  1 file changed, 109 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml

This now fails in linux-next:

/builds/robherring/linux-dt/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:
syscon@fdc50000: compatible: 'oneOf' conditional failed, one must be
fixed:
 ['rockchip,rk3568-pipe-grf', 'syscon'] is too short
 'rockchip,rk3568-pipe-grf' is not one of ['rockchip,rk3288-sgrf',
'rockchip,rk3568-usb2phy-grf', 'rockchip,rv1108-usbgrf']
From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
/builds/robherring/linux-dt/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:
syscon@fdc70000: compatible: 'oneOf' conditional failed, one must be
fixed:
 ['rockchip,rk3568-pipe-phy-grf', 'syscon'] is too short
 'rockchip,rk3568-pipe-phy-grf' is not one of ['rockchip,rk3288-sgrf',
'rockchip,rk3568-usb2phy-grf', 'rockchip,rv1108-usbgrf']
From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/rockchip/grf.yaml


The problem appears to be that patch 1 was applied incorrectly and the
compatibles ended up in the wrong section (the one requiring
'simple-mfd'). Patch 1 probably conflicts as my bot will just skip the
patch if it conflicts which is why this had a different error report.

Rob

_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

Re: [PATCH v8 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings

[Peter Geis]

On Mon, Feb 28, 2022 at 2:18 PM Rob Herring <robh+dt@kernel.org> wrote:
>
> On Tue, Feb 8, 2022 at 3:15 AM Yifeng Zhao <yifeng.zhao@rock-chips.com> wrote:
> >
> > Add the compatible strings for the Naneng combo PHY found on rockchip SoC.
> >
> > Reviewed-by: Rob Herring <robh@kernel.org>
> > Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
> > Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> > ---
> >
> > Changes in v8: None
> > Changes in v7:
> > - remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel
> >
> > Changes in v5:
> > - modify description for ssc and ext-refclk
> > - remove apb reset
> >
> > Changes in v4:
> > - restyle
> > - remove some minItems
> > - add more properties
> > - remove reset-names
> > - move #phy-cells
> > - add rockchip,rk3568-pipe-grf
> > - add rockchip,rk3568-pipe-phy-grf
> >
> > Changes in v3: None
> > Changes in v2:
> > - Fix dtschema/dtc warnings/errors
> >
> >  .../phy/phy-rockchip-naneng-combphy.yaml      | 109 ++++++++++++++++++
> >  1 file changed, 109 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
>
> This now fails in linux-next:
>
> /builds/robherring/linux-dt/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:
> syscon@fdc50000: compatible: 'oneOf' conditional failed, one must be
> fixed:
>  ['rockchip,rk3568-pipe-grf', 'syscon'] is too short
>  'rockchip,rk3568-pipe-grf' is not one of ['rockchip,rk3288-sgrf',
> 'rockchip,rk3568-usb2phy-grf', 'rockchip,rv1108-usbgrf']
> From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> /builds/robherring/linux-dt/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:
> syscon@fdc70000: compatible: 'oneOf' conditional failed, one must be
> fixed:
>  ['rockchip,rk3568-pipe-phy-grf', 'syscon'] is too short
>  'rockchip,rk3568-pipe-phy-grf' is not one of ['rockchip,rk3288-sgrf',
> 'rockchip,rk3568-usb2phy-grf', 'rockchip,rv1108-usbgrf']
> From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
>
>
> The problem appears to be that patch 1 was applied incorrectly and the
> compatibles ended up in the wrong section (the one requiring
> 'simple-mfd'). Patch 1 probably conflicts as my bot will just skip the
> patch if it conflicts which is why this had a different error report.

Good Afternoon Rob,

This is fixed in the first patch of my rk356x dwc3 enablement series:
https://patchwork.kernel.org/project/linux-rockchip/patch/20220228135700.1089526-2-pgwipeout@gmail.com/

Very Respectfully,
Peter Geis

>
> Rob
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip

Re: [PATCH v8 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings

[Peter Geis]

On Mon, Feb 28, 2022 at 2:18 PM Rob Herring <robh+dt@kernel.org> wrote:
>
> On Tue, Feb 8, 2022 at 3:15 AM Yifeng Zhao <yifeng.zhao@rock-chips.com> wrote:
> >
> > Add the compatible strings for the Naneng combo PHY found on rockchip SoC.
> >
> > Reviewed-by: Rob Herring <robh@kernel.org>
> > Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
> > Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> > ---
> >
> > Changes in v8: None
> > Changes in v7:
> > - remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel
> >
> > Changes in v5:
> > - modify description for ssc and ext-refclk
> > - remove apb reset
> >
> > Changes in v4:
> > - restyle
> > - remove some minItems
> > - add more properties
> > - remove reset-names
> > - move #phy-cells
> > - add rockchip,rk3568-pipe-grf
> > - add rockchip,rk3568-pipe-phy-grf
> >
> > Changes in v3: None
> > Changes in v2:
> > - Fix dtschema/dtc warnings/errors
> >
> >  .../phy/phy-rockchip-naneng-combphy.yaml      | 109 ++++++++++++++++++
> >  1 file changed, 109 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
>
> This now fails in linux-next:
>
> /builds/robherring/linux-dt/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:
> syscon@fdc50000: compatible: 'oneOf' conditional failed, one must be
> fixed:
>  ['rockchip,rk3568-pipe-grf', 'syscon'] is too short
>  'rockchip,rk3568-pipe-grf' is not one of ['rockchip,rk3288-sgrf',
> 'rockchip,rk3568-usb2phy-grf', 'rockchip,rv1108-usbgrf']
> From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> /builds/robherring/linux-dt/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:
> syscon@fdc70000: compatible: 'oneOf' conditional failed, one must be
> fixed:
>  ['rockchip,rk3568-pipe-phy-grf', 'syscon'] is too short
>  'rockchip,rk3568-pipe-phy-grf' is not one of ['rockchip,rk3288-sgrf',
> 'rockchip,rk3568-usb2phy-grf', 'rockchip,rv1108-usbgrf']
> From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
>
>
> The problem appears to be that patch 1 was applied incorrectly and the
> compatibles ended up in the wrong section (the one requiring
> 'simple-mfd'). Patch 1 probably conflicts as my bot will just skip the
> patch if it conflicts which is why this had a different error report.

Good Afternoon Rob,

This is fixed in the first patch of my rk356x dwc3 enablement series:
https://patchwork.kernel.org/project/linux-rockchip/patch/20220228135700.1089526-2-pgwipeout@gmail.com/

Very Respectfully,
Peter Geis

>
> Rob
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v8 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings

[Peter Geis]

On Mon, Feb 28, 2022 at 2:18 PM Rob Herring <robh+dt@kernel.org> wrote:
>
> On Tue, Feb 8, 2022 at 3:15 AM Yifeng Zhao <yifeng.zhao@rock-chips.com> wrote:
> >
> > Add the compatible strings for the Naneng combo PHY found on rockchip SoC.
> >
> > Reviewed-by: Rob Herring <robh@kernel.org>
> > Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
> > Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> > ---
> >
> > Changes in v8: None
> > Changes in v7:
> > - remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel
> >
> > Changes in v5:
> > - modify description for ssc and ext-refclk
> > - remove apb reset
> >
> > Changes in v4:
> > - restyle
> > - remove some minItems
> > - add more properties
> > - remove reset-names
> > - move #phy-cells
> > - add rockchip,rk3568-pipe-grf
> > - add rockchip,rk3568-pipe-phy-grf
> >
> > Changes in v3: None
> > Changes in v2:
> > - Fix dtschema/dtc warnings/errors
> >
> >  .../phy/phy-rockchip-naneng-combphy.yaml      | 109 ++++++++++++++++++
> >  1 file changed, 109 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
>
> This now fails in linux-next:
>
> /builds/robherring/linux-dt/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:
> syscon@fdc50000: compatible: 'oneOf' conditional failed, one must be
> fixed:
>  ['rockchip,rk3568-pipe-grf', 'syscon'] is too short
>  'rockchip,rk3568-pipe-grf' is not one of ['rockchip,rk3288-sgrf',
> 'rockchip,rk3568-usb2phy-grf', 'rockchip,rv1108-usbgrf']
> From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> /builds/robherring/linux-dt/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:
> syscon@fdc70000: compatible: 'oneOf' conditional failed, one must be
> fixed:
>  ['rockchip,rk3568-pipe-phy-grf', 'syscon'] is too short
>  'rockchip,rk3568-pipe-phy-grf' is not one of ['rockchip,rk3288-sgrf',
> 'rockchip,rk3568-usb2phy-grf', 'rockchip,rv1108-usbgrf']
> From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
>
>
> The problem appears to be that patch 1 was applied incorrectly and the
> compatibles ended up in the wrong section (the one requiring
> 'simple-mfd'). Patch 1 probably conflicts as my bot will just skip the
> patch if it conflicts which is why this had a different error report.

Good Afternoon Rob,

This is fixed in the first patch of my rk356x dwc3 enablement series:
https://patchwork.kernel.org/project/linux-rockchip/patch/20220228135700.1089526-2-pgwipeout@gmail.com/

Very Respectfully,
Peter Geis

>
> Rob
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip

-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

Re: [PATCH v8 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings

[Peter Geis]

On Mon, Feb 28, 2022 at 2:18 PM Rob Herring <robh+dt@kernel.org> wrote:
>
> On Tue, Feb 8, 2022 at 3:15 AM Yifeng Zhao <yifeng.zhao@rock-chips.com> wrote:
> >
> > Add the compatible strings for the Naneng combo PHY found on rockchip SoC.
> >
> > Reviewed-by: Rob Herring <robh@kernel.org>
> > Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
> > Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> > ---
> >
> > Changes in v8: None
> > Changes in v7:
> > - remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel
> >
> > Changes in v5:
> > - modify description for ssc and ext-refclk
> > - remove apb reset
> >
> > Changes in v4:
> > - restyle
> > - remove some minItems
> > - add more properties
> > - remove reset-names
> > - move #phy-cells
> > - add rockchip,rk3568-pipe-grf
> > - add rockchip,rk3568-pipe-phy-grf
> >
> > Changes in v3: None
> > Changes in v2:
> > - Fix dtschema/dtc warnings/errors
> >
> >  .../phy/phy-rockchip-naneng-combphy.yaml      | 109 ++++++++++++++++++
> >  1 file changed, 109 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
>
> This now fails in linux-next:
>
> /builds/robherring/linux-dt/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:
> syscon@fdc50000: compatible: 'oneOf' conditional failed, one must be
> fixed:
>  ['rockchip,rk3568-pipe-grf', 'syscon'] is too short
>  'rockchip,rk3568-pipe-grf' is not one of ['rockchip,rk3288-sgrf',
> 'rockchip,rk3568-usb2phy-grf', 'rockchip,rv1108-usbgrf']
> From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> /builds/robherring/linux-dt/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:
> syscon@fdc70000: compatible: 'oneOf' conditional failed, one must be
> fixed:
>  ['rockchip,rk3568-pipe-phy-grf', 'syscon'] is too short
>  'rockchip,rk3568-pipe-phy-grf' is not one of ['rockchip,rk3288-sgrf',
> 'rockchip,rk3568-usb2phy-grf', 'rockchip,rv1108-usbgrf']
> From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
>
>
> The problem appears to be that patch 1 was applied incorrectly and the
> compatibles ended up in the wrong section (the one requiring
> 'simple-mfd'). Patch 1 probably conflicts as my bot will just skip the
> patch if it conflicts which is why this had a different error report.

Good Afternoon Rob,

This is fixed in the first patch of my rk356x dwc3 enablement series:
https://patchwork.kernel.org/project/linux-rockchip/patch/20220228135700.1089526-2-pgwipeout@gmail.com/

Very Respectfully,
Peter Geis

>
> Rob
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip

_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

Re: [PATCH v8 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings

[Rob Herring]

On Mon, Feb 28, 2022 at 3:37 PM Peter Geis <pgwipeout@gmail.com> wrote:
>
> On Mon, Feb 28, 2022 at 2:18 PM Rob Herring <robh+dt@kernel.org> wrote:
> >
> > On Tue, Feb 8, 2022 at 3:15 AM Yifeng Zhao <yifeng.zhao@rock-chips.com> wrote:
> > >
> > > Add the compatible strings for the Naneng combo PHY found on rockchip SoC.
> > >
> > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
> > > Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> > > ---
> > >
> > > Changes in v8: None
> > > Changes in v7:
> > > - remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel
> > >
> > > Changes in v5:
> > > - modify description for ssc and ext-refclk
> > > - remove apb reset
> > >
> > > Changes in v4:
> > > - restyle
> > > - remove some minItems
> > > - add more properties
> > > - remove reset-names
> > > - move #phy-cells
> > > - add rockchip,rk3568-pipe-grf
> > > - add rockchip,rk3568-pipe-phy-grf
> > >
> > > Changes in v3: None
> > > Changes in v2:
> > > - Fix dtschema/dtc warnings/errors
> > >
> > >  .../phy/phy-rockchip-naneng-combphy.yaml      | 109 ++++++++++++++++++
> > >  1 file changed, 109 insertions(+)
> > >  create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
> >
> > This now fails in linux-next:
> >
> > /builds/robherring/linux-dt/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:
> > syscon@fdc50000: compatible: 'oneOf' conditional failed, one must be
> > fixed:
> >  ['rockchip,rk3568-pipe-grf', 'syscon'] is too short
> >  'rockchip,rk3568-pipe-grf' is not one of ['rockchip,rk3288-sgrf',
> > 'rockchip,rk3568-usb2phy-grf', 'rockchip,rv1108-usbgrf']
> > From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> > /builds/robherring/linux-dt/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:
> > syscon@fdc70000: compatible: 'oneOf' conditional failed, one must be
> > fixed:
> >  ['rockchip,rk3568-pipe-phy-grf', 'syscon'] is too short
> >  'rockchip,rk3568-pipe-phy-grf' is not one of ['rockchip,rk3288-sgrf',
> > 'rockchip,rk3568-usb2phy-grf', 'rockchip,rv1108-usbgrf']
> > From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> >
> >
> > The problem appears to be that patch 1 was applied incorrectly and the
> > compatibles ended up in the wrong section (the one requiring
> > 'simple-mfd'). Patch 1 probably conflicts as my bot will just skip the
> > patch if it conflicts which is why this had a different error report.
>
> Good Afternoon Rob,
>
> This is fixed in the first patch of my rk356x dwc3 enablement series:
> https://patchwork.kernel.org/project/linux-rockchip/patch/20220228135700.1089526-2-pgwipeout@gmail.com/

Where does that say Vinod incorrectly applied the original patch and
needs to apply it? What's the status of the series? Do we have to wait
for the rest of the series to be applied?

Rob

Re: [PATCH v8 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings

[Rob Herring]

On Mon, Feb 28, 2022 at 3:37 PM Peter Geis <pgwipeout@gmail.com> wrote:
>
> On Mon, Feb 28, 2022 at 2:18 PM Rob Herring <robh+dt@kernel.org> wrote:
> >
> > On Tue, Feb 8, 2022 at 3:15 AM Yifeng Zhao <yifeng.zhao@rock-chips.com> wrote:
> > >
> > > Add the compatible strings for the Naneng combo PHY found on rockchip SoC.
> > >
> > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
> > > Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> > > ---
> > >
> > > Changes in v8: None
> > > Changes in v7:
> > > - remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel
> > >
> > > Changes in v5:
> > > - modify description for ssc and ext-refclk
> > > - remove apb reset
> > >
> > > Changes in v4:
> > > - restyle
> > > - remove some minItems
> > > - add more properties
> > > - remove reset-names
> > > - move #phy-cells
> > > - add rockchip,rk3568-pipe-grf
> > > - add rockchip,rk3568-pipe-phy-grf
> > >
> > > Changes in v3: None
> > > Changes in v2:
> > > - Fix dtschema/dtc warnings/errors
> > >
> > >  .../phy/phy-rockchip-naneng-combphy.yaml      | 109 ++++++++++++++++++
> > >  1 file changed, 109 insertions(+)
> > >  create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
> >
> > This now fails in linux-next:
> >
> > /builds/robherring/linux-dt/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:
> > syscon@fdc50000: compatible: 'oneOf' conditional failed, one must be
> > fixed:
> >  ['rockchip,rk3568-pipe-grf', 'syscon'] is too short
> >  'rockchip,rk3568-pipe-grf' is not one of ['rockchip,rk3288-sgrf',
> > 'rockchip,rk3568-usb2phy-grf', 'rockchip,rv1108-usbgrf']
> > From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> > /builds/robherring/linux-dt/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:
> > syscon@fdc70000: compatible: 'oneOf' conditional failed, one must be
> > fixed:
> >  ['rockchip,rk3568-pipe-phy-grf', 'syscon'] is too short
> >  'rockchip,rk3568-pipe-phy-grf' is not one of ['rockchip,rk3288-sgrf',
> > 'rockchip,rk3568-usb2phy-grf', 'rockchip,rv1108-usbgrf']
> > From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> >
> >
> > The problem appears to be that patch 1 was applied incorrectly and the
> > compatibles ended up in the wrong section (the one requiring
> > 'simple-mfd'). Patch 1 probably conflicts as my bot will just skip the
> > patch if it conflicts which is why this had a different error report.
>
> Good Afternoon Rob,
>
> This is fixed in the first patch of my rk356x dwc3 enablement series:
> https://patchwork.kernel.org/project/linux-rockchip/patch/20220228135700.1089526-2-pgwipeout@gmail.com/

Where does that say Vinod incorrectly applied the original patch and
needs to apply it? What's the status of the series? Do we have to wait
for the rest of the series to be applied?

Rob

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v8 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings

[Rob Herring]

On Mon, Feb 28, 2022 at 3:37 PM Peter Geis <pgwipeout@gmail.com> wrote:
>
> On Mon, Feb 28, 2022 at 2:18 PM Rob Herring <robh+dt@kernel.org> wrote:
> >
> > On Tue, Feb 8, 2022 at 3:15 AM Yifeng Zhao <yifeng.zhao@rock-chips.com> wrote:
> > >
> > > Add the compatible strings for the Naneng combo PHY found on rockchip SoC.
> > >
> > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
> > > Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> > > ---
> > >
> > > Changes in v8: None
> > > Changes in v7:
> > > - remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel
> > >
> > > Changes in v5:
> > > - modify description for ssc and ext-refclk
> > > - remove apb reset
> > >
> > > Changes in v4:
> > > - restyle
> > > - remove some minItems
> > > - add more properties
> > > - remove reset-names
> > > - move #phy-cells
> > > - add rockchip,rk3568-pipe-grf
> > > - add rockchip,rk3568-pipe-phy-grf
> > >
> > > Changes in v3: None
> > > Changes in v2:
> > > - Fix dtschema/dtc warnings/errors
> > >
> > >  .../phy/phy-rockchip-naneng-combphy.yaml      | 109 ++++++++++++++++++
> > >  1 file changed, 109 insertions(+)
> > >  create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
> >
> > This now fails in linux-next:
> >
> > /builds/robherring/linux-dt/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:
> > syscon@fdc50000: compatible: 'oneOf' conditional failed, one must be
> > fixed:
> >  ['rockchip,rk3568-pipe-grf', 'syscon'] is too short
> >  'rockchip,rk3568-pipe-grf' is not one of ['rockchip,rk3288-sgrf',
> > 'rockchip,rk3568-usb2phy-grf', 'rockchip,rv1108-usbgrf']
> > From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> > /builds/robherring/linux-dt/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:
> > syscon@fdc70000: compatible: 'oneOf' conditional failed, one must be
> > fixed:
> >  ['rockchip,rk3568-pipe-phy-grf', 'syscon'] is too short
> >  'rockchip,rk3568-pipe-phy-grf' is not one of ['rockchip,rk3288-sgrf',
> > 'rockchip,rk3568-usb2phy-grf', 'rockchip,rv1108-usbgrf']
> > From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> >
> >
> > The problem appears to be that patch 1 was applied incorrectly and the
> > compatibles ended up in the wrong section (the one requiring
> > 'simple-mfd'). Patch 1 probably conflicts as my bot will just skip the
> > patch if it conflicts which is why this had a different error report.
>
> Good Afternoon Rob,
>
> This is fixed in the first patch of my rk356x dwc3 enablement series:
> https://patchwork.kernel.org/project/linux-rockchip/patch/20220228135700.1089526-2-pgwipeout@gmail.com/

Where does that say Vinod incorrectly applied the original patch and
needs to apply it? What's the status of the series? Do we have to wait
for the rest of the series to be applied?

Rob

_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

Re: [PATCH v8 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings

[Rob Herring]

On Mon, Feb 28, 2022 at 3:37 PM Peter Geis <pgwipeout@gmail.com> wrote:
>
> On Mon, Feb 28, 2022 at 2:18 PM Rob Herring <robh+dt@kernel.org> wrote:
> >
> > On Tue, Feb 8, 2022 at 3:15 AM Yifeng Zhao <yifeng.zhao@rock-chips.com> wrote:
> > >
> > > Add the compatible strings for the Naneng combo PHY found on rockchip SoC.
> > >
> > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
> > > Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> > > ---
> > >
> > > Changes in v8: None
> > > Changes in v7:
> > > - remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel
> > >
> > > Changes in v5:
> > > - modify description for ssc and ext-refclk
> > > - remove apb reset
> > >
> > > Changes in v4:
> > > - restyle
> > > - remove some minItems
> > > - add more properties
> > > - remove reset-names
> > > - move #phy-cells
> > > - add rockchip,rk3568-pipe-grf
> > > - add rockchip,rk3568-pipe-phy-grf
> > >
> > > Changes in v3: None
> > > Changes in v2:
> > > - Fix dtschema/dtc warnings/errors
> > >
> > >  .../phy/phy-rockchip-naneng-combphy.yaml      | 109 ++++++++++++++++++
> > >  1 file changed, 109 insertions(+)
> > >  create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
> >
> > This now fails in linux-next:
> >
> > /builds/robherring/linux-dt/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:
> > syscon@fdc50000: compatible: 'oneOf' conditional failed, one must be
> > fixed:
> >  ['rockchip,rk3568-pipe-grf', 'syscon'] is too short
> >  'rockchip,rk3568-pipe-grf' is not one of ['rockchip,rk3288-sgrf',
> > 'rockchip,rk3568-usb2phy-grf', 'rockchip,rv1108-usbgrf']
> > From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> > /builds/robherring/linux-dt/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:
> > syscon@fdc70000: compatible: 'oneOf' conditional failed, one must be
> > fixed:
> >  ['rockchip,rk3568-pipe-phy-grf', 'syscon'] is too short
> >  'rockchip,rk3568-pipe-phy-grf' is not one of ['rockchip,rk3288-sgrf',
> > 'rockchip,rk3568-usb2phy-grf', 'rockchip,rv1108-usbgrf']
> > From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> >
> >
> > The problem appears to be that patch 1 was applied incorrectly and the
> > compatibles ended up in the wrong section (the one requiring
> > 'simple-mfd'). Patch 1 probably conflicts as my bot will just skip the
> > patch if it conflicts which is why this had a different error report.
>
> Good Afternoon Rob,
>
> This is fixed in the first patch of my rk356x dwc3 enablement series:
> https://patchwork.kernel.org/project/linux-rockchip/patch/20220228135700.1089526-2-pgwipeout@gmail.com/

Where does that say Vinod incorrectly applied the original patch and
needs to apply it? What's the status of the series? Do we have to wait
for the rest of the series to be applied?

Rob

-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

Re: [PATCH v8 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings

[Vinod Koul]

On 01-03-22, 08:06, Rob Herring wrote:
> On Mon, Feb 28, 2022 at 3:37 PM Peter Geis <pgwipeout@gmail.com> wrote:
> >
> > On Mon, Feb 28, 2022 at 2:18 PM Rob Herring <robh+dt@kernel.org> wrote:
> > >
> > > On Tue, Feb 8, 2022 at 3:15 AM Yifeng Zhao <yifeng.zhao@rock-chips.com> wrote:
> > > >
> > > > Add the compatible strings for the Naneng combo PHY found on rockchip SoC.
> > > >
> > > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > > Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
> > > > Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> > > > ---
> > > >
> > > > Changes in v8: None
> > > > Changes in v7:
> > > > - remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel
> > > >
> > > > Changes in v5:
> > > > - modify description for ssc and ext-refclk
> > > > - remove apb reset
> > > >
> > > > Changes in v4:
> > > > - restyle
> > > > - remove some minItems
> > > > - add more properties
> > > > - remove reset-names
> > > > - move #phy-cells
> > > > - add rockchip,rk3568-pipe-grf
> > > > - add rockchip,rk3568-pipe-phy-grf
> > > >
> > > > Changes in v3: None
> > > > Changes in v2:
> > > > - Fix dtschema/dtc warnings/errors
> > > >
> > > >  .../phy/phy-rockchip-naneng-combphy.yaml      | 109 ++++++++++++++++++
> > > >  1 file changed, 109 insertions(+)
> > > >  create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
> > >
> > > This now fails in linux-next:
> > >
> > > /builds/robherring/linux-dt/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:
> > > syscon@fdc50000: compatible: 'oneOf' conditional failed, one must be
> > > fixed:
> > >  ['rockchip,rk3568-pipe-grf', 'syscon'] is too short
> > >  'rockchip,rk3568-pipe-grf' is not one of ['rockchip,rk3288-sgrf',
> > > 'rockchip,rk3568-usb2phy-grf', 'rockchip,rv1108-usbgrf']
> > > From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> > > /builds/robherring/linux-dt/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:
> > > syscon@fdc70000: compatible: 'oneOf' conditional failed, one must be
> > > fixed:
> > >  ['rockchip,rk3568-pipe-phy-grf', 'syscon'] is too short
> > >  'rockchip,rk3568-pipe-phy-grf' is not one of ['rockchip,rk3288-sgrf',
> > > 'rockchip,rk3568-usb2phy-grf', 'rockchip,rv1108-usbgrf']
> > > From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> > >
> > >
> > > The problem appears to be that patch 1 was applied incorrectly and the
> > > compatibles ended up in the wrong section (the one requiring
> > > 'simple-mfd'). Patch 1 probably conflicts as my bot will just skip the
> > > patch if it conflicts which is why this had a different error report.
> >
> > Good Afternoon Rob,
> >
> > This is fixed in the first patch of my rk356x dwc3 enablement series:
> > https://patchwork.kernel.org/project/linux-rockchip/patch/20220228135700.1089526-2-pgwipeout@gmail.com/
> 
> Where does that say Vinod incorrectly applied the original patch and
> needs to apply it? What's the status of the series? Do we have to wait
> for the rest of the series to be applied?

Thanks for pointing that out, I can revert this patch so that corrected
one can be applied... Does that look better

-- 
~Vinod

Re: [PATCH v8 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings

[Vinod Koul]

On 01-03-22, 08:06, Rob Herring wrote:
> On Mon, Feb 28, 2022 at 3:37 PM Peter Geis <pgwipeout@gmail.com> wrote:
> >
> > On Mon, Feb 28, 2022 at 2:18 PM Rob Herring <robh+dt@kernel.org> wrote:
> > >
> > > On Tue, Feb 8, 2022 at 3:15 AM Yifeng Zhao <yifeng.zhao@rock-chips.com> wrote:
> > > >
> > > > Add the compatible strings for the Naneng combo PHY found on rockchip SoC.
> > > >
> > > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > > Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
> > > > Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> > > > ---
> > > >
> > > > Changes in v8: None
> > > > Changes in v7:
> > > > - remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel
> > > >
> > > > Changes in v5:
> > > > - modify description for ssc and ext-refclk
> > > > - remove apb reset
> > > >
> > > > Changes in v4:
> > > > - restyle
> > > > - remove some minItems
> > > > - add more properties
> > > > - remove reset-names
> > > > - move #phy-cells
> > > > - add rockchip,rk3568-pipe-grf
> > > > - add rockchip,rk3568-pipe-phy-grf
> > > >
> > > > Changes in v3: None
> > > > Changes in v2:
> > > > - Fix dtschema/dtc warnings/errors
> > > >
> > > >  .../phy/phy-rockchip-naneng-combphy.yaml      | 109 ++++++++++++++++++
> > > >  1 file changed, 109 insertions(+)
> > > >  create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
> > >
> > > This now fails in linux-next:
> > >
> > > /builds/robherring/linux-dt/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:
> > > syscon@fdc50000: compatible: 'oneOf' conditional failed, one must be
> > > fixed:
> > >  ['rockchip,rk3568-pipe-grf', 'syscon'] is too short
> > >  'rockchip,rk3568-pipe-grf' is not one of ['rockchip,rk3288-sgrf',
> > > 'rockchip,rk3568-usb2phy-grf', 'rockchip,rv1108-usbgrf']
> > > From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> > > /builds/robherring/linux-dt/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:
> > > syscon@fdc70000: compatible: 'oneOf' conditional failed, one must be
> > > fixed:
> > >  ['rockchip,rk3568-pipe-phy-grf', 'syscon'] is too short
> > >  'rockchip,rk3568-pipe-phy-grf' is not one of ['rockchip,rk3288-sgrf',
> > > 'rockchip,rk3568-usb2phy-grf', 'rockchip,rv1108-usbgrf']
> > > From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> > >
> > >
> > > The problem appears to be that patch 1 was applied incorrectly and the
> > > compatibles ended up in the wrong section (the one requiring
> > > 'simple-mfd'). Patch 1 probably conflicts as my bot will just skip the
> > > patch if it conflicts which is why this had a different error report.
> >
> > Good Afternoon Rob,
> >
> > This is fixed in the first patch of my rk356x dwc3 enablement series:
> > https://patchwork.kernel.org/project/linux-rockchip/patch/20220228135700.1089526-2-pgwipeout@gmail.com/
> 
> Where does that say Vinod incorrectly applied the original patch and
> needs to apply it? What's the status of the series? Do we have to wait
> for the rest of the series to be applied?

Thanks for pointing that out, I can revert this patch so that corrected
one can be applied... Does that look better

-- 
~Vinod

_______________________________________________
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Re: [PATCH v8 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings

[Vinod Koul]

On 01-03-22, 08:06, Rob Herring wrote:
> On Mon, Feb 28, 2022 at 3:37 PM Peter Geis <pgwipeout@gmail.com> wrote:
> >
> > On Mon, Feb 28, 2022 at 2:18 PM Rob Herring <robh+dt@kernel.org> wrote:
> > >
> > > On Tue, Feb 8, 2022 at 3:15 AM Yifeng Zhao <yifeng.zhao@rock-chips.com> wrote:
> > > >
> > > > Add the compatible strings for the Naneng combo PHY found on rockchip SoC.
> > > >
> > > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > > Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
> > > > Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> > > > ---
> > > >
> > > > Changes in v8: None
> > > > Changes in v7:
> > > > - remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel
> > > >
> > > > Changes in v5:
> > > > - modify description for ssc and ext-refclk
> > > > - remove apb reset
> > > >
> > > > Changes in v4:
> > > > - restyle
> > > > - remove some minItems
> > > > - add more properties
> > > > - remove reset-names
> > > > - move #phy-cells
> > > > - add rockchip,rk3568-pipe-grf
> > > > - add rockchip,rk3568-pipe-phy-grf
> > > >
> > > > Changes in v3: None
> > > > Changes in v2:
> > > > - Fix dtschema/dtc warnings/errors
> > > >
> > > >  .../phy/phy-rockchip-naneng-combphy.yaml      | 109 ++++++++++++++++++
> > > >  1 file changed, 109 insertions(+)
> > > >  create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
> > >
> > > This now fails in linux-next:
> > >
> > > /builds/robherring/linux-dt/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:
> > > syscon@fdc50000: compatible: 'oneOf' conditional failed, one must be
> > > fixed:
> > >  ['rockchip,rk3568-pipe-grf', 'syscon'] is too short
> > >  'rockchip,rk3568-pipe-grf' is not one of ['rockchip,rk3288-sgrf',
> > > 'rockchip,rk3568-usb2phy-grf', 'rockchip,rv1108-usbgrf']
> > > From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> > > /builds/robherring/linux-dt/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:
> > > syscon@fdc70000: compatible: 'oneOf' conditional failed, one must be
> > > fixed:
> > >  ['rockchip,rk3568-pipe-phy-grf', 'syscon'] is too short
> > >  'rockchip,rk3568-pipe-phy-grf' is not one of ['rockchip,rk3288-sgrf',
> > > 'rockchip,rk3568-usb2phy-grf', 'rockchip,rv1108-usbgrf']
> > > From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> > >
> > >
> > > The problem appears to be that patch 1 was applied incorrectly and the
> > > compatibles ended up in the wrong section (the one requiring
> > > 'simple-mfd'). Patch 1 probably conflicts as my bot will just skip the
> > > patch if it conflicts which is why this had a different error report.
> >
> > Good Afternoon Rob,
> >
> > This is fixed in the first patch of my rk356x dwc3 enablement series:
> > https://patchwork.kernel.org/project/linux-rockchip/patch/20220228135700.1089526-2-pgwipeout@gmail.com/
> 
> Where does that say Vinod incorrectly applied the original patch and
> needs to apply it? What's the status of the series? Do we have to wait
> for the rest of the series to be applied?

Thanks for pointing that out, I can revert this patch so that corrected
one can be applied... Does that look better

-- 
~Vinod

-- 
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https://lists.infradead.org/mailman/listinfo/linux-phy

Re: [PATCH v8 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings

[Vinod Koul]

On 01-03-22, 08:06, Rob Herring wrote:
> On Mon, Feb 28, 2022 at 3:37 PM Peter Geis <pgwipeout@gmail.com> wrote:
> >
> > On Mon, Feb 28, 2022 at 2:18 PM Rob Herring <robh+dt@kernel.org> wrote:
> > >
> > > On Tue, Feb 8, 2022 at 3:15 AM Yifeng Zhao <yifeng.zhao@rock-chips.com> wrote:
> > > >
> > > > Add the compatible strings for the Naneng combo PHY found on rockchip SoC.
> > > >
> > > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > > Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
> > > > Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> > > > ---
> > > >
> > > > Changes in v8: None
> > > > Changes in v7:
> > > > - remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel
> > > >
> > > > Changes in v5:
> > > > - modify description for ssc and ext-refclk
> > > > - remove apb reset
> > > >
> > > > Changes in v4:
> > > > - restyle
> > > > - remove some minItems
> > > > - add more properties
> > > > - remove reset-names
> > > > - move #phy-cells
> > > > - add rockchip,rk3568-pipe-grf
> > > > - add rockchip,rk3568-pipe-phy-grf
> > > >
> > > > Changes in v3: None
> > > > Changes in v2:
> > > > - Fix dtschema/dtc warnings/errors
> > > >
> > > >  .../phy/phy-rockchip-naneng-combphy.yaml      | 109 ++++++++++++++++++
> > > >  1 file changed, 109 insertions(+)
> > > >  create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
> > >
> > > This now fails in linux-next:
> > >
> > > /builds/robherring/linux-dt/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:
> > > syscon@fdc50000: compatible: 'oneOf' conditional failed, one must be
> > > fixed:
> > >  ['rockchip,rk3568-pipe-grf', 'syscon'] is too short
> > >  'rockchip,rk3568-pipe-grf' is not one of ['rockchip,rk3288-sgrf',
> > > 'rockchip,rk3568-usb2phy-grf', 'rockchip,rv1108-usbgrf']
> > > From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> > > /builds/robherring/linux-dt/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:
> > > syscon@fdc70000: compatible: 'oneOf' conditional failed, one must be
> > > fixed:
> > >  ['rockchip,rk3568-pipe-phy-grf', 'syscon'] is too short
> > >  'rockchip,rk3568-pipe-phy-grf' is not one of ['rockchip,rk3288-sgrf',
> > > 'rockchip,rk3568-usb2phy-grf', 'rockchip,rv1108-usbgrf']
> > > From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> > >
> > >
> > > The problem appears to be that patch 1 was applied incorrectly and the
> > > compatibles ended up in the wrong section (the one requiring
> > > 'simple-mfd'). Patch 1 probably conflicts as my bot will just skip the
> > > patch if it conflicts which is why this had a different error report.
> >
> > Good Afternoon Rob,
> >
> > This is fixed in the first patch of my rk356x dwc3 enablement series:
> > https://patchwork.kernel.org/project/linux-rockchip/patch/20220228135700.1089526-2-pgwipeout@gmail.com/
> 
> Where does that say Vinod incorrectly applied the original patch and
> needs to apply it? What's the status of the series? Do we have to wait
> for the rest of the series to be applied?

Thanks for pointing that out, I can revert this patch so that corrected
one can be applied... Does that look better

-- 
~Vinod

_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

[PATCH v8 3/4] phy: rockchip: add naneng combo phy for RK3568

[Yifeng Zhao]

This patch implements a combo phy driver for Rockchip SoCs
with NaNeng IP block. This phy can be used as pcie-phy, usb3-phy,
sata-phy or sgmii-phy.

Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---

Changes in v8:
- rename 'mode' to 'type'
- using devm_reset_control_array_get_exclusive
- move rockchip_combphy_set_mode into rockchip_combphy_init

Changes in v7:
- rename regs
- remove pipe_sgmii_mac_sel, u3otg0_port_en and u3otg1_port_en

Changes in v5:
- add rockchip_combphy_updatel()
- restyle

Changes in v4:
- restyle
- add devm_reset_control_array_get()
- remove clk structure
- change refclk DT parse
- change dev_err message
- add dot to phrase
- add ext_refclk variable
- add enable_ssc variable
- rename rockchip_combphy_param_write
- remove param_read
- replace rockchip-naneng-combphy driver name

Changes in v3:
- Using api devm_reset_control_get_optional_exclusive and dev_err_probe.
- Remove apb_rst.
- Redefine registers address.

Changes in v2:
- Using api devm_platform_get_and_ioremap_resource.
- Modify rockchip_combphy_set_Mode.
- Add some PHY registers definition.

 drivers/phy/rockchip/Kconfig                  |   8 +
 drivers/phy/rockchip/Makefile                 |   1 +
 .../rockchip/phy-rockchip-naneng-combphy.c    | 581 ++++++++++++++++++
 3 files changed, 590 insertions(+)
 create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c

diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
index e812adad7242..9022e395c056 100644
--- a/drivers/phy/rockchip/Kconfig
+++ b/drivers/phy/rockchip/Kconfig
@@ -66,6 +66,14 @@ config PHY_ROCKCHIP_INNO_DSIDPHY
 	  Enable this to support the Rockchip MIPI/LVDS/TTL PHY with
 	  Innosilicon IP block.
 
+config PHY_ROCKCHIP_NANENG_COMBO_PHY
+	tristate "Rockchip NANENG COMBO PHY Driver"
+	depends on ARCH_ROCKCHIP && OF
+	select GENERIC_PHY
+	help
+	  Enable this to support the Rockchip PCIe/USB3.0/SATA/QSGMII
+	  combo PHY with NaNeng IP block.
+
 config PHY_ROCKCHIP_PCIE
 	tristate "Rockchip PCIe PHY Driver"
 	depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST
diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
index f0eec212b2aa..a5041efb5b8f 100644
--- a/drivers/phy/rockchip/Makefile
+++ b/drivers/phy/rockchip/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY)	+= phy-rockchip-inno-csidphy.o
 obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY)	+= phy-rockchip-inno-dsidphy.o
 obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI)	+= phy-rockchip-inno-hdmi.o
 obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)	+= phy-rockchip-inno-usb2.o
+obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY)	+= phy-rockchip-naneng-combphy.o
 obj-$(CONFIG_PHY_ROCKCHIP_PCIE)		+= phy-rockchip-pcie.o
 obj-$(CONFIG_PHY_ROCKCHIP_TYPEC)	+= phy-rockchip-typec.o
 obj-$(CONFIG_PHY_ROCKCHIP_USB)		+= phy-rockchip-usb.o
diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
new file mode 100644
index 000000000000..7b213825fb5d
--- /dev/null
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -0,0 +1,581 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Rockchip PIPE USB3.0 PCIE SATA Combo Phy driver
+ *
+ * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/phy/phy.h>
+#include <linux/clk.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_device.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/units.h>
+
+#define BIT_WRITEABLE_SHIFT		16
+#define REF_CLOCK_24MHz			(24 * HZ_PER_MHZ)
+#define REF_CLOCK_25MHz			(25 * HZ_PER_MHZ)
+#define REF_CLOCK_100MHz		(100 * HZ_PER_MHZ)
+
+/* COMBO PHY REG */
+#define PHYREG6				0x14
+#define PHYREG6_PLL_DIV_MASK		GENMASK(7, 6)
+#define PHYREG6_PLL_DIV_SHIFT		6
+#define PHYREG6_PLL_DIV_2		1
+
+#define PHYREG7				0x18
+#define PHYREG7_TX_RTERM_MASK		GENMASK(7, 4)
+#define PHYREG7_TX_RTERM_SHIFT		4
+#define PHYREG7_TX_RTERM_50OHM		8
+#define PHYREG7_RX_RTERM_MASK		GENMASK(3, 0)
+#define PHYREG7_RX_RTERM_SHIFT		0
+#define PHYREG7_RX_RTERM_44OHM		15
+
+#define PHYREG8				0x1C
+#define PHYREG8_SSC_EN			BIT(4)
+
+#define PHYREG11			0x28
+#define PHYREG11_SU_TRIM_0_7		0xF0
+
+#define PHYREG12			0x2C
+#define PHYREG12_PLL_LPF_ADJ_VALUE	4
+
+#define PHYREG13			0x30
+#define PHYREG13_RESISTER_MASK		GENMASK(5, 4)
+#define PHYREG13_RESISTER_SHIFT		0x4
+#define PHYREG13_RESISTER_HIGH_Z	3
+#define PHYREG13_CKRCV_AMP0		BIT(7)
+
+#define PHYREG14			0x34
+#define PHYREG14_CKRCV_AMP1		BIT(0)
+
+#define PHYREG15			0x38
+#define PHYREG15_CTLE_EN		BIT(0)
+#define PHYREG15_SSC_CNT_MASK		GENMASK(7, 6)
+#define PHYREG15_SSC_CNT_SHIFT		6
+#define PHYREG15_SSC_CNT_VALUE		1
+
+#define PHYREG16			0x3C
+#define PHYREG16_SSC_CNT_VALUE		0x5f
+
+#define PHYREG18			0x44
+#define PHYREG18_PLL_LOOP		0x32
+
+#define PHYREG32			0x7C
+#define PHYREG32_SSC_MASK		GENMASK(7, 4)
+#define PHYREG32_SSC_DIR_SHIFT		4
+#define PHYREG32_SSC_UPWARD		0
+#define PHYREG32_SSC_DOWNWARD		1
+#define PHYREG32_SSC_OFFSET_SHIFT	6
+#define PHYREG32_SSC_OFFSET_500PPM	1
+
+#define PHYREG33			0x80
+#define PHYREG33_PLL_KVCO_MASK		GENMASK(4, 2)
+#define PHYREG33_PLL_KVCO_SHIFT		2
+#define PHYREG33_PLL_KVCO_VALUE		2
+
+struct rockchip_combphy_priv;
+
+struct combphy_reg {
+	u16 offset;
+	u16 bitend;
+	u16 bitstart;
+	u16 disable;
+	u16 enable;
+};
+
+struct rockchip_combphy_grfcfg {
+	struct combphy_reg pcie_mode_set;
+	struct combphy_reg usb_mode_set;
+	struct combphy_reg sgmii_mode_set;
+	struct combphy_reg qsgmii_mode_set;
+	struct combphy_reg pipe_rxterm_set;
+	struct combphy_reg pipe_txelec_set;
+	struct combphy_reg pipe_txcomp_set;
+	struct combphy_reg pipe_clk_25m;
+	struct combphy_reg pipe_clk_100m;
+	struct combphy_reg pipe_phymode_sel;
+	struct combphy_reg pipe_rate_sel;
+	struct combphy_reg pipe_rxterm_sel;
+	struct combphy_reg pipe_txelec_sel;
+	struct combphy_reg pipe_txcomp_sel;
+	struct combphy_reg pipe_clk_ext;
+	struct combphy_reg pipe_sel_usb;
+	struct combphy_reg pipe_sel_qsgmii;
+	struct combphy_reg pipe_phy_status;
+	struct combphy_reg con0_for_pcie;
+	struct combphy_reg con1_for_pcie;
+	struct combphy_reg con2_for_pcie;
+	struct combphy_reg con3_for_pcie;
+	struct combphy_reg con0_for_sata;
+	struct combphy_reg con1_for_sata;
+	struct combphy_reg con2_for_sata;
+	struct combphy_reg con3_for_sata;
+	struct combphy_reg pipe_con0_for_sata;
+	struct combphy_reg pipe_xpcs_phy_ready;
+};
+
+struct rockchip_combphy_cfg {
+	const struct rockchip_combphy_grfcfg *grfcfg;
+	int (*combphy_cfg)(struct rockchip_combphy_priv *priv);
+};
+
+struct rockchip_combphy_priv {
+	u8 type;
+	void __iomem *mmio;
+	int num_clks;
+	struct clk_bulk_data *clks;
+	struct device *dev;
+	struct regmap *pipe_grf;
+	struct regmap *phy_grf;
+	struct phy *phy;
+	struct reset_control *phy_rst;
+	const struct rockchip_combphy_cfg *cfg;
+	bool enable_ssc;
+	bool ext_refclk;
+	struct clk *refclk;
+};
+
+static void rockchip_combphy_updatel(struct rockchip_combphy_priv *priv,
+				     int mask, int val, int reg)
+{
+	unsigned int temp;
+
+	temp = readl(priv->mmio + reg);
+	temp = (temp & ~(mask)) | val;
+	writel(temp, priv->mmio + reg);
+}
+
+static int rockchip_combphy_param_write(struct regmap *base,
+					const struct combphy_reg *reg, bool en)
+{
+	u32 val, mask, tmp;
+
+	tmp = en ? reg->enable : reg->disable;
+	mask = GENMASK(reg->bitend, reg->bitstart);
+	val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
+
+	return regmap_write(base, reg->offset, val);
+}
+
+static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv)
+{
+	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
+	u32 mask, val;
+
+	mask = GENMASK(cfg->pipe_phy_status.bitend,
+		       cfg->pipe_phy_status.bitstart);
+
+	regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val);
+	val = (val & mask) >> cfg->pipe_phy_status.bitstart;
+
+	return val;
+}
+
+static int rockchip_combphy_init(struct phy *phy)
+{
+	struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
+	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
+	u32 val;
+	int ret;
+
+	ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
+	if (ret) {
+		dev_err(priv->dev, "failed to enable clks\n");
+		return ret;
+	}
+
+	switch (priv->type) {
+	case PHY_TYPE_PCIE:
+	case PHY_TYPE_USB3:
+	case PHY_TYPE_SATA:
+	case PHY_TYPE_SGMII:
+	case PHY_TYPE_QSGMII:
+		if (priv->cfg->combphy_cfg)
+			ret = priv->cfg->combphy_cfg(priv);
+		break;
+	default:
+		dev_err(priv->dev, "incompatible PHY type\n");
+		ret = -EINVAL;
+		break;
+	}
+
+	if (ret) {
+		dev_err(priv->dev, "failed to init phy for phy type %x\n", priv->type);
+		goto err_clk;
+	}
+
+	ret = reset_control_deassert(priv->phy_rst);
+	if (ret)
+		goto err_clk;
+
+	if (priv->type == PHY_TYPE_USB3) {
+		ret = readx_poll_timeout_atomic(rockchip_combphy_is_ready,
+						priv, val,
+						val == cfg->pipe_phy_status.enable,
+						10, 1000);
+		if (ret)
+			dev_warn(priv->dev, "wait phy status ready timeout\n");
+	}
+
+	return 0;
+
+err_clk:
+	clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
+
+	return ret;
+}
+
+static int rockchip_combphy_exit(struct phy *phy)
+{
+	struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
+
+	clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
+	reset_control_assert(priv->phy_rst);
+
+	return 0;
+}
+
+static const struct phy_ops rochchip_combphy_ops = {
+	.init = rockchip_combphy_init,
+	.exit = rockchip_combphy_exit,
+	.owner = THIS_MODULE,
+};
+
+static struct phy *rockchip_combphy_xlate(struct device *dev, struct of_phandle_args *args)
+{
+	struct rockchip_combphy_priv *priv = dev_get_drvdata(dev);
+
+	if (args->args_count != 1) {
+		dev_err(dev, "invalid number of arguments\n");
+		return ERR_PTR(-EINVAL);
+	}
+
+	if (priv->type != PHY_NONE && priv->type != args->args[0])
+		dev_warn(dev, "phy type select %d overwriting type %d\n",
+			 args->args[0], priv->type);
+
+	priv->type = args->args[0];
+
+	return priv->phy;
+}
+
+static int rockchip_combphy_parse_dt(struct device *dev, struct rockchip_combphy_priv *priv)
+{
+	int i;
+
+	priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);
+	if (priv->num_clks < 1)
+		return -EINVAL;
+
+	priv->refclk = NULL;
+	for (i = 0; i < priv->num_clks; i++) {
+		if (!strncmp(priv->clks[i].id, "ref", 3)) {
+			priv->refclk = priv->clks[i].clk;
+			break;
+		}
+	}
+
+	if (!priv->refclk) {
+		dev_err(dev, "no refclk found\n");
+		return -EINVAL;
+	}
+
+	priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-grf");
+	if (IS_ERR(priv->pipe_grf)) {
+		dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n");
+		return PTR_ERR(priv->pipe_grf);
+	}
+
+	priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-phy-grf");
+	if (IS_ERR(priv->phy_grf)) {
+		dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n");
+		return PTR_ERR(priv->phy_grf);
+	}
+
+	priv->enable_ssc = device_property_present(dev, "rockchip,enable-ssc");
+
+	priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk");
+
+	priv->phy_rst = devm_reset_control_array_get_exclusive(dev);
+	if (IS_ERR(priv->phy_rst))
+		return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n");
+
+	return 0;
+}
+
+static int rockchip_combphy_probe(struct platform_device *pdev)
+{
+	struct phy_provider *phy_provider;
+	struct device *dev = &pdev->dev;
+	struct rockchip_combphy_priv *priv;
+	const struct rockchip_combphy_cfg *phy_cfg;
+	struct resource *res;
+	int ret;
+
+	phy_cfg = of_device_get_match_data(dev);
+	if (!phy_cfg) {
+		dev_err(dev, "no OF match data provided\n");
+		return -EINVAL;
+	}
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
+	if (IS_ERR(priv->mmio)) {
+		ret = PTR_ERR(priv->mmio);
+		return ret;
+	}
+
+	priv->dev = dev;
+	priv->type = PHY_NONE;
+	priv->cfg = phy_cfg;
+
+	ret = rockchip_combphy_parse_dt(dev, priv);
+	if (ret)
+		return ret;
+
+	ret = reset_control_assert(priv->phy_rst);
+	if (ret) {
+		dev_err(dev, "failed to reset phy\n");
+		return ret;
+	}
+
+	priv->phy = devm_phy_create(dev, NULL, &rochchip_combphy_ops);
+	if (IS_ERR(priv->phy)) {
+		dev_err(dev, "failed to create combphy\n");
+		return PTR_ERR(priv->phy);
+	}
+
+	dev_set_drvdata(dev, priv);
+	phy_set_drvdata(priv->phy, priv);
+
+	phy_provider = devm_of_phy_provider_register(dev, rockchip_combphy_xlate);
+
+	return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
+{
+	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
+	unsigned long rate;
+	u32 val;
+
+	switch (priv->type) {
+	case PHY_TYPE_PCIE:
+		/* Set SSC downward spread spectrum. */
+		rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
+					 PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
+					 PHYREG32);
+
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
+		break;
+
+	case PHY_TYPE_USB3:
+		/* Set SSC downward spread spectrum. */
+		rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
+					 PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
+					 PHYREG32);
+
+		/* Enable adaptive CTLE for USB3.0 Rx. */
+		val = readl(priv->mmio + PHYREG15);
+		val |= PHYREG15_CTLE_EN;
+		writel(val, priv->mmio + PHYREG15);
+
+		/* Set PLL KVCO fine tuning signals. */
+		rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
+					 PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT,
+					 PHYREG33);
+
+		/* Enable controlling random jitter. */
+		writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
+
+		/* Set PLL input clock divider 1/2. */
+		rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
+					 PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT,
+					 PHYREG6);
+
+		writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
+		writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
+
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true);
+		break;
+
+	case PHY_TYPE_SATA:
+		/* Enable adaptive CTLE for SATA Rx. */
+		val = readl(priv->mmio + PHYREG15);
+		val |= PHYREG15_CTLE_EN;
+		writel(val, priv->mmio + PHYREG15);
+		/*
+		 * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA.
+		 * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm)
+		 */
+		val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT;
+		val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT;
+		writel(val, priv->mmio + PHYREG7);
+
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true);
+		rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
+		break;
+
+	case PHY_TYPE_SGMII:
+		rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->sgmii_mode_set, true);
+		break;
+
+	case PHY_TYPE_QSGMII:
+		rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_rate_sel, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true);
+		break;
+
+	default:
+		dev_err(priv->dev, "incompatible PHY type\n");
+		return -EINVAL;
+	}
+
+	rate = clk_get_rate(priv->refclk);
+
+	switch (rate) {
+	case REF_CLOCK_24MHz:
+		if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) {
+			/* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */
+			val = PHYREG15_SSC_CNT_VALUE << PHYREG15_SSC_CNT_SHIFT;
+			rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK,
+						 val, PHYREG15);
+
+			writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
+		}
+		break;
+
+	case REF_CLOCK_25MHz:
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
+		break;
+
+	case REF_CLOCK_100MHz:
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
+		if (priv->type == PHY_TYPE_PCIE) {
+			/* PLL KVCO  fine tuning. */
+			val = PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT;
+			rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
+						 val, PHYREG33);
+
+			/* Enable controlling random jitter. */
+			writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
+
+			val = PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT;
+			rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
+						 val, PHYREG6);
+
+			writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
+			writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
+		} else if (priv->type == PHY_TYPE_SATA) {
+			/* downward spread spectrum +500ppm */
+			val = PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT;
+			val |= PHYREG32_SSC_OFFSET_500PPM << PHYREG32_SSC_OFFSET_SHIFT;
+			rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
+		}
+		break;
+
+	default:
+		dev_err(priv->dev, "unsupported rate: %lu\n", rate);
+		return -EINVAL;
+	}
+
+	if (priv->ext_refclk) {
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
+		if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
+			val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT;
+			val |= PHYREG13_CKRCV_AMP0;
+			rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13);
+
+			val = readl(priv->mmio + PHYREG14);
+			val |= PHYREG14_CKRCV_AMP1;
+			writel(val, priv->mmio + PHYREG14);
+		}
+	}
+
+	if (priv->enable_ssc) {
+		val = readl(priv->mmio + PHYREG8);
+		val |= PHYREG8_SSC_EN;
+		writel(val, priv->mmio + PHYREG8);
+	}
+
+	return 0;
+}
+
+static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = {
+	/* pipe-phy-grf */
+	.pcie_mode_set		= { 0x0000, 5, 0, 0x00, 0x11 },
+	.usb_mode_set		= { 0x0000, 5, 0, 0x00, 0x04 },
+	.sgmii_mode_set		= { 0x0000, 5, 0, 0x00, 0x01 },
+	.qsgmii_mode_set	= { 0x0000, 5, 0, 0x00, 0x21 },
+	.pipe_rxterm_set	= { 0x0000, 12, 12, 0x00, 0x01 },
+	.pipe_txelec_set	= { 0x0004, 1, 1, 0x00, 0x01 },
+	.pipe_txcomp_set	= { 0x0004, 4, 4, 0x00, 0x01 },
+	.pipe_clk_25m		= { 0x0004, 14, 13, 0x00, 0x01 },
+	.pipe_clk_100m		= { 0x0004, 14, 13, 0x00, 0x02 },
+	.pipe_phymode_sel	= { 0x0008, 1, 1, 0x00, 0x01 },
+	.pipe_rate_sel		= { 0x0008, 2, 2, 0x00, 0x01 },
+	.pipe_rxterm_sel	= { 0x0008, 8, 8, 0x00, 0x01 },
+	.pipe_txelec_sel	= { 0x0008, 12, 12, 0x00, 0x01 },
+	.pipe_txcomp_sel	= { 0x0008, 15, 15, 0x00, 0x01 },
+	.pipe_clk_ext		= { 0x000c, 9, 8, 0x02, 0x01 },
+	.pipe_sel_usb		= { 0x000c, 14, 13, 0x00, 0x01 },
+	.pipe_sel_qsgmii	= { 0x000c, 15, 13, 0x00, 0x07 },
+	.pipe_phy_status	= { 0x0034, 6, 6, 0x01, 0x00 },
+	.con0_for_pcie		= { 0x0000, 15, 0, 0x00, 0x1000 },
+	.con1_for_pcie		= { 0x0004, 15, 0, 0x00, 0x0000 },
+	.con2_for_pcie		= { 0x0008, 15, 0, 0x00, 0x0101 },
+	.con3_for_pcie		= { 0x000c, 15, 0, 0x00, 0x0200 },
+	.con0_for_sata		= { 0x0000, 15, 0, 0x00, 0x0119 },
+	.con1_for_sata		= { 0x0004, 15, 0, 0x00, 0x0040 },
+	.con2_for_sata		= { 0x0008, 15, 0, 0x00, 0x80c3 },
+	.con3_for_sata		= { 0x000c, 15, 0, 0x00, 0x4407 },
+	/* pipe-grf */
+	.pipe_con0_for_sata	= { 0x0000, 15, 0, 0x00, 0x2220 },
+	.pipe_xpcs_phy_ready	= { 0x0040, 2, 2, 0x00, 0x01 },
+};
+
+static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {
+	.grfcfg		= &rk3568_combphy_grfcfgs,
+	.combphy_cfg	= rk3568_combphy_cfg,
+};
+
+static const struct of_device_id rockchip_combphy_of_match[] = {
+	{
+		.compatible = "rockchip,rk3568-naneng-combphy",
+		.data = &rk3568_combphy_cfgs,
+	},
+	{ },
+};
+MODULE_DEVICE_TABLE(of, rockchip_combphy_of_match);
+
+static struct platform_driver rockchip_combphy_driver = {
+	.probe	= rockchip_combphy_probe,
+	.driver = {
+		.name = "rockchip-naneng-combphy",
+		.of_match_table = rockchip_combphy_of_match,
+	},
+};
+module_platform_driver(rockchip_combphy_driver);
+
+MODULE_DESCRIPTION("Rockchip NANENG COMBPHY driver");
+MODULE_LICENSE("GPL v2");
-- 
2.17.1


_______________________________________________
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Linux-rockchip@lists.infradead.org
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[PATCH v8 3/4] phy: rockchip: add naneng combo phy for RK3568

[Yifeng Zhao]

This patch implements a combo phy driver for Rockchip SoCs
with NaNeng IP block. This phy can be used as pcie-phy, usb3-phy,
sata-phy or sgmii-phy.

Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---

Changes in v8:
- rename 'mode' to 'type'
- using devm_reset_control_array_get_exclusive
- move rockchip_combphy_set_mode into rockchip_combphy_init

Changes in v7:
- rename regs
- remove pipe_sgmii_mac_sel, u3otg0_port_en and u3otg1_port_en

Changes in v5:
- add rockchip_combphy_updatel()
- restyle

Changes in v4:
- restyle
- add devm_reset_control_array_get()
- remove clk structure
- change refclk DT parse
- change dev_err message
- add dot to phrase
- add ext_refclk variable
- add enable_ssc variable
- rename rockchip_combphy_param_write
- remove param_read
- replace rockchip-naneng-combphy driver name

Changes in v3:
- Using api devm_reset_control_get_optional_exclusive and dev_err_probe.
- Remove apb_rst.
- Redefine registers address.

Changes in v2:
- Using api devm_platform_get_and_ioremap_resource.
- Modify rockchip_combphy_set_Mode.
- Add some PHY registers definition.

 drivers/phy/rockchip/Kconfig                  |   8 +
 drivers/phy/rockchip/Makefile                 |   1 +
 .../rockchip/phy-rockchip-naneng-combphy.c    | 581 ++++++++++++++++++
 3 files changed, 590 insertions(+)
 create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c

diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
index e812adad7242..9022e395c056 100644
--- a/drivers/phy/rockchip/Kconfig
+++ b/drivers/phy/rockchip/Kconfig
@@ -66,6 +66,14 @@ config PHY_ROCKCHIP_INNO_DSIDPHY
 	  Enable this to support the Rockchip MIPI/LVDS/TTL PHY with
 	  Innosilicon IP block.
 
+config PHY_ROCKCHIP_NANENG_COMBO_PHY
+	tristate "Rockchip NANENG COMBO PHY Driver"
+	depends on ARCH_ROCKCHIP && OF
+	select GENERIC_PHY
+	help
+	  Enable this to support the Rockchip PCIe/USB3.0/SATA/QSGMII
+	  combo PHY with NaNeng IP block.
+
 config PHY_ROCKCHIP_PCIE
 	tristate "Rockchip PCIe PHY Driver"
 	depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST
diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
index f0eec212b2aa..a5041efb5b8f 100644
--- a/drivers/phy/rockchip/Makefile
+++ b/drivers/phy/rockchip/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY)	+= phy-rockchip-inno-csidphy.o
 obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY)	+= phy-rockchip-inno-dsidphy.o
 obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI)	+= phy-rockchip-inno-hdmi.o
 obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)	+= phy-rockchip-inno-usb2.o
+obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY)	+= phy-rockchip-naneng-combphy.o
 obj-$(CONFIG_PHY_ROCKCHIP_PCIE)		+= phy-rockchip-pcie.o
 obj-$(CONFIG_PHY_ROCKCHIP_TYPEC)	+= phy-rockchip-typec.o
 obj-$(CONFIG_PHY_ROCKCHIP_USB)		+= phy-rockchip-usb.o
diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
new file mode 100644
index 000000000000..7b213825fb5d
--- /dev/null
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -0,0 +1,581 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Rockchip PIPE USB3.0 PCIE SATA Combo Phy driver
+ *
+ * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/phy/phy.h>
+#include <linux/clk.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_device.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/units.h>
+
+#define BIT_WRITEABLE_SHIFT		16
+#define REF_CLOCK_24MHz			(24 * HZ_PER_MHZ)
+#define REF_CLOCK_25MHz			(25 * HZ_PER_MHZ)
+#define REF_CLOCK_100MHz		(100 * HZ_PER_MHZ)
+
+/* COMBO PHY REG */
+#define PHYREG6				0x14
+#define PHYREG6_PLL_DIV_MASK		GENMASK(7, 6)
+#define PHYREG6_PLL_DIV_SHIFT		6
+#define PHYREG6_PLL_DIV_2		1
+
+#define PHYREG7				0x18
+#define PHYREG7_TX_RTERM_MASK		GENMASK(7, 4)
+#define PHYREG7_TX_RTERM_SHIFT		4
+#define PHYREG7_TX_RTERM_50OHM		8
+#define PHYREG7_RX_RTERM_MASK		GENMASK(3, 0)
+#define PHYREG7_RX_RTERM_SHIFT		0
+#define PHYREG7_RX_RTERM_44OHM		15
+
+#define PHYREG8				0x1C
+#define PHYREG8_SSC_EN			BIT(4)
+
+#define PHYREG11			0x28
+#define PHYREG11_SU_TRIM_0_7		0xF0
+
+#define PHYREG12			0x2C
+#define PHYREG12_PLL_LPF_ADJ_VALUE	4
+
+#define PHYREG13			0x30
+#define PHYREG13_RESISTER_MASK		GENMASK(5, 4)
+#define PHYREG13_RESISTER_SHIFT		0x4
+#define PHYREG13_RESISTER_HIGH_Z	3
+#define PHYREG13_CKRCV_AMP0		BIT(7)
+
+#define PHYREG14			0x34
+#define PHYREG14_CKRCV_AMP1		BIT(0)
+
+#define PHYREG15			0x38
+#define PHYREG15_CTLE_EN		BIT(0)
+#define PHYREG15_SSC_CNT_MASK		GENMASK(7, 6)
+#define PHYREG15_SSC_CNT_SHIFT		6
+#define PHYREG15_SSC_CNT_VALUE		1
+
+#define PHYREG16			0x3C
+#define PHYREG16_SSC_CNT_VALUE		0x5f
+
+#define PHYREG18			0x44
+#define PHYREG18_PLL_LOOP		0x32
+
+#define PHYREG32			0x7C
+#define PHYREG32_SSC_MASK		GENMASK(7, 4)
+#define PHYREG32_SSC_DIR_SHIFT		4
+#define PHYREG32_SSC_UPWARD		0
+#define PHYREG32_SSC_DOWNWARD		1
+#define PHYREG32_SSC_OFFSET_SHIFT	6
+#define PHYREG32_SSC_OFFSET_500PPM	1
+
+#define PHYREG33			0x80
+#define PHYREG33_PLL_KVCO_MASK		GENMASK(4, 2)
+#define PHYREG33_PLL_KVCO_SHIFT		2
+#define PHYREG33_PLL_KVCO_VALUE		2
+
+struct rockchip_combphy_priv;
+
+struct combphy_reg {
+	u16 offset;
+	u16 bitend;
+	u16 bitstart;
+	u16 disable;
+	u16 enable;
+};
+
+struct rockchip_combphy_grfcfg {
+	struct combphy_reg pcie_mode_set;
+	struct combphy_reg usb_mode_set;
+	struct combphy_reg sgmii_mode_set;
+	struct combphy_reg qsgmii_mode_set;
+	struct combphy_reg pipe_rxterm_set;
+	struct combphy_reg pipe_txelec_set;
+	struct combphy_reg pipe_txcomp_set;
+	struct combphy_reg pipe_clk_25m;
+	struct combphy_reg pipe_clk_100m;
+	struct combphy_reg pipe_phymode_sel;
+	struct combphy_reg pipe_rate_sel;
+	struct combphy_reg pipe_rxterm_sel;
+	struct combphy_reg pipe_txelec_sel;
+	struct combphy_reg pipe_txcomp_sel;
+	struct combphy_reg pipe_clk_ext;
+	struct combphy_reg pipe_sel_usb;
+	struct combphy_reg pipe_sel_qsgmii;
+	struct combphy_reg pipe_phy_status;
+	struct combphy_reg con0_for_pcie;
+	struct combphy_reg con1_for_pcie;
+	struct combphy_reg con2_for_pcie;
+	struct combphy_reg con3_for_pcie;
+	struct combphy_reg con0_for_sata;
+	struct combphy_reg con1_for_sata;
+	struct combphy_reg con2_for_sata;
+	struct combphy_reg con3_for_sata;
+	struct combphy_reg pipe_con0_for_sata;
+	struct combphy_reg pipe_xpcs_phy_ready;
+};
+
+struct rockchip_combphy_cfg {
+	const struct rockchip_combphy_grfcfg *grfcfg;
+	int (*combphy_cfg)(struct rockchip_combphy_priv *priv);
+};
+
+struct rockchip_combphy_priv {
+	u8 type;
+	void __iomem *mmio;
+	int num_clks;
+	struct clk_bulk_data *clks;
+	struct device *dev;
+	struct regmap *pipe_grf;
+	struct regmap *phy_grf;
+	struct phy *phy;
+	struct reset_control *phy_rst;
+	const struct rockchip_combphy_cfg *cfg;
+	bool enable_ssc;
+	bool ext_refclk;
+	struct clk *refclk;
+};
+
+static void rockchip_combphy_updatel(struct rockchip_combphy_priv *priv,
+				     int mask, int val, int reg)
+{
+	unsigned int temp;
+
+	temp = readl(priv->mmio + reg);
+	temp = (temp & ~(mask)) | val;
+	writel(temp, priv->mmio + reg);
+}
+
+static int rockchip_combphy_param_write(struct regmap *base,
+					const struct combphy_reg *reg, bool en)
+{
+	u32 val, mask, tmp;
+
+	tmp = en ? reg->enable : reg->disable;
+	mask = GENMASK(reg->bitend, reg->bitstart);
+	val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
+
+	return regmap_write(base, reg->offset, val);
+}
+
+static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv)
+{
+	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
+	u32 mask, val;
+
+	mask = GENMASK(cfg->pipe_phy_status.bitend,
+		       cfg->pipe_phy_status.bitstart);
+
+	regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val);
+	val = (val & mask) >> cfg->pipe_phy_status.bitstart;
+
+	return val;
+}
+
+static int rockchip_combphy_init(struct phy *phy)
+{
+	struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
+	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
+	u32 val;
+	int ret;
+
+	ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
+	if (ret) {
+		dev_err(priv->dev, "failed to enable clks\n");
+		return ret;
+	}
+
+	switch (priv->type) {
+	case PHY_TYPE_PCIE:
+	case PHY_TYPE_USB3:
+	case PHY_TYPE_SATA:
+	case PHY_TYPE_SGMII:
+	case PHY_TYPE_QSGMII:
+		if (priv->cfg->combphy_cfg)
+			ret = priv->cfg->combphy_cfg(priv);
+		break;
+	default:
+		dev_err(priv->dev, "incompatible PHY type\n");
+		ret = -EINVAL;
+		break;
+	}
+
+	if (ret) {
+		dev_err(priv->dev, "failed to init phy for phy type %x\n", priv->type);
+		goto err_clk;
+	}
+
+	ret = reset_control_deassert(priv->phy_rst);
+	if (ret)
+		goto err_clk;
+
+	if (priv->type == PHY_TYPE_USB3) {
+		ret = readx_poll_timeout_atomic(rockchip_combphy_is_ready,
+						priv, val,
+						val == cfg->pipe_phy_status.enable,
+						10, 1000);
+		if (ret)
+			dev_warn(priv->dev, "wait phy status ready timeout\n");
+	}
+
+	return 0;
+
+err_clk:
+	clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
+
+	return ret;
+}
+
+static int rockchip_combphy_exit(struct phy *phy)
+{
+	struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
+
+	clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
+	reset_control_assert(priv->phy_rst);
+
+	return 0;
+}
+
+static const struct phy_ops rochchip_combphy_ops = {
+	.init = rockchip_combphy_init,
+	.exit = rockchip_combphy_exit,
+	.owner = THIS_MODULE,
+};
+
+static struct phy *rockchip_combphy_xlate(struct device *dev, struct of_phandle_args *args)
+{
+	struct rockchip_combphy_priv *priv = dev_get_drvdata(dev);
+
+	if (args->args_count != 1) {
+		dev_err(dev, "invalid number of arguments\n");
+		return ERR_PTR(-EINVAL);
+	}
+
+	if (priv->type != PHY_NONE && priv->type != args->args[0])
+		dev_warn(dev, "phy type select %d overwriting type %d\n",
+			 args->args[0], priv->type);
+
+	priv->type = args->args[0];
+
+	return priv->phy;
+}
+
+static int rockchip_combphy_parse_dt(struct device *dev, struct rockchip_combphy_priv *priv)
+{
+	int i;
+
+	priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);
+	if (priv->num_clks < 1)
+		return -EINVAL;
+
+	priv->refclk = NULL;
+	for (i = 0; i < priv->num_clks; i++) {
+		if (!strncmp(priv->clks[i].id, "ref", 3)) {
+			priv->refclk = priv->clks[i].clk;
+			break;
+		}
+	}
+
+	if (!priv->refclk) {
+		dev_err(dev, "no refclk found\n");
+		return -EINVAL;
+	}
+
+	priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-grf");
+	if (IS_ERR(priv->pipe_grf)) {
+		dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n");
+		return PTR_ERR(priv->pipe_grf);
+	}
+
+	priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-phy-grf");
+	if (IS_ERR(priv->phy_grf)) {
+		dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n");
+		return PTR_ERR(priv->phy_grf);
+	}
+
+	priv->enable_ssc = device_property_present(dev, "rockchip,enable-ssc");
+
+	priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk");
+
+	priv->phy_rst = devm_reset_control_array_get_exclusive(dev);
+	if (IS_ERR(priv->phy_rst))
+		return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n");
+
+	return 0;
+}
+
+static int rockchip_combphy_probe(struct platform_device *pdev)
+{
+	struct phy_provider *phy_provider;
+	struct device *dev = &pdev->dev;
+	struct rockchip_combphy_priv *priv;
+	const struct rockchip_combphy_cfg *phy_cfg;
+	struct resource *res;
+	int ret;
+
+	phy_cfg = of_device_get_match_data(dev);
+	if (!phy_cfg) {
+		dev_err(dev, "no OF match data provided\n");
+		return -EINVAL;
+	}
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
+	if (IS_ERR(priv->mmio)) {
+		ret = PTR_ERR(priv->mmio);
+		return ret;
+	}
+
+	priv->dev = dev;
+	priv->type = PHY_NONE;
+	priv->cfg = phy_cfg;
+
+	ret = rockchip_combphy_parse_dt(dev, priv);
+	if (ret)
+		return ret;
+
+	ret = reset_control_assert(priv->phy_rst);
+	if (ret) {
+		dev_err(dev, "failed to reset phy\n");
+		return ret;
+	}
+
+	priv->phy = devm_phy_create(dev, NULL, &rochchip_combphy_ops);
+	if (IS_ERR(priv->phy)) {
+		dev_err(dev, "failed to create combphy\n");
+		return PTR_ERR(priv->phy);
+	}
+
+	dev_set_drvdata(dev, priv);
+	phy_set_drvdata(priv->phy, priv);
+
+	phy_provider = devm_of_phy_provider_register(dev, rockchip_combphy_xlate);
+
+	return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
+{
+	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
+	unsigned long rate;
+	u32 val;
+
+	switch (priv->type) {
+	case PHY_TYPE_PCIE:
+		/* Set SSC downward spread spectrum. */
+		rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
+					 PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
+					 PHYREG32);
+
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
+		break;
+
+	case PHY_TYPE_USB3:
+		/* Set SSC downward spread spectrum. */
+		rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
+					 PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
+					 PHYREG32);
+
+		/* Enable adaptive CTLE for USB3.0 Rx. */
+		val = readl(priv->mmio + PHYREG15);
+		val |= PHYREG15_CTLE_EN;
+		writel(val, priv->mmio + PHYREG15);
+
+		/* Set PLL KVCO fine tuning signals. */
+		rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
+					 PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT,
+					 PHYREG33);
+
+		/* Enable controlling random jitter. */
+		writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
+
+		/* Set PLL input clock divider 1/2. */
+		rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
+					 PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT,
+					 PHYREG6);
+
+		writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
+		writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
+
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true);
+		break;
+
+	case PHY_TYPE_SATA:
+		/* Enable adaptive CTLE for SATA Rx. */
+		val = readl(priv->mmio + PHYREG15);
+		val |= PHYREG15_CTLE_EN;
+		writel(val, priv->mmio + PHYREG15);
+		/*
+		 * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA.
+		 * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm)
+		 */
+		val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT;
+		val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT;
+		writel(val, priv->mmio + PHYREG7);
+
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true);
+		rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
+		break;
+
+	case PHY_TYPE_SGMII:
+		rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->sgmii_mode_set, true);
+		break;
+
+	case PHY_TYPE_QSGMII:
+		rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_rate_sel, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true);
+		break;
+
+	default:
+		dev_err(priv->dev, "incompatible PHY type\n");
+		return -EINVAL;
+	}
+
+	rate = clk_get_rate(priv->refclk);
+
+	switch (rate) {
+	case REF_CLOCK_24MHz:
+		if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) {
+			/* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */
+			val = PHYREG15_SSC_CNT_VALUE << PHYREG15_SSC_CNT_SHIFT;
+			rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK,
+						 val, PHYREG15);
+
+			writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
+		}
+		break;
+
+	case REF_CLOCK_25MHz:
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
+		break;
+
+	case REF_CLOCK_100MHz:
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
+		if (priv->type == PHY_TYPE_PCIE) {
+			/* PLL KVCO  fine tuning. */
+			val = PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT;
+			rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
+						 val, PHYREG33);
+
+			/* Enable controlling random jitter. */
+			writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
+
+			val = PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT;
+			rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
+						 val, PHYREG6);
+
+			writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
+			writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
+		} else if (priv->type == PHY_TYPE_SATA) {
+			/* downward spread spectrum +500ppm */
+			val = PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT;
+			val |= PHYREG32_SSC_OFFSET_500PPM << PHYREG32_SSC_OFFSET_SHIFT;
+			rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
+		}
+		break;
+
+	default:
+		dev_err(priv->dev, "unsupported rate: %lu\n", rate);
+		return -EINVAL;
+	}
+
+	if (priv->ext_refclk) {
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
+		if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
+			val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT;
+			val |= PHYREG13_CKRCV_AMP0;
+			rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13);
+
+			val = readl(priv->mmio + PHYREG14);
+			val |= PHYREG14_CKRCV_AMP1;
+			writel(val, priv->mmio + PHYREG14);
+		}
+	}
+
+	if (priv->enable_ssc) {
+		val = readl(priv->mmio + PHYREG8);
+		val |= PHYREG8_SSC_EN;
+		writel(val, priv->mmio + PHYREG8);
+	}
+
+	return 0;
+}
+
+static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = {
+	/* pipe-phy-grf */
+	.pcie_mode_set		= { 0x0000, 5, 0, 0x00, 0x11 },
+	.usb_mode_set		= { 0x0000, 5, 0, 0x00, 0x04 },
+	.sgmii_mode_set		= { 0x0000, 5, 0, 0x00, 0x01 },
+	.qsgmii_mode_set	= { 0x0000, 5, 0, 0x00, 0x21 },
+	.pipe_rxterm_set	= { 0x0000, 12, 12, 0x00, 0x01 },
+	.pipe_txelec_set	= { 0x0004, 1, 1, 0x00, 0x01 },
+	.pipe_txcomp_set	= { 0x0004, 4, 4, 0x00, 0x01 },
+	.pipe_clk_25m		= { 0x0004, 14, 13, 0x00, 0x01 },
+	.pipe_clk_100m		= { 0x0004, 14, 13, 0x00, 0x02 },
+	.pipe_phymode_sel	= { 0x0008, 1, 1, 0x00, 0x01 },
+	.pipe_rate_sel		= { 0x0008, 2, 2, 0x00, 0x01 },
+	.pipe_rxterm_sel	= { 0x0008, 8, 8, 0x00, 0x01 },
+	.pipe_txelec_sel	= { 0x0008, 12, 12, 0x00, 0x01 },
+	.pipe_txcomp_sel	= { 0x0008, 15, 15, 0x00, 0x01 },
+	.pipe_clk_ext		= { 0x000c, 9, 8, 0x02, 0x01 },
+	.pipe_sel_usb		= { 0x000c, 14, 13, 0x00, 0x01 },
+	.pipe_sel_qsgmii	= { 0x000c, 15, 13, 0x00, 0x07 },
+	.pipe_phy_status	= { 0x0034, 6, 6, 0x01, 0x00 },
+	.con0_for_pcie		= { 0x0000, 15, 0, 0x00, 0x1000 },
+	.con1_for_pcie		= { 0x0004, 15, 0, 0x00, 0x0000 },
+	.con2_for_pcie		= { 0x0008, 15, 0, 0x00, 0x0101 },
+	.con3_for_pcie		= { 0x000c, 15, 0, 0x00, 0x0200 },
+	.con0_for_sata		= { 0x0000, 15, 0, 0x00, 0x0119 },
+	.con1_for_sata		= { 0x0004, 15, 0, 0x00, 0x0040 },
+	.con2_for_sata		= { 0x0008, 15, 0, 0x00, 0x80c3 },
+	.con3_for_sata		= { 0x000c, 15, 0, 0x00, 0x4407 },
+	/* pipe-grf */
+	.pipe_con0_for_sata	= { 0x0000, 15, 0, 0x00, 0x2220 },
+	.pipe_xpcs_phy_ready	= { 0x0040, 2, 2, 0x00, 0x01 },
+};
+
+static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {
+	.grfcfg		= &rk3568_combphy_grfcfgs,
+	.combphy_cfg	= rk3568_combphy_cfg,
+};
+
+static const struct of_device_id rockchip_combphy_of_match[] = {
+	{
+		.compatible = "rockchip,rk3568-naneng-combphy",
+		.data = &rk3568_combphy_cfgs,
+	},
+	{ },
+};
+MODULE_DEVICE_TABLE(of, rockchip_combphy_of_match);
+
+static struct platform_driver rockchip_combphy_driver = {
+	.probe	= rockchip_combphy_probe,
+	.driver = {
+		.name = "rockchip-naneng-combphy",
+		.of_match_table = rockchip_combphy_of_match,
+	},
+};
+module_platform_driver(rockchip_combphy_driver);
+
+MODULE_DESCRIPTION("Rockchip NANENG COMBPHY driver");
+MODULE_LICENSE("GPL v2");
-- 
2.17.1

[PATCH v8 3/4] phy: rockchip: add naneng combo phy for RK3568

[Yifeng Zhao]

This patch implements a combo phy driver for Rockchip SoCs
with NaNeng IP block. This phy can be used as pcie-phy, usb3-phy,
sata-phy or sgmii-phy.

Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---

Changes in v8:
- rename 'mode' to 'type'
- using devm_reset_control_array_get_exclusive
- move rockchip_combphy_set_mode into rockchip_combphy_init

Changes in v7:
- rename regs
- remove pipe_sgmii_mac_sel, u3otg0_port_en and u3otg1_port_en

Changes in v5:
- add rockchip_combphy_updatel()
- restyle

Changes in v4:
- restyle
- add devm_reset_control_array_get()
- remove clk structure
- change refclk DT parse
- change dev_err message
- add dot to phrase
- add ext_refclk variable
- add enable_ssc variable
- rename rockchip_combphy_param_write
- remove param_read
- replace rockchip-naneng-combphy driver name

Changes in v3:
- Using api devm_reset_control_get_optional_exclusive and dev_err_probe.
- Remove apb_rst.
- Redefine registers address.

Changes in v2:
- Using api devm_platform_get_and_ioremap_resource.
- Modify rockchip_combphy_set_Mode.
- Add some PHY registers definition.

 drivers/phy/rockchip/Kconfig                  |   8 +
 drivers/phy/rockchip/Makefile                 |   1 +
 .../rockchip/phy-rockchip-naneng-combphy.c    | 581 ++++++++++++++++++
 3 files changed, 590 insertions(+)
 create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c

diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
index e812adad7242..9022e395c056 100644
--- a/drivers/phy/rockchip/Kconfig
+++ b/drivers/phy/rockchip/Kconfig
@@ -66,6 +66,14 @@ config PHY_ROCKCHIP_INNO_DSIDPHY
 	  Enable this to support the Rockchip MIPI/LVDS/TTL PHY with
 	  Innosilicon IP block.
 
+config PHY_ROCKCHIP_NANENG_COMBO_PHY
+	tristate "Rockchip NANENG COMBO PHY Driver"
+	depends on ARCH_ROCKCHIP && OF
+	select GENERIC_PHY
+	help
+	  Enable this to support the Rockchip PCIe/USB3.0/SATA/QSGMII
+	  combo PHY with NaNeng IP block.
+
 config PHY_ROCKCHIP_PCIE
 	tristate "Rockchip PCIe PHY Driver"
 	depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST
diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
index f0eec212b2aa..a5041efb5b8f 100644
--- a/drivers/phy/rockchip/Makefile
+++ b/drivers/phy/rockchip/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY)	+= phy-rockchip-inno-csidphy.o
 obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY)	+= phy-rockchip-inno-dsidphy.o
 obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI)	+= phy-rockchip-inno-hdmi.o
 obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)	+= phy-rockchip-inno-usb2.o
+obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY)	+= phy-rockchip-naneng-combphy.o
 obj-$(CONFIG_PHY_ROCKCHIP_PCIE)		+= phy-rockchip-pcie.o
 obj-$(CONFIG_PHY_ROCKCHIP_TYPEC)	+= phy-rockchip-typec.o
 obj-$(CONFIG_PHY_ROCKCHIP_USB)		+= phy-rockchip-usb.o
diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
new file mode 100644
index 000000000000..7b213825fb5d
--- /dev/null
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -0,0 +1,581 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Rockchip PIPE USB3.0 PCIE SATA Combo Phy driver
+ *
+ * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/phy/phy.h>
+#include <linux/clk.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_device.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/units.h>
+
+#define BIT_WRITEABLE_SHIFT		16
+#define REF_CLOCK_24MHz			(24 * HZ_PER_MHZ)
+#define REF_CLOCK_25MHz			(25 * HZ_PER_MHZ)
+#define REF_CLOCK_100MHz		(100 * HZ_PER_MHZ)
+
+/* COMBO PHY REG */
+#define PHYREG6				0x14
+#define PHYREG6_PLL_DIV_MASK		GENMASK(7, 6)
+#define PHYREG6_PLL_DIV_SHIFT		6
+#define PHYREG6_PLL_DIV_2		1
+
+#define PHYREG7				0x18
+#define PHYREG7_TX_RTERM_MASK		GENMASK(7, 4)
+#define PHYREG7_TX_RTERM_SHIFT		4
+#define PHYREG7_TX_RTERM_50OHM		8
+#define PHYREG7_RX_RTERM_MASK		GENMASK(3, 0)
+#define PHYREG7_RX_RTERM_SHIFT		0
+#define PHYREG7_RX_RTERM_44OHM		15
+
+#define PHYREG8				0x1C
+#define PHYREG8_SSC_EN			BIT(4)
+
+#define PHYREG11			0x28
+#define PHYREG11_SU_TRIM_0_7		0xF0
+
+#define PHYREG12			0x2C
+#define PHYREG12_PLL_LPF_ADJ_VALUE	4
+
+#define PHYREG13			0x30
+#define PHYREG13_RESISTER_MASK		GENMASK(5, 4)
+#define PHYREG13_RESISTER_SHIFT		0x4
+#define PHYREG13_RESISTER_HIGH_Z	3
+#define PHYREG13_CKRCV_AMP0		BIT(7)
+
+#define PHYREG14			0x34
+#define PHYREG14_CKRCV_AMP1		BIT(0)
+
+#define PHYREG15			0x38
+#define PHYREG15_CTLE_EN		BIT(0)
+#define PHYREG15_SSC_CNT_MASK		GENMASK(7, 6)
+#define PHYREG15_SSC_CNT_SHIFT		6
+#define PHYREG15_SSC_CNT_VALUE		1
+
+#define PHYREG16			0x3C
+#define PHYREG16_SSC_CNT_VALUE		0x5f
+
+#define PHYREG18			0x44
+#define PHYREG18_PLL_LOOP		0x32
+
+#define PHYREG32			0x7C
+#define PHYREG32_SSC_MASK		GENMASK(7, 4)
+#define PHYREG32_SSC_DIR_SHIFT		4
+#define PHYREG32_SSC_UPWARD		0
+#define PHYREG32_SSC_DOWNWARD		1
+#define PHYREG32_SSC_OFFSET_SHIFT	6
+#define PHYREG32_SSC_OFFSET_500PPM	1
+
+#define PHYREG33			0x80
+#define PHYREG33_PLL_KVCO_MASK		GENMASK(4, 2)
+#define PHYREG33_PLL_KVCO_SHIFT		2
+#define PHYREG33_PLL_KVCO_VALUE		2
+
+struct rockchip_combphy_priv;
+
+struct combphy_reg {
+	u16 offset;
+	u16 bitend;
+	u16 bitstart;
+	u16 disable;
+	u16 enable;
+};
+
+struct rockchip_combphy_grfcfg {
+	struct combphy_reg pcie_mode_set;
+	struct combphy_reg usb_mode_set;
+	struct combphy_reg sgmii_mode_set;
+	struct combphy_reg qsgmii_mode_set;
+	struct combphy_reg pipe_rxterm_set;
+	struct combphy_reg pipe_txelec_set;
+	struct combphy_reg pipe_txcomp_set;
+	struct combphy_reg pipe_clk_25m;
+	struct combphy_reg pipe_clk_100m;
+	struct combphy_reg pipe_phymode_sel;
+	struct combphy_reg pipe_rate_sel;
+	struct combphy_reg pipe_rxterm_sel;
+	struct combphy_reg pipe_txelec_sel;
+	struct combphy_reg pipe_txcomp_sel;
+	struct combphy_reg pipe_clk_ext;
+	struct combphy_reg pipe_sel_usb;
+	struct combphy_reg pipe_sel_qsgmii;
+	struct combphy_reg pipe_phy_status;
+	struct combphy_reg con0_for_pcie;
+	struct combphy_reg con1_for_pcie;
+	struct combphy_reg con2_for_pcie;
+	struct combphy_reg con3_for_pcie;
+	struct combphy_reg con0_for_sata;
+	struct combphy_reg con1_for_sata;
+	struct combphy_reg con2_for_sata;
+	struct combphy_reg con3_for_sata;
+	struct combphy_reg pipe_con0_for_sata;
+	struct combphy_reg pipe_xpcs_phy_ready;
+};
+
+struct rockchip_combphy_cfg {
+	const struct rockchip_combphy_grfcfg *grfcfg;
+	int (*combphy_cfg)(struct rockchip_combphy_priv *priv);
+};
+
+struct rockchip_combphy_priv {
+	u8 type;
+	void __iomem *mmio;
+	int num_clks;
+	struct clk_bulk_data *clks;
+	struct device *dev;
+	struct regmap *pipe_grf;
+	struct regmap *phy_grf;
+	struct phy *phy;
+	struct reset_control *phy_rst;
+	const struct rockchip_combphy_cfg *cfg;
+	bool enable_ssc;
+	bool ext_refclk;
+	struct clk *refclk;
+};
+
+static void rockchip_combphy_updatel(struct rockchip_combphy_priv *priv,
+				     int mask, int val, int reg)
+{
+	unsigned int temp;
+
+	temp = readl(priv->mmio + reg);
+	temp = (temp & ~(mask)) | val;
+	writel(temp, priv->mmio + reg);
+}
+
+static int rockchip_combphy_param_write(struct regmap *base,
+					const struct combphy_reg *reg, bool en)
+{
+	u32 val, mask, tmp;
+
+	tmp = en ? reg->enable : reg->disable;
+	mask = GENMASK(reg->bitend, reg->bitstart);
+	val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
+
+	return regmap_write(base, reg->offset, val);
+}
+
+static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv)
+{
+	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
+	u32 mask, val;
+
+	mask = GENMASK(cfg->pipe_phy_status.bitend,
+		       cfg->pipe_phy_status.bitstart);
+
+	regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val);
+	val = (val & mask) >> cfg->pipe_phy_status.bitstart;
+
+	return val;
+}
+
+static int rockchip_combphy_init(struct phy *phy)
+{
+	struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
+	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
+	u32 val;
+	int ret;
+
+	ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
+	if (ret) {
+		dev_err(priv->dev, "failed to enable clks\n");
+		return ret;
+	}
+
+	switch (priv->type) {
+	case PHY_TYPE_PCIE:
+	case PHY_TYPE_USB3:
+	case PHY_TYPE_SATA:
+	case PHY_TYPE_SGMII:
+	case PHY_TYPE_QSGMII:
+		if (priv->cfg->combphy_cfg)
+			ret = priv->cfg->combphy_cfg(priv);
+		break;
+	default:
+		dev_err(priv->dev, "incompatible PHY type\n");
+		ret = -EINVAL;
+		break;
+	}
+
+	if (ret) {
+		dev_err(priv->dev, "failed to init phy for phy type %x\n", priv->type);
+		goto err_clk;
+	}
+
+	ret = reset_control_deassert(priv->phy_rst);
+	if (ret)
+		goto err_clk;
+
+	if (priv->type == PHY_TYPE_USB3) {
+		ret = readx_poll_timeout_atomic(rockchip_combphy_is_ready,
+						priv, val,
+						val == cfg->pipe_phy_status.enable,
+						10, 1000);
+		if (ret)
+			dev_warn(priv->dev, "wait phy status ready timeout\n");
+	}
+
+	return 0;
+
+err_clk:
+	clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
+
+	return ret;
+}
+
+static int rockchip_combphy_exit(struct phy *phy)
+{
+	struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
+
+	clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
+	reset_control_assert(priv->phy_rst);
+
+	return 0;
+}
+
+static const struct phy_ops rochchip_combphy_ops = {
+	.init = rockchip_combphy_init,
+	.exit = rockchip_combphy_exit,
+	.owner = THIS_MODULE,
+};
+
+static struct phy *rockchip_combphy_xlate(struct device *dev, struct of_phandle_args *args)
+{
+	struct rockchip_combphy_priv *priv = dev_get_drvdata(dev);
+
+	if (args->args_count != 1) {
+		dev_err(dev, "invalid number of arguments\n");
+		return ERR_PTR(-EINVAL);
+	}
+
+	if (priv->type != PHY_NONE && priv->type != args->args[0])
+		dev_warn(dev, "phy type select %d overwriting type %d\n",
+			 args->args[0], priv->type);
+
+	priv->type = args->args[0];
+
+	return priv->phy;
+}
+
+static int rockchip_combphy_parse_dt(struct device *dev, struct rockchip_combphy_priv *priv)
+{
+	int i;
+
+	priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);
+	if (priv->num_clks < 1)
+		return -EINVAL;
+
+	priv->refclk = NULL;
+	for (i = 0; i < priv->num_clks; i++) {
+		if (!strncmp(priv->clks[i].id, "ref", 3)) {
+			priv->refclk = priv->clks[i].clk;
+			break;
+		}
+	}
+
+	if (!priv->refclk) {
+		dev_err(dev, "no refclk found\n");
+		return -EINVAL;
+	}
+
+	priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-grf");
+	if (IS_ERR(priv->pipe_grf)) {
+		dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n");
+		return PTR_ERR(priv->pipe_grf);
+	}
+
+	priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-phy-grf");
+	if (IS_ERR(priv->phy_grf)) {
+		dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n");
+		return PTR_ERR(priv->phy_grf);
+	}
+
+	priv->enable_ssc = device_property_present(dev, "rockchip,enable-ssc");
+
+	priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk");
+
+	priv->phy_rst = devm_reset_control_array_get_exclusive(dev);
+	if (IS_ERR(priv->phy_rst))
+		return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n");
+
+	return 0;
+}
+
+static int rockchip_combphy_probe(struct platform_device *pdev)
+{
+	struct phy_provider *phy_provider;
+	struct device *dev = &pdev->dev;
+	struct rockchip_combphy_priv *priv;
+	const struct rockchip_combphy_cfg *phy_cfg;
+	struct resource *res;
+	int ret;
+
+	phy_cfg = of_device_get_match_data(dev);
+	if (!phy_cfg) {
+		dev_err(dev, "no OF match data provided\n");
+		return -EINVAL;
+	}
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
+	if (IS_ERR(priv->mmio)) {
+		ret = PTR_ERR(priv->mmio);
+		return ret;
+	}
+
+	priv->dev = dev;
+	priv->type = PHY_NONE;
+	priv->cfg = phy_cfg;
+
+	ret = rockchip_combphy_parse_dt(dev, priv);
+	if (ret)
+		return ret;
+
+	ret = reset_control_assert(priv->phy_rst);
+	if (ret) {
+		dev_err(dev, "failed to reset phy\n");
+		return ret;
+	}
+
+	priv->phy = devm_phy_create(dev, NULL, &rochchip_combphy_ops);
+	if (IS_ERR(priv->phy)) {
+		dev_err(dev, "failed to create combphy\n");
+		return PTR_ERR(priv->phy);
+	}
+
+	dev_set_drvdata(dev, priv);
+	phy_set_drvdata(priv->phy, priv);
+
+	phy_provider = devm_of_phy_provider_register(dev, rockchip_combphy_xlate);
+
+	return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
+{
+	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
+	unsigned long rate;
+	u32 val;
+
+	switch (priv->type) {
+	case PHY_TYPE_PCIE:
+		/* Set SSC downward spread spectrum. */
+		rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
+					 PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
+					 PHYREG32);
+
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
+		break;
+
+	case PHY_TYPE_USB3:
+		/* Set SSC downward spread spectrum. */
+		rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
+					 PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
+					 PHYREG32);
+
+		/* Enable adaptive CTLE for USB3.0 Rx. */
+		val = readl(priv->mmio + PHYREG15);
+		val |= PHYREG15_CTLE_EN;
+		writel(val, priv->mmio + PHYREG15);
+
+		/* Set PLL KVCO fine tuning signals. */
+		rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
+					 PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT,
+					 PHYREG33);
+
+		/* Enable controlling random jitter. */
+		writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
+
+		/* Set PLL input clock divider 1/2. */
+		rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
+					 PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT,
+					 PHYREG6);
+
+		writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
+		writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
+
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true);
+		break;
+
+	case PHY_TYPE_SATA:
+		/* Enable adaptive CTLE for SATA Rx. */
+		val = readl(priv->mmio + PHYREG15);
+		val |= PHYREG15_CTLE_EN;
+		writel(val, priv->mmio + PHYREG15);
+		/*
+		 * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA.
+		 * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm)
+		 */
+		val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT;
+		val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT;
+		writel(val, priv->mmio + PHYREG7);
+
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true);
+		rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
+		break;
+
+	case PHY_TYPE_SGMII:
+		rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->sgmii_mode_set, true);
+		break;
+
+	case PHY_TYPE_QSGMII:
+		rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_rate_sel, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true);
+		break;
+
+	default:
+		dev_err(priv->dev, "incompatible PHY type\n");
+		return -EINVAL;
+	}
+
+	rate = clk_get_rate(priv->refclk);
+
+	switch (rate) {
+	case REF_CLOCK_24MHz:
+		if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) {
+			/* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */
+			val = PHYREG15_SSC_CNT_VALUE << PHYREG15_SSC_CNT_SHIFT;
+			rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK,
+						 val, PHYREG15);
+
+			writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
+		}
+		break;
+
+	case REF_CLOCK_25MHz:
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
+		break;
+
+	case REF_CLOCK_100MHz:
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
+		if (priv->type == PHY_TYPE_PCIE) {
+			/* PLL KVCO  fine tuning. */
+			val = PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT;
+			rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
+						 val, PHYREG33);
+
+			/* Enable controlling random jitter. */
+			writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
+
+			val = PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT;
+			rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
+						 val, PHYREG6);
+
+			writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
+			writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
+		} else if (priv->type == PHY_TYPE_SATA) {
+			/* downward spread spectrum +500ppm */
+			val = PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT;
+			val |= PHYREG32_SSC_OFFSET_500PPM << PHYREG32_SSC_OFFSET_SHIFT;
+			rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
+		}
+		break;
+
+	default:
+		dev_err(priv->dev, "unsupported rate: %lu\n", rate);
+		return -EINVAL;
+	}
+
+	if (priv->ext_refclk) {
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
+		if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
+			val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT;
+			val |= PHYREG13_CKRCV_AMP0;
+			rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13);
+
+			val = readl(priv->mmio + PHYREG14);
+			val |= PHYREG14_CKRCV_AMP1;
+			writel(val, priv->mmio + PHYREG14);
+		}
+	}
+
+	if (priv->enable_ssc) {
+		val = readl(priv->mmio + PHYREG8);
+		val |= PHYREG8_SSC_EN;
+		writel(val, priv->mmio + PHYREG8);
+	}
+
+	return 0;
+}
+
+static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = {
+	/* pipe-phy-grf */
+	.pcie_mode_set		= { 0x0000, 5, 0, 0x00, 0x11 },
+	.usb_mode_set		= { 0x0000, 5, 0, 0x00, 0x04 },
+	.sgmii_mode_set		= { 0x0000, 5, 0, 0x00, 0x01 },
+	.qsgmii_mode_set	= { 0x0000, 5, 0, 0x00, 0x21 },
+	.pipe_rxterm_set	= { 0x0000, 12, 12, 0x00, 0x01 },
+	.pipe_txelec_set	= { 0x0004, 1, 1, 0x00, 0x01 },
+	.pipe_txcomp_set	= { 0x0004, 4, 4, 0x00, 0x01 },
+	.pipe_clk_25m		= { 0x0004, 14, 13, 0x00, 0x01 },
+	.pipe_clk_100m		= { 0x0004, 14, 13, 0x00, 0x02 },
+	.pipe_phymode_sel	= { 0x0008, 1, 1, 0x00, 0x01 },
+	.pipe_rate_sel		= { 0x0008, 2, 2, 0x00, 0x01 },
+	.pipe_rxterm_sel	= { 0x0008, 8, 8, 0x00, 0x01 },
+	.pipe_txelec_sel	= { 0x0008, 12, 12, 0x00, 0x01 },
+	.pipe_txcomp_sel	= { 0x0008, 15, 15, 0x00, 0x01 },
+	.pipe_clk_ext		= { 0x000c, 9, 8, 0x02, 0x01 },
+	.pipe_sel_usb		= { 0x000c, 14, 13, 0x00, 0x01 },
+	.pipe_sel_qsgmii	= { 0x000c, 15, 13, 0x00, 0x07 },
+	.pipe_phy_status	= { 0x0034, 6, 6, 0x01, 0x00 },
+	.con0_for_pcie		= { 0x0000, 15, 0, 0x00, 0x1000 },
+	.con1_for_pcie		= { 0x0004, 15, 0, 0x00, 0x0000 },
+	.con2_for_pcie		= { 0x0008, 15, 0, 0x00, 0x0101 },
+	.con3_for_pcie		= { 0x000c, 15, 0, 0x00, 0x0200 },
+	.con0_for_sata		= { 0x0000, 15, 0, 0x00, 0x0119 },
+	.con1_for_sata		= { 0x0004, 15, 0, 0x00, 0x0040 },
+	.con2_for_sata		= { 0x0008, 15, 0, 0x00, 0x80c3 },
+	.con3_for_sata		= { 0x000c, 15, 0, 0x00, 0x4407 },
+	/* pipe-grf */
+	.pipe_con0_for_sata	= { 0x0000, 15, 0, 0x00, 0x2220 },
+	.pipe_xpcs_phy_ready	= { 0x0040, 2, 2, 0x00, 0x01 },
+};
+
+static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {
+	.grfcfg		= &rk3568_combphy_grfcfgs,
+	.combphy_cfg	= rk3568_combphy_cfg,
+};
+
+static const struct of_device_id rockchip_combphy_of_match[] = {
+	{
+		.compatible = "rockchip,rk3568-naneng-combphy",
+		.data = &rk3568_combphy_cfgs,
+	},
+	{ },
+};
+MODULE_DEVICE_TABLE(of, rockchip_combphy_of_match);
+
+static struct platform_driver rockchip_combphy_driver = {
+	.probe	= rockchip_combphy_probe,
+	.driver = {
+		.name = "rockchip-naneng-combphy",
+		.of_match_table = rockchip_combphy_of_match,
+	},
+};
+module_platform_driver(rockchip_combphy_driver);
+
+MODULE_DESCRIPTION("Rockchip NANENG COMBPHY driver");
+MODULE_LICENSE("GPL v2");
-- 
2.17.1


_______________________________________________
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[PATCH v8 3/4] phy: rockchip: add naneng combo phy for RK3568

[Yifeng Zhao]

This patch implements a combo phy driver for Rockchip SoCs
with NaNeng IP block. This phy can be used as pcie-phy, usb3-phy,
sata-phy or sgmii-phy.

Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---

Changes in v8:
- rename 'mode' to 'type'
- using devm_reset_control_array_get_exclusive
- move rockchip_combphy_set_mode into rockchip_combphy_init

Changes in v7:
- rename regs
- remove pipe_sgmii_mac_sel, u3otg0_port_en and u3otg1_port_en

Changes in v5:
- add rockchip_combphy_updatel()
- restyle

Changes in v4:
- restyle
- add devm_reset_control_array_get()
- remove clk structure
- change refclk DT parse
- change dev_err message
- add dot to phrase
- add ext_refclk variable
- add enable_ssc variable
- rename rockchip_combphy_param_write
- remove param_read
- replace rockchip-naneng-combphy driver name

Changes in v3:
- Using api devm_reset_control_get_optional_exclusive and dev_err_probe.
- Remove apb_rst.
- Redefine registers address.

Changes in v2:
- Using api devm_platform_get_and_ioremap_resource.
- Modify rockchip_combphy_set_Mode.
- Add some PHY registers definition.

 drivers/phy/rockchip/Kconfig                  |   8 +
 drivers/phy/rockchip/Makefile                 |   1 +
 .../rockchip/phy-rockchip-naneng-combphy.c    | 581 ++++++++++++++++++
 3 files changed, 590 insertions(+)
 create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c

diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
index e812adad7242..9022e395c056 100644
--- a/drivers/phy/rockchip/Kconfig
+++ b/drivers/phy/rockchip/Kconfig
@@ -66,6 +66,14 @@ config PHY_ROCKCHIP_INNO_DSIDPHY
 	  Enable this to support the Rockchip MIPI/LVDS/TTL PHY with
 	  Innosilicon IP block.
 
+config PHY_ROCKCHIP_NANENG_COMBO_PHY
+	tristate "Rockchip NANENG COMBO PHY Driver"
+	depends on ARCH_ROCKCHIP && OF
+	select GENERIC_PHY
+	help
+	  Enable this to support the Rockchip PCIe/USB3.0/SATA/QSGMII
+	  combo PHY with NaNeng IP block.
+
 config PHY_ROCKCHIP_PCIE
 	tristate "Rockchip PCIe PHY Driver"
 	depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST
diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
index f0eec212b2aa..a5041efb5b8f 100644
--- a/drivers/phy/rockchip/Makefile
+++ b/drivers/phy/rockchip/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY)	+= phy-rockchip-inno-csidphy.o
 obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY)	+= phy-rockchip-inno-dsidphy.o
 obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI)	+= phy-rockchip-inno-hdmi.o
 obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)	+= phy-rockchip-inno-usb2.o
+obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY)	+= phy-rockchip-naneng-combphy.o
 obj-$(CONFIG_PHY_ROCKCHIP_PCIE)		+= phy-rockchip-pcie.o
 obj-$(CONFIG_PHY_ROCKCHIP_TYPEC)	+= phy-rockchip-typec.o
 obj-$(CONFIG_PHY_ROCKCHIP_USB)		+= phy-rockchip-usb.o
diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
new file mode 100644
index 000000000000..7b213825fb5d
--- /dev/null
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -0,0 +1,581 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Rockchip PIPE USB3.0 PCIE SATA Combo Phy driver
+ *
+ * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/phy/phy.h>
+#include <linux/clk.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_device.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/units.h>
+
+#define BIT_WRITEABLE_SHIFT		16
+#define REF_CLOCK_24MHz			(24 * HZ_PER_MHZ)
+#define REF_CLOCK_25MHz			(25 * HZ_PER_MHZ)
+#define REF_CLOCK_100MHz		(100 * HZ_PER_MHZ)
+
+/* COMBO PHY REG */
+#define PHYREG6				0x14
+#define PHYREG6_PLL_DIV_MASK		GENMASK(7, 6)
+#define PHYREG6_PLL_DIV_SHIFT		6
+#define PHYREG6_PLL_DIV_2		1
+
+#define PHYREG7				0x18
+#define PHYREG7_TX_RTERM_MASK		GENMASK(7, 4)
+#define PHYREG7_TX_RTERM_SHIFT		4
+#define PHYREG7_TX_RTERM_50OHM		8
+#define PHYREG7_RX_RTERM_MASK		GENMASK(3, 0)
+#define PHYREG7_RX_RTERM_SHIFT		0
+#define PHYREG7_RX_RTERM_44OHM		15
+
+#define PHYREG8				0x1C
+#define PHYREG8_SSC_EN			BIT(4)
+
+#define PHYREG11			0x28
+#define PHYREG11_SU_TRIM_0_7		0xF0
+
+#define PHYREG12			0x2C
+#define PHYREG12_PLL_LPF_ADJ_VALUE	4
+
+#define PHYREG13			0x30
+#define PHYREG13_RESISTER_MASK		GENMASK(5, 4)
+#define PHYREG13_RESISTER_SHIFT		0x4
+#define PHYREG13_RESISTER_HIGH_Z	3
+#define PHYREG13_CKRCV_AMP0		BIT(7)
+
+#define PHYREG14			0x34
+#define PHYREG14_CKRCV_AMP1		BIT(0)
+
+#define PHYREG15			0x38
+#define PHYREG15_CTLE_EN		BIT(0)
+#define PHYREG15_SSC_CNT_MASK		GENMASK(7, 6)
+#define PHYREG15_SSC_CNT_SHIFT		6
+#define PHYREG15_SSC_CNT_VALUE		1
+
+#define PHYREG16			0x3C
+#define PHYREG16_SSC_CNT_VALUE		0x5f
+
+#define PHYREG18			0x44
+#define PHYREG18_PLL_LOOP		0x32
+
+#define PHYREG32			0x7C
+#define PHYREG32_SSC_MASK		GENMASK(7, 4)
+#define PHYREG32_SSC_DIR_SHIFT		4
+#define PHYREG32_SSC_UPWARD		0
+#define PHYREG32_SSC_DOWNWARD		1
+#define PHYREG32_SSC_OFFSET_SHIFT	6
+#define PHYREG32_SSC_OFFSET_500PPM	1
+
+#define PHYREG33			0x80
+#define PHYREG33_PLL_KVCO_MASK		GENMASK(4, 2)
+#define PHYREG33_PLL_KVCO_SHIFT		2
+#define PHYREG33_PLL_KVCO_VALUE		2
+
+struct rockchip_combphy_priv;
+
+struct combphy_reg {
+	u16 offset;
+	u16 bitend;
+	u16 bitstart;
+	u16 disable;
+	u16 enable;
+};
+
+struct rockchip_combphy_grfcfg {
+	struct combphy_reg pcie_mode_set;
+	struct combphy_reg usb_mode_set;
+	struct combphy_reg sgmii_mode_set;
+	struct combphy_reg qsgmii_mode_set;
+	struct combphy_reg pipe_rxterm_set;
+	struct combphy_reg pipe_txelec_set;
+	struct combphy_reg pipe_txcomp_set;
+	struct combphy_reg pipe_clk_25m;
+	struct combphy_reg pipe_clk_100m;
+	struct combphy_reg pipe_phymode_sel;
+	struct combphy_reg pipe_rate_sel;
+	struct combphy_reg pipe_rxterm_sel;
+	struct combphy_reg pipe_txelec_sel;
+	struct combphy_reg pipe_txcomp_sel;
+	struct combphy_reg pipe_clk_ext;
+	struct combphy_reg pipe_sel_usb;
+	struct combphy_reg pipe_sel_qsgmii;
+	struct combphy_reg pipe_phy_status;
+	struct combphy_reg con0_for_pcie;
+	struct combphy_reg con1_for_pcie;
+	struct combphy_reg con2_for_pcie;
+	struct combphy_reg con3_for_pcie;
+	struct combphy_reg con0_for_sata;
+	struct combphy_reg con1_for_sata;
+	struct combphy_reg con2_for_sata;
+	struct combphy_reg con3_for_sata;
+	struct combphy_reg pipe_con0_for_sata;
+	struct combphy_reg pipe_xpcs_phy_ready;
+};
+
+struct rockchip_combphy_cfg {
+	const struct rockchip_combphy_grfcfg *grfcfg;
+	int (*combphy_cfg)(struct rockchip_combphy_priv *priv);
+};
+
+struct rockchip_combphy_priv {
+	u8 type;
+	void __iomem *mmio;
+	int num_clks;
+	struct clk_bulk_data *clks;
+	struct device *dev;
+	struct regmap *pipe_grf;
+	struct regmap *phy_grf;
+	struct phy *phy;
+	struct reset_control *phy_rst;
+	const struct rockchip_combphy_cfg *cfg;
+	bool enable_ssc;
+	bool ext_refclk;
+	struct clk *refclk;
+};
+
+static void rockchip_combphy_updatel(struct rockchip_combphy_priv *priv,
+				     int mask, int val, int reg)
+{
+	unsigned int temp;
+
+	temp = readl(priv->mmio + reg);
+	temp = (temp & ~(mask)) | val;
+	writel(temp, priv->mmio + reg);
+}
+
+static int rockchip_combphy_param_write(struct regmap *base,
+					const struct combphy_reg *reg, bool en)
+{
+	u32 val, mask, tmp;
+
+	tmp = en ? reg->enable : reg->disable;
+	mask = GENMASK(reg->bitend, reg->bitstart);
+	val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
+
+	return regmap_write(base, reg->offset, val);
+}
+
+static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv)
+{
+	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
+	u32 mask, val;
+
+	mask = GENMASK(cfg->pipe_phy_status.bitend,
+		       cfg->pipe_phy_status.bitstart);
+
+	regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val);
+	val = (val & mask) >> cfg->pipe_phy_status.bitstart;
+
+	return val;
+}
+
+static int rockchip_combphy_init(struct phy *phy)
+{
+	struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
+	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
+	u32 val;
+	int ret;
+
+	ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
+	if (ret) {
+		dev_err(priv->dev, "failed to enable clks\n");
+		return ret;
+	}
+
+	switch (priv->type) {
+	case PHY_TYPE_PCIE:
+	case PHY_TYPE_USB3:
+	case PHY_TYPE_SATA:
+	case PHY_TYPE_SGMII:
+	case PHY_TYPE_QSGMII:
+		if (priv->cfg->combphy_cfg)
+			ret = priv->cfg->combphy_cfg(priv);
+		break;
+	default:
+		dev_err(priv->dev, "incompatible PHY type\n");
+		ret = -EINVAL;
+		break;
+	}
+
+	if (ret) {
+		dev_err(priv->dev, "failed to init phy for phy type %x\n", priv->type);
+		goto err_clk;
+	}
+
+	ret = reset_control_deassert(priv->phy_rst);
+	if (ret)
+		goto err_clk;
+
+	if (priv->type == PHY_TYPE_USB3) {
+		ret = readx_poll_timeout_atomic(rockchip_combphy_is_ready,
+						priv, val,
+						val == cfg->pipe_phy_status.enable,
+						10, 1000);
+		if (ret)
+			dev_warn(priv->dev, "wait phy status ready timeout\n");
+	}
+
+	return 0;
+
+err_clk:
+	clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
+
+	return ret;
+}
+
+static int rockchip_combphy_exit(struct phy *phy)
+{
+	struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
+
+	clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
+	reset_control_assert(priv->phy_rst);
+
+	return 0;
+}
+
+static const struct phy_ops rochchip_combphy_ops = {
+	.init = rockchip_combphy_init,
+	.exit = rockchip_combphy_exit,
+	.owner = THIS_MODULE,
+};
+
+static struct phy *rockchip_combphy_xlate(struct device *dev, struct of_phandle_args *args)
+{
+	struct rockchip_combphy_priv *priv = dev_get_drvdata(dev);
+
+	if (args->args_count != 1) {
+		dev_err(dev, "invalid number of arguments\n");
+		return ERR_PTR(-EINVAL);
+	}
+
+	if (priv->type != PHY_NONE && priv->type != args->args[0])
+		dev_warn(dev, "phy type select %d overwriting type %d\n",
+			 args->args[0], priv->type);
+
+	priv->type = args->args[0];
+
+	return priv->phy;
+}
+
+static int rockchip_combphy_parse_dt(struct device *dev, struct rockchip_combphy_priv *priv)
+{
+	int i;
+
+	priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);
+	if (priv->num_clks < 1)
+		return -EINVAL;
+
+	priv->refclk = NULL;
+	for (i = 0; i < priv->num_clks; i++) {
+		if (!strncmp(priv->clks[i].id, "ref", 3)) {
+			priv->refclk = priv->clks[i].clk;
+			break;
+		}
+	}
+
+	if (!priv->refclk) {
+		dev_err(dev, "no refclk found\n");
+		return -EINVAL;
+	}
+
+	priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-grf");
+	if (IS_ERR(priv->pipe_grf)) {
+		dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n");
+		return PTR_ERR(priv->pipe_grf);
+	}
+
+	priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-phy-grf");
+	if (IS_ERR(priv->phy_grf)) {
+		dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n");
+		return PTR_ERR(priv->phy_grf);
+	}
+
+	priv->enable_ssc = device_property_present(dev, "rockchip,enable-ssc");
+
+	priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk");
+
+	priv->phy_rst = devm_reset_control_array_get_exclusive(dev);
+	if (IS_ERR(priv->phy_rst))
+		return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n");
+
+	return 0;
+}
+
+static int rockchip_combphy_probe(struct platform_device *pdev)
+{
+	struct phy_provider *phy_provider;
+	struct device *dev = &pdev->dev;
+	struct rockchip_combphy_priv *priv;
+	const struct rockchip_combphy_cfg *phy_cfg;
+	struct resource *res;
+	int ret;
+
+	phy_cfg = of_device_get_match_data(dev);
+	if (!phy_cfg) {
+		dev_err(dev, "no OF match data provided\n");
+		return -EINVAL;
+	}
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
+	if (IS_ERR(priv->mmio)) {
+		ret = PTR_ERR(priv->mmio);
+		return ret;
+	}
+
+	priv->dev = dev;
+	priv->type = PHY_NONE;
+	priv->cfg = phy_cfg;
+
+	ret = rockchip_combphy_parse_dt(dev, priv);
+	if (ret)
+		return ret;
+
+	ret = reset_control_assert(priv->phy_rst);
+	if (ret) {
+		dev_err(dev, "failed to reset phy\n");
+		return ret;
+	}
+
+	priv->phy = devm_phy_create(dev, NULL, &rochchip_combphy_ops);
+	if (IS_ERR(priv->phy)) {
+		dev_err(dev, "failed to create combphy\n");
+		return PTR_ERR(priv->phy);
+	}
+
+	dev_set_drvdata(dev, priv);
+	phy_set_drvdata(priv->phy, priv);
+
+	phy_provider = devm_of_phy_provider_register(dev, rockchip_combphy_xlate);
+
+	return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
+{
+	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
+	unsigned long rate;
+	u32 val;
+
+	switch (priv->type) {
+	case PHY_TYPE_PCIE:
+		/* Set SSC downward spread spectrum. */
+		rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
+					 PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
+					 PHYREG32);
+
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
+		break;
+
+	case PHY_TYPE_USB3:
+		/* Set SSC downward spread spectrum. */
+		rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
+					 PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
+					 PHYREG32);
+
+		/* Enable adaptive CTLE for USB3.0 Rx. */
+		val = readl(priv->mmio + PHYREG15);
+		val |= PHYREG15_CTLE_EN;
+		writel(val, priv->mmio + PHYREG15);
+
+		/* Set PLL KVCO fine tuning signals. */
+		rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
+					 PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT,
+					 PHYREG33);
+
+		/* Enable controlling random jitter. */
+		writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
+
+		/* Set PLL input clock divider 1/2. */
+		rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
+					 PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT,
+					 PHYREG6);
+
+		writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
+		writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
+
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true);
+		break;
+
+	case PHY_TYPE_SATA:
+		/* Enable adaptive CTLE for SATA Rx. */
+		val = readl(priv->mmio + PHYREG15);
+		val |= PHYREG15_CTLE_EN;
+		writel(val, priv->mmio + PHYREG15);
+		/*
+		 * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA.
+		 * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm)
+		 */
+		val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT;
+		val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT;
+		writel(val, priv->mmio + PHYREG7);
+
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true);
+		rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
+		break;
+
+	case PHY_TYPE_SGMII:
+		rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->sgmii_mode_set, true);
+		break;
+
+	case PHY_TYPE_QSGMII:
+		rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_rate_sel, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true);
+		break;
+
+	default:
+		dev_err(priv->dev, "incompatible PHY type\n");
+		return -EINVAL;
+	}
+
+	rate = clk_get_rate(priv->refclk);
+
+	switch (rate) {
+	case REF_CLOCK_24MHz:
+		if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) {
+			/* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */
+			val = PHYREG15_SSC_CNT_VALUE << PHYREG15_SSC_CNT_SHIFT;
+			rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK,
+						 val, PHYREG15);
+
+			writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
+		}
+		break;
+
+	case REF_CLOCK_25MHz:
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
+		break;
+
+	case REF_CLOCK_100MHz:
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
+		if (priv->type == PHY_TYPE_PCIE) {
+			/* PLL KVCO  fine tuning. */
+			val = PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT;
+			rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
+						 val, PHYREG33);
+
+			/* Enable controlling random jitter. */
+			writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
+
+			val = PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT;
+			rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
+						 val, PHYREG6);
+
+			writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
+			writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
+		} else if (priv->type == PHY_TYPE_SATA) {
+			/* downward spread spectrum +500ppm */
+			val = PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT;
+			val |= PHYREG32_SSC_OFFSET_500PPM << PHYREG32_SSC_OFFSET_SHIFT;
+			rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
+		}
+		break;
+
+	default:
+		dev_err(priv->dev, "unsupported rate: %lu\n", rate);
+		return -EINVAL;
+	}
+
+	if (priv->ext_refclk) {
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
+		if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
+			val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT;
+			val |= PHYREG13_CKRCV_AMP0;
+			rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13);
+
+			val = readl(priv->mmio + PHYREG14);
+			val |= PHYREG14_CKRCV_AMP1;
+			writel(val, priv->mmio + PHYREG14);
+		}
+	}
+
+	if (priv->enable_ssc) {
+		val = readl(priv->mmio + PHYREG8);
+		val |= PHYREG8_SSC_EN;
+		writel(val, priv->mmio + PHYREG8);
+	}
+
+	return 0;
+}
+
+static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = {
+	/* pipe-phy-grf */
+	.pcie_mode_set		= { 0x0000, 5, 0, 0x00, 0x11 },
+	.usb_mode_set		= { 0x0000, 5, 0, 0x00, 0x04 },
+	.sgmii_mode_set		= { 0x0000, 5, 0, 0x00, 0x01 },
+	.qsgmii_mode_set	= { 0x0000, 5, 0, 0x00, 0x21 },
+	.pipe_rxterm_set	= { 0x0000, 12, 12, 0x00, 0x01 },
+	.pipe_txelec_set	= { 0x0004, 1, 1, 0x00, 0x01 },
+	.pipe_txcomp_set	= { 0x0004, 4, 4, 0x00, 0x01 },
+	.pipe_clk_25m		= { 0x0004, 14, 13, 0x00, 0x01 },
+	.pipe_clk_100m		= { 0x0004, 14, 13, 0x00, 0x02 },
+	.pipe_phymode_sel	= { 0x0008, 1, 1, 0x00, 0x01 },
+	.pipe_rate_sel		= { 0x0008, 2, 2, 0x00, 0x01 },
+	.pipe_rxterm_sel	= { 0x0008, 8, 8, 0x00, 0x01 },
+	.pipe_txelec_sel	= { 0x0008, 12, 12, 0x00, 0x01 },
+	.pipe_txcomp_sel	= { 0x0008, 15, 15, 0x00, 0x01 },
+	.pipe_clk_ext		= { 0x000c, 9, 8, 0x02, 0x01 },
+	.pipe_sel_usb		= { 0x000c, 14, 13, 0x00, 0x01 },
+	.pipe_sel_qsgmii	= { 0x000c, 15, 13, 0x00, 0x07 },
+	.pipe_phy_status	= { 0x0034, 6, 6, 0x01, 0x00 },
+	.con0_for_pcie		= { 0x0000, 15, 0, 0x00, 0x1000 },
+	.con1_for_pcie		= { 0x0004, 15, 0, 0x00, 0x0000 },
+	.con2_for_pcie		= { 0x0008, 15, 0, 0x00, 0x0101 },
+	.con3_for_pcie		= { 0x000c, 15, 0, 0x00, 0x0200 },
+	.con0_for_sata		= { 0x0000, 15, 0, 0x00, 0x0119 },
+	.con1_for_sata		= { 0x0004, 15, 0, 0x00, 0x0040 },
+	.con2_for_sata		= { 0x0008, 15, 0, 0x00, 0x80c3 },
+	.con3_for_sata		= { 0x000c, 15, 0, 0x00, 0x4407 },
+	/* pipe-grf */
+	.pipe_con0_for_sata	= { 0x0000, 15, 0, 0x00, 0x2220 },
+	.pipe_xpcs_phy_ready	= { 0x0040, 2, 2, 0x00, 0x01 },
+};
+
+static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {
+	.grfcfg		= &rk3568_combphy_grfcfgs,
+	.combphy_cfg	= rk3568_combphy_cfg,
+};
+
+static const struct of_device_id rockchip_combphy_of_match[] = {
+	{
+		.compatible = "rockchip,rk3568-naneng-combphy",
+		.data = &rk3568_combphy_cfgs,
+	},
+	{ },
+};
+MODULE_DEVICE_TABLE(of, rockchip_combphy_of_match);
+
+static struct platform_driver rockchip_combphy_driver = {
+	.probe	= rockchip_combphy_probe,
+	.driver = {
+		.name = "rockchip-naneng-combphy",
+		.of_match_table = rockchip_combphy_of_match,
+	},
+};
+module_platform_driver(rockchip_combphy_driver);
+
+MODULE_DESCRIPTION("Rockchip NANENG COMBPHY driver");
+MODULE_LICENSE("GPL v2");
-- 
2.17.1


-- 
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Re: [PATCH v8 3/4] phy: rockchip: add naneng combo phy for RK3568

[Peter Geis]

On Tue, Feb 8, 2022 at 4:14 AM Yifeng Zhao <yifeng.zhao@rock-chips.com> wrote:
>
> This patch implements a combo phy driver for Rockchip SoCs
> with NaNeng IP block. This phy can be used as pcie-phy, usb3-phy,
> sata-phy or sgmii-phy.
>
> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>

Tested successfully on Quartz64-A and Quartz64-B in SATA, USB3, and PCIe modes.
Tested-by: Peter Geis <pgwipeout@gmail.com>

> ---
>
> Changes in v8:
> - rename 'mode' to 'type'
> - using devm_reset_control_array_get_exclusive
> - move rockchip_combphy_set_mode into rockchip_combphy_init
>
> Changes in v7:
> - rename regs
> - remove pipe_sgmii_mac_sel, u3otg0_port_en and u3otg1_port_en
>
> Changes in v5:
> - add rockchip_combphy_updatel()
> - restyle
>
> Changes in v4:
> - restyle
> - add devm_reset_control_array_get()
> - remove clk structure
> - change refclk DT parse
> - change dev_err message
> - add dot to phrase
> - add ext_refclk variable
> - add enable_ssc variable
> - rename rockchip_combphy_param_write
> - remove param_read
> - replace rockchip-naneng-combphy driver name
>
> Changes in v3:
> - Using api devm_reset_control_get_optional_exclusive and dev_err_probe.
> - Remove apb_rst.
> - Redefine registers address.
>
> Changes in v2:
> - Using api devm_platform_get_and_ioremap_resource.
> - Modify rockchip_combphy_set_Mode.
> - Add some PHY registers definition.
>
>  drivers/phy/rockchip/Kconfig                  |   8 +
>  drivers/phy/rockchip/Makefile                 |   1 +
>  .../rockchip/phy-rockchip-naneng-combphy.c    | 581 ++++++++++++++++++
>  3 files changed, 590 insertions(+)
>  create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
>
> diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
> index e812adad7242..9022e395c056 100644
> --- a/drivers/phy/rockchip/Kconfig
> +++ b/drivers/phy/rockchip/Kconfig
> @@ -66,6 +66,14 @@ config PHY_ROCKCHIP_INNO_DSIDPHY
>           Enable this to support the Rockchip MIPI/LVDS/TTL PHY with
>           Innosilicon IP block.
>
> +config PHY_ROCKCHIP_NANENG_COMBO_PHY
> +       tristate "Rockchip NANENG COMBO PHY Driver"
> +       depends on ARCH_ROCKCHIP && OF
> +       select GENERIC_PHY
> +       help
> +         Enable this to support the Rockchip PCIe/USB3.0/SATA/QSGMII
> +         combo PHY with NaNeng IP block.
> +
>  config PHY_ROCKCHIP_PCIE
>         tristate "Rockchip PCIe PHY Driver"
>         depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST
> diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
> index f0eec212b2aa..a5041efb5b8f 100644
> --- a/drivers/phy/rockchip/Makefile
> +++ b/drivers/phy/rockchip/Makefile
> @@ -6,6 +6,7 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY) += phy-rockchip-inno-csidphy.o
>  obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY)        += phy-rockchip-inno-dsidphy.o
>  obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI)   += phy-rockchip-inno-hdmi.o
>  obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)   += phy-rockchip-inno-usb2.o
> +obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY)    += phy-rockchip-naneng-combphy.o
>  obj-$(CONFIG_PHY_ROCKCHIP_PCIE)                += phy-rockchip-pcie.o
>  obj-$(CONFIG_PHY_ROCKCHIP_TYPEC)       += phy-rockchip-typec.o
>  obj-$(CONFIG_PHY_ROCKCHIP_USB)         += phy-rockchip-usb.o
> diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> new file mode 100644
> index 000000000000..7b213825fb5d
> --- /dev/null
> +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> @@ -0,0 +1,581 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Rockchip PIPE USB3.0 PCIE SATA Combo Phy driver
> + *
> + * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
> + */
> +
> +#include <dt-bindings/phy/phy.h>
> +#include <linux/clk.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/of_device.h>
> +#include <linux/phy/phy.h>
> +#include <linux/regmap.h>
> +#include <linux/reset.h>
> +#include <linux/units.h>
> +
> +#define BIT_WRITEABLE_SHIFT            16
> +#define REF_CLOCK_24MHz                        (24 * HZ_PER_MHZ)
> +#define REF_CLOCK_25MHz                        (25 * HZ_PER_MHZ)
> +#define REF_CLOCK_100MHz               (100 * HZ_PER_MHZ)
> +
> +/* COMBO PHY REG */
> +#define PHYREG6                                0x14
> +#define PHYREG6_PLL_DIV_MASK           GENMASK(7, 6)
> +#define PHYREG6_PLL_DIV_SHIFT          6
> +#define PHYREG6_PLL_DIV_2              1
> +
> +#define PHYREG7                                0x18
> +#define PHYREG7_TX_RTERM_MASK          GENMASK(7, 4)
> +#define PHYREG7_TX_RTERM_SHIFT         4
> +#define PHYREG7_TX_RTERM_50OHM         8
> +#define PHYREG7_RX_RTERM_MASK          GENMASK(3, 0)
> +#define PHYREG7_RX_RTERM_SHIFT         0
> +#define PHYREG7_RX_RTERM_44OHM         15
> +
> +#define PHYREG8                                0x1C
> +#define PHYREG8_SSC_EN                 BIT(4)
> +
> +#define PHYREG11                       0x28
> +#define PHYREG11_SU_TRIM_0_7           0xF0
> +
> +#define PHYREG12                       0x2C
> +#define PHYREG12_PLL_LPF_ADJ_VALUE     4
> +
> +#define PHYREG13                       0x30
> +#define PHYREG13_RESISTER_MASK         GENMASK(5, 4)
> +#define PHYREG13_RESISTER_SHIFT                0x4
> +#define PHYREG13_RESISTER_HIGH_Z       3
> +#define PHYREG13_CKRCV_AMP0            BIT(7)
> +
> +#define PHYREG14                       0x34
> +#define PHYREG14_CKRCV_AMP1            BIT(0)
> +
> +#define PHYREG15                       0x38
> +#define PHYREG15_CTLE_EN               BIT(0)
> +#define PHYREG15_SSC_CNT_MASK          GENMASK(7, 6)
> +#define PHYREG15_SSC_CNT_SHIFT         6
> +#define PHYREG15_SSC_CNT_VALUE         1
> +
> +#define PHYREG16                       0x3C
> +#define PHYREG16_SSC_CNT_VALUE         0x5f
> +
> +#define PHYREG18                       0x44
> +#define PHYREG18_PLL_LOOP              0x32
> +
> +#define PHYREG32                       0x7C
> +#define PHYREG32_SSC_MASK              GENMASK(7, 4)
> +#define PHYREG32_SSC_DIR_SHIFT         4
> +#define PHYREG32_SSC_UPWARD            0
> +#define PHYREG32_SSC_DOWNWARD          1
> +#define PHYREG32_SSC_OFFSET_SHIFT      6
> +#define PHYREG32_SSC_OFFSET_500PPM     1
> +
> +#define PHYREG33                       0x80
> +#define PHYREG33_PLL_KVCO_MASK         GENMASK(4, 2)
> +#define PHYREG33_PLL_KVCO_SHIFT                2
> +#define PHYREG33_PLL_KVCO_VALUE                2
> +
> +struct rockchip_combphy_priv;
> +
> +struct combphy_reg {
> +       u16 offset;
> +       u16 bitend;
> +       u16 bitstart;
> +       u16 disable;
> +       u16 enable;
> +};
> +
> +struct rockchip_combphy_grfcfg {
> +       struct combphy_reg pcie_mode_set;
> +       struct combphy_reg usb_mode_set;
> +       struct combphy_reg sgmii_mode_set;
> +       struct combphy_reg qsgmii_mode_set;
> +       struct combphy_reg pipe_rxterm_set;
> +       struct combphy_reg pipe_txelec_set;
> +       struct combphy_reg pipe_txcomp_set;
> +       struct combphy_reg pipe_clk_25m;
> +       struct combphy_reg pipe_clk_100m;
> +       struct combphy_reg pipe_phymode_sel;
> +       struct combphy_reg pipe_rate_sel;
> +       struct combphy_reg pipe_rxterm_sel;
> +       struct combphy_reg pipe_txelec_sel;
> +       struct combphy_reg pipe_txcomp_sel;
> +       struct combphy_reg pipe_clk_ext;
> +       struct combphy_reg pipe_sel_usb;
> +       struct combphy_reg pipe_sel_qsgmii;
> +       struct combphy_reg pipe_phy_status;
> +       struct combphy_reg con0_for_pcie;
> +       struct combphy_reg con1_for_pcie;
> +       struct combphy_reg con2_for_pcie;
> +       struct combphy_reg con3_for_pcie;
> +       struct combphy_reg con0_for_sata;
> +       struct combphy_reg con1_for_sata;
> +       struct combphy_reg con2_for_sata;
> +       struct combphy_reg con3_for_sata;
> +       struct combphy_reg pipe_con0_for_sata;
> +       struct combphy_reg pipe_xpcs_phy_ready;
> +};
> +
> +struct rockchip_combphy_cfg {
> +       const struct rockchip_combphy_grfcfg *grfcfg;
> +       int (*combphy_cfg)(struct rockchip_combphy_priv *priv);
> +};
> +
> +struct rockchip_combphy_priv {
> +       u8 type;
> +       void __iomem *mmio;
> +       int num_clks;
> +       struct clk_bulk_data *clks;
> +       struct device *dev;
> +       struct regmap *pipe_grf;
> +       struct regmap *phy_grf;
> +       struct phy *phy;
> +       struct reset_control *phy_rst;
> +       const struct rockchip_combphy_cfg *cfg;
> +       bool enable_ssc;
> +       bool ext_refclk;
> +       struct clk *refclk;
> +};
> +
> +static void rockchip_combphy_updatel(struct rockchip_combphy_priv *priv,
> +                                    int mask, int val, int reg)
> +{
> +       unsigned int temp;
> +
> +       temp = readl(priv->mmio + reg);
> +       temp = (temp & ~(mask)) | val;
> +       writel(temp, priv->mmio + reg);
> +}
> +
> +static int rockchip_combphy_param_write(struct regmap *base,
> +                                       const struct combphy_reg *reg, bool en)
> +{
> +       u32 val, mask, tmp;
> +
> +       tmp = en ? reg->enable : reg->disable;
> +       mask = GENMASK(reg->bitend, reg->bitstart);
> +       val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
> +
> +       return regmap_write(base, reg->offset, val);
> +}
> +
> +static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv)
> +{
> +       const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
> +       u32 mask, val;
> +
> +       mask = GENMASK(cfg->pipe_phy_status.bitend,
> +                      cfg->pipe_phy_status.bitstart);
> +
> +       regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val);
> +       val = (val & mask) >> cfg->pipe_phy_status.bitstart;
> +
> +       return val;
> +}
> +
> +static int rockchip_combphy_init(struct phy *phy)
> +{
> +       struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
> +       const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
> +       u32 val;
> +       int ret;
> +
> +       ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
> +       if (ret) {
> +               dev_err(priv->dev, "failed to enable clks\n");
> +               return ret;
> +       }
> +
> +       switch (priv->type) {
> +       case PHY_TYPE_PCIE:
> +       case PHY_TYPE_USB3:
> +       case PHY_TYPE_SATA:
> +       case PHY_TYPE_SGMII:
> +       case PHY_TYPE_QSGMII:
> +               if (priv->cfg->combphy_cfg)
> +                       ret = priv->cfg->combphy_cfg(priv);
> +               break;
> +       default:
> +               dev_err(priv->dev, "incompatible PHY type\n");
> +               ret = -EINVAL;
> +               break;
> +       }
> +
> +       if (ret) {
> +               dev_err(priv->dev, "failed to init phy for phy type %x\n", priv->type);
> +               goto err_clk;
> +       }
> +
> +       ret = reset_control_deassert(priv->phy_rst);
> +       if (ret)
> +               goto err_clk;
> +
> +       if (priv->type == PHY_TYPE_USB3) {
> +               ret = readx_poll_timeout_atomic(rockchip_combphy_is_ready,
> +                                               priv, val,
> +                                               val == cfg->pipe_phy_status.enable,
> +                                               10, 1000);
> +               if (ret)
> +                       dev_warn(priv->dev, "wait phy status ready timeout\n");
> +       }
> +
> +       return 0;
> +
> +err_clk:
> +       clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
> +
> +       return ret;
> +}
> +
> +static int rockchip_combphy_exit(struct phy *phy)
> +{
> +       struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
> +
> +       clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
> +       reset_control_assert(priv->phy_rst);
> +
> +       return 0;
> +}
> +
> +static const struct phy_ops rochchip_combphy_ops = {
> +       .init = rockchip_combphy_init,
> +       .exit = rockchip_combphy_exit,
> +       .owner = THIS_MODULE,
> +};
> +
> +static struct phy *rockchip_combphy_xlate(struct device *dev, struct of_phandle_args *args)
> +{
> +       struct rockchip_combphy_priv *priv = dev_get_drvdata(dev);
> +
> +       if (args->args_count != 1) {
> +               dev_err(dev, "invalid number of arguments\n");
> +               return ERR_PTR(-EINVAL);
> +       }
> +
> +       if (priv->type != PHY_NONE && priv->type != args->args[0])
> +               dev_warn(dev, "phy type select %d overwriting type %d\n",
> +                        args->args[0], priv->type);
> +
> +       priv->type = args->args[0];
> +
> +       return priv->phy;
> +}
> +
> +static int rockchip_combphy_parse_dt(struct device *dev, struct rockchip_combphy_priv *priv)
> +{
> +       int i;
> +
> +       priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);
> +       if (priv->num_clks < 1)
> +               return -EINVAL;
> +
> +       priv->refclk = NULL;
> +       for (i = 0; i < priv->num_clks; i++) {
> +               if (!strncmp(priv->clks[i].id, "ref", 3)) {
> +                       priv->refclk = priv->clks[i].clk;
> +                       break;
> +               }
> +       }
> +
> +       if (!priv->refclk) {
> +               dev_err(dev, "no refclk found\n");
> +               return -EINVAL;
> +       }
> +
> +       priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-grf");
> +       if (IS_ERR(priv->pipe_grf)) {
> +               dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n");
> +               return PTR_ERR(priv->pipe_grf);
> +       }
> +
> +       priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-phy-grf");
> +       if (IS_ERR(priv->phy_grf)) {
> +               dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n");
> +               return PTR_ERR(priv->phy_grf);
> +       }
> +
> +       priv->enable_ssc = device_property_present(dev, "rockchip,enable-ssc");
> +
> +       priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk");
> +
> +       priv->phy_rst = devm_reset_control_array_get_exclusive(dev);
> +       if (IS_ERR(priv->phy_rst))
> +               return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n");
> +
> +       return 0;
> +}
> +
> +static int rockchip_combphy_probe(struct platform_device *pdev)
> +{
> +       struct phy_provider *phy_provider;
> +       struct device *dev = &pdev->dev;
> +       struct rockchip_combphy_priv *priv;
> +       const struct rockchip_combphy_cfg *phy_cfg;
> +       struct resource *res;
> +       int ret;
> +
> +       phy_cfg = of_device_get_match_data(dev);
> +       if (!phy_cfg) {
> +               dev_err(dev, "no OF match data provided\n");
> +               return -EINVAL;
> +       }
> +
> +       priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> +       if (!priv)
> +               return -ENOMEM;
> +
> +       priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
> +       if (IS_ERR(priv->mmio)) {
> +               ret = PTR_ERR(priv->mmio);
> +               return ret;
> +       }
> +
> +       priv->dev = dev;
> +       priv->type = PHY_NONE;
> +       priv->cfg = phy_cfg;
> +
> +       ret = rockchip_combphy_parse_dt(dev, priv);
> +       if (ret)
> +               return ret;
> +
> +       ret = reset_control_assert(priv->phy_rst);
> +       if (ret) {
> +               dev_err(dev, "failed to reset phy\n");
> +               return ret;
> +       }
> +
> +       priv->phy = devm_phy_create(dev, NULL, &rochchip_combphy_ops);
> +       if (IS_ERR(priv->phy)) {
> +               dev_err(dev, "failed to create combphy\n");
> +               return PTR_ERR(priv->phy);
> +       }
> +
> +       dev_set_drvdata(dev, priv);
> +       phy_set_drvdata(priv->phy, priv);
> +
> +       phy_provider = devm_of_phy_provider_register(dev, rockchip_combphy_xlate);
> +
> +       return PTR_ERR_OR_ZERO(phy_provider);
> +}
> +
> +static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
> +{
> +       const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
> +       unsigned long rate;
> +       u32 val;
> +
> +       switch (priv->type) {
> +       case PHY_TYPE_PCIE:
> +               /* Set SSC downward spread spectrum. */
> +               rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
> +                                        PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
> +                                        PHYREG32);
> +
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
> +               break;
> +
> +       case PHY_TYPE_USB3:
> +               /* Set SSC downward spread spectrum. */
> +               rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
> +                                        PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
> +                                        PHYREG32);
> +
> +               /* Enable adaptive CTLE for USB3.0 Rx. */
> +               val = readl(priv->mmio + PHYREG15);
> +               val |= PHYREG15_CTLE_EN;
> +               writel(val, priv->mmio + PHYREG15);
> +
> +               /* Set PLL KVCO fine tuning signals. */
> +               rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
> +                                        PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT,
> +                                        PHYREG33);
> +
> +               /* Enable controlling random jitter. */
> +               writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
> +
> +               /* Set PLL input clock divider 1/2. */
> +               rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
> +                                        PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT,
> +                                        PHYREG6);
> +
> +               writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
> +               writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
> +
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true);
> +               break;
> +
> +       case PHY_TYPE_SATA:
> +               /* Enable adaptive CTLE for SATA Rx. */
> +               val = readl(priv->mmio + PHYREG15);
> +               val |= PHYREG15_CTLE_EN;
> +               writel(val, priv->mmio + PHYREG15);
> +               /*
> +                * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA.
> +                * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm)
> +                */
> +               val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT;
> +               val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT;
> +               writel(val, priv->mmio + PHYREG7);
> +
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true);
> +               rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
> +               break;
> +
> +       case PHY_TYPE_SGMII:
> +               rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->sgmii_mode_set, true);
> +               break;
> +
> +       case PHY_TYPE_QSGMII:
> +               rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_rate_sel, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true);
> +               break;
> +
> +       default:
> +               dev_err(priv->dev, "incompatible PHY type\n");
> +               return -EINVAL;
> +       }
> +
> +       rate = clk_get_rate(priv->refclk);
> +
> +       switch (rate) {
> +       case REF_CLOCK_24MHz:
> +               if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) {
> +                       /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */
> +                       val = PHYREG15_SSC_CNT_VALUE << PHYREG15_SSC_CNT_SHIFT;
> +                       rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK,
> +                                                val, PHYREG15);
> +
> +                       writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
> +               }
> +               break;
> +
> +       case REF_CLOCK_25MHz:
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
> +               break;
> +
> +       case REF_CLOCK_100MHz:
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
> +               if (priv->type == PHY_TYPE_PCIE) {
> +                       /* PLL KVCO  fine tuning. */
> +                       val = PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT;
> +                       rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
> +                                                val, PHYREG33);
> +
> +                       /* Enable controlling random jitter. */
> +                       writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
> +
> +                       val = PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT;
> +                       rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
> +                                                val, PHYREG6);
> +
> +                       writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
> +                       writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
> +               } else if (priv->type == PHY_TYPE_SATA) {
> +                       /* downward spread spectrum +500ppm */
> +                       val = PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT;
> +                       val |= PHYREG32_SSC_OFFSET_500PPM << PHYREG32_SSC_OFFSET_SHIFT;
> +                       rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
> +               }
> +               break;
> +
> +       default:
> +               dev_err(priv->dev, "unsupported rate: %lu\n", rate);
> +               return -EINVAL;
> +       }
> +
> +       if (priv->ext_refclk) {
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
> +               if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
> +                       val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT;
> +                       val |= PHYREG13_CKRCV_AMP0;
> +                       rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13);
> +
> +                       val = readl(priv->mmio + PHYREG14);
> +                       val |= PHYREG14_CKRCV_AMP1;
> +                       writel(val, priv->mmio + PHYREG14);
> +               }
> +       }
> +
> +       if (priv->enable_ssc) {
> +               val = readl(priv->mmio + PHYREG8);
> +               val |= PHYREG8_SSC_EN;
> +               writel(val, priv->mmio + PHYREG8);
> +       }
> +
> +       return 0;
> +}
> +
> +static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = {
> +       /* pipe-phy-grf */
> +       .pcie_mode_set          = { 0x0000, 5, 0, 0x00, 0x11 },
> +       .usb_mode_set           = { 0x0000, 5, 0, 0x00, 0x04 },
> +       .sgmii_mode_set         = { 0x0000, 5, 0, 0x00, 0x01 },
> +       .qsgmii_mode_set        = { 0x0000, 5, 0, 0x00, 0x21 },
> +       .pipe_rxterm_set        = { 0x0000, 12, 12, 0x00, 0x01 },
> +       .pipe_txelec_set        = { 0x0004, 1, 1, 0x00, 0x01 },
> +       .pipe_txcomp_set        = { 0x0004, 4, 4, 0x00, 0x01 },
> +       .pipe_clk_25m           = { 0x0004, 14, 13, 0x00, 0x01 },
> +       .pipe_clk_100m          = { 0x0004, 14, 13, 0x00, 0x02 },
> +       .pipe_phymode_sel       = { 0x0008, 1, 1, 0x00, 0x01 },
> +       .pipe_rate_sel          = { 0x0008, 2, 2, 0x00, 0x01 },
> +       .pipe_rxterm_sel        = { 0x0008, 8, 8, 0x00, 0x01 },
> +       .pipe_txelec_sel        = { 0x0008, 12, 12, 0x00, 0x01 },
> +       .pipe_txcomp_sel        = { 0x0008, 15, 15, 0x00, 0x01 },
> +       .pipe_clk_ext           = { 0x000c, 9, 8, 0x02, 0x01 },
> +       .pipe_sel_usb           = { 0x000c, 14, 13, 0x00, 0x01 },
> +       .pipe_sel_qsgmii        = { 0x000c, 15, 13, 0x00, 0x07 },
> +       .pipe_phy_status        = { 0x0034, 6, 6, 0x01, 0x00 },
> +       .con0_for_pcie          = { 0x0000, 15, 0, 0x00, 0x1000 },
> +       .con1_for_pcie          = { 0x0004, 15, 0, 0x00, 0x0000 },
> +       .con2_for_pcie          = { 0x0008, 15, 0, 0x00, 0x0101 },
> +       .con3_for_pcie          = { 0x000c, 15, 0, 0x00, 0x0200 },
> +       .con0_for_sata          = { 0x0000, 15, 0, 0x00, 0x0119 },
> +       .con1_for_sata          = { 0x0004, 15, 0, 0x00, 0x0040 },
> +       .con2_for_sata          = { 0x0008, 15, 0, 0x00, 0x80c3 },
> +       .con3_for_sata          = { 0x000c, 15, 0, 0x00, 0x4407 },
> +       /* pipe-grf */
> +       .pipe_con0_for_sata     = { 0x0000, 15, 0, 0x00, 0x2220 },
> +       .pipe_xpcs_phy_ready    = { 0x0040, 2, 2, 0x00, 0x01 },
> +};
> +
> +static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {
> +       .grfcfg         = &rk3568_combphy_grfcfgs,
> +       .combphy_cfg    = rk3568_combphy_cfg,
> +};
> +
> +static const struct of_device_id rockchip_combphy_of_match[] = {
> +       {
> +               .compatible = "rockchip,rk3568-naneng-combphy",
> +               .data = &rk3568_combphy_cfgs,
> +       },
> +       { },
> +};
> +MODULE_DEVICE_TABLE(of, rockchip_combphy_of_match);
> +
> +static struct platform_driver rockchip_combphy_driver = {
> +       .probe  = rockchip_combphy_probe,
> +       .driver = {
> +               .name = "rockchip-naneng-combphy",
> +               .of_match_table = rockchip_combphy_of_match,
> +       },
> +};
> +module_platform_driver(rockchip_combphy_driver);
> +
> +MODULE_DESCRIPTION("Rockchip NANENG COMBPHY driver");
> +MODULE_LICENSE("GPL v2");
> --
> 2.17.1
>
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip

Re: [PATCH v8 3/4] phy: rockchip: add naneng combo phy for RK3568

[Peter Geis]

On Tue, Feb 8, 2022 at 4:14 AM Yifeng Zhao <yifeng.zhao@rock-chips.com> wrote:
>
> This patch implements a combo phy driver for Rockchip SoCs
> with NaNeng IP block. This phy can be used as pcie-phy, usb3-phy,
> sata-phy or sgmii-phy.
>
> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>

Tested successfully on Quartz64-A and Quartz64-B in SATA, USB3, and PCIe modes.
Tested-by: Peter Geis <pgwipeout@gmail.com>

> ---
>
> Changes in v8:
> - rename 'mode' to 'type'
> - using devm_reset_control_array_get_exclusive
> - move rockchip_combphy_set_mode into rockchip_combphy_init
>
> Changes in v7:
> - rename regs
> - remove pipe_sgmii_mac_sel, u3otg0_port_en and u3otg1_port_en
>
> Changes in v5:
> - add rockchip_combphy_updatel()
> - restyle
>
> Changes in v4:
> - restyle
> - add devm_reset_control_array_get()
> - remove clk structure
> - change refclk DT parse
> - change dev_err message
> - add dot to phrase
> - add ext_refclk variable
> - add enable_ssc variable
> - rename rockchip_combphy_param_write
> - remove param_read
> - replace rockchip-naneng-combphy driver name
>
> Changes in v3:
> - Using api devm_reset_control_get_optional_exclusive and dev_err_probe.
> - Remove apb_rst.
> - Redefine registers address.
>
> Changes in v2:
> - Using api devm_platform_get_and_ioremap_resource.
> - Modify rockchip_combphy_set_Mode.
> - Add some PHY registers definition.
>
>  drivers/phy/rockchip/Kconfig                  |   8 +
>  drivers/phy/rockchip/Makefile                 |   1 +
>  .../rockchip/phy-rockchip-naneng-combphy.c    | 581 ++++++++++++++++++
>  3 files changed, 590 insertions(+)
>  create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
>
> diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
> index e812adad7242..9022e395c056 100644
> --- a/drivers/phy/rockchip/Kconfig
> +++ b/drivers/phy/rockchip/Kconfig
> @@ -66,6 +66,14 @@ config PHY_ROCKCHIP_INNO_DSIDPHY
>           Enable this to support the Rockchip MIPI/LVDS/TTL PHY with
>           Innosilicon IP block.
>
> +config PHY_ROCKCHIP_NANENG_COMBO_PHY
> +       tristate "Rockchip NANENG COMBO PHY Driver"
> +       depends on ARCH_ROCKCHIP && OF
> +       select GENERIC_PHY
> +       help
> +         Enable this to support the Rockchip PCIe/USB3.0/SATA/QSGMII
> +         combo PHY with NaNeng IP block.
> +
>  config PHY_ROCKCHIP_PCIE
>         tristate "Rockchip PCIe PHY Driver"
>         depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST
> diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
> index f0eec212b2aa..a5041efb5b8f 100644
> --- a/drivers/phy/rockchip/Makefile
> +++ b/drivers/phy/rockchip/Makefile
> @@ -6,6 +6,7 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY) += phy-rockchip-inno-csidphy.o
>  obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY)        += phy-rockchip-inno-dsidphy.o
>  obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI)   += phy-rockchip-inno-hdmi.o
>  obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)   += phy-rockchip-inno-usb2.o
> +obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY)    += phy-rockchip-naneng-combphy.o
>  obj-$(CONFIG_PHY_ROCKCHIP_PCIE)                += phy-rockchip-pcie.o
>  obj-$(CONFIG_PHY_ROCKCHIP_TYPEC)       += phy-rockchip-typec.o
>  obj-$(CONFIG_PHY_ROCKCHIP_USB)         += phy-rockchip-usb.o
> diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> new file mode 100644
> index 000000000000..7b213825fb5d
> --- /dev/null
> +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> @@ -0,0 +1,581 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Rockchip PIPE USB3.0 PCIE SATA Combo Phy driver
> + *
> + * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
> + */
> +
> +#include <dt-bindings/phy/phy.h>
> +#include <linux/clk.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/of_device.h>
> +#include <linux/phy/phy.h>
> +#include <linux/regmap.h>
> +#include <linux/reset.h>
> +#include <linux/units.h>
> +
> +#define BIT_WRITEABLE_SHIFT            16
> +#define REF_CLOCK_24MHz                        (24 * HZ_PER_MHZ)
> +#define REF_CLOCK_25MHz                        (25 * HZ_PER_MHZ)
> +#define REF_CLOCK_100MHz               (100 * HZ_PER_MHZ)
> +
> +/* COMBO PHY REG */
> +#define PHYREG6                                0x14
> +#define PHYREG6_PLL_DIV_MASK           GENMASK(7, 6)
> +#define PHYREG6_PLL_DIV_SHIFT          6
> +#define PHYREG6_PLL_DIV_2              1
> +
> +#define PHYREG7                                0x18
> +#define PHYREG7_TX_RTERM_MASK          GENMASK(7, 4)
> +#define PHYREG7_TX_RTERM_SHIFT         4
> +#define PHYREG7_TX_RTERM_50OHM         8
> +#define PHYREG7_RX_RTERM_MASK          GENMASK(3, 0)
> +#define PHYREG7_RX_RTERM_SHIFT         0
> +#define PHYREG7_RX_RTERM_44OHM         15
> +
> +#define PHYREG8                                0x1C
> +#define PHYREG8_SSC_EN                 BIT(4)
> +
> +#define PHYREG11                       0x28
> +#define PHYREG11_SU_TRIM_0_7           0xF0
> +
> +#define PHYREG12                       0x2C
> +#define PHYREG12_PLL_LPF_ADJ_VALUE     4
> +
> +#define PHYREG13                       0x30
> +#define PHYREG13_RESISTER_MASK         GENMASK(5, 4)
> +#define PHYREG13_RESISTER_SHIFT                0x4
> +#define PHYREG13_RESISTER_HIGH_Z       3
> +#define PHYREG13_CKRCV_AMP0            BIT(7)
> +
> +#define PHYREG14                       0x34
> +#define PHYREG14_CKRCV_AMP1            BIT(0)
> +
> +#define PHYREG15                       0x38
> +#define PHYREG15_CTLE_EN               BIT(0)
> +#define PHYREG15_SSC_CNT_MASK          GENMASK(7, 6)
> +#define PHYREG15_SSC_CNT_SHIFT         6
> +#define PHYREG15_SSC_CNT_VALUE         1
> +
> +#define PHYREG16                       0x3C
> +#define PHYREG16_SSC_CNT_VALUE         0x5f
> +
> +#define PHYREG18                       0x44
> +#define PHYREG18_PLL_LOOP              0x32
> +
> +#define PHYREG32                       0x7C
> +#define PHYREG32_SSC_MASK              GENMASK(7, 4)
> +#define PHYREG32_SSC_DIR_SHIFT         4
> +#define PHYREG32_SSC_UPWARD            0
> +#define PHYREG32_SSC_DOWNWARD          1
> +#define PHYREG32_SSC_OFFSET_SHIFT      6
> +#define PHYREG32_SSC_OFFSET_500PPM     1
> +
> +#define PHYREG33                       0x80
> +#define PHYREG33_PLL_KVCO_MASK         GENMASK(4, 2)
> +#define PHYREG33_PLL_KVCO_SHIFT                2
> +#define PHYREG33_PLL_KVCO_VALUE                2
> +
> +struct rockchip_combphy_priv;
> +
> +struct combphy_reg {
> +       u16 offset;
> +       u16 bitend;
> +       u16 bitstart;
> +       u16 disable;
> +       u16 enable;
> +};
> +
> +struct rockchip_combphy_grfcfg {
> +       struct combphy_reg pcie_mode_set;
> +       struct combphy_reg usb_mode_set;
> +       struct combphy_reg sgmii_mode_set;
> +       struct combphy_reg qsgmii_mode_set;
> +       struct combphy_reg pipe_rxterm_set;
> +       struct combphy_reg pipe_txelec_set;
> +       struct combphy_reg pipe_txcomp_set;
> +       struct combphy_reg pipe_clk_25m;
> +       struct combphy_reg pipe_clk_100m;
> +       struct combphy_reg pipe_phymode_sel;
> +       struct combphy_reg pipe_rate_sel;
> +       struct combphy_reg pipe_rxterm_sel;
> +       struct combphy_reg pipe_txelec_sel;
> +       struct combphy_reg pipe_txcomp_sel;
> +       struct combphy_reg pipe_clk_ext;
> +       struct combphy_reg pipe_sel_usb;
> +       struct combphy_reg pipe_sel_qsgmii;
> +       struct combphy_reg pipe_phy_status;
> +       struct combphy_reg con0_for_pcie;
> +       struct combphy_reg con1_for_pcie;
> +       struct combphy_reg con2_for_pcie;
> +       struct combphy_reg con3_for_pcie;
> +       struct combphy_reg con0_for_sata;
> +       struct combphy_reg con1_for_sata;
> +       struct combphy_reg con2_for_sata;
> +       struct combphy_reg con3_for_sata;
> +       struct combphy_reg pipe_con0_for_sata;
> +       struct combphy_reg pipe_xpcs_phy_ready;
> +};
> +
> +struct rockchip_combphy_cfg {
> +       const struct rockchip_combphy_grfcfg *grfcfg;
> +       int (*combphy_cfg)(struct rockchip_combphy_priv *priv);
> +};
> +
> +struct rockchip_combphy_priv {
> +       u8 type;
> +       void __iomem *mmio;
> +       int num_clks;
> +       struct clk_bulk_data *clks;
> +       struct device *dev;
> +       struct regmap *pipe_grf;
> +       struct regmap *phy_grf;
> +       struct phy *phy;
> +       struct reset_control *phy_rst;
> +       const struct rockchip_combphy_cfg *cfg;
> +       bool enable_ssc;
> +       bool ext_refclk;
> +       struct clk *refclk;
> +};
> +
> +static void rockchip_combphy_updatel(struct rockchip_combphy_priv *priv,
> +                                    int mask, int val, int reg)
> +{
> +       unsigned int temp;
> +
> +       temp = readl(priv->mmio + reg);
> +       temp = (temp & ~(mask)) | val;
> +       writel(temp, priv->mmio + reg);
> +}
> +
> +static int rockchip_combphy_param_write(struct regmap *base,
> +                                       const struct combphy_reg *reg, bool en)
> +{
> +       u32 val, mask, tmp;
> +
> +       tmp = en ? reg->enable : reg->disable;
> +       mask = GENMASK(reg->bitend, reg->bitstart);
> +       val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
> +
> +       return regmap_write(base, reg->offset, val);
> +}
> +
> +static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv)
> +{
> +       const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
> +       u32 mask, val;
> +
> +       mask = GENMASK(cfg->pipe_phy_status.bitend,
> +                      cfg->pipe_phy_status.bitstart);
> +
> +       regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val);
> +       val = (val & mask) >> cfg->pipe_phy_status.bitstart;
> +
> +       return val;
> +}
> +
> +static int rockchip_combphy_init(struct phy *phy)
> +{
> +       struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
> +       const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
> +       u32 val;
> +       int ret;
> +
> +       ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
> +       if (ret) {
> +               dev_err(priv->dev, "failed to enable clks\n");
> +               return ret;
> +       }
> +
> +       switch (priv->type) {
> +       case PHY_TYPE_PCIE:
> +       case PHY_TYPE_USB3:
> +       case PHY_TYPE_SATA:
> +       case PHY_TYPE_SGMII:
> +       case PHY_TYPE_QSGMII:
> +               if (priv->cfg->combphy_cfg)
> +                       ret = priv->cfg->combphy_cfg(priv);
> +               break;
> +       default:
> +               dev_err(priv->dev, "incompatible PHY type\n");
> +               ret = -EINVAL;
> +               break;
> +       }
> +
> +       if (ret) {
> +               dev_err(priv->dev, "failed to init phy for phy type %x\n", priv->type);
> +               goto err_clk;
> +       }
> +
> +       ret = reset_control_deassert(priv->phy_rst);
> +       if (ret)
> +               goto err_clk;
> +
> +       if (priv->type == PHY_TYPE_USB3) {
> +               ret = readx_poll_timeout_atomic(rockchip_combphy_is_ready,
> +                                               priv, val,
> +                                               val == cfg->pipe_phy_status.enable,
> +                                               10, 1000);
> +               if (ret)
> +                       dev_warn(priv->dev, "wait phy status ready timeout\n");
> +       }
> +
> +       return 0;
> +
> +err_clk:
> +       clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
> +
> +       return ret;
> +}
> +
> +static int rockchip_combphy_exit(struct phy *phy)
> +{
> +       struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
> +
> +       clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
> +       reset_control_assert(priv->phy_rst);
> +
> +       return 0;
> +}
> +
> +static const struct phy_ops rochchip_combphy_ops = {
> +       .init = rockchip_combphy_init,
> +       .exit = rockchip_combphy_exit,
> +       .owner = THIS_MODULE,
> +};
> +
> +static struct phy *rockchip_combphy_xlate(struct device *dev, struct of_phandle_args *args)
> +{
> +       struct rockchip_combphy_priv *priv = dev_get_drvdata(dev);
> +
> +       if (args->args_count != 1) {
> +               dev_err(dev, "invalid number of arguments\n");
> +               return ERR_PTR(-EINVAL);
> +       }
> +
> +       if (priv->type != PHY_NONE && priv->type != args->args[0])
> +               dev_warn(dev, "phy type select %d overwriting type %d\n",
> +                        args->args[0], priv->type);
> +
> +       priv->type = args->args[0];
> +
> +       return priv->phy;
> +}
> +
> +static int rockchip_combphy_parse_dt(struct device *dev, struct rockchip_combphy_priv *priv)
> +{
> +       int i;
> +
> +       priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);
> +       if (priv->num_clks < 1)
> +               return -EINVAL;
> +
> +       priv->refclk = NULL;
> +       for (i = 0; i < priv->num_clks; i++) {
> +               if (!strncmp(priv->clks[i].id, "ref", 3)) {
> +                       priv->refclk = priv->clks[i].clk;
> +                       break;
> +               }
> +       }
> +
> +       if (!priv->refclk) {
> +               dev_err(dev, "no refclk found\n");
> +               return -EINVAL;
> +       }
> +
> +       priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-grf");
> +       if (IS_ERR(priv->pipe_grf)) {
> +               dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n");
> +               return PTR_ERR(priv->pipe_grf);
> +       }
> +
> +       priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-phy-grf");
> +       if (IS_ERR(priv->phy_grf)) {
> +               dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n");
> +               return PTR_ERR(priv->phy_grf);
> +       }
> +
> +       priv->enable_ssc = device_property_present(dev, "rockchip,enable-ssc");
> +
> +       priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk");
> +
> +       priv->phy_rst = devm_reset_control_array_get_exclusive(dev);
> +       if (IS_ERR(priv->phy_rst))
> +               return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n");
> +
> +       return 0;
> +}
> +
> +static int rockchip_combphy_probe(struct platform_device *pdev)
> +{
> +       struct phy_provider *phy_provider;
> +       struct device *dev = &pdev->dev;
> +       struct rockchip_combphy_priv *priv;
> +       const struct rockchip_combphy_cfg *phy_cfg;
> +       struct resource *res;
> +       int ret;
> +
> +       phy_cfg = of_device_get_match_data(dev);
> +       if (!phy_cfg) {
> +               dev_err(dev, "no OF match data provided\n");
> +               return -EINVAL;
> +       }
> +
> +       priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> +       if (!priv)
> +               return -ENOMEM;
> +
> +       priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
> +       if (IS_ERR(priv->mmio)) {
> +               ret = PTR_ERR(priv->mmio);
> +               return ret;
> +       }
> +
> +       priv->dev = dev;
> +       priv->type = PHY_NONE;
> +       priv->cfg = phy_cfg;
> +
> +       ret = rockchip_combphy_parse_dt(dev, priv);
> +       if (ret)
> +               return ret;
> +
> +       ret = reset_control_assert(priv->phy_rst);
> +       if (ret) {
> +               dev_err(dev, "failed to reset phy\n");
> +               return ret;
> +       }
> +
> +       priv->phy = devm_phy_create(dev, NULL, &rochchip_combphy_ops);
> +       if (IS_ERR(priv->phy)) {
> +               dev_err(dev, "failed to create combphy\n");
> +               return PTR_ERR(priv->phy);
> +       }
> +
> +       dev_set_drvdata(dev, priv);
> +       phy_set_drvdata(priv->phy, priv);
> +
> +       phy_provider = devm_of_phy_provider_register(dev, rockchip_combphy_xlate);
> +
> +       return PTR_ERR_OR_ZERO(phy_provider);
> +}
> +
> +static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
> +{
> +       const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
> +       unsigned long rate;
> +       u32 val;
> +
> +       switch (priv->type) {
> +       case PHY_TYPE_PCIE:
> +               /* Set SSC downward spread spectrum. */
> +               rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
> +                                        PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
> +                                        PHYREG32);
> +
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
> +               break;
> +
> +       case PHY_TYPE_USB3:
> +               /* Set SSC downward spread spectrum. */
> +               rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
> +                                        PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
> +                                        PHYREG32);
> +
> +               /* Enable adaptive CTLE for USB3.0 Rx. */
> +               val = readl(priv->mmio + PHYREG15);
> +               val |= PHYREG15_CTLE_EN;
> +               writel(val, priv->mmio + PHYREG15);
> +
> +               /* Set PLL KVCO fine tuning signals. */
> +               rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
> +                                        PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT,
> +                                        PHYREG33);
> +
> +               /* Enable controlling random jitter. */
> +               writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
> +
> +               /* Set PLL input clock divider 1/2. */
> +               rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
> +                                        PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT,
> +                                        PHYREG6);
> +
> +               writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
> +               writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
> +
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true);
> +               break;
> +
> +       case PHY_TYPE_SATA:
> +               /* Enable adaptive CTLE for SATA Rx. */
> +               val = readl(priv->mmio + PHYREG15);
> +               val |= PHYREG15_CTLE_EN;
> +               writel(val, priv->mmio + PHYREG15);
> +               /*
> +                * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA.
> +                * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm)
> +                */
> +               val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT;
> +               val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT;
> +               writel(val, priv->mmio + PHYREG7);
> +
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true);
> +               rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
> +               break;
> +
> +       case PHY_TYPE_SGMII:
> +               rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->sgmii_mode_set, true);
> +               break;
> +
> +       case PHY_TYPE_QSGMII:
> +               rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_rate_sel, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true);
> +               break;
> +
> +       default:
> +               dev_err(priv->dev, "incompatible PHY type\n");
> +               return -EINVAL;
> +       }
> +
> +       rate = clk_get_rate(priv->refclk);
> +
> +       switch (rate) {
> +       case REF_CLOCK_24MHz:
> +               if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) {
> +                       /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */
> +                       val = PHYREG15_SSC_CNT_VALUE << PHYREG15_SSC_CNT_SHIFT;
> +                       rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK,
> +                                                val, PHYREG15);
> +
> +                       writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
> +               }
> +               break;
> +
> +       case REF_CLOCK_25MHz:
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
> +               break;
> +
> +       case REF_CLOCK_100MHz:
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
> +               if (priv->type == PHY_TYPE_PCIE) {
> +                       /* PLL KVCO  fine tuning. */
> +                       val = PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT;
> +                       rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
> +                                                val, PHYREG33);
> +
> +                       /* Enable controlling random jitter. */
> +                       writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
> +
> +                       val = PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT;
> +                       rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
> +                                                val, PHYREG6);
> +
> +                       writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
> +                       writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
> +               } else if (priv->type == PHY_TYPE_SATA) {
> +                       /* downward spread spectrum +500ppm */
> +                       val = PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT;
> +                       val |= PHYREG32_SSC_OFFSET_500PPM << PHYREG32_SSC_OFFSET_SHIFT;
> +                       rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
> +               }
> +               break;
> +
> +       default:
> +               dev_err(priv->dev, "unsupported rate: %lu\n", rate);
> +               return -EINVAL;
> +       }
> +
> +       if (priv->ext_refclk) {
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
> +               if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
> +                       val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT;
> +                       val |= PHYREG13_CKRCV_AMP0;
> +                       rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13);
> +
> +                       val = readl(priv->mmio + PHYREG14);
> +                       val |= PHYREG14_CKRCV_AMP1;
> +                       writel(val, priv->mmio + PHYREG14);
> +               }
> +       }
> +
> +       if (priv->enable_ssc) {
> +               val = readl(priv->mmio + PHYREG8);
> +               val |= PHYREG8_SSC_EN;
> +               writel(val, priv->mmio + PHYREG8);
> +       }
> +
> +       return 0;
> +}
> +
> +static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = {
> +       /* pipe-phy-grf */
> +       .pcie_mode_set          = { 0x0000, 5, 0, 0x00, 0x11 },
> +       .usb_mode_set           = { 0x0000, 5, 0, 0x00, 0x04 },
> +       .sgmii_mode_set         = { 0x0000, 5, 0, 0x00, 0x01 },
> +       .qsgmii_mode_set        = { 0x0000, 5, 0, 0x00, 0x21 },
> +       .pipe_rxterm_set        = { 0x0000, 12, 12, 0x00, 0x01 },
> +       .pipe_txelec_set        = { 0x0004, 1, 1, 0x00, 0x01 },
> +       .pipe_txcomp_set        = { 0x0004, 4, 4, 0x00, 0x01 },
> +       .pipe_clk_25m           = { 0x0004, 14, 13, 0x00, 0x01 },
> +       .pipe_clk_100m          = { 0x0004, 14, 13, 0x00, 0x02 },
> +       .pipe_phymode_sel       = { 0x0008, 1, 1, 0x00, 0x01 },
> +       .pipe_rate_sel          = { 0x0008, 2, 2, 0x00, 0x01 },
> +       .pipe_rxterm_sel        = { 0x0008, 8, 8, 0x00, 0x01 },
> +       .pipe_txelec_sel        = { 0x0008, 12, 12, 0x00, 0x01 },
> +       .pipe_txcomp_sel        = { 0x0008, 15, 15, 0x00, 0x01 },
> +       .pipe_clk_ext           = { 0x000c, 9, 8, 0x02, 0x01 },
> +       .pipe_sel_usb           = { 0x000c, 14, 13, 0x00, 0x01 },
> +       .pipe_sel_qsgmii        = { 0x000c, 15, 13, 0x00, 0x07 },
> +       .pipe_phy_status        = { 0x0034, 6, 6, 0x01, 0x00 },
> +       .con0_for_pcie          = { 0x0000, 15, 0, 0x00, 0x1000 },
> +       .con1_for_pcie          = { 0x0004, 15, 0, 0x00, 0x0000 },
> +       .con2_for_pcie          = { 0x0008, 15, 0, 0x00, 0x0101 },
> +       .con3_for_pcie          = { 0x000c, 15, 0, 0x00, 0x0200 },
> +       .con0_for_sata          = { 0x0000, 15, 0, 0x00, 0x0119 },
> +       .con1_for_sata          = { 0x0004, 15, 0, 0x00, 0x0040 },
> +       .con2_for_sata          = { 0x0008, 15, 0, 0x00, 0x80c3 },
> +       .con3_for_sata          = { 0x000c, 15, 0, 0x00, 0x4407 },
> +       /* pipe-grf */
> +       .pipe_con0_for_sata     = { 0x0000, 15, 0, 0x00, 0x2220 },
> +       .pipe_xpcs_phy_ready    = { 0x0040, 2, 2, 0x00, 0x01 },
> +};
> +
> +static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {
> +       .grfcfg         = &rk3568_combphy_grfcfgs,
> +       .combphy_cfg    = rk3568_combphy_cfg,
> +};
> +
> +static const struct of_device_id rockchip_combphy_of_match[] = {
> +       {
> +               .compatible = "rockchip,rk3568-naneng-combphy",
> +               .data = &rk3568_combphy_cfgs,
> +       },
> +       { },
> +};
> +MODULE_DEVICE_TABLE(of, rockchip_combphy_of_match);
> +
> +static struct platform_driver rockchip_combphy_driver = {
> +       .probe  = rockchip_combphy_probe,
> +       .driver = {
> +               .name = "rockchip-naneng-combphy",
> +               .of_match_table = rockchip_combphy_of_match,
> +       },
> +};
> +module_platform_driver(rockchip_combphy_driver);
> +
> +MODULE_DESCRIPTION("Rockchip NANENG COMBPHY driver");
> +MODULE_LICENSE("GPL v2");
> --
> 2.17.1
>
>
> _______________________________________________
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> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip

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Re: [PATCH v8 3/4] phy: rockchip: add naneng combo phy for RK3568

[Peter Geis]

On Tue, Feb 8, 2022 at 4:14 AM Yifeng Zhao <yifeng.zhao@rock-chips.com> wrote:
>
> This patch implements a combo phy driver for Rockchip SoCs
> with NaNeng IP block. This phy can be used as pcie-phy, usb3-phy,
> sata-phy or sgmii-phy.
>
> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>

Tested successfully on Quartz64-A and Quartz64-B in SATA, USB3, and PCIe modes.
Tested-by: Peter Geis <pgwipeout@gmail.com>

> ---
>
> Changes in v8:
> - rename 'mode' to 'type'
> - using devm_reset_control_array_get_exclusive
> - move rockchip_combphy_set_mode into rockchip_combphy_init
>
> Changes in v7:
> - rename regs
> - remove pipe_sgmii_mac_sel, u3otg0_port_en and u3otg1_port_en
>
> Changes in v5:
> - add rockchip_combphy_updatel()
> - restyle
>
> Changes in v4:
> - restyle
> - add devm_reset_control_array_get()
> - remove clk structure
> - change refclk DT parse
> - change dev_err message
> - add dot to phrase
> - add ext_refclk variable
> - add enable_ssc variable
> - rename rockchip_combphy_param_write
> - remove param_read
> - replace rockchip-naneng-combphy driver name
>
> Changes in v3:
> - Using api devm_reset_control_get_optional_exclusive and dev_err_probe.
> - Remove apb_rst.
> - Redefine registers address.
>
> Changes in v2:
> - Using api devm_platform_get_and_ioremap_resource.
> - Modify rockchip_combphy_set_Mode.
> - Add some PHY registers definition.
>
>  drivers/phy/rockchip/Kconfig                  |   8 +
>  drivers/phy/rockchip/Makefile                 |   1 +
>  .../rockchip/phy-rockchip-naneng-combphy.c    | 581 ++++++++++++++++++
>  3 files changed, 590 insertions(+)
>  create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
>
> diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
> index e812adad7242..9022e395c056 100644
> --- a/drivers/phy/rockchip/Kconfig
> +++ b/drivers/phy/rockchip/Kconfig
> @@ -66,6 +66,14 @@ config PHY_ROCKCHIP_INNO_DSIDPHY
>           Enable this to support the Rockchip MIPI/LVDS/TTL PHY with
>           Innosilicon IP block.
>
> +config PHY_ROCKCHIP_NANENG_COMBO_PHY
> +       tristate "Rockchip NANENG COMBO PHY Driver"
> +       depends on ARCH_ROCKCHIP && OF
> +       select GENERIC_PHY
> +       help
> +         Enable this to support the Rockchip PCIe/USB3.0/SATA/QSGMII
> +         combo PHY with NaNeng IP block.
> +
>  config PHY_ROCKCHIP_PCIE
>         tristate "Rockchip PCIe PHY Driver"
>         depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST
> diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
> index f0eec212b2aa..a5041efb5b8f 100644
> --- a/drivers/phy/rockchip/Makefile
> +++ b/drivers/phy/rockchip/Makefile
> @@ -6,6 +6,7 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY) += phy-rockchip-inno-csidphy.o
>  obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY)        += phy-rockchip-inno-dsidphy.o
>  obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI)   += phy-rockchip-inno-hdmi.o
>  obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)   += phy-rockchip-inno-usb2.o
> +obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY)    += phy-rockchip-naneng-combphy.o
>  obj-$(CONFIG_PHY_ROCKCHIP_PCIE)                += phy-rockchip-pcie.o
>  obj-$(CONFIG_PHY_ROCKCHIP_TYPEC)       += phy-rockchip-typec.o
>  obj-$(CONFIG_PHY_ROCKCHIP_USB)         += phy-rockchip-usb.o
> diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> new file mode 100644
> index 000000000000..7b213825fb5d
> --- /dev/null
> +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> @@ -0,0 +1,581 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Rockchip PIPE USB3.0 PCIE SATA Combo Phy driver
> + *
> + * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
> + */
> +
> +#include <dt-bindings/phy/phy.h>
> +#include <linux/clk.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/of_device.h>
> +#include <linux/phy/phy.h>
> +#include <linux/regmap.h>
> +#include <linux/reset.h>
> +#include <linux/units.h>
> +
> +#define BIT_WRITEABLE_SHIFT            16
> +#define REF_CLOCK_24MHz                        (24 * HZ_PER_MHZ)
> +#define REF_CLOCK_25MHz                        (25 * HZ_PER_MHZ)
> +#define REF_CLOCK_100MHz               (100 * HZ_PER_MHZ)
> +
> +/* COMBO PHY REG */
> +#define PHYREG6                                0x14
> +#define PHYREG6_PLL_DIV_MASK           GENMASK(7, 6)
> +#define PHYREG6_PLL_DIV_SHIFT          6
> +#define PHYREG6_PLL_DIV_2              1
> +
> +#define PHYREG7                                0x18
> +#define PHYREG7_TX_RTERM_MASK          GENMASK(7, 4)
> +#define PHYREG7_TX_RTERM_SHIFT         4
> +#define PHYREG7_TX_RTERM_50OHM         8
> +#define PHYREG7_RX_RTERM_MASK          GENMASK(3, 0)
> +#define PHYREG7_RX_RTERM_SHIFT         0
> +#define PHYREG7_RX_RTERM_44OHM         15
> +
> +#define PHYREG8                                0x1C
> +#define PHYREG8_SSC_EN                 BIT(4)
> +
> +#define PHYREG11                       0x28
> +#define PHYREG11_SU_TRIM_0_7           0xF0
> +
> +#define PHYREG12                       0x2C
> +#define PHYREG12_PLL_LPF_ADJ_VALUE     4
> +
> +#define PHYREG13                       0x30
> +#define PHYREG13_RESISTER_MASK         GENMASK(5, 4)
> +#define PHYREG13_RESISTER_SHIFT                0x4
> +#define PHYREG13_RESISTER_HIGH_Z       3
> +#define PHYREG13_CKRCV_AMP0            BIT(7)
> +
> +#define PHYREG14                       0x34
> +#define PHYREG14_CKRCV_AMP1            BIT(0)
> +
> +#define PHYREG15                       0x38
> +#define PHYREG15_CTLE_EN               BIT(0)
> +#define PHYREG15_SSC_CNT_MASK          GENMASK(7, 6)
> +#define PHYREG15_SSC_CNT_SHIFT         6
> +#define PHYREG15_SSC_CNT_VALUE         1
> +
> +#define PHYREG16                       0x3C
> +#define PHYREG16_SSC_CNT_VALUE         0x5f
> +
> +#define PHYREG18                       0x44
> +#define PHYREG18_PLL_LOOP              0x32
> +
> +#define PHYREG32                       0x7C
> +#define PHYREG32_SSC_MASK              GENMASK(7, 4)
> +#define PHYREG32_SSC_DIR_SHIFT         4
> +#define PHYREG32_SSC_UPWARD            0
> +#define PHYREG32_SSC_DOWNWARD          1
> +#define PHYREG32_SSC_OFFSET_SHIFT      6
> +#define PHYREG32_SSC_OFFSET_500PPM     1
> +
> +#define PHYREG33                       0x80
> +#define PHYREG33_PLL_KVCO_MASK         GENMASK(4, 2)
> +#define PHYREG33_PLL_KVCO_SHIFT                2
> +#define PHYREG33_PLL_KVCO_VALUE                2
> +
> +struct rockchip_combphy_priv;
> +
> +struct combphy_reg {
> +       u16 offset;
> +       u16 bitend;
> +       u16 bitstart;
> +       u16 disable;
> +       u16 enable;
> +};
> +
> +struct rockchip_combphy_grfcfg {
> +       struct combphy_reg pcie_mode_set;
> +       struct combphy_reg usb_mode_set;
> +       struct combphy_reg sgmii_mode_set;
> +       struct combphy_reg qsgmii_mode_set;
> +       struct combphy_reg pipe_rxterm_set;
> +       struct combphy_reg pipe_txelec_set;
> +       struct combphy_reg pipe_txcomp_set;
> +       struct combphy_reg pipe_clk_25m;
> +       struct combphy_reg pipe_clk_100m;
> +       struct combphy_reg pipe_phymode_sel;
> +       struct combphy_reg pipe_rate_sel;
> +       struct combphy_reg pipe_rxterm_sel;
> +       struct combphy_reg pipe_txelec_sel;
> +       struct combphy_reg pipe_txcomp_sel;
> +       struct combphy_reg pipe_clk_ext;
> +       struct combphy_reg pipe_sel_usb;
> +       struct combphy_reg pipe_sel_qsgmii;
> +       struct combphy_reg pipe_phy_status;
> +       struct combphy_reg con0_for_pcie;
> +       struct combphy_reg con1_for_pcie;
> +       struct combphy_reg con2_for_pcie;
> +       struct combphy_reg con3_for_pcie;
> +       struct combphy_reg con0_for_sata;
> +       struct combphy_reg con1_for_sata;
> +       struct combphy_reg con2_for_sata;
> +       struct combphy_reg con3_for_sata;
> +       struct combphy_reg pipe_con0_for_sata;
> +       struct combphy_reg pipe_xpcs_phy_ready;
> +};
> +
> +struct rockchip_combphy_cfg {
> +       const struct rockchip_combphy_grfcfg *grfcfg;
> +       int (*combphy_cfg)(struct rockchip_combphy_priv *priv);
> +};
> +
> +struct rockchip_combphy_priv {
> +       u8 type;
> +       void __iomem *mmio;
> +       int num_clks;
> +       struct clk_bulk_data *clks;
> +       struct device *dev;
> +       struct regmap *pipe_grf;
> +       struct regmap *phy_grf;
> +       struct phy *phy;
> +       struct reset_control *phy_rst;
> +       const struct rockchip_combphy_cfg *cfg;
> +       bool enable_ssc;
> +       bool ext_refclk;
> +       struct clk *refclk;
> +};
> +
> +static void rockchip_combphy_updatel(struct rockchip_combphy_priv *priv,
> +                                    int mask, int val, int reg)
> +{
> +       unsigned int temp;
> +
> +       temp = readl(priv->mmio + reg);
> +       temp = (temp & ~(mask)) | val;
> +       writel(temp, priv->mmio + reg);
> +}
> +
> +static int rockchip_combphy_param_write(struct regmap *base,
> +                                       const struct combphy_reg *reg, bool en)
> +{
> +       u32 val, mask, tmp;
> +
> +       tmp = en ? reg->enable : reg->disable;
> +       mask = GENMASK(reg->bitend, reg->bitstart);
> +       val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
> +
> +       return regmap_write(base, reg->offset, val);
> +}
> +
> +static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv)
> +{
> +       const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
> +       u32 mask, val;
> +
> +       mask = GENMASK(cfg->pipe_phy_status.bitend,
> +                      cfg->pipe_phy_status.bitstart);
> +
> +       regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val);
> +       val = (val & mask) >> cfg->pipe_phy_status.bitstart;
> +
> +       return val;
> +}
> +
> +static int rockchip_combphy_init(struct phy *phy)
> +{
> +       struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
> +       const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
> +       u32 val;
> +       int ret;
> +
> +       ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
> +       if (ret) {
> +               dev_err(priv->dev, "failed to enable clks\n");
> +               return ret;
> +       }
> +
> +       switch (priv->type) {
> +       case PHY_TYPE_PCIE:
> +       case PHY_TYPE_USB3:
> +       case PHY_TYPE_SATA:
> +       case PHY_TYPE_SGMII:
> +       case PHY_TYPE_QSGMII:
> +               if (priv->cfg->combphy_cfg)
> +                       ret = priv->cfg->combphy_cfg(priv);
> +               break;
> +       default:
> +               dev_err(priv->dev, "incompatible PHY type\n");
> +               ret = -EINVAL;
> +               break;
> +       }
> +
> +       if (ret) {
> +               dev_err(priv->dev, "failed to init phy for phy type %x\n", priv->type);
> +               goto err_clk;
> +       }
> +
> +       ret = reset_control_deassert(priv->phy_rst);
> +       if (ret)
> +               goto err_clk;
> +
> +       if (priv->type == PHY_TYPE_USB3) {
> +               ret = readx_poll_timeout_atomic(rockchip_combphy_is_ready,
> +                                               priv, val,
> +                                               val == cfg->pipe_phy_status.enable,
> +                                               10, 1000);
> +               if (ret)
> +                       dev_warn(priv->dev, "wait phy status ready timeout\n");
> +       }
> +
> +       return 0;
> +
> +err_clk:
> +       clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
> +
> +       return ret;
> +}
> +
> +static int rockchip_combphy_exit(struct phy *phy)
> +{
> +       struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
> +
> +       clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
> +       reset_control_assert(priv->phy_rst);
> +
> +       return 0;
> +}
> +
> +static const struct phy_ops rochchip_combphy_ops = {
> +       .init = rockchip_combphy_init,
> +       .exit = rockchip_combphy_exit,
> +       .owner = THIS_MODULE,
> +};
> +
> +static struct phy *rockchip_combphy_xlate(struct device *dev, struct of_phandle_args *args)
> +{
> +       struct rockchip_combphy_priv *priv = dev_get_drvdata(dev);
> +
> +       if (args->args_count != 1) {
> +               dev_err(dev, "invalid number of arguments\n");
> +               return ERR_PTR(-EINVAL);
> +       }
> +
> +       if (priv->type != PHY_NONE && priv->type != args->args[0])
> +               dev_warn(dev, "phy type select %d overwriting type %d\n",
> +                        args->args[0], priv->type);
> +
> +       priv->type = args->args[0];
> +
> +       return priv->phy;
> +}
> +
> +static int rockchip_combphy_parse_dt(struct device *dev, struct rockchip_combphy_priv *priv)
> +{
> +       int i;
> +
> +       priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);
> +       if (priv->num_clks < 1)
> +               return -EINVAL;
> +
> +       priv->refclk = NULL;
> +       for (i = 0; i < priv->num_clks; i++) {
> +               if (!strncmp(priv->clks[i].id, "ref", 3)) {
> +                       priv->refclk = priv->clks[i].clk;
> +                       break;
> +               }
> +       }
> +
> +       if (!priv->refclk) {
> +               dev_err(dev, "no refclk found\n");
> +               return -EINVAL;
> +       }
> +
> +       priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-grf");
> +       if (IS_ERR(priv->pipe_grf)) {
> +               dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n");
> +               return PTR_ERR(priv->pipe_grf);
> +       }
> +
> +       priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-phy-grf");
> +       if (IS_ERR(priv->phy_grf)) {
> +               dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n");
> +               return PTR_ERR(priv->phy_grf);
> +       }
> +
> +       priv->enable_ssc = device_property_present(dev, "rockchip,enable-ssc");
> +
> +       priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk");
> +
> +       priv->phy_rst = devm_reset_control_array_get_exclusive(dev);
> +       if (IS_ERR(priv->phy_rst))
> +               return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n");
> +
> +       return 0;
> +}
> +
> +static int rockchip_combphy_probe(struct platform_device *pdev)
> +{
> +       struct phy_provider *phy_provider;
> +       struct device *dev = &pdev->dev;
> +       struct rockchip_combphy_priv *priv;
> +       const struct rockchip_combphy_cfg *phy_cfg;
> +       struct resource *res;
> +       int ret;
> +
> +       phy_cfg = of_device_get_match_data(dev);
> +       if (!phy_cfg) {
> +               dev_err(dev, "no OF match data provided\n");
> +               return -EINVAL;
> +       }
> +
> +       priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> +       if (!priv)
> +               return -ENOMEM;
> +
> +       priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
> +       if (IS_ERR(priv->mmio)) {
> +               ret = PTR_ERR(priv->mmio);
> +               return ret;
> +       }
> +
> +       priv->dev = dev;
> +       priv->type = PHY_NONE;
> +       priv->cfg = phy_cfg;
> +
> +       ret = rockchip_combphy_parse_dt(dev, priv);
> +       if (ret)
> +               return ret;
> +
> +       ret = reset_control_assert(priv->phy_rst);
> +       if (ret) {
> +               dev_err(dev, "failed to reset phy\n");
> +               return ret;
> +       }
> +
> +       priv->phy = devm_phy_create(dev, NULL, &rochchip_combphy_ops);
> +       if (IS_ERR(priv->phy)) {
> +               dev_err(dev, "failed to create combphy\n");
> +               return PTR_ERR(priv->phy);
> +       }
> +
> +       dev_set_drvdata(dev, priv);
> +       phy_set_drvdata(priv->phy, priv);
> +
> +       phy_provider = devm_of_phy_provider_register(dev, rockchip_combphy_xlate);
> +
> +       return PTR_ERR_OR_ZERO(phy_provider);
> +}
> +
> +static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
> +{
> +       const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
> +       unsigned long rate;
> +       u32 val;
> +
> +       switch (priv->type) {
> +       case PHY_TYPE_PCIE:
> +               /* Set SSC downward spread spectrum. */
> +               rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
> +                                        PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
> +                                        PHYREG32);
> +
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
> +               break;
> +
> +       case PHY_TYPE_USB3:
> +               /* Set SSC downward spread spectrum. */
> +               rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
> +                                        PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
> +                                        PHYREG32);
> +
> +               /* Enable adaptive CTLE for USB3.0 Rx. */
> +               val = readl(priv->mmio + PHYREG15);
> +               val |= PHYREG15_CTLE_EN;
> +               writel(val, priv->mmio + PHYREG15);
> +
> +               /* Set PLL KVCO fine tuning signals. */
> +               rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
> +                                        PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT,
> +                                        PHYREG33);
> +
> +               /* Enable controlling random jitter. */
> +               writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
> +
> +               /* Set PLL input clock divider 1/2. */
> +               rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
> +                                        PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT,
> +                                        PHYREG6);
> +
> +               writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
> +               writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
> +
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true);
> +               break;
> +
> +       case PHY_TYPE_SATA:
> +               /* Enable adaptive CTLE for SATA Rx. */
> +               val = readl(priv->mmio + PHYREG15);
> +               val |= PHYREG15_CTLE_EN;
> +               writel(val, priv->mmio + PHYREG15);
> +               /*
> +                * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA.
> +                * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm)
> +                */
> +               val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT;
> +               val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT;
> +               writel(val, priv->mmio + PHYREG7);
> +
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true);
> +               rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
> +               break;
> +
> +       case PHY_TYPE_SGMII:
> +               rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->sgmii_mode_set, true);
> +               break;
> +
> +       case PHY_TYPE_QSGMII:
> +               rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_rate_sel, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true);
> +               break;
> +
> +       default:
> +               dev_err(priv->dev, "incompatible PHY type\n");
> +               return -EINVAL;
> +       }
> +
> +       rate = clk_get_rate(priv->refclk);
> +
> +       switch (rate) {
> +       case REF_CLOCK_24MHz:
> +               if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) {
> +                       /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */
> +                       val = PHYREG15_SSC_CNT_VALUE << PHYREG15_SSC_CNT_SHIFT;
> +                       rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK,
> +                                                val, PHYREG15);
> +
> +                       writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
> +               }
> +               break;
> +
> +       case REF_CLOCK_25MHz:
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
> +               break;
> +
> +       case REF_CLOCK_100MHz:
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
> +               if (priv->type == PHY_TYPE_PCIE) {
> +                       /* PLL KVCO  fine tuning. */
> +                       val = PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT;
> +                       rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
> +                                                val, PHYREG33);
> +
> +                       /* Enable controlling random jitter. */
> +                       writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
> +
> +                       val = PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT;
> +                       rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
> +                                                val, PHYREG6);
> +
> +                       writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
> +                       writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
> +               } else if (priv->type == PHY_TYPE_SATA) {
> +                       /* downward spread spectrum +500ppm */
> +                       val = PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT;
> +                       val |= PHYREG32_SSC_OFFSET_500PPM << PHYREG32_SSC_OFFSET_SHIFT;
> +                       rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
> +               }
> +               break;
> +
> +       default:
> +               dev_err(priv->dev, "unsupported rate: %lu\n", rate);
> +               return -EINVAL;
> +       }
> +
> +       if (priv->ext_refclk) {
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
> +               if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
> +                       val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT;
> +                       val |= PHYREG13_CKRCV_AMP0;
> +                       rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13);
> +
> +                       val = readl(priv->mmio + PHYREG14);
> +                       val |= PHYREG14_CKRCV_AMP1;
> +                       writel(val, priv->mmio + PHYREG14);
> +               }
> +       }
> +
> +       if (priv->enable_ssc) {
> +               val = readl(priv->mmio + PHYREG8);
> +               val |= PHYREG8_SSC_EN;
> +               writel(val, priv->mmio + PHYREG8);
> +       }
> +
> +       return 0;
> +}
> +
> +static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = {
> +       /* pipe-phy-grf */
> +       .pcie_mode_set          = { 0x0000, 5, 0, 0x00, 0x11 },
> +       .usb_mode_set           = { 0x0000, 5, 0, 0x00, 0x04 },
> +       .sgmii_mode_set         = { 0x0000, 5, 0, 0x00, 0x01 },
> +       .qsgmii_mode_set        = { 0x0000, 5, 0, 0x00, 0x21 },
> +       .pipe_rxterm_set        = { 0x0000, 12, 12, 0x00, 0x01 },
> +       .pipe_txelec_set        = { 0x0004, 1, 1, 0x00, 0x01 },
> +       .pipe_txcomp_set        = { 0x0004, 4, 4, 0x00, 0x01 },
> +       .pipe_clk_25m           = { 0x0004, 14, 13, 0x00, 0x01 },
> +       .pipe_clk_100m          = { 0x0004, 14, 13, 0x00, 0x02 },
> +       .pipe_phymode_sel       = { 0x0008, 1, 1, 0x00, 0x01 },
> +       .pipe_rate_sel          = { 0x0008, 2, 2, 0x00, 0x01 },
> +       .pipe_rxterm_sel        = { 0x0008, 8, 8, 0x00, 0x01 },
> +       .pipe_txelec_sel        = { 0x0008, 12, 12, 0x00, 0x01 },
> +       .pipe_txcomp_sel        = { 0x0008, 15, 15, 0x00, 0x01 },
> +       .pipe_clk_ext           = { 0x000c, 9, 8, 0x02, 0x01 },
> +       .pipe_sel_usb           = { 0x000c, 14, 13, 0x00, 0x01 },
> +       .pipe_sel_qsgmii        = { 0x000c, 15, 13, 0x00, 0x07 },
> +       .pipe_phy_status        = { 0x0034, 6, 6, 0x01, 0x00 },
> +       .con0_for_pcie          = { 0x0000, 15, 0, 0x00, 0x1000 },
> +       .con1_for_pcie          = { 0x0004, 15, 0, 0x00, 0x0000 },
> +       .con2_for_pcie          = { 0x0008, 15, 0, 0x00, 0x0101 },
> +       .con3_for_pcie          = { 0x000c, 15, 0, 0x00, 0x0200 },
> +       .con0_for_sata          = { 0x0000, 15, 0, 0x00, 0x0119 },
> +       .con1_for_sata          = { 0x0004, 15, 0, 0x00, 0x0040 },
> +       .con2_for_sata          = { 0x0008, 15, 0, 0x00, 0x80c3 },
> +       .con3_for_sata          = { 0x000c, 15, 0, 0x00, 0x4407 },
> +       /* pipe-grf */
> +       .pipe_con0_for_sata     = { 0x0000, 15, 0, 0x00, 0x2220 },
> +       .pipe_xpcs_phy_ready    = { 0x0040, 2, 2, 0x00, 0x01 },
> +};
> +
> +static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {
> +       .grfcfg         = &rk3568_combphy_grfcfgs,
> +       .combphy_cfg    = rk3568_combphy_cfg,
> +};
> +
> +static const struct of_device_id rockchip_combphy_of_match[] = {
> +       {
> +               .compatible = "rockchip,rk3568-naneng-combphy",
> +               .data = &rk3568_combphy_cfgs,
> +       },
> +       { },
> +};
> +MODULE_DEVICE_TABLE(of, rockchip_combphy_of_match);
> +
> +static struct platform_driver rockchip_combphy_driver = {
> +       .probe  = rockchip_combphy_probe,
> +       .driver = {
> +               .name = "rockchip-naneng-combphy",
> +               .of_match_table = rockchip_combphy_of_match,
> +       },
> +};
> +module_platform_driver(rockchip_combphy_driver);
> +
> +MODULE_DESCRIPTION("Rockchip NANENG COMBPHY driver");
> +MODULE_LICENSE("GPL v2");
> --
> 2.17.1
>
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip

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linux-phy@lists.infradead.org
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Re: [PATCH v8 3/4] phy: rockchip: add naneng combo phy for RK3568

[Peter Geis]

On Tue, Feb 8, 2022 at 4:14 AM Yifeng Zhao <yifeng.zhao@rock-chips.com> wrote:
>
> This patch implements a combo phy driver for Rockchip SoCs
> with NaNeng IP block. This phy can be used as pcie-phy, usb3-phy,
> sata-phy or sgmii-phy.
>
> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>

Tested successfully on Quartz64-A and Quartz64-B in SATA, USB3, and PCIe modes.
Tested-by: Peter Geis <pgwipeout@gmail.com>

> ---
>
> Changes in v8:
> - rename 'mode' to 'type'
> - using devm_reset_control_array_get_exclusive
> - move rockchip_combphy_set_mode into rockchip_combphy_init
>
> Changes in v7:
> - rename regs
> - remove pipe_sgmii_mac_sel, u3otg0_port_en and u3otg1_port_en
>
> Changes in v5:
> - add rockchip_combphy_updatel()
> - restyle
>
> Changes in v4:
> - restyle
> - add devm_reset_control_array_get()
> - remove clk structure
> - change refclk DT parse
> - change dev_err message
> - add dot to phrase
> - add ext_refclk variable
> - add enable_ssc variable
> - rename rockchip_combphy_param_write
> - remove param_read
> - replace rockchip-naneng-combphy driver name
>
> Changes in v3:
> - Using api devm_reset_control_get_optional_exclusive and dev_err_probe.
> - Remove apb_rst.
> - Redefine registers address.
>
> Changes in v2:
> - Using api devm_platform_get_and_ioremap_resource.
> - Modify rockchip_combphy_set_Mode.
> - Add some PHY registers definition.
>
>  drivers/phy/rockchip/Kconfig                  |   8 +
>  drivers/phy/rockchip/Makefile                 |   1 +
>  .../rockchip/phy-rockchip-naneng-combphy.c    | 581 ++++++++++++++++++
>  3 files changed, 590 insertions(+)
>  create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
>
> diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
> index e812adad7242..9022e395c056 100644
> --- a/drivers/phy/rockchip/Kconfig
> +++ b/drivers/phy/rockchip/Kconfig
> @@ -66,6 +66,14 @@ config PHY_ROCKCHIP_INNO_DSIDPHY
>           Enable this to support the Rockchip MIPI/LVDS/TTL PHY with
>           Innosilicon IP block.
>
> +config PHY_ROCKCHIP_NANENG_COMBO_PHY
> +       tristate "Rockchip NANENG COMBO PHY Driver"
> +       depends on ARCH_ROCKCHIP && OF
> +       select GENERIC_PHY
> +       help
> +         Enable this to support the Rockchip PCIe/USB3.0/SATA/QSGMII
> +         combo PHY with NaNeng IP block.
> +
>  config PHY_ROCKCHIP_PCIE
>         tristate "Rockchip PCIe PHY Driver"
>         depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST
> diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
> index f0eec212b2aa..a5041efb5b8f 100644
> --- a/drivers/phy/rockchip/Makefile
> +++ b/drivers/phy/rockchip/Makefile
> @@ -6,6 +6,7 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY) += phy-rockchip-inno-csidphy.o
>  obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY)        += phy-rockchip-inno-dsidphy.o
>  obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI)   += phy-rockchip-inno-hdmi.o
>  obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)   += phy-rockchip-inno-usb2.o
> +obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY)    += phy-rockchip-naneng-combphy.o
>  obj-$(CONFIG_PHY_ROCKCHIP_PCIE)                += phy-rockchip-pcie.o
>  obj-$(CONFIG_PHY_ROCKCHIP_TYPEC)       += phy-rockchip-typec.o
>  obj-$(CONFIG_PHY_ROCKCHIP_USB)         += phy-rockchip-usb.o
> diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> new file mode 100644
> index 000000000000..7b213825fb5d
> --- /dev/null
> +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> @@ -0,0 +1,581 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Rockchip PIPE USB3.0 PCIE SATA Combo Phy driver
> + *
> + * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
> + */
> +
> +#include <dt-bindings/phy/phy.h>
> +#include <linux/clk.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/of_device.h>
> +#include <linux/phy/phy.h>
> +#include <linux/regmap.h>
> +#include <linux/reset.h>
> +#include <linux/units.h>
> +
> +#define BIT_WRITEABLE_SHIFT            16
> +#define REF_CLOCK_24MHz                        (24 * HZ_PER_MHZ)
> +#define REF_CLOCK_25MHz                        (25 * HZ_PER_MHZ)
> +#define REF_CLOCK_100MHz               (100 * HZ_PER_MHZ)
> +
> +/* COMBO PHY REG */
> +#define PHYREG6                                0x14
> +#define PHYREG6_PLL_DIV_MASK           GENMASK(7, 6)
> +#define PHYREG6_PLL_DIV_SHIFT          6
> +#define PHYREG6_PLL_DIV_2              1
> +
> +#define PHYREG7                                0x18
> +#define PHYREG7_TX_RTERM_MASK          GENMASK(7, 4)
> +#define PHYREG7_TX_RTERM_SHIFT         4
> +#define PHYREG7_TX_RTERM_50OHM         8
> +#define PHYREG7_RX_RTERM_MASK          GENMASK(3, 0)
> +#define PHYREG7_RX_RTERM_SHIFT         0
> +#define PHYREG7_RX_RTERM_44OHM         15
> +
> +#define PHYREG8                                0x1C
> +#define PHYREG8_SSC_EN                 BIT(4)
> +
> +#define PHYREG11                       0x28
> +#define PHYREG11_SU_TRIM_0_7           0xF0
> +
> +#define PHYREG12                       0x2C
> +#define PHYREG12_PLL_LPF_ADJ_VALUE     4
> +
> +#define PHYREG13                       0x30
> +#define PHYREG13_RESISTER_MASK         GENMASK(5, 4)
> +#define PHYREG13_RESISTER_SHIFT                0x4
> +#define PHYREG13_RESISTER_HIGH_Z       3
> +#define PHYREG13_CKRCV_AMP0            BIT(7)
> +
> +#define PHYREG14                       0x34
> +#define PHYREG14_CKRCV_AMP1            BIT(0)
> +
> +#define PHYREG15                       0x38
> +#define PHYREG15_CTLE_EN               BIT(0)
> +#define PHYREG15_SSC_CNT_MASK          GENMASK(7, 6)
> +#define PHYREG15_SSC_CNT_SHIFT         6
> +#define PHYREG15_SSC_CNT_VALUE         1
> +
> +#define PHYREG16                       0x3C
> +#define PHYREG16_SSC_CNT_VALUE         0x5f
> +
> +#define PHYREG18                       0x44
> +#define PHYREG18_PLL_LOOP              0x32
> +
> +#define PHYREG32                       0x7C
> +#define PHYREG32_SSC_MASK              GENMASK(7, 4)
> +#define PHYREG32_SSC_DIR_SHIFT         4
> +#define PHYREG32_SSC_UPWARD            0
> +#define PHYREG32_SSC_DOWNWARD          1
> +#define PHYREG32_SSC_OFFSET_SHIFT      6
> +#define PHYREG32_SSC_OFFSET_500PPM     1
> +
> +#define PHYREG33                       0x80
> +#define PHYREG33_PLL_KVCO_MASK         GENMASK(4, 2)
> +#define PHYREG33_PLL_KVCO_SHIFT                2
> +#define PHYREG33_PLL_KVCO_VALUE                2
> +
> +struct rockchip_combphy_priv;
> +
> +struct combphy_reg {
> +       u16 offset;
> +       u16 bitend;
> +       u16 bitstart;
> +       u16 disable;
> +       u16 enable;
> +};
> +
> +struct rockchip_combphy_grfcfg {
> +       struct combphy_reg pcie_mode_set;
> +       struct combphy_reg usb_mode_set;
> +       struct combphy_reg sgmii_mode_set;
> +       struct combphy_reg qsgmii_mode_set;
> +       struct combphy_reg pipe_rxterm_set;
> +       struct combphy_reg pipe_txelec_set;
> +       struct combphy_reg pipe_txcomp_set;
> +       struct combphy_reg pipe_clk_25m;
> +       struct combphy_reg pipe_clk_100m;
> +       struct combphy_reg pipe_phymode_sel;
> +       struct combphy_reg pipe_rate_sel;
> +       struct combphy_reg pipe_rxterm_sel;
> +       struct combphy_reg pipe_txelec_sel;
> +       struct combphy_reg pipe_txcomp_sel;
> +       struct combphy_reg pipe_clk_ext;
> +       struct combphy_reg pipe_sel_usb;
> +       struct combphy_reg pipe_sel_qsgmii;
> +       struct combphy_reg pipe_phy_status;
> +       struct combphy_reg con0_for_pcie;
> +       struct combphy_reg con1_for_pcie;
> +       struct combphy_reg con2_for_pcie;
> +       struct combphy_reg con3_for_pcie;
> +       struct combphy_reg con0_for_sata;
> +       struct combphy_reg con1_for_sata;
> +       struct combphy_reg con2_for_sata;
> +       struct combphy_reg con3_for_sata;
> +       struct combphy_reg pipe_con0_for_sata;
> +       struct combphy_reg pipe_xpcs_phy_ready;
> +};
> +
> +struct rockchip_combphy_cfg {
> +       const struct rockchip_combphy_grfcfg *grfcfg;
> +       int (*combphy_cfg)(struct rockchip_combphy_priv *priv);
> +};
> +
> +struct rockchip_combphy_priv {
> +       u8 type;
> +       void __iomem *mmio;
> +       int num_clks;
> +       struct clk_bulk_data *clks;
> +       struct device *dev;
> +       struct regmap *pipe_grf;
> +       struct regmap *phy_grf;
> +       struct phy *phy;
> +       struct reset_control *phy_rst;
> +       const struct rockchip_combphy_cfg *cfg;
> +       bool enable_ssc;
> +       bool ext_refclk;
> +       struct clk *refclk;
> +};
> +
> +static void rockchip_combphy_updatel(struct rockchip_combphy_priv *priv,
> +                                    int mask, int val, int reg)
> +{
> +       unsigned int temp;
> +
> +       temp = readl(priv->mmio + reg);
> +       temp = (temp & ~(mask)) | val;
> +       writel(temp, priv->mmio + reg);
> +}
> +
> +static int rockchip_combphy_param_write(struct regmap *base,
> +                                       const struct combphy_reg *reg, bool en)
> +{
> +       u32 val, mask, tmp;
> +
> +       tmp = en ? reg->enable : reg->disable;
> +       mask = GENMASK(reg->bitend, reg->bitstart);
> +       val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
> +
> +       return regmap_write(base, reg->offset, val);
> +}
> +
> +static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv)
> +{
> +       const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
> +       u32 mask, val;
> +
> +       mask = GENMASK(cfg->pipe_phy_status.bitend,
> +                      cfg->pipe_phy_status.bitstart);
> +
> +       regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val);
> +       val = (val & mask) >> cfg->pipe_phy_status.bitstart;
> +
> +       return val;
> +}
> +
> +static int rockchip_combphy_init(struct phy *phy)
> +{
> +       struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
> +       const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
> +       u32 val;
> +       int ret;
> +
> +       ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
> +       if (ret) {
> +               dev_err(priv->dev, "failed to enable clks\n");
> +               return ret;
> +       }
> +
> +       switch (priv->type) {
> +       case PHY_TYPE_PCIE:
> +       case PHY_TYPE_USB3:
> +       case PHY_TYPE_SATA:
> +       case PHY_TYPE_SGMII:
> +       case PHY_TYPE_QSGMII:
> +               if (priv->cfg->combphy_cfg)
> +                       ret = priv->cfg->combphy_cfg(priv);
> +               break;
> +       default:
> +               dev_err(priv->dev, "incompatible PHY type\n");
> +               ret = -EINVAL;
> +               break;
> +       }
> +
> +       if (ret) {
> +               dev_err(priv->dev, "failed to init phy for phy type %x\n", priv->type);
> +               goto err_clk;
> +       }
> +
> +       ret = reset_control_deassert(priv->phy_rst);
> +       if (ret)
> +               goto err_clk;
> +
> +       if (priv->type == PHY_TYPE_USB3) {
> +               ret = readx_poll_timeout_atomic(rockchip_combphy_is_ready,
> +                                               priv, val,
> +                                               val == cfg->pipe_phy_status.enable,
> +                                               10, 1000);
> +               if (ret)
> +                       dev_warn(priv->dev, "wait phy status ready timeout\n");
> +       }
> +
> +       return 0;
> +
> +err_clk:
> +       clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
> +
> +       return ret;
> +}
> +
> +static int rockchip_combphy_exit(struct phy *phy)
> +{
> +       struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
> +
> +       clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
> +       reset_control_assert(priv->phy_rst);
> +
> +       return 0;
> +}
> +
> +static const struct phy_ops rochchip_combphy_ops = {
> +       .init = rockchip_combphy_init,
> +       .exit = rockchip_combphy_exit,
> +       .owner = THIS_MODULE,
> +};
> +
> +static struct phy *rockchip_combphy_xlate(struct device *dev, struct of_phandle_args *args)
> +{
> +       struct rockchip_combphy_priv *priv = dev_get_drvdata(dev);
> +
> +       if (args->args_count != 1) {
> +               dev_err(dev, "invalid number of arguments\n");
> +               return ERR_PTR(-EINVAL);
> +       }
> +
> +       if (priv->type != PHY_NONE && priv->type != args->args[0])
> +               dev_warn(dev, "phy type select %d overwriting type %d\n",
> +                        args->args[0], priv->type);
> +
> +       priv->type = args->args[0];
> +
> +       return priv->phy;
> +}
> +
> +static int rockchip_combphy_parse_dt(struct device *dev, struct rockchip_combphy_priv *priv)
> +{
> +       int i;
> +
> +       priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);
> +       if (priv->num_clks < 1)
> +               return -EINVAL;
> +
> +       priv->refclk = NULL;
> +       for (i = 0; i < priv->num_clks; i++) {
> +               if (!strncmp(priv->clks[i].id, "ref", 3)) {
> +                       priv->refclk = priv->clks[i].clk;
> +                       break;
> +               }
> +       }
> +
> +       if (!priv->refclk) {
> +               dev_err(dev, "no refclk found\n");
> +               return -EINVAL;
> +       }
> +
> +       priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-grf");
> +       if (IS_ERR(priv->pipe_grf)) {
> +               dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n");
> +               return PTR_ERR(priv->pipe_grf);
> +       }
> +
> +       priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-phy-grf");
> +       if (IS_ERR(priv->phy_grf)) {
> +               dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n");
> +               return PTR_ERR(priv->phy_grf);
> +       }
> +
> +       priv->enable_ssc = device_property_present(dev, "rockchip,enable-ssc");
> +
> +       priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk");
> +
> +       priv->phy_rst = devm_reset_control_array_get_exclusive(dev);
> +       if (IS_ERR(priv->phy_rst))
> +               return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n");
> +
> +       return 0;
> +}
> +
> +static int rockchip_combphy_probe(struct platform_device *pdev)
> +{
> +       struct phy_provider *phy_provider;
> +       struct device *dev = &pdev->dev;
> +       struct rockchip_combphy_priv *priv;
> +       const struct rockchip_combphy_cfg *phy_cfg;
> +       struct resource *res;
> +       int ret;
> +
> +       phy_cfg = of_device_get_match_data(dev);
> +       if (!phy_cfg) {
> +               dev_err(dev, "no OF match data provided\n");
> +               return -EINVAL;
> +       }
> +
> +       priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> +       if (!priv)
> +               return -ENOMEM;
> +
> +       priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
> +       if (IS_ERR(priv->mmio)) {
> +               ret = PTR_ERR(priv->mmio);
> +               return ret;
> +       }
> +
> +       priv->dev = dev;
> +       priv->type = PHY_NONE;
> +       priv->cfg = phy_cfg;
> +
> +       ret = rockchip_combphy_parse_dt(dev, priv);
> +       if (ret)
> +               return ret;
> +
> +       ret = reset_control_assert(priv->phy_rst);
> +       if (ret) {
> +               dev_err(dev, "failed to reset phy\n");
> +               return ret;
> +       }
> +
> +       priv->phy = devm_phy_create(dev, NULL, &rochchip_combphy_ops);
> +       if (IS_ERR(priv->phy)) {
> +               dev_err(dev, "failed to create combphy\n");
> +               return PTR_ERR(priv->phy);
> +       }
> +
> +       dev_set_drvdata(dev, priv);
> +       phy_set_drvdata(priv->phy, priv);
> +
> +       phy_provider = devm_of_phy_provider_register(dev, rockchip_combphy_xlate);
> +
> +       return PTR_ERR_OR_ZERO(phy_provider);
> +}
> +
> +static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
> +{
> +       const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
> +       unsigned long rate;
> +       u32 val;
> +
> +       switch (priv->type) {
> +       case PHY_TYPE_PCIE:
> +               /* Set SSC downward spread spectrum. */
> +               rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
> +                                        PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
> +                                        PHYREG32);
> +
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
> +               break;
> +
> +       case PHY_TYPE_USB3:
> +               /* Set SSC downward spread spectrum. */
> +               rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
> +                                        PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
> +                                        PHYREG32);
> +
> +               /* Enable adaptive CTLE for USB3.0 Rx. */
> +               val = readl(priv->mmio + PHYREG15);
> +               val |= PHYREG15_CTLE_EN;
> +               writel(val, priv->mmio + PHYREG15);
> +
> +               /* Set PLL KVCO fine tuning signals. */
> +               rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
> +                                        PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT,
> +                                        PHYREG33);
> +
> +               /* Enable controlling random jitter. */
> +               writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
> +
> +               /* Set PLL input clock divider 1/2. */
> +               rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
> +                                        PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT,
> +                                        PHYREG6);
> +
> +               writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
> +               writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
> +
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true);
> +               break;
> +
> +       case PHY_TYPE_SATA:
> +               /* Enable adaptive CTLE for SATA Rx. */
> +               val = readl(priv->mmio + PHYREG15);
> +               val |= PHYREG15_CTLE_EN;
> +               writel(val, priv->mmio + PHYREG15);
> +               /*
> +                * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA.
> +                * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm)
> +                */
> +               val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT;
> +               val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT;
> +               writel(val, priv->mmio + PHYREG7);
> +
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true);
> +               rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
> +               break;
> +
> +       case PHY_TYPE_SGMII:
> +               rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->sgmii_mode_set, true);
> +               break;
> +
> +       case PHY_TYPE_QSGMII:
> +               rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_rate_sel, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true);
> +               break;
> +
> +       default:
> +               dev_err(priv->dev, "incompatible PHY type\n");
> +               return -EINVAL;
> +       }
> +
> +       rate = clk_get_rate(priv->refclk);
> +
> +       switch (rate) {
> +       case REF_CLOCK_24MHz:
> +               if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) {
> +                       /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */
> +                       val = PHYREG15_SSC_CNT_VALUE << PHYREG15_SSC_CNT_SHIFT;
> +                       rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK,
> +                                                val, PHYREG15);
> +
> +                       writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
> +               }
> +               break;
> +
> +       case REF_CLOCK_25MHz:
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
> +               break;
> +
> +       case REF_CLOCK_100MHz:
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
> +               if (priv->type == PHY_TYPE_PCIE) {
> +                       /* PLL KVCO  fine tuning. */
> +                       val = PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT;
> +                       rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
> +                                                val, PHYREG33);
> +
> +                       /* Enable controlling random jitter. */
> +                       writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
> +
> +                       val = PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT;
> +                       rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
> +                                                val, PHYREG6);
> +
> +                       writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
> +                       writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
> +               } else if (priv->type == PHY_TYPE_SATA) {
> +                       /* downward spread spectrum +500ppm */
> +                       val = PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT;
> +                       val |= PHYREG32_SSC_OFFSET_500PPM << PHYREG32_SSC_OFFSET_SHIFT;
> +                       rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
> +               }
> +               break;
> +
> +       default:
> +               dev_err(priv->dev, "unsupported rate: %lu\n", rate);
> +               return -EINVAL;
> +       }
> +
> +       if (priv->ext_refclk) {
> +               rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
> +               if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
> +                       val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT;
> +                       val |= PHYREG13_CKRCV_AMP0;
> +                       rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13);
> +
> +                       val = readl(priv->mmio + PHYREG14);
> +                       val |= PHYREG14_CKRCV_AMP1;
> +                       writel(val, priv->mmio + PHYREG14);
> +               }
> +       }
> +
> +       if (priv->enable_ssc) {
> +               val = readl(priv->mmio + PHYREG8);
> +               val |= PHYREG8_SSC_EN;
> +               writel(val, priv->mmio + PHYREG8);
> +       }
> +
> +       return 0;
> +}
> +
> +static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = {
> +       /* pipe-phy-grf */
> +       .pcie_mode_set          = { 0x0000, 5, 0, 0x00, 0x11 },
> +       .usb_mode_set           = { 0x0000, 5, 0, 0x00, 0x04 },
> +       .sgmii_mode_set         = { 0x0000, 5, 0, 0x00, 0x01 },
> +       .qsgmii_mode_set        = { 0x0000, 5, 0, 0x00, 0x21 },
> +       .pipe_rxterm_set        = { 0x0000, 12, 12, 0x00, 0x01 },
> +       .pipe_txelec_set        = { 0x0004, 1, 1, 0x00, 0x01 },
> +       .pipe_txcomp_set        = { 0x0004, 4, 4, 0x00, 0x01 },
> +       .pipe_clk_25m           = { 0x0004, 14, 13, 0x00, 0x01 },
> +       .pipe_clk_100m          = { 0x0004, 14, 13, 0x00, 0x02 },
> +       .pipe_phymode_sel       = { 0x0008, 1, 1, 0x00, 0x01 },
> +       .pipe_rate_sel          = { 0x0008, 2, 2, 0x00, 0x01 },
> +       .pipe_rxterm_sel        = { 0x0008, 8, 8, 0x00, 0x01 },
> +       .pipe_txelec_sel        = { 0x0008, 12, 12, 0x00, 0x01 },
> +       .pipe_txcomp_sel        = { 0x0008, 15, 15, 0x00, 0x01 },
> +       .pipe_clk_ext           = { 0x000c, 9, 8, 0x02, 0x01 },
> +       .pipe_sel_usb           = { 0x000c, 14, 13, 0x00, 0x01 },
> +       .pipe_sel_qsgmii        = { 0x000c, 15, 13, 0x00, 0x07 },
> +       .pipe_phy_status        = { 0x0034, 6, 6, 0x01, 0x00 },
> +       .con0_for_pcie          = { 0x0000, 15, 0, 0x00, 0x1000 },
> +       .con1_for_pcie          = { 0x0004, 15, 0, 0x00, 0x0000 },
> +       .con2_for_pcie          = { 0x0008, 15, 0, 0x00, 0x0101 },
> +       .con3_for_pcie          = { 0x000c, 15, 0, 0x00, 0x0200 },
> +       .con0_for_sata          = { 0x0000, 15, 0, 0x00, 0x0119 },
> +       .con1_for_sata          = { 0x0004, 15, 0, 0x00, 0x0040 },
> +       .con2_for_sata          = { 0x0008, 15, 0, 0x00, 0x80c3 },
> +       .con3_for_sata          = { 0x000c, 15, 0, 0x00, 0x4407 },
> +       /* pipe-grf */
> +       .pipe_con0_for_sata     = { 0x0000, 15, 0, 0x00, 0x2220 },
> +       .pipe_xpcs_phy_ready    = { 0x0040, 2, 2, 0x00, 0x01 },
> +};
> +
> +static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {
> +       .grfcfg         = &rk3568_combphy_grfcfgs,
> +       .combphy_cfg    = rk3568_combphy_cfg,
> +};
> +
> +static const struct of_device_id rockchip_combphy_of_match[] = {
> +       {
> +               .compatible = "rockchip,rk3568-naneng-combphy",
> +               .data = &rk3568_combphy_cfgs,
> +       },
> +       { },
> +};
> +MODULE_DEVICE_TABLE(of, rockchip_combphy_of_match);
> +
> +static struct platform_driver rockchip_combphy_driver = {
> +       .probe  = rockchip_combphy_probe,
> +       .driver = {
> +               .name = "rockchip-naneng-combphy",
> +               .of_match_table = rockchip_combphy_of_match,
> +       },
> +};
> +module_platform_driver(rockchip_combphy_driver);
> +
> +MODULE_DESCRIPTION("Rockchip NANENG COMBPHY driver");
> +MODULE_LICENSE("GPL v2");
> --
> 2.17.1
>
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip

_______________________________________________
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Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

[PATCH v8 4/4] arm64: dts: rockchip: add naneng combo phy nodes for rk3568

[Yifeng Zhao]

Add the core dt-node for the rk3568's naneng combo phys.

Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---

Changes in v8: None
Changes in v7: None
Changes in v5:
- remove apb reset

Changes in v4:
- rename node name
- remove reset-names
- move #phy-cells
- add rockchip,rk3568-pipe-grf
- add rockchip,rk3568-pipe-phy-grf

Changes in v3:
- Move pipe_phy_grf0 to rk3568.dtsi

Changes in v2:
- Move phy0 to rk3568.dtsi

 arch/arm64/boot/dts/rockchip/rk3568.dtsi | 21 +++++++++++
 arch/arm64/boot/dts/rockchip/rk356x.dtsi | 47 ++++++++++++++++++++++++
 2 files changed, 68 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
index d91df1cde736..5b0f528d6818 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -8,6 +8,11 @@
 / {
 	compatible = "rockchip,rk3568";
 
+	pipe_phy_grf0: syscon@fdc70000 {
+		compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
+		reg = <0x0 0xfdc70000 0x0 0x1000>;
+	};
+
 	qos_pcie3x1: qos@fe190080 {
 		compatible = "rockchip,rk3568-qos", "syscon";
 		reg = <0x0 0xfe190080 0x0 0x20>;
@@ -69,6 +74,22 @@
 			queue0 {};
 		};
 	};
+
+	combphy0: phy@fe820000 {
+		compatible = "rockchip,rk3568-naneng-combphy";
+		reg = <0x0 0xfe820000 0x0 0x100>;
+		clocks = <&pmucru CLK_PCIEPHY0_REF>,
+			 <&cru PCLK_PIPEPHY0>,
+			 <&cru PCLK_PIPE>;
+		clock-names = "ref", "apb", "pipe";
+		assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
+		assigned-clock-rates = <100000000>;
+		resets = <&cru SRST_PIPEPHY0>;
+		rockchip,pipe-grf = <&pipegrf>;
+		rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
+		#phy-cells = <1>;
+		status = "disabled";
+	};
 };
 
 &cpu0_opp_table {
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index bce20729be1a..cae76568e66d 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -262,11 +262,26 @@
 		};
 	};
 
+	pipegrf: syscon@fdc50000 {
+		compatible = "rockchip,rk3568-pipe-grf", "syscon";
+		reg = <0x0 0xfdc50000 0x0 0x1000>;
+	};
+
 	grf: syscon@fdc60000 {
 		compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
 		reg = <0x0 0xfdc60000 0x0 0x10000>;
 	};
 
+	pipe_phy_grf1: syscon@fdc80000 {
+		compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
+		reg = <0x0 0xfdc80000 0x0 0x1000>;
+	};
+
+	pipe_phy_grf2: syscon@fdc90000 {
+		compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
+		reg = <0x0 0xfdc90000 0x0 0x1000>;
+	};
+
 	usb2phy0_grf: syscon@fdca0000 {
 		compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
 		reg = <0x0 0xfdca0000 0x0 0x8000>;
@@ -1195,6 +1210,38 @@
 		status = "disabled";
 	};
 
+	combphy1: phy@fe830000 {
+		compatible = "rockchip,rk3568-naneng-combphy";
+		reg = <0x0 0xfe830000 0x0 0x100>;
+		clocks = <&pmucru CLK_PCIEPHY1_REF>,
+			 <&cru PCLK_PIPEPHY1>,
+			 <&cru PCLK_PIPE>;
+		clock-names = "ref", "apb", "pipe";
+		assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
+		assigned-clock-rates = <100000000>;
+		resets = <&cru SRST_PIPEPHY1>;
+		rockchip,pipe-grf = <&pipegrf>;
+		rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
+		#phy-cells = <1>;
+		status = "disabled";
+	};
+
+	combphy2: phy@fe840000 {
+		compatible = "rockchip,rk3568-naneng-combphy";
+		reg = <0x0 0xfe840000 0x0 0x100>;
+		clocks = <&pmucru CLK_PCIEPHY2_REF>,
+			 <&cru PCLK_PIPEPHY2>,
+			 <&cru PCLK_PIPE>;
+		clock-names = "ref", "apb", "pipe";
+		assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
+		assigned-clock-rates = <100000000>;
+		resets = <&cru SRST_PIPEPHY2>;
+		rockchip,pipe-grf = <&pipegrf>;
+		rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
+		#phy-cells = <1>;
+		status = "disabled";
+	};
+
 	u2phy0: usb2phy@fe8a0000 {
 		compatible = "rockchip,rk3568-usb2phy";
 		reg = <0x0 0xfe8a0000 0x0 0x10000>;
-- 
2.17.1


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[PATCH v8 4/4] arm64: dts: rockchip: add naneng combo phy nodes for rk3568

[Yifeng Zhao]

Add the core dt-node for the rk3568's naneng combo phys.

Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---

Changes in v8: None
Changes in v7: None
Changes in v5:
- remove apb reset

Changes in v4:
- rename node name
- remove reset-names
- move #phy-cells
- add rockchip,rk3568-pipe-grf
- add rockchip,rk3568-pipe-phy-grf

Changes in v3:
- Move pipe_phy_grf0 to rk3568.dtsi

Changes in v2:
- Move phy0 to rk3568.dtsi

 arch/arm64/boot/dts/rockchip/rk3568.dtsi | 21 +++++++++++
 arch/arm64/boot/dts/rockchip/rk356x.dtsi | 47 ++++++++++++++++++++++++
 2 files changed, 68 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
index d91df1cde736..5b0f528d6818 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -8,6 +8,11 @@
 / {
 	compatible = "rockchip,rk3568";
 
+	pipe_phy_grf0: syscon@fdc70000 {
+		compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
+		reg = <0x0 0xfdc70000 0x0 0x1000>;
+	};
+
 	qos_pcie3x1: qos@fe190080 {
 		compatible = "rockchip,rk3568-qos", "syscon";
 		reg = <0x0 0xfe190080 0x0 0x20>;
@@ -69,6 +74,22 @@
 			queue0 {};
 		};
 	};
+
+	combphy0: phy@fe820000 {
+		compatible = "rockchip,rk3568-naneng-combphy";
+		reg = <0x0 0xfe820000 0x0 0x100>;
+		clocks = <&pmucru CLK_PCIEPHY0_REF>,
+			 <&cru PCLK_PIPEPHY0>,
+			 <&cru PCLK_PIPE>;
+		clock-names = "ref", "apb", "pipe";
+		assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
+		assigned-clock-rates = <100000000>;
+		resets = <&cru SRST_PIPEPHY0>;
+		rockchip,pipe-grf = <&pipegrf>;
+		rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
+		#phy-cells = <1>;
+		status = "disabled";
+	};
 };
 
 &cpu0_opp_table {
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index bce20729be1a..cae76568e66d 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -262,11 +262,26 @@
 		};
 	};
 
+	pipegrf: syscon@fdc50000 {
+		compatible = "rockchip,rk3568-pipe-grf", "syscon";
+		reg = <0x0 0xfdc50000 0x0 0x1000>;
+	};
+
 	grf: syscon@fdc60000 {
 		compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
 		reg = <0x0 0xfdc60000 0x0 0x10000>;
 	};
 
+	pipe_phy_grf1: syscon@fdc80000 {
+		compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
+		reg = <0x0 0xfdc80000 0x0 0x1000>;
+	};
+
+	pipe_phy_grf2: syscon@fdc90000 {
+		compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
+		reg = <0x0 0xfdc90000 0x0 0x1000>;
+	};
+
 	usb2phy0_grf: syscon@fdca0000 {
 		compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
 		reg = <0x0 0xfdca0000 0x0 0x8000>;
@@ -1195,6 +1210,38 @@
 		status = "disabled";
 	};
 
+	combphy1: phy@fe830000 {
+		compatible = "rockchip,rk3568-naneng-combphy";
+		reg = <0x0 0xfe830000 0x0 0x100>;
+		clocks = <&pmucru CLK_PCIEPHY1_REF>,
+			 <&cru PCLK_PIPEPHY1>,
+			 <&cru PCLK_PIPE>;
+		clock-names = "ref", "apb", "pipe";
+		assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
+		assigned-clock-rates = <100000000>;
+		resets = <&cru SRST_PIPEPHY1>;
+		rockchip,pipe-grf = <&pipegrf>;
+		rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
+		#phy-cells = <1>;
+		status = "disabled";
+	};
+
+	combphy2: phy@fe840000 {
+		compatible = "rockchip,rk3568-naneng-combphy";
+		reg = <0x0 0xfe840000 0x0 0x100>;
+		clocks = <&pmucru CLK_PCIEPHY2_REF>,
+			 <&cru PCLK_PIPEPHY2>,
+			 <&cru PCLK_PIPE>;
+		clock-names = "ref", "apb", "pipe";
+		assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
+		assigned-clock-rates = <100000000>;
+		resets = <&cru SRST_PIPEPHY2>;
+		rockchip,pipe-grf = <&pipegrf>;
+		rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
+		#phy-cells = <1>;
+		status = "disabled";
+	};
+
 	u2phy0: usb2phy@fe8a0000 {
 		compatible = "rockchip,rk3568-usb2phy";
 		reg = <0x0 0xfe8a0000 0x0 0x10000>;
-- 
2.17.1

[PATCH v8 4/4] arm64: dts: rockchip: add naneng combo phy nodes for rk3568

[Yifeng Zhao]

Add the core dt-node for the rk3568's naneng combo phys.

Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---

Changes in v8: None
Changes in v7: None
Changes in v5:
- remove apb reset

Changes in v4:
- rename node name
- remove reset-names
- move #phy-cells
- add rockchip,rk3568-pipe-grf
- add rockchip,rk3568-pipe-phy-grf

Changes in v3:
- Move pipe_phy_grf0 to rk3568.dtsi

Changes in v2:
- Move phy0 to rk3568.dtsi

 arch/arm64/boot/dts/rockchip/rk3568.dtsi | 21 +++++++++++
 arch/arm64/boot/dts/rockchip/rk356x.dtsi | 47 ++++++++++++++++++++++++
 2 files changed, 68 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
index d91df1cde736..5b0f528d6818 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -8,6 +8,11 @@
 / {
 	compatible = "rockchip,rk3568";
 
+	pipe_phy_grf0: syscon@fdc70000 {
+		compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
+		reg = <0x0 0xfdc70000 0x0 0x1000>;
+	};
+
 	qos_pcie3x1: qos@fe190080 {
 		compatible = "rockchip,rk3568-qos", "syscon";
 		reg = <0x0 0xfe190080 0x0 0x20>;
@@ -69,6 +74,22 @@
 			queue0 {};
 		};
 	};
+
+	combphy0: phy@fe820000 {
+		compatible = "rockchip,rk3568-naneng-combphy";
+		reg = <0x0 0xfe820000 0x0 0x100>;
+		clocks = <&pmucru CLK_PCIEPHY0_REF>,
+			 <&cru PCLK_PIPEPHY0>,
+			 <&cru PCLK_PIPE>;
+		clock-names = "ref", "apb", "pipe";
+		assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
+		assigned-clock-rates = <100000000>;
+		resets = <&cru SRST_PIPEPHY0>;
+		rockchip,pipe-grf = <&pipegrf>;
+		rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
+		#phy-cells = <1>;
+		status = "disabled";
+	};
 };
 
 &cpu0_opp_table {
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index bce20729be1a..cae76568e66d 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -262,11 +262,26 @@
 		};
 	};
 
+	pipegrf: syscon@fdc50000 {
+		compatible = "rockchip,rk3568-pipe-grf", "syscon";
+		reg = <0x0 0xfdc50000 0x0 0x1000>;
+	};
+
 	grf: syscon@fdc60000 {
 		compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
 		reg = <0x0 0xfdc60000 0x0 0x10000>;
 	};
 
+	pipe_phy_grf1: syscon@fdc80000 {
+		compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
+		reg = <0x0 0xfdc80000 0x0 0x1000>;
+	};
+
+	pipe_phy_grf2: syscon@fdc90000 {
+		compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
+		reg = <0x0 0xfdc90000 0x0 0x1000>;
+	};
+
 	usb2phy0_grf: syscon@fdca0000 {
 		compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
 		reg = <0x0 0xfdca0000 0x0 0x8000>;
@@ -1195,6 +1210,38 @@
 		status = "disabled";
 	};
 
+	combphy1: phy@fe830000 {
+		compatible = "rockchip,rk3568-naneng-combphy";
+		reg = <0x0 0xfe830000 0x0 0x100>;
+		clocks = <&pmucru CLK_PCIEPHY1_REF>,
+			 <&cru PCLK_PIPEPHY1>,
+			 <&cru PCLK_PIPE>;
+		clock-names = "ref", "apb", "pipe";
+		assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
+		assigned-clock-rates = <100000000>;
+		resets = <&cru SRST_PIPEPHY1>;
+		rockchip,pipe-grf = <&pipegrf>;
+		rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
+		#phy-cells = <1>;
+		status = "disabled";
+	};
+
+	combphy2: phy@fe840000 {
+		compatible = "rockchip,rk3568-naneng-combphy";
+		reg = <0x0 0xfe840000 0x0 0x100>;
+		clocks = <&pmucru CLK_PCIEPHY2_REF>,
+			 <&cru PCLK_PIPEPHY2>,
+			 <&cru PCLK_PIPE>;
+		clock-names = "ref", "apb", "pipe";
+		assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
+		assigned-clock-rates = <100000000>;
+		resets = <&cru SRST_PIPEPHY2>;
+		rockchip,pipe-grf = <&pipegrf>;
+		rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
+		#phy-cells = <1>;
+		status = "disabled";
+	};
+
 	u2phy0: usb2phy@fe8a0000 {
 		compatible = "rockchip,rk3568-usb2phy";
 		reg = <0x0 0xfe8a0000 0x0 0x10000>;
-- 
2.17.1


_______________________________________________
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[PATCH v8 4/4] arm64: dts: rockchip: add naneng combo phy nodes for rk3568

[Yifeng Zhao]

Add the core dt-node for the rk3568's naneng combo phys.

Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---

Changes in v8: None
Changes in v7: None
Changes in v5:
- remove apb reset

Changes in v4:
- rename node name
- remove reset-names
- move #phy-cells
- add rockchip,rk3568-pipe-grf
- add rockchip,rk3568-pipe-phy-grf

Changes in v3:
- Move pipe_phy_grf0 to rk3568.dtsi

Changes in v2:
- Move phy0 to rk3568.dtsi

 arch/arm64/boot/dts/rockchip/rk3568.dtsi | 21 +++++++++++
 arch/arm64/boot/dts/rockchip/rk356x.dtsi | 47 ++++++++++++++++++++++++
 2 files changed, 68 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
index d91df1cde736..5b0f528d6818 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -8,6 +8,11 @@
 / {
 	compatible = "rockchip,rk3568";
 
+	pipe_phy_grf0: syscon@fdc70000 {
+		compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
+		reg = <0x0 0xfdc70000 0x0 0x1000>;
+	};
+
 	qos_pcie3x1: qos@fe190080 {
 		compatible = "rockchip,rk3568-qos", "syscon";
 		reg = <0x0 0xfe190080 0x0 0x20>;
@@ -69,6 +74,22 @@
 			queue0 {};
 		};
 	};
+
+	combphy0: phy@fe820000 {
+		compatible = "rockchip,rk3568-naneng-combphy";
+		reg = <0x0 0xfe820000 0x0 0x100>;
+		clocks = <&pmucru CLK_PCIEPHY0_REF>,
+			 <&cru PCLK_PIPEPHY0>,
+			 <&cru PCLK_PIPE>;
+		clock-names = "ref", "apb", "pipe";
+		assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
+		assigned-clock-rates = <100000000>;
+		resets = <&cru SRST_PIPEPHY0>;
+		rockchip,pipe-grf = <&pipegrf>;
+		rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
+		#phy-cells = <1>;
+		status = "disabled";
+	};
 };
 
 &cpu0_opp_table {
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index bce20729be1a..cae76568e66d 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -262,11 +262,26 @@
 		};
 	};
 
+	pipegrf: syscon@fdc50000 {
+		compatible = "rockchip,rk3568-pipe-grf", "syscon";
+		reg = <0x0 0xfdc50000 0x0 0x1000>;
+	};
+
 	grf: syscon@fdc60000 {
 		compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
 		reg = <0x0 0xfdc60000 0x0 0x10000>;
 	};
 
+	pipe_phy_grf1: syscon@fdc80000 {
+		compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
+		reg = <0x0 0xfdc80000 0x0 0x1000>;
+	};
+
+	pipe_phy_grf2: syscon@fdc90000 {
+		compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
+		reg = <0x0 0xfdc90000 0x0 0x1000>;
+	};
+
 	usb2phy0_grf: syscon@fdca0000 {
 		compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
 		reg = <0x0 0xfdca0000 0x0 0x8000>;
@@ -1195,6 +1210,38 @@
 		status = "disabled";
 	};
 
+	combphy1: phy@fe830000 {
+		compatible = "rockchip,rk3568-naneng-combphy";
+		reg = <0x0 0xfe830000 0x0 0x100>;
+		clocks = <&pmucru CLK_PCIEPHY1_REF>,
+			 <&cru PCLK_PIPEPHY1>,
+			 <&cru PCLK_PIPE>;
+		clock-names = "ref", "apb", "pipe";
+		assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
+		assigned-clock-rates = <100000000>;
+		resets = <&cru SRST_PIPEPHY1>;
+		rockchip,pipe-grf = <&pipegrf>;
+		rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
+		#phy-cells = <1>;
+		status = "disabled";
+	};
+
+	combphy2: phy@fe840000 {
+		compatible = "rockchip,rk3568-naneng-combphy";
+		reg = <0x0 0xfe840000 0x0 0x100>;
+		clocks = <&pmucru CLK_PCIEPHY2_REF>,
+			 <&cru PCLK_PIPEPHY2>,
+			 <&cru PCLK_PIPE>;
+		clock-names = "ref", "apb", "pipe";
+		assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
+		assigned-clock-rates = <100000000>;
+		resets = <&cru SRST_PIPEPHY2>;
+		rockchip,pipe-grf = <&pipegrf>;
+		rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
+		#phy-cells = <1>;
+		status = "disabled";
+	};
+
 	u2phy0: usb2phy@fe8a0000 {
 		compatible = "rockchip,rk3568-usb2phy";
 		reg = <0x0 0xfe8a0000 0x0 0x10000>;
-- 
2.17.1


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Aw: [PATCH v8 4/4] arm64: dts: rockchip: add naneng combo phy nodes for rk3568

[Frank Wunderlich]

Hi

Tested complete series on rk3568 based Bananapi R2 Pro

combphy0: usb3 (usbdrd3_0)
combphy1: usb3 (usbdrd3_1)
combphy2: sata (sata2)

Tested-by: Frank Wunderlich <frank-w@public-files.de>

regards Frank

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Aw: [PATCH v8 4/4] arm64: dts: rockchip: add naneng combo phy nodes for rk3568

[Frank Wunderlich]

Hi

Tested complete series on rk3568 based Bananapi R2 Pro

combphy0: usb3 (usbdrd3_0)
combphy1: usb3 (usbdrd3_1)
combphy2: sata (sata2)

Tested-by: Frank Wunderlich <frank-w@public-files.de>

regards Frank

Aw: [PATCH v8 4/4] arm64: dts: rockchip: add naneng combo phy nodes for rk3568

[Frank Wunderlich]

Hi

Tested complete series on rk3568 based Bananapi R2 Pro

combphy0: usb3 (usbdrd3_0)
combphy1: usb3 (usbdrd3_1)
combphy2: sata (sata2)

Tested-by: Frank Wunderlich <frank-w@public-files.de>

regards Frank

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Aw: [PATCH v8 4/4] arm64: dts: rockchip: add naneng combo phy nodes for rk3568

[Frank Wunderlich]

Hi

Tested complete series on rk3568 based Bananapi R2 Pro

combphy0: usb3 (usbdrd3_0)
combphy1: usb3 (usbdrd3_1)
combphy2: sata (sata2)

Tested-by: Frank Wunderlich <frank-w@public-files.de>

regards Frank

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Aw: [PATCH v8 0/4] Add Naneng combo PHY support for RK3568

[Frank Wunderlich]

Hi

Tested complete series on rk3568 based Bananapi R2 Pro

combphy0: usb3 (usbdrd3_0)
combphy1: usb3 (usbdrd3_1)
combphy2: sata (sata2)

Tested-by: Frank Wunderlich <frank-w@public-files.de>

regards Frank

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Aw: [PATCH v8 0/4] Add Naneng combo PHY support for RK3568

[Frank Wunderlich]

Hi

Tested complete series on rk3568 based Bananapi R2 Pro

combphy0: usb3 (usbdrd3_0)
combphy1: usb3 (usbdrd3_1)
combphy2: sata (sata2)

Tested-by: Frank Wunderlich <frank-w@public-files.de>

regards Frank

Aw: [PATCH v8 0/4] Add Naneng combo PHY support for RK3568

[Frank Wunderlich]

Hi

Tested complete series on rk3568 based Bananapi R2 Pro

combphy0: usb3 (usbdrd3_0)
combphy1: usb3 (usbdrd3_1)
combphy2: sata (sata2)

Tested-by: Frank Wunderlich <frank-w@public-files.de>

regards Frank

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Aw: [PATCH v8 0/4] Add Naneng combo PHY support for RK3568

[Frank Wunderlich]

Hi

Tested complete series on rk3568 based Bananapi R2 Pro

combphy0: usb3 (usbdrd3_0)
combphy1: usb3 (usbdrd3_1)
combphy2: sata (sata2)

Tested-by: Frank Wunderlich <frank-w@public-files.de>

regards Frank

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Re: [PATCH v8 0/4] Add Naneng combo PHY support for RK3568

[Vinod Koul]

On 08-02-22, 17:13, Yifeng Zhao wrote:
> 
> This phy can be used as pcie-phy, usb3-phy, sata-phy or sgmii-phy.

Applied 1-3, thanks

-- 
~Vinod

Re: [PATCH v8 0/4] Add Naneng combo PHY support for RK3568

[Vinod Koul]

On 08-02-22, 17:13, Yifeng Zhao wrote:
> 
> This phy can be used as pcie-phy, usb3-phy, sata-phy or sgmii-phy.

Applied 1-3, thanks

-- 
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Re: [PATCH v8 0/4] Add Naneng combo PHY support for RK3568

[Vinod Koul]

On 08-02-22, 17:13, Yifeng Zhao wrote:
> 
> This phy can be used as pcie-phy, usb3-phy, sata-phy or sgmii-phy.

Applied 1-3, thanks

-- 
~Vinod

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Re: [PATCH v8 0/4] Add Naneng combo PHY support for RK3568

[Vinod Koul]

On 08-02-22, 17:13, Yifeng Zhao wrote:
> 
> This phy can be used as pcie-phy, usb3-phy, sata-phy or sgmii-phy.

Applied 1-3, thanks

-- 
~Vinod

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Re: [PATCH v8 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings

[zyf]

Hi Rob，

I can't reproduce this issue unless revert "[v8,1/4] dt-bindings: soc: grf: add naneng combo phy register compatible".

build log:
  DTC     Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml
  CHECK   Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml

build environment:

yamllint version: yamllint 1.26.3

kernel base:
commit 44948bd49d878dad6c9707e34f4a06df73c3a800 (tag: next-20220224, origin/master, origin/HEAD)

dtschema version:
pip3 install dtschema --upgrade
Defaulting to user installation because normal site-packages is not writeable
Requirement already satisfied: dtschema in /home2/zyf/.local/lib/python3.6/site-packages (2021.10)
Collecting dtschema
  Using cached dtschema-2022.1-py3-none-any.whl (63 kB)
Requirement already satisfied: rfc3987 in /home2/zyf/.local/lib/python3.6/site-packages (from dtschema) (1.3.8)
Requirement already satisfied: ruamel.yaml>0.15.69 in /home2/zyf/.local/lib/python3.6/site-packages (from dtschema) (0.17.16)
  Using cached dtschema-2021.12-py3-none-any.whl (62 kB)
Requirement already satisfied: jsonschema>=3.0.1 in /home2/zyf/.local/lib/python3.6/site-packages (from dtschema) (4.0.0)
Requirement already satisfied: importlib-metadata in /home2/zyf/.local/lib/python3.6/site-packages (from jsonschema>=3.0.1->dtschema) (4.8.3)
Requirement already satisfied: pyrsistent!=0.17.0,!=0.17.1,!=0.17.2,>=0.14.0 in /home2/zyf/.local/lib/python3.6/site-packages (from jsonschema>=3.0.1->dtschema) (0.18.0)
Requirement already satisfied: attrs>=17.4.0 in /home2/zyf/.local/lib/python3.6/site-packages (from jsonschema>=3.0.1->dtschema) (21.4.0)
Requirement already satisfied: ruamel.yaml.clib>=0.1.2 in /home2/zyf/.local/lib/python3.6/site-packages (from ruamel.yaml>0.15.69->dtschema) (0.2.6)
Requirement already satisfied: typing-extensions>=3.6.4 in /home2/zyf/.local/lib/python3.6/site-packages (from importlib-metadata->jsonschema>=3.0.1->dtschema) (4.1.1)
Requirement already satisfied: zipp>=0.5 in /home2/zyf/.local/lib/python3.6/site-packages (from importlib-metadata->jsonschema>=3.0.1->dtschema) (3.6.0)


>From："Rob Herring  <robh@kernel.org>"
>To：Yifeng Zhao  <yifeng.zhao@rock-chips.com>
>Date：2022-02-09 04:33:32
>Subject：Re: [PATCH v8 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings
>
>On Tue, 08 Feb 2022 17:13:24 +0800, Yifeng Zhao wrote:
>> Add the compatible strings for the Naneng combo PHY found on rockchip SoC.
>> 
>> Reviewed-by: Rob Herring <robh@kernel.org>
>> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
>> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
>> ---
>> 
>> Changes in v8: None
>> Changes in v7:
>> - remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel
>> 
>> Changes in v5:
>> - modify description for ssc and ext-refclk
>> - remove apb reset
>> 
>> Changes in v4:
>> - restyle
>> - remove some minItems
>> - add more properties
>> - remove reset-names
>> - move #phy-cells
>> - add rockchip,rk3568-pipe-grf
>> - add rockchip,rk3568-pipe-phy-grf
>> 
>> Changes in v3: None
>> Changes in v2:
>> - Fix dtschema/dtc warnings/errors
>> 
>>  .../phy/phy-rockchip-naneng-combphy.yaml      | 109 ++++++++++++++++++
>>  1 file changed, 109 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
>> 
>
>My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
>on your patch (DT_CHECKER_FLAGS is new in v5.13):
>
>yamllint warnings/errors:
>
>dtschema/dtc warnings/errors:
>Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:0:0: /example-0/syscon@fdc50000: failed to match any schema with compatible: ['rockchip,rk3568-pipe-grf', 'syscon']
>Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:0:0: /example-0/syscon@fdc70000: failed to match any schema with compatible: ['rockchip,rk3568-pipe-phy-grf', 'syscon']
>
>doc reference errors (make refcheckdocs):
>
>See https://patchwork.ozlabs.org/patch/1589719
>
>This check can fail if there are any dependencies. The base for a patch
>series is generally the most recent rc1.
>
>If you already ran 'make dt_binding_check' and didn't see the above
>error(s), then make sure 'yamllint' is installed and dt-schema is up to
>date:
>
>pip3 install dtschema --upgrade
>
>Please check and re-submit.
-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

Re: [PATCH v8 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings

[zyf]

Hi Rob，

I can't reproduce this issue unless revert "[v8,1/4] dt-bindings: soc: grf: add naneng combo phy register compatible".

build log:
  DTC     Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml
  CHECK   Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml

build environment:

yamllint version: yamllint 1.26.3

kernel base:
commit 44948bd49d878dad6c9707e34f4a06df73c3a800 (tag: next-20220224, origin/master, origin/HEAD)

dtschema version:
pip3 install dtschema --upgrade
Defaulting to user installation because normal site-packages is not writeable
Requirement already satisfied: dtschema in /home2/zyf/.local/lib/python3.6/site-packages (2021.10)
Collecting dtschema
  Using cached dtschema-2022.1-py3-none-any.whl (63 kB)
Requirement already satisfied: rfc3987 in /home2/zyf/.local/lib/python3.6/site-packages (from dtschema) (1.3.8)
Requirement already satisfied: ruamel.yaml>0.15.69 in /home2/zyf/.local/lib/python3.6/site-packages (from dtschema) (0.17.16)
  Using cached dtschema-2021.12-py3-none-any.whl (62 kB)
Requirement already satisfied: jsonschema>=3.0.1 in /home2/zyf/.local/lib/python3.6/site-packages (from dtschema) (4.0.0)
Requirement already satisfied: importlib-metadata in /home2/zyf/.local/lib/python3.6/site-packages (from jsonschema>=3.0.1->dtschema) (4.8.3)
Requirement already satisfied: pyrsistent!=0.17.0,!=0.17.1,!=0.17.2,>=0.14.0 in /home2/zyf/.local/lib/python3.6/site-packages (from jsonschema>=3.0.1->dtschema) (0.18.0)
Requirement already satisfied: attrs>=17.4.0 in /home2/zyf/.local/lib/python3.6/site-packages (from jsonschema>=3.0.1->dtschema) (21.4.0)
Requirement already satisfied: ruamel.yaml.clib>=0.1.2 in /home2/zyf/.local/lib/python3.6/site-packages (from ruamel.yaml>0.15.69->dtschema) (0.2.6)
Requirement already satisfied: typing-extensions>=3.6.4 in /home2/zyf/.local/lib/python3.6/site-packages (from importlib-metadata->jsonschema>=3.0.1->dtschema) (4.1.1)
Requirement already satisfied: zipp>=0.5 in /home2/zyf/.local/lib/python3.6/site-packages (from importlib-metadata->jsonschema>=3.0.1->dtschema) (3.6.0)


>From："Rob Herring  <robh@kernel.org>"
>To：Yifeng Zhao  <yifeng.zhao@rock-chips.com>
>Date：2022-02-09 04:33:32
>Subject：Re: [PATCH v8 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings
>
>On Tue, 08 Feb 2022 17:13:24 +0800, Yifeng Zhao wrote:
>> Add the compatible strings for the Naneng combo PHY found on rockchip SoC.
>> 
>> Reviewed-by: Rob Herring <robh@kernel.org>
>> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
>> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
>> ---
>> 
>> Changes in v8: None
>> Changes in v7:
>> - remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel
>> 
>> Changes in v5:
>> - modify description for ssc and ext-refclk
>> - remove apb reset
>> 
>> Changes in v4:
>> - restyle
>> - remove some minItems
>> - add more properties
>> - remove reset-names
>> - move #phy-cells
>> - add rockchip,rk3568-pipe-grf
>> - add rockchip,rk3568-pipe-phy-grf
>> 
>> Changes in v3: None
>> Changes in v2:
>> - Fix dtschema/dtc warnings/errors
>> 
>>  .../phy/phy-rockchip-naneng-combphy.yaml      | 109 ++++++++++++++++++
>>  1 file changed, 109 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
>> 
>
>My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
>on your patch (DT_CHECKER_FLAGS is new in v5.13):
>
>yamllint warnings/errors:
>
>dtschema/dtc warnings/errors:
>Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:0:0: /example-0/syscon@fdc50000: failed to match any schema with compatible: ['rockchip,rk3568-pipe-grf', 'syscon']
>Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:0:0: /example-0/syscon@fdc70000: failed to match any schema with compatible: ['rockchip,rk3568-pipe-phy-grf', 'syscon']
>
>doc reference errors (make refcheckdocs):
>
>See https://patchwork.ozlabs.org/patch/1589719
>
>This check can fail if there are any dependencies. The base for a patch
>series is generally the most recent rc1.
>
>If you already ran 'make dt_binding_check' and didn't see the above
>error(s), then make sure 'yamllint' is installed and dt-schema is up to
>date:
>
>pip3 install dtschema --upgrade
>
>Please check and re-submit.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v8 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings

[zyf]

Hi Rob，

I can't reproduce this issue unless revert "[v8,1/4] dt-bindings: soc: grf: add naneng combo phy register compatible".

build log:
  DTC     Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml
  CHECK   Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml

build environment:

yamllint version: yamllint 1.26.3

kernel base:
commit 44948bd49d878dad6c9707e34f4a06df73c3a800 (tag: next-20220224, origin/master, origin/HEAD)

dtschema version:
pip3 install dtschema --upgrade
Defaulting to user installation because normal site-packages is not writeable
Requirement already satisfied: dtschema in /home2/zyf/.local/lib/python3.6/site-packages (2021.10)
Collecting dtschema
  Using cached dtschema-2022.1-py3-none-any.whl (63 kB)
Requirement already satisfied: rfc3987 in /home2/zyf/.local/lib/python3.6/site-packages (from dtschema) (1.3.8)
Requirement already satisfied: ruamel.yaml>0.15.69 in /home2/zyf/.local/lib/python3.6/site-packages (from dtschema) (0.17.16)
  Using cached dtschema-2021.12-py3-none-any.whl (62 kB)
Requirement already satisfied: jsonschema>=3.0.1 in /home2/zyf/.local/lib/python3.6/site-packages (from dtschema) (4.0.0)
Requirement already satisfied: importlib-metadata in /home2/zyf/.local/lib/python3.6/site-packages (from jsonschema>=3.0.1->dtschema) (4.8.3)
Requirement already satisfied: pyrsistent!=0.17.0,!=0.17.1,!=0.17.2,>=0.14.0 in /home2/zyf/.local/lib/python3.6/site-packages (from jsonschema>=3.0.1->dtschema) (0.18.0)
Requirement already satisfied: attrs>=17.4.0 in /home2/zyf/.local/lib/python3.6/site-packages (from jsonschema>=3.0.1->dtschema) (21.4.0)
Requirement already satisfied: ruamel.yaml.clib>=0.1.2 in /home2/zyf/.local/lib/python3.6/site-packages (from ruamel.yaml>0.15.69->dtschema) (0.2.6)
Requirement already satisfied: typing-extensions>=3.6.4 in /home2/zyf/.local/lib/python3.6/site-packages (from importlib-metadata->jsonschema>=3.0.1->dtschema) (4.1.1)
Requirement already satisfied: zipp>=0.5 in /home2/zyf/.local/lib/python3.6/site-packages (from importlib-metadata->jsonschema>=3.0.1->dtschema) (3.6.0)


>From："Rob Herring  <robh@kernel.org>"
>To：Yifeng Zhao  <yifeng.zhao@rock-chips.com>
>Date：2022-02-09 04:33:32
>Subject：Re: [PATCH v8 2/4] dt-bindings: phy: rockchip: Add Naneng combo PHY bindings
>
>On Tue, 08 Feb 2022 17:13:24 +0800, Yifeng Zhao wrote:
>> Add the compatible strings for the Naneng combo PHY found on rockchip SoC.
>> 
>> Reviewed-by: Rob Herring <robh@kernel.org>
>> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
>> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
>> ---
>> 
>> Changes in v8: None
>> Changes in v7:
>> - remove u3otg0_port_en, u3otg1_port_en and pipe_sgmii_mac_sel
>> 
>> Changes in v5:
>> - modify description for ssc and ext-refclk
>> - remove apb reset
>> 
>> Changes in v4:
>> - restyle
>> - remove some minItems
>> - add more properties
>> - remove reset-names
>> - move #phy-cells
>> - add rockchip,rk3568-pipe-grf
>> - add rockchip,rk3568-pipe-phy-grf
>> 
>> Changes in v3: None
>> Changes in v2:
>> - Fix dtschema/dtc warnings/errors
>> 
>>  .../phy/phy-rockchip-naneng-combphy.yaml      | 109 ++++++++++++++++++
>>  1 file changed, 109 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
>> 
>
>My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
>on your patch (DT_CHECKER_FLAGS is new in v5.13):
>
>yamllint warnings/errors:
>
>dtschema/dtc warnings/errors:
>Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:0:0: /example-0/syscon@fdc50000: failed to match any schema with compatible: ['rockchip,rk3568-pipe-grf', 'syscon']
>Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.example.dt.yaml:0:0: /example-0/syscon@fdc70000: failed to match any schema with compatible: ['rockchip,rk3568-pipe-phy-grf', 'syscon']
>
>doc reference errors (make refcheckdocs):
>
>See https://patchwork.ozlabs.org/patch/1589719
>
>This check can fail if there are any dependencies. The base for a patch
>series is generally the most recent rc1.
>
>If you already ran 'make dt_binding_check' and didn't see the above
>error(s), then make sure 'yamllint' is installed and dt-schema is up to
>date:
>
>pip3 install dtschema --upgrade
>
>Please check and re-submit.
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

Re: (subset) [PATCH v8 0/4] Add Naneng combo PHY support for RK3568

[Heiko Stuebner]

On Tue, 8 Feb 2022 17:13:22 +0800, Yifeng Zhao wrote:
> This phy can be used as pcie-phy, usb3-phy, sata-phy or sgmii-phy.
> 
> Changes in v8:
> - rename 'mode' to 'type'
> - using devm_reset_control_array_get_exclusive
> - move rockchip_combphy_set_mode into rockchip_combphy_init
> 
> [...]

Applied, thanks!

[4/4] arm64: dts: rockchip: add naneng combo phy nodes for rk3568
      commit: 3cc8cd2d25954ed5794df2d190b81c7325c584e3

Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>

Re: (subset) [PATCH v8 0/4] Add Naneng combo PHY support for RK3568

[Heiko Stuebner]

On Tue, 8 Feb 2022 17:13:22 +0800, Yifeng Zhao wrote:
> This phy can be used as pcie-phy, usb3-phy, sata-phy or sgmii-phy.
> 
> Changes in v8:
> - rename 'mode' to 'type'
> - using devm_reset_control_array_get_exclusive
> - move rockchip_combphy_set_mode into rockchip_combphy_init
> 
> [...]

Applied, thanks!

[4/4] arm64: dts: rockchip: add naneng combo phy nodes for rk3568
      commit: 3cc8cd2d25954ed5794df2d190b81c7325c584e3

Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: (subset) [PATCH v8 0/4] Add Naneng combo PHY support for RK3568

[Heiko Stuebner]

On Tue, 8 Feb 2022 17:13:22 +0800, Yifeng Zhao wrote:
> This phy can be used as pcie-phy, usb3-phy, sata-phy or sgmii-phy.
> 
> Changes in v8:
> - rename 'mode' to 'type'
> - using devm_reset_control_array_get_exclusive
> - move rockchip_combphy_set_mode into rockchip_combphy_init
> 
> [...]

Applied, thanks!

[4/4] arm64: dts: rockchip: add naneng combo phy nodes for rk3568
      commit: 3cc8cd2d25954ed5794df2d190b81c7325c584e3

Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>

-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

Re: (subset) [PATCH v8 0/4] Add Naneng combo PHY support for RK3568

[Heiko Stuebner]

On Tue, 8 Feb 2022 17:13:22 +0800, Yifeng Zhao wrote:
> This phy can be used as pcie-phy, usb3-phy, sata-phy or sgmii-phy.
> 
> Changes in v8:
> - rename 'mode' to 'type'
> - using devm_reset_control_array_get_exclusive
> - move rockchip_combphy_set_mode into rockchip_combphy_init
> 
> [...]

Applied, thanks!

[4/4] arm64: dts: rockchip: add naneng combo phy nodes for rk3568
      commit: 3cc8cd2d25954ed5794df2d190b81c7325c584e3

Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>

_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip