* [PATCH] soc: soc_ti_k3: update j721e revision numbering
@ 2022-01-26 22:07 Bryan Brattlof
2022-01-27 19:01 ` Bryan Brattlof
2022-02-08 17:32 ` Tom Rini
0 siblings, 2 replies; 4+ messages in thread
From: Bryan Brattlof @ 2022-01-26 22:07 UTC (permalink / raw)
To: u-boot; +Cc: Bryan Brattlof, Dave Gerlach
There is a 4 bit VARIANT number inside the JTAGID register that TI
increments any time a new variant for a chip is produced. Each
family of TI's SoCs uses a different versioning scheme based off
that VARIANT number.
CC: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
---
drivers/soc/soc_ti_k3.c | 40 +++++++++++++++++++++++++++-------------
1 file changed, 27 insertions(+), 13 deletions(-)
diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c
index 9abed7d490a2c..7a126857cd709 100644
--- a/drivers/soc/soc_ti_k3.c
+++ b/drivers/soc/soc_ti_k3.c
@@ -15,9 +15,6 @@
#define J7200 0xbb6d
#define AM64X 0xbb38
-#define REV_SR1_0 0
-#define REV_SR2_0 1
-
#define JTAG_ID_VARIANT_SHIFT 28
#define JTAG_ID_VARIANT_MASK (0xf << 28)
#define JTAG_ID_PARTNO_SHIFT 12
@@ -55,25 +52,42 @@ static const char *get_family_string(u32 idreg)
return family;
}
+static char *j721e_rev_string_map[] = {
+ "1.0", "1.1",
+};
+
+static char *am65x_rev_string_map[] = {
+ "1.0", "2.0",
+};
+
static const char *get_rev_string(u32 idreg)
{
- const char *revision;
u32 rev;
+ u32 soc;
rev = (idreg & JTAG_ID_VARIANT_MASK) >> JTAG_ID_VARIANT_SHIFT;
+ soc = (idreg & JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
- switch (rev) {
- case REV_SR1_0:
- revision = "1.0";
- break;
- case REV_SR2_0:
- revision = "2.0";
- break;
+ switch (soc) {
+ case J721E:
+ if (rev > ARRAY_SIZE(j721e_rev_string_map))
+ goto bail;
+ return j721e_rev_string_map[rev];
+
+ case AM65X:
+ if (rev > ARRAY_SIZE(am65x_rev_string_map))
+ goto bail;
+ return am65x_rev_string_map[rev];
+
+ case AM64X:
+ case J7200:
default:
- revision = "Unknown Revision";
+ if (!rev)
+ return "1.0";
};
- return revision;
+bail:
+ return "Unknown Revision";
}
static int soc_ti_k3_get_family(struct udevice *dev, char *buf, int size)
--
2.17.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] soc: soc_ti_k3: update j721e revision numbering
2022-01-26 22:07 [PATCH] soc: soc_ti_k3: update j721e revision numbering Bryan Brattlof
@ 2022-01-27 19:01 ` Bryan Brattlof
2022-01-27 19:10 ` Tom Rini
2022-02-08 17:32 ` Tom Rini
1 sibling, 1 reply; 4+ messages in thread
From: Bryan Brattlof @ 2022-01-27 19:01 UTC (permalink / raw)
To: Tom Rini; +Cc: Dave Gerlach, u-boot
Sorry Tom!
On this day, January 26, 2022, thus sayeth Bryan Brattlof:
> There is a 4 bit VARIANT number inside the JTAGID register that TI
> increments any time a new variant for a chip is produced. Each
> family of TI's SoCs uses a different versioning scheme based off
> that VARIANT number.
>
> CC: Dave Gerlach <d-gerlach@ti.com>
> Signed-off-by: Bryan Brattlof <bb@ti.com>
> ---
> drivers/soc/soc_ti_k3.c | 40 +++++++++++++++++++++++++++-------------
> 1 file changed, 27 insertions(+), 13 deletions(-)
>
I should have sent this to you.
~Bryan
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] soc: soc_ti_k3: update j721e revision numbering
2022-01-27 19:01 ` Bryan Brattlof
@ 2022-01-27 19:10 ` Tom Rini
0 siblings, 0 replies; 4+ messages in thread
From: Tom Rini @ 2022-01-27 19:10 UTC (permalink / raw)
To: Bryan Brattlof; +Cc: Dave Gerlach, u-boot
[-- Attachment #1: Type: text/plain, Size: 704 bytes --]
On Thu, Jan 27, 2022 at 01:01:33PM -0600, Bryan Brattlof wrote:
> Sorry Tom!
>
> On this day, January 26, 2022, thus sayeth Bryan Brattlof:
> > There is a 4 bit VARIANT number inside the JTAGID register that TI
> > increments any time a new variant for a chip is produced. Each
> > family of TI's SoCs uses a different versioning scheme based off
> > that VARIANT number.
> >
> > CC: Dave Gerlach <d-gerlach@ti.com>
> > Signed-off-by: Bryan Brattlof <bb@ti.com>
> > ---
> > drivers/soc/soc_ti_k3.c | 40 +++++++++++++++++++++++++++-------------
> > 1 file changed, 27 insertions(+), 13 deletions(-)
> >
>
> I should have sent this to you.
I saw on the list, thanks.
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] soc: soc_ti_k3: update j721e revision numbering
2022-01-26 22:07 [PATCH] soc: soc_ti_k3: update j721e revision numbering Bryan Brattlof
2022-01-27 19:01 ` Bryan Brattlof
@ 2022-02-08 17:32 ` Tom Rini
1 sibling, 0 replies; 4+ messages in thread
From: Tom Rini @ 2022-02-08 17:32 UTC (permalink / raw)
To: Bryan Brattlof; +Cc: u-boot, Dave Gerlach
[-- Attachment #1: Type: text/plain, Size: 432 bytes --]
On Wed, Jan 26, 2022 at 04:07:33PM -0600, Bryan Brattlof wrote:
> There is a 4 bit VARIANT number inside the JTAGID register that TI
> increments any time a new variant for a chip is produced. Each
> family of TI's SoCs uses a different versioning scheme based off
> that VARIANT number.
>
> CC: Dave Gerlach <d-gerlach@ti.com>
> Signed-off-by: Bryan Brattlof <bb@ti.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2022-02-08 17:34 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-01-26 22:07 [PATCH] soc: soc_ti_k3: update j721e revision numbering Bryan Brattlof
2022-01-27 19:01 ` Bryan Brattlof
2022-01-27 19:10 ` Tom Rini
2022-02-08 17:32 ` Tom Rini
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.