From: Mao Jinlong <quic_jinlmao@quicinc.com> To: Mathieu Poirier <mathieu.poirier@linaro.org>, Suzuki K Poulose <suzuki.poulose@arm.com>, Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Mao Jinlong <quic_jinlmao@quicinc.com>, Mike Leach <mike.leach@linaro.org>, Leo Yan <leo.yan@linaro.org>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, <coresight@lists.linaro.org>, <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, Tingwei Zhang <quic_tingweiz@quicinc.com>, Yuanfang Zhang <quic_yuanfang@quicinc.com>, Tao Zhang <quic_taozha@quicinc.com>, Trilok Soni <quic_tsoni@quicinc.com>, Hao Zhang <quic_hazha@quicinc.com>, <linux-arm-msm@vger.kernel.org> Subject: [PATCH v3 06/10] coresight-tpdm: Add integration test support Date: Wed, 9 Feb 2022 18:57:02 +0800 [thread overview] Message-ID: <20220209105706.18852-7-quic_jinlmao@quicinc.com> (raw) In-Reply-To: <20220209105706.18852-1-quic_jinlmao@quicinc.com> Integration test for tpdm can help to generate the data for verification of the topology during TPDM software bring up. Sample: echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink echo 1 > /sys/bus/coresight/devices/tpdm1/enable_source echo 1 > /sys/bus/coresight/devices/tpdm1/integration_test echo 2 > /sys/bus/coresight/devices/tpdm1/integration_test cat /dev/tmc_etf0 > /data/etf-tpdm1.bin Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com> --- drivers/hwtracing/coresight/Kconfig | 9 ++++ drivers/hwtracing/coresight/coresight-tpdm.c | 54 ++++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 8 +++ 3 files changed, 71 insertions(+) diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index 5c506a1cd08f..60248fef4089 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -214,4 +214,13 @@ config CORESIGHT_TPDM To compile this driver as a module, choose M here: the module will be called coresight-tpdm. +config CORESIGHT_TPDM_INTEGRATION_TEST + bool "Enable CoreSight Integration Test For TPDM" + depends on CORESIGHT_TPDM + help + This option adds support for the CoreSight integration test on this + devie. Coresight architecture provides integration control modes of + operation to facilitate integration testing and software bringup + and/or to instrument topology discovery. The TPDM utilizes integration + mode to accomplish integration testing and software bringup. endif diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index c6480b7389b0..7a2b9097b470 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -136,6 +136,59 @@ static void tpdm_init_default_data(struct tpdm_drvdata *drvdata) CS_LOCK(drvdata->base); } +#ifdef CONFIG_CORESIGHT_TPDM_INTEGRATION_TEST +static ssize_t integration_test_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + int i, ret = 0; + unsigned long val; + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + ret = kstrtoul(buf, 10, &val); + if (ret) + return ret; + + if (val != 1 && val != 2) + return -EINVAL; + + if (!drvdata->enable) + return -EINVAL; + + if (val == 1) + val = ATBCNTRL_VAL_64; + else + val = ATBCNTRL_VAL_32; + CS_UNLOCK(drvdata->base); + writel_relaxed(0x1, drvdata->base + TPDM_ITCNTRL); + + for (i = 1; i < 5; i++) + writel_relaxed(val, drvdata->base + TPDM_ITATBCNTRL); + + writel_relaxed(0, drvdata->base + TPDM_ITCNTRL); + CS_LOCK(drvdata->base); + return size; +} +static DEVICE_ATTR_WO(integration_test); +#endif /* CORESIGHT_TPDM_INTEGRATION_TEST */ + +static struct attribute *tpdm_attrs[] = { +#ifdef CONFIG_CORESIGHT_TPDM_INTEGRATION_TEST + &dev_attr_integration_test.attr, +#endif /* CORESIGHT_TPDM_INTEGRATION_TEST */ + NULL, +}; + +static struct attribute_group tpdm_attr_grp = { + .attrs = tpdm_attrs, +}; + +static const struct attribute_group *tpdm_attr_grps[] = { + &tpdm_attr_grp, + NULL, +}; + static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) { struct device *dev = &adev->dev; @@ -171,6 +224,7 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) desc.ops = &tpdm_cs_ops; desc.pdata = adev->dev.platform_data; desc.dev = &adev->dev; + desc.groups = tpdm_attr_grps; drvdata->csdev = coresight_register(&desc); if (IS_ERR(drvdata->csdev)) return PTR_ERR(drvdata->csdev); diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index cb3ddc6c89ae..128fcff37192 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -12,6 +12,14 @@ /* DSB Subunit Registers */ #define TPDM_DSB_CR (0x780) +/* TPDM integration test registers */ +#define TPDM_ITATBCNTRL (0xEF0) +#define TPDM_ITCNTRL (0xF00) + +/* Register value for integration test */ +#define ATBCNTRL_VAL_32 0xC00F1409 +#define ATBCNTRL_VAL_64 0xC01F1409 + /** * This enum is for PERIPHIDR0 register of TPDM. * The fields [6:0] of PERIPHIDR0 are used to determine what -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Mao Jinlong <quic_jinlmao@quicinc.com> To: Mathieu Poirier <mathieu.poirier@linaro.org>, Suzuki K Poulose <suzuki.poulose@arm.com>, Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Mao Jinlong <quic_jinlmao@quicinc.com>, Mike Leach <mike.leach@linaro.org>, Leo Yan <leo.yan@linaro.org>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, <coresight@lists.linaro.org>, <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, Tingwei Zhang <quic_tingweiz@quicinc.com>, Yuanfang Zhang <quic_yuanfang@quicinc.com>, Tao Zhang <quic_taozha@quicinc.com>, Trilok Soni <quic_tsoni@quicinc.com>, Hao Zhang <quic_hazha@quicinc.com>, <linux-arm-msm@vger.kernel.org> Subject: [PATCH v3 06/10] coresight-tpdm: Add integration test support Date: Wed, 9 Feb 2022 18:57:02 +0800 [thread overview] Message-ID: <20220209105706.18852-7-quic_jinlmao@quicinc.com> (raw) In-Reply-To: <20220209105706.18852-1-quic_jinlmao@quicinc.com> Integration test for tpdm can help to generate the data for verification of the topology during TPDM software bring up. Sample: echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink echo 1 > /sys/bus/coresight/devices/tpdm1/enable_source echo 1 > /sys/bus/coresight/devices/tpdm1/integration_test echo 2 > /sys/bus/coresight/devices/tpdm1/integration_test cat /dev/tmc_etf0 > /data/etf-tpdm1.bin Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com> --- drivers/hwtracing/coresight/Kconfig | 9 ++++ drivers/hwtracing/coresight/coresight-tpdm.c | 54 ++++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 8 +++ 3 files changed, 71 insertions(+) diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index 5c506a1cd08f..60248fef4089 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -214,4 +214,13 @@ config CORESIGHT_TPDM To compile this driver as a module, choose M here: the module will be called coresight-tpdm. +config CORESIGHT_TPDM_INTEGRATION_TEST + bool "Enable CoreSight Integration Test For TPDM" + depends on CORESIGHT_TPDM + help + This option adds support for the CoreSight integration test on this + devie. Coresight architecture provides integration control modes of + operation to facilitate integration testing and software bringup + and/or to instrument topology discovery. The TPDM utilizes integration + mode to accomplish integration testing and software bringup. endif diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index c6480b7389b0..7a2b9097b470 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -136,6 +136,59 @@ static void tpdm_init_default_data(struct tpdm_drvdata *drvdata) CS_LOCK(drvdata->base); } +#ifdef CONFIG_CORESIGHT_TPDM_INTEGRATION_TEST +static ssize_t integration_test_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + int i, ret = 0; + unsigned long val; + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + ret = kstrtoul(buf, 10, &val); + if (ret) + return ret; + + if (val != 1 && val != 2) + return -EINVAL; + + if (!drvdata->enable) + return -EINVAL; + + if (val == 1) + val = ATBCNTRL_VAL_64; + else + val = ATBCNTRL_VAL_32; + CS_UNLOCK(drvdata->base); + writel_relaxed(0x1, drvdata->base + TPDM_ITCNTRL); + + for (i = 1; i < 5; i++) + writel_relaxed(val, drvdata->base + TPDM_ITATBCNTRL); + + writel_relaxed(0, drvdata->base + TPDM_ITCNTRL); + CS_LOCK(drvdata->base); + return size; +} +static DEVICE_ATTR_WO(integration_test); +#endif /* CORESIGHT_TPDM_INTEGRATION_TEST */ + +static struct attribute *tpdm_attrs[] = { +#ifdef CONFIG_CORESIGHT_TPDM_INTEGRATION_TEST + &dev_attr_integration_test.attr, +#endif /* CORESIGHT_TPDM_INTEGRATION_TEST */ + NULL, +}; + +static struct attribute_group tpdm_attr_grp = { + .attrs = tpdm_attrs, +}; + +static const struct attribute_group *tpdm_attr_grps[] = { + &tpdm_attr_grp, + NULL, +}; + static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) { struct device *dev = &adev->dev; @@ -171,6 +224,7 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) desc.ops = &tpdm_cs_ops; desc.pdata = adev->dev.platform_data; desc.dev = &adev->dev; + desc.groups = tpdm_attr_grps; drvdata->csdev = coresight_register(&desc); if (IS_ERR(drvdata->csdev)) return PTR_ERR(drvdata->csdev); diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index cb3ddc6c89ae..128fcff37192 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -12,6 +12,14 @@ /* DSB Subunit Registers */ #define TPDM_DSB_CR (0x780) +/* TPDM integration test registers */ +#define TPDM_ITATBCNTRL (0xEF0) +#define TPDM_ITCNTRL (0xF00) + +/* Register value for integration test */ +#define ATBCNTRL_VAL_32 0xC00F1409 +#define ATBCNTRL_VAL_64 0xC01F1409 + /** * This enum is for PERIPHIDR0 register of TPDM. * The fields [6:0] of PERIPHIDR0 are used to determine what -- 2.17.1
next prev parent reply other threads:[~2022-02-09 11:00 UTC|newest] Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-02-09 10:56 [PATCH v3 00/10] Coresight: Add support for TPDM and TPDA Mao Jinlong 2022-02-09 10:56 ` Mao Jinlong 2022-02-09 10:56 ` [PATCH v3 01/10] Use IDR to maintain all the enabled sources' paths Mao Jinlong 2022-02-09 10:56 ` Mao Jinlong 2022-02-09 15:34 ` Mike Leach 2022-02-09 15:34 ` Mike Leach 2022-02-09 10:56 ` [PATCH v3 02/10] coresight: Use bitmap to assign trace id to the sources Mao Jinlong 2022-02-09 10:56 ` Mao Jinlong 2022-02-17 17:35 ` Mike Leach 2022-02-17 17:35 ` Mike Leach 2022-02-09 10:56 ` [PATCH v3 03/10] Coresight: Add coresight TPDM source driver Mao Jinlong 2022-02-09 10:56 ` Mao Jinlong 2022-02-18 16:10 ` Mike Leach 2022-02-18 16:10 ` Mike Leach 2022-02-09 10:57 ` [PATCH v3 04/10] dt-bindings: arm: Adds CoreSight TPDM hardware definitions Mao Jinlong 2022-02-09 10:57 ` Mao Jinlong 2022-02-17 17:48 ` Mike Leach 2022-02-17 17:48 ` Mike Leach 2022-02-09 10:57 ` [PATCH v3 05/10] coresight-tpdm: Add DSB dataset support Mao Jinlong 2022-02-09 10:57 ` Mao Jinlong 2022-02-18 16:10 ` Mike Leach 2022-02-18 16:10 ` Mike Leach 2022-02-09 10:57 ` Mao Jinlong [this message] 2022-02-09 10:57 ` [PATCH v3 06/10] coresight-tpdm: Add integration test support Mao Jinlong 2022-02-09 10:57 ` [PATCH v3 07/10] docs: sysfs: coresight: Add sysfs ABI documentation for TPDM Mao Jinlong 2022-02-09 10:57 ` Mao Jinlong 2022-02-09 10:57 ` [PATCH v3 08/10] Coresight: Add TPDA link driver Mao Jinlong 2022-02-09 10:57 ` Mao Jinlong 2022-02-09 10:57 ` [PATCH v3 09/10] dt-bindings: arm: Adds CoreSight TPDA hardware definitions Mao Jinlong 2022-02-09 10:57 ` Mao Jinlong 2022-02-09 10:57 ` [PATCH v3 10/10] ARM: dts: msm: Add coresight components for SM8250 Mao Jinlong 2022-02-09 10:57 ` Mao Jinlong 2022-02-18 16:10 ` Mike Leach 2022-02-18 16:10 ` Mike Leach 2022-02-10 10:30 ` [PATCH v3 00/10] Coresight: Add support for TPDM and TPDA Mike Leach 2022-02-10 10:30 ` Mike Leach 2022-02-11 4:17 ` Jinlong Mao 2022-02-11 4:17 ` Jinlong Mao 2022-02-17 9:16 ` Jinlong Mao 2022-02-17 9:16 ` Jinlong Mao 2022-02-17 15:30 ` Mike Leach 2022-02-17 15:30 ` Mike Leach 2022-02-28 2:49 ` Jinlong Mao 2022-02-28 2:49 ` Jinlong Mao
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20220209105706.18852-7-quic_jinlmao@quicinc.com \ --to=quic_jinlmao@quicinc.com \ --cc=alexander.shishkin@linux.intel.com \ --cc=coresight@lists.linaro.org \ --cc=gregkh@linuxfoundation.org \ --cc=leo.yan@linaro.org \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-arm-msm@vger.kernel.org \ --cc=linux-kernel@vger.kernel.org \ --cc=mathieu.poirier@linaro.org \ --cc=mike.leach@linaro.org \ --cc=quic_hazha@quicinc.com \ --cc=quic_taozha@quicinc.com \ --cc=quic_tingweiz@quicinc.com \ --cc=quic_tsoni@quicinc.com \ --cc=quic_yuanfang@quicinc.com \ --cc=suzuki.poulose@arm.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.