[Intel-gfx] [PATCH 1/7] drm/i915: Move vblank waits out from IPS code

[Intel-gfx] [PATCH 1/7] drm/i915: Move vblank waits out from IPS code

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Hoist the IPS related vblank waits one level up. Later on we'll
want to consolidate all the potential pre-plane update vblank
waits into one so we can't be hiding any in low level code.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 19 ++++++++++++-------
 drivers/gpu/drm/i915/display/intel_display.h |  2 +-
 2 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7f512f9e9e5c..5cc142a83ad7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -752,8 +752,9 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
 	crtc_state->data_rate[plane->id] = 0;
 	crtc_state->min_cdclk[plane->id] = 0;
 
-	if (plane->id == PLANE_PRIMARY)
-		hsw_disable_ips(crtc_state);
+	if (plane->id == PLANE_PRIMARY &&
+	    hsw_disable_ips(crtc_state))
+		intel_crtc_wait_for_next_vblank(crtc);
 
 	/*
 	 * Vblank time updates from the shadow to live plane control register
@@ -1127,14 +1128,15 @@ void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
 	}
 }
 
-void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
+bool hsw_disable_ips(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
+	bool need_vblank_wait = false;
 
 	if (!crtc_state->ips_enabled)
-		return;
+		return need_vblank_wait;
 
 	if (IS_BROADWELL(dev_priv)) {
 		drm_WARN_ON(dev,
@@ -1153,7 +1155,9 @@ void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
 	}
 
 	/* We need to wait for a vblank before we can disable the plane. */
-	intel_crtc_wait_for_next_vblank(crtc);
+	need_vblank_wait = true;
+
+	return need_vblank_wait;
 }
 
 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
@@ -1426,8 +1430,9 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
 
 	intel_psr_pre_plane_update(state, crtc);
 
-	if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
-		hsw_disable_ips(old_crtc_state);
+	if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state) &&
+	    hsw_disable_ips(old_crtc_state))
+		intel_crtc_wait_for_next_vblank(crtc);
 
 	if (intel_fbc_pre_update(state, crtc))
 		intel_crtc_wait_for_next_vblank(crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 457738aeee3e..8f9bec36898e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -634,7 +634,7 @@ void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
-void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
+bool hsw_disable_ips(const struct intel_crtc_state *crtc_state);
 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
 enum intel_display_power_domain
 intel_aux_power_domain(struct intel_digital_port *dig_port);
-- 
2.34.1

[Intel-gfx] [PATCH 2/7] drm/i915: Change IPS calling convention

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Follow the modern state+crtc calling convention for the IPS
code as well.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 38 +++++++++++---------
 1 file changed, 22 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5cc142a83ad7..c5d30c683911 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1170,11 +1170,14 @@ static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
 	 */
 }
 
-static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
-				       const struct intel_crtc_state *new_crtc_state)
+static bool hsw_pre_update_disable_ips(struct intel_atomic_state *state,
+				       struct intel_crtc *crtc)
 {
-	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	const struct intel_crtc_state *old_crtc_state =
+		intel_atomic_get_old_crtc_state(state, crtc);
+	const struct intel_crtc_state *new_crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
 
 	if (!old_crtc_state->ips_enabled)
 		return false;
@@ -1197,11 +1200,14 @@ static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_s
 	return !new_crtc_state->ips_enabled;
 }
 
-static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
-				       const struct intel_crtc_state *new_crtc_state)
+static bool hsw_post_update_enable_ips(struct intel_atomic_state *state,
+				       struct intel_crtc *crtc)
 {
-	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	const struct intel_crtc_state *old_crtc_state =
+		intel_atomic_get_old_crtc_state(state, crtc);
+	const struct intel_crtc_state *new_crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
 
 	if (!new_crtc_state->ips_enabled)
 		return false;
@@ -1325,7 +1331,7 @@ static void intel_post_plane_update(struct intel_atomic_state *state,
 	if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
 		intel_update_watermarks(dev_priv);
 
-	if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
+	if (hsw_post_update_enable_ips(state, crtc))
 		hsw_enable_ips(new_crtc_state);
 
 	intel_fbc_post_update(state, crtc);
@@ -1430,7 +1436,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
 
 	intel_psr_pre_plane_update(state, crtc);
 
-	if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state) &&
+	if (hsw_pre_update_disable_ips(state, crtc) &&
 	    hsw_disable_ips(old_crtc_state))
 		intel_crtc_wait_for_next_vblank(crtc);
 
@@ -2812,12 +2818,12 @@ bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
 	return true;
 }
 
-static int hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
+static int hsw_ips_compute_config(struct intel_atomic_state *state,
+				  struct intel_crtc *crtc)
 {
-	struct drm_i915_private *dev_priv =
-		to_i915(crtc_state->uapi.crtc->dev);
-	struct intel_atomic_state *state =
-		to_intel_atomic_state(crtc_state->uapi.state);
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
 
 	crtc_state->ips_enabled = false;
 
@@ -5322,7 +5328,7 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
 	}
 
 	if (HAS_IPS(dev_priv)) {
-		ret = hsw_compute_ips_config(crtc_state);
+		ret = hsw_ips_compute_config(state, crtc);
 		if (ret)
 			return ret;
 	}
-- 
2.34.1

[Intel-gfx] [PATCH 3/7] drm/i915: Hoover the IPS enable/disable calls into the pre/post update hooks

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

No reason the caller of the IPS pre/post update hooks should
be responsible for the actual IPS enab/disable. Just pull those
calls into the pre/post update hooks themselves. And while
at it let's adjust the function naming a bit to have a consistent
namespace.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 46 +++++++++++++++-----
 drivers/gpu/drm/i915/display/intel_display.h |  2 -
 2 files changed, 34 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c5d30c683911..08c59fdb24e5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -125,6 +125,7 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
 static void intel_modeset_setup_hw_state(struct drm_device *dev,
 					 struct drm_modeset_acquire_ctx *ctx);
+static bool hsw_ips_disable(const struct intel_crtc_state *crtc_state);
 
 /**
  * intel_update_watermarks - update FIFO watermark values based on current modes
@@ -753,7 +754,7 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
 	crtc_state->min_cdclk[plane->id] = 0;
 
 	if (plane->id == PLANE_PRIMARY &&
-	    hsw_disable_ips(crtc_state))
+	    hsw_ips_disable(crtc_state))
 		intel_crtc_wait_for_next_vblank(crtc);
 
 	/*
@@ -1091,7 +1092,7 @@ static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
 	intel_de_write(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
 }
 
-void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
+static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_device *dev = crtc->base.dev;
@@ -1128,7 +1129,7 @@ void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
 	}
 }
 
-bool hsw_disable_ips(const struct intel_crtc_state *crtc_state)
+static bool hsw_ips_disable(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_device *dev = crtc->base.dev;
@@ -1170,8 +1171,8 @@ static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
 	 */
 }
 
-static bool hsw_pre_update_disable_ips(struct intel_atomic_state *state,
-				       struct intel_crtc *crtc)
+static bool hsw_ips_need_disable(struct intel_atomic_state *state,
+				 struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 	const struct intel_crtc_state *old_crtc_state =
@@ -1200,8 +1201,20 @@ static bool hsw_pre_update_disable_ips(struct intel_atomic_state *state,
 	return !new_crtc_state->ips_enabled;
 }
 
-static bool hsw_post_update_enable_ips(struct intel_atomic_state *state,
-				       struct intel_crtc *crtc)
+static bool hsw_ips_pre_update(struct intel_atomic_state *state,
+			       struct intel_crtc *crtc)
+{
+	const struct intel_crtc_state *old_crtc_state =
+		intel_atomic_get_old_crtc_state(state, crtc);
+
+	if (!hsw_ips_need_disable(state, crtc))
+		return false;
+
+	return hsw_ips_disable(old_crtc_state);
+}
+
+static bool hsw_ips_need_enable(struct intel_atomic_state *state,
+				struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 	const struct intel_crtc_state *old_crtc_state =
@@ -1237,6 +1250,18 @@ static bool hsw_post_update_enable_ips(struct intel_atomic_state *state,
 	return !old_crtc_state->ips_enabled;
 }
 
+static void hsw_ips_post_update(struct intel_atomic_state *state,
+				struct intel_crtc *crtc)
+{
+	const struct intel_crtc_state *new_crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+
+	if (!hsw_ips_need_enable(state, crtc))
+		return;
+
+	hsw_ips_enable(new_crtc_state);
+}
+
 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
@@ -1331,9 +1356,7 @@ static void intel_post_plane_update(struct intel_atomic_state *state,
 	if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
 		intel_update_watermarks(dev_priv);
 
-	if (hsw_post_update_enable_ips(state, crtc))
-		hsw_enable_ips(new_crtc_state);
-
+	hsw_ips_post_update(state, crtc);
 	intel_fbc_post_update(state, crtc);
 	intel_drrs_page_flip(state, crtc);
 
@@ -1436,8 +1459,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
 
 	intel_psr_pre_plane_update(state, crtc);
 
-	if (hsw_pre_update_disable_ips(state, crtc) &&
-	    hsw_disable_ips(old_crtc_state))
+	if (hsw_ips_pre_update(state, crtc))
 		intel_crtc_wait_for_next_vblank(crtc);
 
 	if (intel_fbc_pre_update(state, crtc))
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 8f9bec36898e..2315088a280d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -633,8 +633,6 @@ void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 			 struct intel_crtc_state *pipe_config);
 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
-void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
-bool hsw_disable_ips(const struct intel_crtc_state *crtc_state);
 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
 enum intel_display_power_domain
 intel_aux_power_domain(struct intel_digital_port *dig_port);
-- 
2.34.1

[Intel-gfx] [PATCH 4/7] drm/i915: Move the IPS code to its own file

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

IPS is a prety well isolated feature. Move the relevant code
to a separate file from polluting intel_display.c.

I stuck to the hsw_ips since that's what the function were already
using, and also to avoid confusion with the ILK
"Intelligen Power Sharing"/intel_ips GPU turbo stuff.

And let's also do the s/dev_priv/i915/ rename while touching
most of the code.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/Makefile                |   1 +
 drivers/gpu/drm/i915/display/hsw_ips.c       | 251 +++++++++++++++++++
 drivers/gpu/drm/i915/display/hsw_ips.h       |  25 ++
 drivers/gpu/drm/i915/display/intel_cdclk.c   |   1 +
 drivers/gpu/drm/i915/display/intel_display.c | 239 +-----------------
 drivers/gpu/drm/i915/display/intel_display.h |   1 -
 6 files changed, 279 insertions(+), 239 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/hsw_ips.c
 create mode 100644 drivers/gpu/drm/i915/display/hsw_ips.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a26e6736bebb..226dbef5f64a 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -197,6 +197,7 @@ i915-y += gt/uc/intel_uc.o \
 
 # modesetting core code
 i915-y += \
+	display/hsw_ips.o \
 	display/intel_atomic.o \
 	display/intel_atomic_plane.o \
 	display/intel_audio.o \
diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c
new file mode 100644
index 000000000000..fb34ef615025
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/hsw_ips.c
@@ -0,0 +1,251 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include "hsw_ips.h"
+#include "i915_drv.h"
+#include "i915_reg.h"
+#include "intel_de.h"
+#include "intel_display_types.h"
+#include "intel_pcode.h"
+
+static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+
+	if (!crtc_state->ips_enabled)
+		return;
+
+	/*
+	 * We can only enable IPS after we enable a plane and wait for a vblank
+	 * This function is called from post_plane_update, which is run after
+	 * a vblank wait.
+	 */
+	drm_WARN_ON(&i915->drm,
+		    !(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
+
+	if (IS_BROADWELL(i915)) {
+		drm_WARN_ON(&i915->drm,
+			    snb_pcode_write(i915, DISPLAY_IPS_CONTROL,
+					    IPS_ENABLE | IPS_PCODE_CONTROL));
+		/*
+		 * Quoting Art Runyan: "its not safe to expect any particular
+		 * value in IPS_CTL bit 31 after enabling IPS through the
+		 * mailbox." Moreover, the mailbox may return a bogus state,
+		 * so we need to just enable it and continue on.
+		 */
+	} else {
+		intel_de_write(i915, IPS_CTL, IPS_ENABLE);
+		/*
+		 * The bit only becomes 1 in the next vblank, so this wait here
+		 * is essentially intel_wait_for_vblank. If we don't have this
+		 * and don't wait for vblanks until the end of crtc_enable, then
+		 * the HW state readout code will complain that the expected
+		 * IPS_CTL value is not the one we read.
+		 */
+		if (intel_de_wait_for_set(i915, IPS_CTL, IPS_ENABLE, 50))
+			drm_err(&i915->drm,
+				"Timed out waiting for IPS enable\n");
+	}
+}
+
+bool hsw_ips_disable(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+	bool need_vblank_wait = false;
+
+	if (!crtc_state->ips_enabled)
+		return need_vblank_wait;
+
+	if (IS_BROADWELL(i915)) {
+		drm_WARN_ON(&i915->drm,
+			    snb_pcode_write(i915, DISPLAY_IPS_CONTROL, 0));
+		/*
+		 * Wait for PCODE to finish disabling IPS. The BSpec specified
+		 * 42ms timeout value leads to occasional timeouts so use 100ms
+		 * instead.
+		 */
+		if (intel_de_wait_for_clear(i915, IPS_CTL, IPS_ENABLE, 100))
+			drm_err(&i915->drm,
+				"Timed out waiting for IPS disable\n");
+	} else {
+		intel_de_write(i915, IPS_CTL, 0);
+		intel_de_posting_read(i915, IPS_CTL);
+	}
+
+	/* We need to wait for a vblank before we can disable the plane. */
+	need_vblank_wait = true;
+
+	return need_vblank_wait;
+}
+
+static bool hsw_ips_need_disable(struct intel_atomic_state *state,
+				 struct intel_crtc *crtc)
+{
+	struct drm_i915_private *i915 = to_i915(state->base.dev);
+	const struct intel_crtc_state *old_crtc_state =
+		intel_atomic_get_old_crtc_state(state, crtc);
+	const struct intel_crtc_state *new_crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+
+	if (!old_crtc_state->ips_enabled)
+		return false;
+
+	if (intel_crtc_needs_modeset(new_crtc_state))
+		return true;
+
+	/*
+	 * Workaround : Do not read or write the pipe palette/gamma data while
+	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
+	 *
+	 * Disable IPS before we program the LUT.
+	 */
+	if (IS_HASWELL(i915) &&
+	    (new_crtc_state->uapi.color_mgmt_changed ||
+	     new_crtc_state->update_pipe) &&
+	    new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
+		return true;
+
+	return !new_crtc_state->ips_enabled;
+}
+
+bool hsw_ips_pre_update(struct intel_atomic_state *state,
+			struct intel_crtc *crtc)
+{
+	const struct intel_crtc_state *old_crtc_state =
+		intel_atomic_get_old_crtc_state(state, crtc);
+
+	if (!hsw_ips_need_disable(state, crtc))
+		return false;
+
+	return hsw_ips_disable(old_crtc_state);
+}
+
+static bool hsw_ips_need_enable(struct intel_atomic_state *state,
+				struct intel_crtc *crtc)
+{
+	struct drm_i915_private *i915 = to_i915(state->base.dev);
+	const struct intel_crtc_state *old_crtc_state =
+		intel_atomic_get_old_crtc_state(state, crtc);
+	const struct intel_crtc_state *new_crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+
+	if (!new_crtc_state->ips_enabled)
+		return false;
+
+	if (intel_crtc_needs_modeset(new_crtc_state))
+		return true;
+
+	/*
+	 * Workaround : Do not read or write the pipe palette/gamma data while
+	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
+	 *
+	 * Re-enable IPS after the LUT has been programmed.
+	 */
+	if (IS_HASWELL(i915) &&
+	    (new_crtc_state->uapi.color_mgmt_changed ||
+	     new_crtc_state->update_pipe) &&
+	    new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
+		return true;
+
+	/*
+	 * We can't read out IPS on broadwell, assume the worst and
+	 * forcibly enable IPS on the first fastset.
+	 */
+	if (new_crtc_state->update_pipe && old_crtc_state->inherited)
+		return true;
+
+	return !old_crtc_state->ips_enabled;
+}
+
+void hsw_ips_post_update(struct intel_atomic_state *state,
+			 struct intel_crtc *crtc)
+{
+	const struct intel_crtc_state *new_crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+
+	if (!hsw_ips_need_enable(state, crtc))
+		return;
+
+	hsw_ips_enable(new_crtc_state);
+}
+
+/* IPS only exists on ULT machines and is tied to pipe A. */
+bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
+{
+	return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
+}
+
+bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+
+	/* IPS only exists on ULT machines and is tied to pipe A. */
+	if (!hsw_crtc_supports_ips(crtc))
+		return false;
+
+	if (!i915->params.enable_ips)
+		return false;
+
+	if (crtc_state->pipe_bpp > 24)
+		return false;
+
+	/*
+	 * We compare against max which means we must take
+	 * the increased cdclk requirement into account when
+	 * calculating the new cdclk.
+	 *
+	 * Should measure whether using a lower cdclk w/o IPS
+	 */
+	if (IS_BROADWELL(i915) &&
+	    crtc_state->pixel_rate > i915->max_cdclk_freq * 95 / 100)
+		return false;
+
+	return true;
+}
+
+int hsw_ips_compute_config(struct intel_atomic_state *state,
+			   struct intel_crtc *crtc)
+{
+	struct drm_i915_private *i915 = to_i915(state->base.dev);
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+
+	crtc_state->ips_enabled = false;
+
+	if (!hsw_crtc_state_ips_capable(crtc_state))
+		return 0;
+
+	/*
+	 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
+	 * enabled and disabled dynamically based on package C states,
+	 * user space can't make reliable use of the CRCs, so let's just
+	 * completely disable it.
+	 */
+	if (crtc_state->crc_enabled)
+		return 0;
+
+	/* IPS should be fine as long as at least one plane is enabled. */
+	if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
+		return 0;
+
+	if (IS_BROADWELL(i915)) {
+		const struct intel_cdclk_state *cdclk_state;
+
+		cdclk_state = intel_atomic_get_cdclk_state(state);
+		if (IS_ERR(cdclk_state))
+			return PTR_ERR(cdclk_state);
+
+		/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
+		if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
+			return 0;
+	}
+
+	crtc_state->ips_enabled = true;
+
+	return 0;
+}
diff --git a/drivers/gpu/drm/i915/display/hsw_ips.h b/drivers/gpu/drm/i915/display/hsw_ips.h
new file mode 100644
index 000000000000..d63bdef5100a
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/hsw_ips.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __HSW_IPS_H__
+#define __HSW_IPS_H__
+
+#include <linux/types.h>
+
+struct intel_atomic_state;
+struct intel_crtc;
+struct intel_crtc_state;
+
+bool hsw_ips_disable(const struct intel_crtc_state *crtc_state);
+bool hsw_ips_pre_update(struct intel_atomic_state *state,
+			struct intel_crtc *crtc);
+void hsw_ips_post_update(struct intel_atomic_state *state,
+			 struct intel_crtc *crtc);
+bool hsw_crtc_supports_ips(struct intel_crtc *crtc);
+bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
+int hsw_ips_compute_config(struct intel_atomic_state *state,
+			   struct intel_crtc *crtc);
+
+#endif /* __HSW_IPS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 4b140a014ca8..118ef391b560 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -23,6 +23,7 @@
 
 #include <linux/time.h>
 
+#include "hsw_ips.h"
 #include "intel_atomic.h"
 #include "intel_atomic_plane.h"
 #include "intel_audio.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 08c59fdb24e5..134527981e2b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -74,6 +74,7 @@
 
 #include "g4x_dp.h"
 #include "g4x_hdmi.h"
+#include "hsw_ips.h"
 #include "i915_drv.h"
 #include "icl_dsi.h"
 #include "intel_acpi.h"
@@ -125,7 +126,6 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
 static void intel_modeset_setup_hw_state(struct drm_device *dev,
 					 struct drm_modeset_acquire_ctx *ctx);
-static bool hsw_ips_disable(const struct intel_crtc_state *crtc_state);
 
 /**
  * intel_update_watermarks - update FIFO watermark values based on current modes
@@ -1092,75 +1092,6 @@ static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
 	intel_de_write(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
 }
 
-static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)
-{
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_device *dev = crtc->base.dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
-
-	if (!crtc_state->ips_enabled)
-		return;
-
-	/*
-	 * We can only enable IPS after we enable a plane and wait for a vblank
-	 * This function is called from post_plane_update, which is run after
-	 * a vblank wait.
-	 */
-	drm_WARN_ON(dev, !(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
-
-	if (IS_BROADWELL(dev_priv)) {
-		drm_WARN_ON(dev, snb_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
-						 IPS_ENABLE | IPS_PCODE_CONTROL));
-		/* Quoting Art Runyan: "its not safe to expect any particular
-		 * value in IPS_CTL bit 31 after enabling IPS through the
-		 * mailbox." Moreover, the mailbox may return a bogus state,
-		 * so we need to just enable it and continue on.
-		 */
-	} else {
-		intel_de_write(dev_priv, IPS_CTL, IPS_ENABLE);
-		/* The bit only becomes 1 in the next vblank, so this wait here
-		 * is essentially intel_wait_for_vblank. If we don't have this
-		 * and don't wait for vblanks until the end of crtc_enable, then
-		 * the HW state readout code will complain that the expected
-		 * IPS_CTL value is not the one we read. */
-		if (intel_de_wait_for_set(dev_priv, IPS_CTL, IPS_ENABLE, 50))
-			drm_err(&dev_priv->drm,
-				"Timed out waiting for IPS enable\n");
-	}
-}
-
-static bool hsw_ips_disable(const struct intel_crtc_state *crtc_state)
-{
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_device *dev = crtc->base.dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
-	bool need_vblank_wait = false;
-
-	if (!crtc_state->ips_enabled)
-		return need_vblank_wait;
-
-	if (IS_BROADWELL(dev_priv)) {
-		drm_WARN_ON(dev,
-			    snb_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
-		/*
-		 * Wait for PCODE to finish disabling IPS. The BSpec specified
-		 * 42ms timeout value leads to occasional timeouts so use 100ms
-		 * instead.
-		 */
-		if (intel_de_wait_for_clear(dev_priv, IPS_CTL, IPS_ENABLE, 100))
-			drm_err(&dev_priv->drm,
-				"Timed out waiting for IPS disable\n");
-	} else {
-		intel_de_write(dev_priv, IPS_CTL, 0);
-		intel_de_posting_read(dev_priv, IPS_CTL);
-	}
-
-	/* We need to wait for a vblank before we can disable the plane. */
-	need_vblank_wait = true;
-
-	return need_vblank_wait;
-}
-
 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
 {
 	if (crtc->overlay)
@@ -1171,97 +1102,6 @@ static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
 	 */
 }
 
-static bool hsw_ips_need_disable(struct intel_atomic_state *state,
-				 struct intel_crtc *crtc)
-{
-	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-	const struct intel_crtc_state *old_crtc_state =
-		intel_atomic_get_old_crtc_state(state, crtc);
-	const struct intel_crtc_state *new_crtc_state =
-		intel_atomic_get_new_crtc_state(state, crtc);
-
-	if (!old_crtc_state->ips_enabled)
-		return false;
-
-	if (intel_crtc_needs_modeset(new_crtc_state))
-		return true;
-
-	/*
-	 * Workaround : Do not read or write the pipe palette/gamma data while
-	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
-	 *
-	 * Disable IPS before we program the LUT.
-	 */
-	if (IS_HASWELL(dev_priv) &&
-	    (new_crtc_state->uapi.color_mgmt_changed ||
-	     new_crtc_state->update_pipe) &&
-	    new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
-		return true;
-
-	return !new_crtc_state->ips_enabled;
-}
-
-static bool hsw_ips_pre_update(struct intel_atomic_state *state,
-			       struct intel_crtc *crtc)
-{
-	const struct intel_crtc_state *old_crtc_state =
-		intel_atomic_get_old_crtc_state(state, crtc);
-
-	if (!hsw_ips_need_disable(state, crtc))
-		return false;
-
-	return hsw_ips_disable(old_crtc_state);
-}
-
-static bool hsw_ips_need_enable(struct intel_atomic_state *state,
-				struct intel_crtc *crtc)
-{
-	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-	const struct intel_crtc_state *old_crtc_state =
-		intel_atomic_get_old_crtc_state(state, crtc);
-	const struct intel_crtc_state *new_crtc_state =
-		intel_atomic_get_new_crtc_state(state, crtc);
-
-	if (!new_crtc_state->ips_enabled)
-		return false;
-
-	if (intel_crtc_needs_modeset(new_crtc_state))
-		return true;
-
-	/*
-	 * Workaround : Do not read or write the pipe palette/gamma data while
-	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
-	 *
-	 * Re-enable IPS after the LUT has been programmed.
-	 */
-	if (IS_HASWELL(dev_priv) &&
-	    (new_crtc_state->uapi.color_mgmt_changed ||
-	     new_crtc_state->update_pipe) &&
-	    new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
-		return true;
-
-	/*
-	 * We can't read out IPS on broadwell, assume the worst and
-	 * forcibly enable IPS on the first fastset.
-	 */
-	if (new_crtc_state->update_pipe && old_crtc_state->inherited)
-		return true;
-
-	return !old_crtc_state->ips_enabled;
-}
-
-static void hsw_ips_post_update(struct intel_atomic_state *state,
-				struct intel_crtc *crtc)
-{
-	const struct intel_crtc_state *new_crtc_state =
-		intel_atomic_get_new_crtc_state(state, crtc);
-
-	if (!hsw_ips_need_enable(state, crtc))
-		return;
-
-	hsw_ips_enable(new_crtc_state);
-}
-
 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
@@ -1938,12 +1778,6 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,
 	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
 }
 
-/* IPS only exists on ULT machines and is tied to pipe A. */
-static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
-{
-	return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
-}
-
 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
 					    enum pipe pipe, bool apply)
 {
@@ -2811,77 +2645,6 @@ static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
 	}
 }
 
-bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
-{
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-
-	/* IPS only exists on ULT machines and is tied to pipe A. */
-	if (!hsw_crtc_supports_ips(crtc))
-		return false;
-
-	if (!dev_priv->params.enable_ips)
-		return false;
-
-	if (crtc_state->pipe_bpp > 24)
-		return false;
-
-	/*
-	 * We compare against max which means we must take
-	 * the increased cdclk requirement into account when
-	 * calculating the new cdclk.
-	 *
-	 * Should measure whether using a lower cdclk w/o IPS
-	 */
-	if (IS_BROADWELL(dev_priv) &&
-	    crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
-		return false;
-
-	return true;
-}
-
-static int hsw_ips_compute_config(struct intel_atomic_state *state,
-				  struct intel_crtc *crtc)
-{
-	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-	struct intel_crtc_state *crtc_state =
-		intel_atomic_get_new_crtc_state(state, crtc);
-
-	crtc_state->ips_enabled = false;
-
-	if (!hsw_crtc_state_ips_capable(crtc_state))
-		return 0;
-
-	/*
-	 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
-	 * enabled and disabled dynamically based on package C states,
-	 * user space can't make reliable use of the CRCs, so let's just
-	 * completely disable it.
-	 */
-	if (crtc_state->crc_enabled)
-		return 0;
-
-	/* IPS should be fine as long as at least one plane is enabled. */
-	if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
-		return 0;
-
-	if (IS_BROADWELL(dev_priv)) {
-		const struct intel_cdclk_state *cdclk_state;
-
-		cdclk_state = intel_atomic_get_cdclk_state(state);
-		if (IS_ERR(cdclk_state))
-			return PTR_ERR(cdclk_state);
-
-		/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
-		if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
-			return 0;
-	}
-
-	crtc_state->ips_enabled = true;
-
-	return 0;
-}
-
 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
 {
 	const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 2315088a280d..b8455e2b2373 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -632,7 +632,6 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
 void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 			 struct intel_crtc_state *pipe_config);
 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
-bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
 enum intel_display_power_domain
 intel_aux_power_domain(struct intel_digital_port *dig_port);
-- 
2.34.1

[Intel-gfx] [PATCH 5/7] drm/i915: Extract hsw_ips_get_config()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Pull the IPS state readout into hsw_ips.c.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/hsw_ips.c       | 20 ++++++++++++++++++++
 drivers/gpu/drm/i915/display/hsw_ips.h       |  1 +
 drivers/gpu/drm/i915/display/intel_display.c | 14 +-------------
 3 files changed, 22 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c
index fb34ef615025..38014e0cc9ad 100644
--- a/drivers/gpu/drm/i915/display/hsw_ips.c
+++ b/drivers/gpu/drm/i915/display/hsw_ips.c
@@ -249,3 +249,23 @@ int hsw_ips_compute_config(struct intel_atomic_state *state,
 
 	return 0;
 }
+
+void hsw_ips_get_config(struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+
+	if (!hsw_crtc_supports_ips(crtc))
+		return;
+
+	if (IS_HASWELL(i915)) {
+		crtc_state->ips_enabled = intel_de_read(i915, IPS_CTL) & IPS_ENABLE;
+	} else {
+		/*
+		 * We cannot readout IPS state on broadwell, set to
+		 * true so we can set it to a defined state on first
+		 * commit.
+		 */
+		crtc_state->ips_enabled = true;
+	}
+}
diff --git a/drivers/gpu/drm/i915/display/hsw_ips.h b/drivers/gpu/drm/i915/display/hsw_ips.h
index d63bdef5100a..4564dee497d7 100644
--- a/drivers/gpu/drm/i915/display/hsw_ips.h
+++ b/drivers/gpu/drm/i915/display/hsw_ips.h
@@ -21,5 +21,6 @@ bool hsw_crtc_supports_ips(struct intel_crtc *crtc);
 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
 int hsw_ips_compute_config(struct intel_atomic_state *state,
 			   struct intel_crtc *crtc);
+void hsw_ips_get_config(struct intel_crtc_state *crtc_state);
 
 #endif /* __HSW_IPS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 134527981e2b..cdfee4ba1166 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4191,19 +4191,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
 			ilk_get_pfit_config(pipe_config);
 	}
 
-	if (hsw_crtc_supports_ips(crtc)) {
-		if (IS_HASWELL(dev_priv))
-			pipe_config->ips_enabled = intel_de_read(dev_priv,
-								 IPS_CTL) & IPS_ENABLE;
-		else {
-			/*
-			 * We cannot readout IPS state on broadwell, set to
-			 * true so we can set it to a defined state on first
-			 * commit.
-			 */
-			pipe_config->ips_enabled = true;
-		}
-	}
+	hsw_ips_get_config(pipe_config);
 
 	if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
 	    !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
-- 
2.34.1

[Intel-gfx] [PATCH 6/7] drm/i915: Fix IPS disable in intel_plane_disable_noatomic()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

IPS must be disabled prior to disabling the last plane (excluding
the cursor). Make the code do that instead of assuming the primary
plane would be the last one. This is probably 100% theoretical
as the BIOS should never light up the other planes anyway. But
no harm in making the code totally consistent.

Also let's update the ips_enabled flag in the crtc state afterwards
so that the first atomic commit has accurate information about
the state of IPS.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index cdfee4ba1166..401a339973bf 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -753,9 +753,11 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
 	crtc_state->data_rate[plane->id] = 0;
 	crtc_state->min_cdclk[plane->id] = 0;
 
-	if (plane->id == PLANE_PRIMARY &&
-	    hsw_ips_disable(crtc_state))
+	if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 &&
+	    hsw_ips_disable(crtc_state)) {
+		crtc_state->ips_enabled = false;
 		intel_crtc_wait_for_next_vblank(crtc);
+	}
 
 	/*
 	 * Vblank time updates from the shadow to live plane control register
-- 
2.34.1

[Intel-gfx] [PATCH 7/7] drm/i915: Consolidate all pre plane update vblank waits

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

There are several reasons why we might have to do a vblank wait
between some of the pre_plane_update() steps and the actual
plane update. Currently we do a vblank wait for each of those
individually. Let's consolidate things so that we just do a
single vblank wait at the end of the pre_plane_update() step.

Note that I don't think we should be hitting multiple vblank
waits here currently, at least in most cases. But no real
reason that couldn't happen in the future when some new
features/workarounds are introduced.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 35 ++++++++++++--------
 1 file changed, 22 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 401a339973bf..7c37c4355606 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -742,6 +742,7 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
 		to_intel_crtc_state(crtc->base.state);
 	struct intel_plane_state *plane_state =
 		to_intel_plane_state(plane->base.state);
+	bool need_vblank_wait = false;
 
 	drm_dbg_kms(&dev_priv->drm,
 		    "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
@@ -756,7 +757,7 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
 	if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 &&
 	    hsw_ips_disable(crtc_state)) {
 		crtc_state->ips_enabled = false;
-		intel_crtc_wait_for_next_vblank(crtc);
+		need_vblank_wait = true;
 	}
 
 	/*
@@ -770,7 +771,7 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
 	 */
 	if (HAS_GMCH(dev_priv) &&
 	    intel_set_memory_cxsr(dev_priv, false))
-		intel_crtc_wait_for_next_vblank(crtc);
+		need_vblank_wait = true;
 
 	/*
 	 * Gen2 reports pipe underruns whenever all planes are disabled.
@@ -779,6 +780,9 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
 	if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes)
 		intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
 
+	if (need_vblank_wait)
+		intel_crtc_wait_for_next_vblank(crtc);
+
 	intel_plane_disable_arm(plane, crtc_state);
 	intel_crtc_wait_for_next_vblank(crtc);
 }
@@ -1258,7 +1262,7 @@ static void intel_crtc_disable_flip_done(struct intel_atomic_state *state,
 	}
 }
 
-static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
+static bool intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
 					     struct intel_crtc *crtc)
 {
 	const struct intel_crtc_state *old_crtc_state =
@@ -1268,7 +1272,7 @@ static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
 	u8 update_planes = new_crtc_state->update_planes;
 	const struct intel_plane_state *old_plane_state;
 	struct intel_plane *plane;
-	bool need_vbl_wait = false;
+	bool need_vblank_wait = false;
 	int i;
 
 	for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
@@ -1281,12 +1285,11 @@ static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
 			 */
 			plane->async_flip(plane, old_crtc_state,
 					  old_plane_state, false);
-			need_vbl_wait = true;
+			need_vblank_wait = true;
 		}
 	}
 
-	if (need_vbl_wait)
-		intel_crtc_wait_for_next_vblank(crtc);
+	return need_vblank_wait;
 }
 
 static void intel_pre_plane_update(struct intel_atomic_state *state,
@@ -1298,14 +1301,15 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
 	const struct intel_crtc_state *new_crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	enum pipe pipe = crtc->pipe;
+	bool need_vblank_wait = false;
 
 	intel_psr_pre_plane_update(state, crtc);
 
 	if (hsw_ips_pre_update(state, crtc))
-		intel_crtc_wait_for_next_vblank(crtc);
+		need_vblank_wait = true;
 
 	if (intel_fbc_pre_update(state, crtc))
-		intel_crtc_wait_for_next_vblank(crtc);
+		need_vblank_wait = true;
 
 	if (!needs_async_flip_vtd_wa(old_crtc_state) &&
 	    needs_async_flip_vtd_wa(new_crtc_state))
@@ -1337,7 +1341,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
 	 */
 	if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
 	    new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
-		intel_crtc_wait_for_next_vblank(crtc);
+		need_vblank_wait = true;
 
 	/*
 	 * IVB workaround: must disable low power watermarks for at least
@@ -1348,7 +1352,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
 	 */
 	if (old_crtc_state->hw.active &&
 	    new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
-		intel_crtc_wait_for_next_vblank(crtc);
+		need_vblank_wait = true;
 
 	/*
 	 * If we're doing a modeset we don't need to do any
@@ -1389,8 +1393,13 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
 	 * WA for platforms where async address update enable bit
 	 * is double buffered and only latched at start of vblank.
 	 */
-	if (old_crtc_state->uapi.async_flip && !new_crtc_state->uapi.async_flip)
-		intel_crtc_async_flip_disable_wa(state, crtc);
+	if (old_crtc_state->uapi.async_flip &&
+	    !new_crtc_state->uapi.async_flip &&
+	    intel_crtc_async_flip_disable_wa(state, crtc))
+		need_vblank_wait = true;
+
+	if (need_vblank_wait)
+		intel_crtc_wait_for_next_vblank(crtc);
 }
 
 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
-- 
2.34.1

Re: [Intel-gfx] [PATCH 1/7] drm/i915: Move vblank waits out from IPS code

[Jani Nikula]

On Wed, 09 Feb 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Hoist the IPS related vblank waits one level up. Later on we'll
> want to consolidate all the potential pre-plane update vblank
> waits into one so we can't be hiding any in low level code.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 19 ++++++++++++-------
>  drivers/gpu/drm/i915/display/intel_display.h |  2 +-
>  2 files changed, 13 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 7f512f9e9e5c..5cc142a83ad7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -752,8 +752,9 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
>  	crtc_state->data_rate[plane->id] = 0;
>  	crtc_state->min_cdclk[plane->id] = 0;
>  
> -	if (plane->id == PLANE_PRIMARY)
> -		hsw_disable_ips(crtc_state);
> +	if (plane->id == PLANE_PRIMARY &&
> +	    hsw_disable_ips(crtc_state))
> +		intel_crtc_wait_for_next_vblank(crtc);
>  
>  	/*
>  	 * Vblank time updates from the shadow to live plane control register
> @@ -1127,14 +1128,15 @@ void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
>  	}
>  }
>  
> -void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
> +bool hsw_disable_ips(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> +	bool need_vblank_wait = false;
>  
>  	if (!crtc_state->ips_enabled)
> -		return;
> +		return need_vblank_wait;
>  
>  	if (IS_BROADWELL(dev_priv)) {
>  		drm_WARN_ON(dev,
> @@ -1153,7 +1155,9 @@ void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
>  	}
>  
>  	/* We need to wait for a vblank before we can disable the plane. */
> -	intel_crtc_wait_for_next_vblank(crtc);
> +	need_vblank_wait = true;
> +
> +	return need_vblank_wait;
>  }
>  
>  static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
> @@ -1426,8 +1430,9 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
>  
>  	intel_psr_pre_plane_update(state, crtc);
>  
> -	if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
> -		hsw_disable_ips(old_crtc_state);
> +	if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state) &&
> +	    hsw_disable_ips(old_crtc_state))
> +		intel_crtc_wait_for_next_vblank(crtc);
>  
>  	if (intel_fbc_pre_update(state, crtc))
>  		intel_crtc_wait_for_next_vblank(crtc);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index 457738aeee3e..8f9bec36898e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -634,7 +634,7 @@ void i9xx_crtc_clock_get(struct intel_crtc *crtc,
>  int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
>  bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
>  void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
> -void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
> +bool hsw_disable_ips(const struct intel_crtc_state *crtc_state);
>  enum intel_display_power_domain intel_port_to_power_domain(enum port port);
>  enum intel_display_power_domain
>  intel_aux_power_domain(struct intel_digital_port *dig_port);

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 2/7] drm/i915: Change IPS calling convention

[Jani Nikula]

On Wed, 09 Feb 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Follow the modern state+crtc calling convention for the IPS
> code as well.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 38 +++++++++++---------
>  1 file changed, 22 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 5cc142a83ad7..c5d30c683911 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1170,11 +1170,14 @@ static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
>  	 */
>  }
>  
> -static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
> -				       const struct intel_crtc_state *new_crtc_state)
> +static bool hsw_pre_update_disable_ips(struct intel_atomic_state *state,
> +				       struct intel_crtc *crtc)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> +	const struct intel_crtc_state *old_crtc_state =
> +		intel_atomic_get_old_crtc_state(state, crtc);
> +	const struct intel_crtc_state *new_crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
>  
>  	if (!old_crtc_state->ips_enabled)
>  		return false;
> @@ -1197,11 +1200,14 @@ static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_s
>  	return !new_crtc_state->ips_enabled;
>  }
>  
> -static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
> -				       const struct intel_crtc_state *new_crtc_state)
> +static bool hsw_post_update_enable_ips(struct intel_atomic_state *state,
> +				       struct intel_crtc *crtc)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> +	const struct intel_crtc_state *old_crtc_state =
> +		intel_atomic_get_old_crtc_state(state, crtc);
> +	const struct intel_crtc_state *new_crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
>  
>  	if (!new_crtc_state->ips_enabled)
>  		return false;
> @@ -1325,7 +1331,7 @@ static void intel_post_plane_update(struct intel_atomic_state *state,
>  	if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
>  		intel_update_watermarks(dev_priv);
>  
> -	if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
> +	if (hsw_post_update_enable_ips(state, crtc))
>  		hsw_enable_ips(new_crtc_state);
>  
>  	intel_fbc_post_update(state, crtc);
> @@ -1430,7 +1436,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
>  
>  	intel_psr_pre_plane_update(state, crtc);
>  
> -	if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state) &&
> +	if (hsw_pre_update_disable_ips(state, crtc) &&
>  	    hsw_disable_ips(old_crtc_state))
>  		intel_crtc_wait_for_next_vblank(crtc);
>  
> @@ -2812,12 +2818,12 @@ bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
>  	return true;
>  }
>  
> -static int hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
> +static int hsw_ips_compute_config(struct intel_atomic_state *state,
> +				  struct intel_crtc *crtc)
>  {
> -	struct drm_i915_private *dev_priv =
> -		to_i915(crtc_state->uapi.crtc->dev);
> -	struct intel_atomic_state *state =
> -		to_intel_atomic_state(crtc_state->uapi.state);
> +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> +	struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
>  
>  	crtc_state->ips_enabled = false;
>  
> @@ -5322,7 +5328,7 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
>  	}
>  
>  	if (HAS_IPS(dev_priv)) {
> -		ret = hsw_compute_ips_config(crtc_state);
> +		ret = hsw_ips_compute_config(state, crtc);
>  		if (ret)
>  			return ret;
>  	}

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 3/7] drm/i915: Hoover the IPS enable/disable calls into the pre/post update hooks

[Jani Nikula]

On Wed, 09 Feb 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> No reason the caller of the IPS pre/post update hooks should
> be responsible for the actual IPS enab/disable. Just pull those
> calls into the pre/post update hooks themselves. And while
> at it let's adjust the function naming a bit to have a consistent
> namespace.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Seems like some of the calling convention changes here should've been
put in the preceding patch, but not a big deal.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 46 +++++++++++++++-----
>  drivers/gpu/drm/i915/display/intel_display.h |  2 -
>  2 files changed, 34 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index c5d30c683911..08c59fdb24e5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -125,6 +125,7 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
>  static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
>  static void intel_modeset_setup_hw_state(struct drm_device *dev,
>  					 struct drm_modeset_acquire_ctx *ctx);
> +static bool hsw_ips_disable(const struct intel_crtc_state *crtc_state);
>  
>  /**
>   * intel_update_watermarks - update FIFO watermark values based on current modes
> @@ -753,7 +754,7 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
>  	crtc_state->min_cdclk[plane->id] = 0;
>  
>  	if (plane->id == PLANE_PRIMARY &&
> -	    hsw_disable_ips(crtc_state))
> +	    hsw_ips_disable(crtc_state))
>  		intel_crtc_wait_for_next_vblank(crtc);
>  
>  	/*
> @@ -1091,7 +1092,7 @@ static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
>  	intel_de_write(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
>  }
>  
> -void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
> +static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_device *dev = crtc->base.dev;
> @@ -1128,7 +1129,7 @@ void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
>  	}
>  }
>  
> -bool hsw_disable_ips(const struct intel_crtc_state *crtc_state)
> +static bool hsw_ips_disable(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_device *dev = crtc->base.dev;
> @@ -1170,8 +1171,8 @@ static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
>  	 */
>  }
>  
> -static bool hsw_pre_update_disable_ips(struct intel_atomic_state *state,
> -				       struct intel_crtc *crtc)
> +static bool hsw_ips_need_disable(struct intel_atomic_state *state,
> +				 struct intel_crtc *crtc)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>  	const struct intel_crtc_state *old_crtc_state =
> @@ -1200,8 +1201,20 @@ static bool hsw_pre_update_disable_ips(struct intel_atomic_state *state,
>  	return !new_crtc_state->ips_enabled;
>  }
>  
> -static bool hsw_post_update_enable_ips(struct intel_atomic_state *state,
> -				       struct intel_crtc *crtc)
> +static bool hsw_ips_pre_update(struct intel_atomic_state *state,
> +			       struct intel_crtc *crtc)
> +{
> +	const struct intel_crtc_state *old_crtc_state =
> +		intel_atomic_get_old_crtc_state(state, crtc);
> +
> +	if (!hsw_ips_need_disable(state, crtc))
> +		return false;
> +
> +	return hsw_ips_disable(old_crtc_state);
> +}
> +
> +static bool hsw_ips_need_enable(struct intel_atomic_state *state,
> +				struct intel_crtc *crtc)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>  	const struct intel_crtc_state *old_crtc_state =
> @@ -1237,6 +1250,18 @@ static bool hsw_post_update_enable_ips(struct intel_atomic_state *state,
>  	return !old_crtc_state->ips_enabled;
>  }
>  
> +static void hsw_ips_post_update(struct intel_atomic_state *state,
> +				struct intel_crtc *crtc)
> +{
> +	const struct intel_crtc_state *new_crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +
> +	if (!hsw_ips_need_enable(state, crtc))
> +		return;
> +
> +	hsw_ips_enable(new_crtc_state);
> +}
> +
>  static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> @@ -1331,9 +1356,7 @@ static void intel_post_plane_update(struct intel_atomic_state *state,
>  	if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
>  		intel_update_watermarks(dev_priv);
>  
> -	if (hsw_post_update_enable_ips(state, crtc))
> -		hsw_enable_ips(new_crtc_state);
> -
> +	hsw_ips_post_update(state, crtc);
>  	intel_fbc_post_update(state, crtc);
>  	intel_drrs_page_flip(state, crtc);
>  
> @@ -1436,8 +1459,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
>  
>  	intel_psr_pre_plane_update(state, crtc);
>  
> -	if (hsw_pre_update_disable_ips(state, crtc) &&
> -	    hsw_disable_ips(old_crtc_state))
> +	if (hsw_ips_pre_update(state, crtc))
>  		intel_crtc_wait_for_next_vblank(crtc);
>  
>  	if (intel_fbc_pre_update(state, crtc))
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index 8f9bec36898e..2315088a280d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -633,8 +633,6 @@ void i9xx_crtc_clock_get(struct intel_crtc *crtc,
>  			 struct intel_crtc_state *pipe_config);
>  int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
>  bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
> -void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
> -bool hsw_disable_ips(const struct intel_crtc_state *crtc_state);
>  enum intel_display_power_domain intel_port_to_power_domain(enum port port);
>  enum intel_display_power_domain
>  intel_aux_power_domain(struct intel_digital_port *dig_port);

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 4/7] drm/i915: Move the IPS code to its own file

[Jani Nikula]

On Wed, 09 Feb 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> IPS is a prety well isolated feature. Move the relevant code

*pretty

> to a separate file from polluting intel_display.c.
>
> I stuck to the hsw_ips since that's what the function were already
> using, and also to avoid confusion with the ILK
> "Intelligen Power Sharing"/intel_ips GPU turbo stuff.
>
> And let's also do the s/dev_priv/i915/ rename while touching
> most of the code.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/Makefile                |   1 +
>  drivers/gpu/drm/i915/display/hsw_ips.c       | 251 +++++++++++++++++++
>  drivers/gpu/drm/i915/display/hsw_ips.h       |  25 ++
>  drivers/gpu/drm/i915/display/intel_cdclk.c   |   1 +
>  drivers/gpu/drm/i915/display/intel_display.c | 239 +-----------------
>  drivers/gpu/drm/i915/display/intel_display.h |   1 -
>  6 files changed, 279 insertions(+), 239 deletions(-)
>  create mode 100644 drivers/gpu/drm/i915/display/hsw_ips.c
>  create mode 100644 drivers/gpu/drm/i915/display/hsw_ips.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index a26e6736bebb..226dbef5f64a 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -197,6 +197,7 @@ i915-y += gt/uc/intel_uc.o \
>  
>  # modesetting core code
>  i915-y += \
> +	display/hsw_ips.o \
>  	display/intel_atomic.o \
>  	display/intel_atomic_plane.o \
>  	display/intel_audio.o \
> diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c
> new file mode 100644
> index 000000000000..fb34ef615025
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/hsw_ips.c
> @@ -0,0 +1,251 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#include "hsw_ips.h"
> +#include "i915_drv.h"
> +#include "i915_reg.h"
> +#include "intel_de.h"
> +#include "intel_display_types.h"
> +#include "intel_pcode.h"
> +
> +static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> +
> +	if (!crtc_state->ips_enabled)
> +		return;
> +
> +	/*
> +	 * We can only enable IPS after we enable a plane and wait for a vblank
> +	 * This function is called from post_plane_update, which is run after
> +	 * a vblank wait.
> +	 */
> +	drm_WARN_ON(&i915->drm,
> +		    !(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
> +
> +	if (IS_BROADWELL(i915)) {
> +		drm_WARN_ON(&i915->drm,
> +			    snb_pcode_write(i915, DISPLAY_IPS_CONTROL,
> +					    IPS_ENABLE | IPS_PCODE_CONTROL));
> +		/*
> +		 * Quoting Art Runyan: "its not safe to expect any particular
> +		 * value in IPS_CTL bit 31 after enabling IPS through the
> +		 * mailbox." Moreover, the mailbox may return a bogus state,
> +		 * so we need to just enable it and continue on.
> +		 */
> +	} else {
> +		intel_de_write(i915, IPS_CTL, IPS_ENABLE);
> +		/*
> +		 * The bit only becomes 1 in the next vblank, so this wait here
> +		 * is essentially intel_wait_for_vblank. If we don't have this
> +		 * and don't wait for vblanks until the end of crtc_enable, then
> +		 * the HW state readout code will complain that the expected
> +		 * IPS_CTL value is not the one we read.
> +		 */
> +		if (intel_de_wait_for_set(i915, IPS_CTL, IPS_ENABLE, 50))
> +			drm_err(&i915->drm,
> +				"Timed out waiting for IPS enable\n");
> +	}
> +}
> +
> +bool hsw_ips_disable(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> +	bool need_vblank_wait = false;
> +
> +	if (!crtc_state->ips_enabled)
> +		return need_vblank_wait;
> +
> +	if (IS_BROADWELL(i915)) {
> +		drm_WARN_ON(&i915->drm,
> +			    snb_pcode_write(i915, DISPLAY_IPS_CONTROL, 0));
> +		/*
> +		 * Wait for PCODE to finish disabling IPS. The BSpec specified
> +		 * 42ms timeout value leads to occasional timeouts so use 100ms
> +		 * instead.
> +		 */
> +		if (intel_de_wait_for_clear(i915, IPS_CTL, IPS_ENABLE, 100))
> +			drm_err(&i915->drm,
> +				"Timed out waiting for IPS disable\n");
> +	} else {
> +		intel_de_write(i915, IPS_CTL, 0);
> +		intel_de_posting_read(i915, IPS_CTL);
> +	}
> +
> +	/* We need to wait for a vblank before we can disable the plane. */
> +	need_vblank_wait = true;
> +
> +	return need_vblank_wait;
> +}
> +
> +static bool hsw_ips_need_disable(struct intel_atomic_state *state,
> +				 struct intel_crtc *crtc)
> +{
> +	struct drm_i915_private *i915 = to_i915(state->base.dev);
> +	const struct intel_crtc_state *old_crtc_state =
> +		intel_atomic_get_old_crtc_state(state, crtc);
> +	const struct intel_crtc_state *new_crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +
> +	if (!old_crtc_state->ips_enabled)
> +		return false;
> +
> +	if (intel_crtc_needs_modeset(new_crtc_state))
> +		return true;
> +
> +	/*
> +	 * Workaround : Do not read or write the pipe palette/gamma data while
> +	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
> +	 *
> +	 * Disable IPS before we program the LUT.
> +	 */
> +	if (IS_HASWELL(i915) &&
> +	    (new_crtc_state->uapi.color_mgmt_changed ||
> +	     new_crtc_state->update_pipe) &&
> +	    new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
> +		return true;
> +
> +	return !new_crtc_state->ips_enabled;
> +}
> +
> +bool hsw_ips_pre_update(struct intel_atomic_state *state,
> +			struct intel_crtc *crtc)
> +{
> +	const struct intel_crtc_state *old_crtc_state =
> +		intel_atomic_get_old_crtc_state(state, crtc);
> +
> +	if (!hsw_ips_need_disable(state, crtc))
> +		return false;
> +
> +	return hsw_ips_disable(old_crtc_state);
> +}
> +
> +static bool hsw_ips_need_enable(struct intel_atomic_state *state,
> +				struct intel_crtc *crtc)
> +{
> +	struct drm_i915_private *i915 = to_i915(state->base.dev);
> +	const struct intel_crtc_state *old_crtc_state =
> +		intel_atomic_get_old_crtc_state(state, crtc);
> +	const struct intel_crtc_state *new_crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +
> +	if (!new_crtc_state->ips_enabled)
> +		return false;
> +
> +	if (intel_crtc_needs_modeset(new_crtc_state))
> +		return true;
> +
> +	/*
> +	 * Workaround : Do not read or write the pipe palette/gamma data while
> +	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
> +	 *
> +	 * Re-enable IPS after the LUT has been programmed.
> +	 */
> +	if (IS_HASWELL(i915) &&
> +	    (new_crtc_state->uapi.color_mgmt_changed ||
> +	     new_crtc_state->update_pipe) &&
> +	    new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
> +		return true;
> +
> +	/*
> +	 * We can't read out IPS on broadwell, assume the worst and
> +	 * forcibly enable IPS on the first fastset.
> +	 */
> +	if (new_crtc_state->update_pipe && old_crtc_state->inherited)
> +		return true;
> +
> +	return !old_crtc_state->ips_enabled;
> +}
> +
> +void hsw_ips_post_update(struct intel_atomic_state *state,
> +			 struct intel_crtc *crtc)
> +{
> +	const struct intel_crtc_state *new_crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +
> +	if (!hsw_ips_need_enable(state, crtc))
> +		return;
> +
> +	hsw_ips_enable(new_crtc_state);
> +}
> +
> +/* IPS only exists on ULT machines and is tied to pipe A. */
> +bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
> +{
> +	return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
> +}
> +
> +bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> +
> +	/* IPS only exists on ULT machines and is tied to pipe A. */
> +	if (!hsw_crtc_supports_ips(crtc))
> +		return false;
> +
> +	if (!i915->params.enable_ips)
> +		return false;
> +
> +	if (crtc_state->pipe_bpp > 24)
> +		return false;
> +
> +	/*
> +	 * We compare against max which means we must take
> +	 * the increased cdclk requirement into account when
> +	 * calculating the new cdclk.
> +	 *
> +	 * Should measure whether using a lower cdclk w/o IPS
> +	 */
> +	if (IS_BROADWELL(i915) &&
> +	    crtc_state->pixel_rate > i915->max_cdclk_freq * 95 / 100)
> +		return false;
> +
> +	return true;
> +}
> +
> +int hsw_ips_compute_config(struct intel_atomic_state *state,
> +			   struct intel_crtc *crtc)
> +{
> +	struct drm_i915_private *i915 = to_i915(state->base.dev);
> +	struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +
> +	crtc_state->ips_enabled = false;
> +
> +	if (!hsw_crtc_state_ips_capable(crtc_state))
> +		return 0;
> +
> +	/*
> +	 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
> +	 * enabled and disabled dynamically based on package C states,
> +	 * user space can't make reliable use of the CRCs, so let's just
> +	 * completely disable it.
> +	 */
> +	if (crtc_state->crc_enabled)
> +		return 0;
> +
> +	/* IPS should be fine as long as at least one plane is enabled. */
> +	if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
> +		return 0;
> +
> +	if (IS_BROADWELL(i915)) {
> +		const struct intel_cdclk_state *cdclk_state;
> +
> +		cdclk_state = intel_atomic_get_cdclk_state(state);
> +		if (IS_ERR(cdclk_state))
> +			return PTR_ERR(cdclk_state);
> +
> +		/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> +		if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
> +			return 0;
> +	}
> +
> +	crtc_state->ips_enabled = true;
> +
> +	return 0;
> +}
> diff --git a/drivers/gpu/drm/i915/display/hsw_ips.h b/drivers/gpu/drm/i915/display/hsw_ips.h
> new file mode 100644
> index 000000000000..d63bdef5100a
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/hsw_ips.h
> @@ -0,0 +1,25 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#ifndef __HSW_IPS_H__
> +#define __HSW_IPS_H__
> +
> +#include <linux/types.h>
> +
> +struct intel_atomic_state;
> +struct intel_crtc;
> +struct intel_crtc_state;
> +
> +bool hsw_ips_disable(const struct intel_crtc_state *crtc_state);
> +bool hsw_ips_pre_update(struct intel_atomic_state *state,
> +			struct intel_crtc *crtc);
> +void hsw_ips_post_update(struct intel_atomic_state *state,
> +			 struct intel_crtc *crtc);
> +bool hsw_crtc_supports_ips(struct intel_crtc *crtc);
> +bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
> +int hsw_ips_compute_config(struct intel_atomic_state *state,
> +			   struct intel_crtc *crtc);
> +
> +#endif /* __HSW_IPS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 4b140a014ca8..118ef391b560 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -23,6 +23,7 @@
>  
>  #include <linux/time.h>
>  
> +#include "hsw_ips.h"
>  #include "intel_atomic.h"
>  #include "intel_atomic_plane.h"
>  #include "intel_audio.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 08c59fdb24e5..134527981e2b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -74,6 +74,7 @@
>  
>  #include "g4x_dp.h"
>  #include "g4x_hdmi.h"
> +#include "hsw_ips.h"
>  #include "i915_drv.h"
>  #include "icl_dsi.h"
>  #include "intel_acpi.h"
> @@ -125,7 +126,6 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
>  static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
>  static void intel_modeset_setup_hw_state(struct drm_device *dev,
>  					 struct drm_modeset_acquire_ctx *ctx);
> -static bool hsw_ips_disable(const struct intel_crtc_state *crtc_state);
>  
>  /**
>   * intel_update_watermarks - update FIFO watermark values based on current modes
> @@ -1092,75 +1092,6 @@ static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
>  	intel_de_write(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
>  }
>  
> -static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)
> -{
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -	struct drm_device *dev = crtc->base.dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> -
> -	if (!crtc_state->ips_enabled)
> -		return;
> -
> -	/*
> -	 * We can only enable IPS after we enable a plane and wait for a vblank
> -	 * This function is called from post_plane_update, which is run after
> -	 * a vblank wait.
> -	 */
> -	drm_WARN_ON(dev, !(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
> -
> -	if (IS_BROADWELL(dev_priv)) {
> -		drm_WARN_ON(dev, snb_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
> -						 IPS_ENABLE | IPS_PCODE_CONTROL));
> -		/* Quoting Art Runyan: "its not safe to expect any particular
> -		 * value in IPS_CTL bit 31 after enabling IPS through the
> -		 * mailbox." Moreover, the mailbox may return a bogus state,
> -		 * so we need to just enable it and continue on.
> -		 */
> -	} else {
> -		intel_de_write(dev_priv, IPS_CTL, IPS_ENABLE);
> -		/* The bit only becomes 1 in the next vblank, so this wait here
> -		 * is essentially intel_wait_for_vblank. If we don't have this
> -		 * and don't wait for vblanks until the end of crtc_enable, then
> -		 * the HW state readout code will complain that the expected
> -		 * IPS_CTL value is not the one we read. */
> -		if (intel_de_wait_for_set(dev_priv, IPS_CTL, IPS_ENABLE, 50))
> -			drm_err(&dev_priv->drm,
> -				"Timed out waiting for IPS enable\n");
> -	}
> -}
> -
> -static bool hsw_ips_disable(const struct intel_crtc_state *crtc_state)
> -{
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -	struct drm_device *dev = crtc->base.dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> -	bool need_vblank_wait = false;
> -
> -	if (!crtc_state->ips_enabled)
> -		return need_vblank_wait;
> -
> -	if (IS_BROADWELL(dev_priv)) {
> -		drm_WARN_ON(dev,
> -			    snb_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
> -		/*
> -		 * Wait for PCODE to finish disabling IPS. The BSpec specified
> -		 * 42ms timeout value leads to occasional timeouts so use 100ms
> -		 * instead.
> -		 */
> -		if (intel_de_wait_for_clear(dev_priv, IPS_CTL, IPS_ENABLE, 100))
> -			drm_err(&dev_priv->drm,
> -				"Timed out waiting for IPS disable\n");
> -	} else {
> -		intel_de_write(dev_priv, IPS_CTL, 0);
> -		intel_de_posting_read(dev_priv, IPS_CTL);
> -	}
> -
> -	/* We need to wait for a vblank before we can disable the plane. */
> -	need_vblank_wait = true;
> -
> -	return need_vblank_wait;
> -}
> -
>  static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
>  {
>  	if (crtc->overlay)
> @@ -1171,97 +1102,6 @@ static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
>  	 */
>  }
>  
> -static bool hsw_ips_need_disable(struct intel_atomic_state *state,
> -				 struct intel_crtc *crtc)
> -{
> -	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> -	const struct intel_crtc_state *old_crtc_state =
> -		intel_atomic_get_old_crtc_state(state, crtc);
> -	const struct intel_crtc_state *new_crtc_state =
> -		intel_atomic_get_new_crtc_state(state, crtc);
> -
> -	if (!old_crtc_state->ips_enabled)
> -		return false;
> -
> -	if (intel_crtc_needs_modeset(new_crtc_state))
> -		return true;
> -
> -	/*
> -	 * Workaround : Do not read or write the pipe palette/gamma data while
> -	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
> -	 *
> -	 * Disable IPS before we program the LUT.
> -	 */
> -	if (IS_HASWELL(dev_priv) &&
> -	    (new_crtc_state->uapi.color_mgmt_changed ||
> -	     new_crtc_state->update_pipe) &&
> -	    new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
> -		return true;
> -
> -	return !new_crtc_state->ips_enabled;
> -}
> -
> -static bool hsw_ips_pre_update(struct intel_atomic_state *state,
> -			       struct intel_crtc *crtc)
> -{
> -	const struct intel_crtc_state *old_crtc_state =
> -		intel_atomic_get_old_crtc_state(state, crtc);
> -
> -	if (!hsw_ips_need_disable(state, crtc))
> -		return false;
> -
> -	return hsw_ips_disable(old_crtc_state);
> -}
> -
> -static bool hsw_ips_need_enable(struct intel_atomic_state *state,
> -				struct intel_crtc *crtc)
> -{
> -	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> -	const struct intel_crtc_state *old_crtc_state =
> -		intel_atomic_get_old_crtc_state(state, crtc);
> -	const struct intel_crtc_state *new_crtc_state =
> -		intel_atomic_get_new_crtc_state(state, crtc);
> -
> -	if (!new_crtc_state->ips_enabled)
> -		return false;
> -
> -	if (intel_crtc_needs_modeset(new_crtc_state))
> -		return true;
> -
> -	/*
> -	 * Workaround : Do not read or write the pipe palette/gamma data while
> -	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
> -	 *
> -	 * Re-enable IPS after the LUT has been programmed.
> -	 */
> -	if (IS_HASWELL(dev_priv) &&
> -	    (new_crtc_state->uapi.color_mgmt_changed ||
> -	     new_crtc_state->update_pipe) &&
> -	    new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
> -		return true;
> -
> -	/*
> -	 * We can't read out IPS on broadwell, assume the worst and
> -	 * forcibly enable IPS on the first fastset.
> -	 */
> -	if (new_crtc_state->update_pipe && old_crtc_state->inherited)
> -		return true;
> -
> -	return !old_crtc_state->ips_enabled;
> -}
> -
> -static void hsw_ips_post_update(struct intel_atomic_state *state,
> -				struct intel_crtc *crtc)
> -{
> -	const struct intel_crtc_state *new_crtc_state =
> -		intel_atomic_get_new_crtc_state(state, crtc);
> -
> -	if (!hsw_ips_need_enable(state, crtc))
> -		return;
> -
> -	hsw_ips_enable(new_crtc_state);
> -}
> -
>  static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> @@ -1938,12 +1778,6 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,
>  	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
>  }
>  
> -/* IPS only exists on ULT machines and is tied to pipe A. */
> -static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
> -{
> -	return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
> -}
> -
>  static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
>  					    enum pipe pipe, bool apply)
>  {
> @@ -2811,77 +2645,6 @@ static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
>  	}
>  }
>  
> -bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
> -{
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -
> -	/* IPS only exists on ULT machines and is tied to pipe A. */
> -	if (!hsw_crtc_supports_ips(crtc))
> -		return false;
> -
> -	if (!dev_priv->params.enable_ips)
> -		return false;
> -
> -	if (crtc_state->pipe_bpp > 24)
> -		return false;
> -
> -	/*
> -	 * We compare against max which means we must take
> -	 * the increased cdclk requirement into account when
> -	 * calculating the new cdclk.
> -	 *
> -	 * Should measure whether using a lower cdclk w/o IPS
> -	 */
> -	if (IS_BROADWELL(dev_priv) &&
> -	    crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
> -		return false;
> -
> -	return true;
> -}
> -
> -static int hsw_ips_compute_config(struct intel_atomic_state *state,
> -				  struct intel_crtc *crtc)
> -{
> -	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> -	struct intel_crtc_state *crtc_state =
> -		intel_atomic_get_new_crtc_state(state, crtc);
> -
> -	crtc_state->ips_enabled = false;
> -
> -	if (!hsw_crtc_state_ips_capable(crtc_state))
> -		return 0;
> -
> -	/*
> -	 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
> -	 * enabled and disabled dynamically based on package C states,
> -	 * user space can't make reliable use of the CRCs, so let's just
> -	 * completely disable it.
> -	 */
> -	if (crtc_state->crc_enabled)
> -		return 0;
> -
> -	/* IPS should be fine as long as at least one plane is enabled. */
> -	if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
> -		return 0;
> -
> -	if (IS_BROADWELL(dev_priv)) {
> -		const struct intel_cdclk_state *cdclk_state;
> -
> -		cdclk_state = intel_atomic_get_cdclk_state(state);
> -		if (IS_ERR(cdclk_state))
> -			return PTR_ERR(cdclk_state);
> -
> -		/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> -		if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
> -			return 0;
> -	}
> -
> -	crtc_state->ips_enabled = true;
> -
> -	return 0;
> -}
> -
>  static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
>  {
>  	const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index 2315088a280d..b8455e2b2373 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -632,7 +632,6 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
>  void i9xx_crtc_clock_get(struct intel_crtc *crtc,
>  			 struct intel_crtc_state *pipe_config);
>  int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
> -bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
>  enum intel_display_power_domain intel_port_to_power_domain(enum port port);
>  enum intel_display_power_domain
>  intel_aux_power_domain(struct intel_digital_port *dig_port);

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 5/7] drm/i915: Extract hsw_ips_get_config()

[Jani Nikula]

On Wed, 09 Feb 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Pull the IPS state readout into hsw_ips.c.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/hsw_ips.c       | 20 ++++++++++++++++++++
>  drivers/gpu/drm/i915/display/hsw_ips.h       |  1 +
>  drivers/gpu/drm/i915/display/intel_display.c | 14 +-------------
>  3 files changed, 22 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c
> index fb34ef615025..38014e0cc9ad 100644
> --- a/drivers/gpu/drm/i915/display/hsw_ips.c
> +++ b/drivers/gpu/drm/i915/display/hsw_ips.c
> @@ -249,3 +249,23 @@ int hsw_ips_compute_config(struct intel_atomic_state *state,
>  
>  	return 0;
>  }
> +
> +void hsw_ips_get_config(struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> +
> +	if (!hsw_crtc_supports_ips(crtc))
> +		return;
> +
> +	if (IS_HASWELL(i915)) {
> +		crtc_state->ips_enabled = intel_de_read(i915, IPS_CTL) & IPS_ENABLE;
> +	} else {
> +		/*
> +		 * We cannot readout IPS state on broadwell, set to
> +		 * true so we can set it to a defined state on first
> +		 * commit.
> +		 */
> +		crtc_state->ips_enabled = true;
> +	}
> +}
> diff --git a/drivers/gpu/drm/i915/display/hsw_ips.h b/drivers/gpu/drm/i915/display/hsw_ips.h
> index d63bdef5100a..4564dee497d7 100644
> --- a/drivers/gpu/drm/i915/display/hsw_ips.h
> +++ b/drivers/gpu/drm/i915/display/hsw_ips.h
> @@ -21,5 +21,6 @@ bool hsw_crtc_supports_ips(struct intel_crtc *crtc);
>  bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
>  int hsw_ips_compute_config(struct intel_atomic_state *state,
>  			   struct intel_crtc *crtc);
> +void hsw_ips_get_config(struct intel_crtc_state *crtc_state);
>  
>  #endif /* __HSW_IPS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 134527981e2b..cdfee4ba1166 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4191,19 +4191,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
>  			ilk_get_pfit_config(pipe_config);
>  	}
>  
> -	if (hsw_crtc_supports_ips(crtc)) {
> -		if (IS_HASWELL(dev_priv))
> -			pipe_config->ips_enabled = intel_de_read(dev_priv,
> -								 IPS_CTL) & IPS_ENABLE;
> -		else {
> -			/*
> -			 * We cannot readout IPS state on broadwell, set to
> -			 * true so we can set it to a defined state on first
> -			 * commit.
> -			 */
> -			pipe_config->ips_enabled = true;
> -		}
> -	}
> +	hsw_ips_get_config(pipe_config);
>  
>  	if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
>  	    !transcoder_is_dsi(pipe_config->cpu_transcoder)) {

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 7/7] drm/i915: Consolidate all pre plane update vblank waits

[Jani Nikula]

On Wed, 09 Feb 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> There are several reasons why we might have to do a vblank wait
> between some of the pre_plane_update() steps and the actual
> plane update. Currently we do a vblank wait for each of those
> individually. Let's consolidate things so that we just do a
> single vblank wait at the end of the pre_plane_update() step.
>
> Note that I don't think we should be hitting multiple vblank
> waits here currently, at least in most cases. But no real
> reason that couldn't happen in the future when some new
> features/workarounds are introduced.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 35 ++++++++++++--------
>  1 file changed, 22 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 401a339973bf..7c37c4355606 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -742,6 +742,7 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
>  		to_intel_crtc_state(crtc->base.state);
>  	struct intel_plane_state *plane_state =
>  		to_intel_plane_state(plane->base.state);
> +	bool need_vblank_wait = false;
>  
>  	drm_dbg_kms(&dev_priv->drm,
>  		    "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
> @@ -756,7 +757,7 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
>  	if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 &&
>  	    hsw_ips_disable(crtc_state)) {
>  		crtc_state->ips_enabled = false;
> -		intel_crtc_wait_for_next_vblank(crtc);
> +		need_vblank_wait = true;
>  	}
>  
>  	/*
> @@ -770,7 +771,7 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
>  	 */
>  	if (HAS_GMCH(dev_priv) &&
>  	    intel_set_memory_cxsr(dev_priv, false))
> -		intel_crtc_wait_for_next_vblank(crtc);
> +		need_vblank_wait = true;
>  
>  	/*
>  	 * Gen2 reports pipe underruns whenever all planes are disabled.
> @@ -779,6 +780,9 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
>  	if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes)
>  		intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
>  
> +	if (need_vblank_wait)
> +		intel_crtc_wait_for_next_vblank(crtc);
> +
>  	intel_plane_disable_arm(plane, crtc_state);
>  	intel_crtc_wait_for_next_vblank(crtc);
>  }
> @@ -1258,7 +1262,7 @@ static void intel_crtc_disable_flip_done(struct intel_atomic_state *state,
>  	}
>  }
>  
> -static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
> +static bool intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
>  					     struct intel_crtc *crtc)
>  {
>  	const struct intel_crtc_state *old_crtc_state =
> @@ -1268,7 +1272,7 @@ static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
>  	u8 update_planes = new_crtc_state->update_planes;
>  	const struct intel_plane_state *old_plane_state;
>  	struct intel_plane *plane;
> -	bool need_vbl_wait = false;
> +	bool need_vblank_wait = false;
>  	int i;
>  
>  	for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
> @@ -1281,12 +1285,11 @@ static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
>  			 */
>  			plane->async_flip(plane, old_crtc_state,
>  					  old_plane_state, false);
> -			need_vbl_wait = true;
> +			need_vblank_wait = true;
>  		}
>  	}
>  
> -	if (need_vbl_wait)
> -		intel_crtc_wait_for_next_vblank(crtc);
> +	return need_vblank_wait;
>  }
>  
>  static void intel_pre_plane_update(struct intel_atomic_state *state,
> @@ -1298,14 +1301,15 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
>  	const struct intel_crtc_state *new_crtc_state =
>  		intel_atomic_get_new_crtc_state(state, crtc);
>  	enum pipe pipe = crtc->pipe;
> +	bool need_vblank_wait = false;
>  
>  	intel_psr_pre_plane_update(state, crtc);
>  
>  	if (hsw_ips_pre_update(state, crtc))
> -		intel_crtc_wait_for_next_vblank(crtc);
> +		need_vblank_wait = true;
>  
>  	if (intel_fbc_pre_update(state, crtc))
> -		intel_crtc_wait_for_next_vblank(crtc);
> +		need_vblank_wait = true;
>  
>  	if (!needs_async_flip_vtd_wa(old_crtc_state) &&
>  	    needs_async_flip_vtd_wa(new_crtc_state))
> @@ -1337,7 +1341,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
>  	 */
>  	if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
>  	    new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
> -		intel_crtc_wait_for_next_vblank(crtc);
> +		need_vblank_wait = true;
>  
>  	/*
>  	 * IVB workaround: must disable low power watermarks for at least
> @@ -1348,7 +1352,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
>  	 */
>  	if (old_crtc_state->hw.active &&
>  	    new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
> -		intel_crtc_wait_for_next_vblank(crtc);
> +		need_vblank_wait = true;
>  
>  	/*
>  	 * If we're doing a modeset we don't need to do any
> @@ -1389,8 +1393,13 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
>  	 * WA for platforms where async address update enable bit
>  	 * is double buffered and only latched at start of vblank.
>  	 */
> -	if (old_crtc_state->uapi.async_flip && !new_crtc_state->uapi.async_flip)
> -		intel_crtc_async_flip_disable_wa(state, crtc);
> +	if (old_crtc_state->uapi.async_flip &&
> +	    !new_crtc_state->uapi.async_flip &&
> +	    intel_crtc_async_flip_disable_wa(state, crtc))
> +		need_vblank_wait = true;
> +
> +	if (need_vblank_wait)
> +		intel_crtc_wait_for_next_vblank(crtc);
>  }
>  
>  static void intel_crtc_disable_planes(struct intel_atomic_state *state,

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 6/7] drm/i915: Fix IPS disable in intel_plane_disable_noatomic()

[Jani Nikula]

On Wed, 09 Feb 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> IPS must be disabled prior to disabling the last plane (excluding
> the cursor). Make the code do that instead of assuming the primary
> plane would be the last one. This is probably 100% theoretical
> as the BIOS should never light up the other planes anyway. But
> no harm in making the code totally consistent.
>
> Also let's update the ips_enabled flag in the crtc state afterwards
> so that the first atomic commit has accurate information about
> the state of IPS.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

I admit, didn't have the time to dig into the details here now, so let's
just say, seems reasonable,

Acked-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index cdfee4ba1166..401a339973bf 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -753,9 +753,11 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
>  	crtc_state->data_rate[plane->id] = 0;
>  	crtc_state->min_cdclk[plane->id] = 0;
>  
> -	if (plane->id == PLANE_PRIMARY &&
> -	    hsw_ips_disable(crtc_state))
> +	if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 &&
> +	    hsw_ips_disable(crtc_state)) {
> +		crtc_state->ips_enabled = false;
>  		intel_crtc_wait_for_next_vblank(crtc);
> +	}
>  
>  	/*
>  	 * Vblank time updates from the shadow to live plane control register

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/7] drm/i915: Move vblank waits out from IPS code

[Patchwork]

== Series Details ==

Series: series starting with [1/7] drm/i915: Move vblank waits out from IPS code
URL   : https://patchwork.freedesktop.org/series/99898/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
07fcb18e1bb8 drm/i915: Move vblank waits out from IPS code
38cc565cd61b drm/i915: Change IPS calling convention
ec0006d584e0 drm/i915: Hoover the IPS enable/disable calls into the pre/post update hooks
8f2e708760bd drm/i915: Move the IPS code to its own file
-:35: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#35: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 572 lines checked
79ae7f91c747 drm/i915: Extract hsw_ips_get_config()
57d28de511dc drm/i915: Fix IPS disable in intel_plane_disable_noatomic()
b79f7b4e43e9 drm/i915: Consolidate all pre plane update vblank waits

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/7] drm/i915: Move vblank waits out from IPS code

[Patchwork]

== Series Details ==

Series: series starting with [1/7] drm/i915: Move vblank waits out from IPS code
URL   : https://patchwork.freedesktop.org/series/99898/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/7] drm/i915: Move vblank waits out from IPS code

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 3964 bytes --]

== Series Details ==

Series: series starting with [1/7] drm/i915: Move vblank waits out from IPS code
URL   : https://patchwork.freedesktop.org/series/99898/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11207 -> Patchwork_22221
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/index.html

Participating hosts (45 -> 43)
------------------------------

  Additional (1): bat-rpls-1 
  Missing    (3): fi-bsw-cyan fi-icl-u2 shard-tglu 

Known issues
------------

  Here are the changes found in Patchwork_22221 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_flink_basic@bad-flink:
    - fi-skl-6600u:       [PASS][1] -> [INCOMPLETE][2] ([i915#4547])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html

  * igt@i915_selftest@live@hangcheck:
    - bat-dg1-6:          [PASS][3] -> [DMESG-FAIL][4] ([i915#4494] / [i915#4957])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
    - fi-hsw-4770:        [PASS][5] -> [INCOMPLETE][6] ([i915#3303])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html

  * igt@runner@aborted:
    - fi-hsw-4770:        NOTRUN -> [FAIL][7] ([fdo#109271] / [i915#1436] / [i915#4312])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/fi-hsw-4770/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@requests:
    - fi-kbl-soraka:      [INCOMPLETE][8] -> [PASS][9]
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/fi-kbl-soraka/igt@i915_selftest@live@requests.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/fi-kbl-soraka/igt@i915_selftest@live@requests.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
  [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
  [i915#4897]: https://gitlab.freedesktop.org/drm/intel/issues/4897
  [i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957


Build changes
-------------

  * Linux: CI_DRM_11207 -> Patchwork_22221

  CI-20190529: 20190529
  CI_DRM_11207: 0d650d738ee924dc0c367ff1f33c61237a635933 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6342: 1bd167a3af9e8f6168ac89c64c64b929694d9be7 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_22221: b79f7b4e43e9130b388c41b2bae4dd01498d9b53 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

b79f7b4e43e9 drm/i915: Consolidate all pre plane update vblank waits
57d28de511dc drm/i915: Fix IPS disable in intel_plane_disable_noatomic()
79ae7f91c747 drm/i915: Extract hsw_ips_get_config()
8f2e708760bd drm/i915: Move the IPS code to its own file
ec0006d584e0 drm/i915: Hoover the IPS enable/disable calls into the pre/post update hooks
38cc565cd61b drm/i915: Change IPS calling convention
07fcb18e1bb8 drm/i915: Move vblank waits out from IPS code

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/index.html

[-- Attachment #2: Type: text/html, Size: 4649 bytes --]

Re: [Intel-gfx] [PATCH 7/7] drm/i915: Consolidate all pre plane update vblank waits

[Murthy, Arun R]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, February 9, 2022 5:05 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 7/7] drm/i915: Consolidate all pre plane update
> vblank waits
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> There are several reasons why we might have to do a vblank wait between
> some of the pre_plane_update() steps and the actual plane update.
> Currently we do a vblank wait for each of those individually. Let's consolidate
> things so that we just do a single vblank wait at the end of the
> pre_plane_update() step.
> 
> Note that I don't think we should be hitting multiple vblank waits here
> currently, at least in most cases. But no real reason that couldn't happen in
> the future when some new features/workarounds are introduced.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---

Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>


Thanks and Regards,
Arun R Murthy
--------------------

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/7] drm/i915: Move vblank waits out from IPS code

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 30295 bytes --]

== Series Details ==

Series: series starting with [1/7] drm/i915: Move vblank waits out from IPS code
URL   : https://patchwork.freedesktop.org/series/99898/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11207_full -> Patchwork_22221_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_22221_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22221_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (11 -> 12)
------------------------------

  Additional (1): shard-rkl 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_22221_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_plane_cursor@pipe-a-viewport-size-64:
    - shard-snb:          [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-snb4/igt@kms_plane_cursor@pipe-a-viewport-size-64.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-snb6/igt@kms_plane_cursor@pipe-a-viewport-size-64.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@syncobj_timeline@invalid-transfer-non-existent-point:
    - {shard-rkl}:        NOTRUN -> [DMESG-WARN][3]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-rkl-2/igt@syncobj_timeline@invalid-transfer-non-existent-point.html

  
Known issues
------------

  Here are the changes found in Patchwork_22221_full that come from known issues:

### CI changes ###

#### Issues hit ####

  * boot:
    - shard-glk:          ([PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28]) -> ([PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [FAIL][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53]) ([i915#4392])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk1/boot.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk7/boot.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk6/boot.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk6/boot.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk6/boot.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk6/boot.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk5/boot.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk5/boot.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk5/boot.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk4/boot.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk4/boot.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk3/boot.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk3/boot.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk2/boot.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk2/boot.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk2/boot.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk1/boot.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk1/boot.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk9/boot.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk9/boot.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk9/boot.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk8/boot.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk8/boot.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk8/boot.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk7/boot.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-glk9/boot.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-glk1/boot.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-glk1/boot.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-glk1/boot.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-glk2/boot.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-glk2/boot.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-glk2/boot.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-glk3/boot.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-glk3/boot.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-glk3/boot.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-glk4/boot.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-glk4/boot.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-glk4/boot.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-glk5/boot.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-glk5/boot.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-glk5/boot.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-glk6/boot.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-glk6/boot.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-glk6/boot.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-glk7/boot.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-glk7/boot.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-glk7/boot.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-glk8/boot.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-glk8/boot.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-glk9/boot.html

  

### IGT changes ###

#### Issues hit ####

  * igt@feature_discovery@psr2:
    - shard-iclb:         NOTRUN -> [SKIP][54] ([i915#658])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-iclb1/igt@feature_discovery@psr2.html

  * igt@gem_ctx_isolation@preservation-s3@vcs0:
    - shard-kbl:          [PASS][55] -> [DMESG-WARN][56] ([i915#180]) +5 similar issues
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@vcs0.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-kbl1/igt@gem_ctx_isolation@preservation-s3@vcs0.html

  * igt@gem_eio@in-flight-suspend:
    - shard-apl:          [PASS][57] -> [DMESG-WARN][58] ([i915#180]) +1 similar issue
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-apl4/igt@gem_eio@in-flight-suspend.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-apl3/igt@gem_eio@in-flight-suspend.html

  * igt@gem_exec_balancer@parallel-contexts:
    - shard-iclb:         NOTRUN -> [DMESG-WARN][59] ([i915#5076])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-iclb1/igt@gem_exec_balancer@parallel-contexts.html

  * igt@gem_exec_balancer@parallel-ordering:
    - shard-iclb:         NOTRUN -> [SKIP][60] ([i915#4525])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-iclb8/igt@gem_exec_balancer@parallel-ordering.html

  * igt@gem_exec_balancer@parallel-out-fence:
    - shard-kbl:          NOTRUN -> [DMESG-WARN][61] ([i915#5076])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-kbl7/igt@gem_exec_balancer@parallel-out-fence.html

  * igt@gem_exec_capture@pi@rcs0:
    - shard-skl:          [PASS][62] -> [INCOMPLETE][63] ([i915#4547])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-skl2/igt@gem_exec_capture@pi@rcs0.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-skl2/igt@gem_exec_capture@pi@rcs0.html

  * igt@gem_exec_capture@pi@vcs1:
    - shard-tglb:         [PASS][64] -> [INCOMPLETE][65] ([i915#3371])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-tglb5/igt@gem_exec_capture@pi@vcs1.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-tglb6/igt@gem_exec_capture@pi@vcs1.html

  * igt@gem_exec_fair@basic-flow@rcs0:
    - shard-tglb:         [PASS][66] -> [FAIL][67] ([i915#2842])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-tglb6/igt@gem_exec_fair@basic-flow@rcs0.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-tglb6/igt@gem_exec_fair@basic-flow@rcs0.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-kbl:          NOTRUN -> [FAIL][68] ([i915#2842])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-kbl7/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
    - shard-iclb:         NOTRUN -> [FAIL][69] ([i915#2842])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-iclb1/igt@gem_exec_fair@basic-pace@vcs1.html

  * igt@gem_exec_fair@basic-pace@vecs0:
    - shard-kbl:          [PASS][70] -> [FAIL][71] ([i915#2842]) +2 similar issues
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-kbl7/igt@gem_exec_fair@basic-pace@vecs0.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-kbl7/igt@gem_exec_fair@basic-pace@vecs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-iclb:         [PASS][72] -> [FAIL][73] ([i915#2849])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-iclb2/igt@gem_exec_fair@basic-throttle@rcs0.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-iclb7/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_exec_schedule@smoketest-all:
    - shard-glk:          [PASS][74] -> [DMESG-WARN][75] ([i915#118])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk5/igt@gem_exec_schedule@smoketest-all.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-glk2/igt@gem_exec_schedule@smoketest-all.html

  * igt@gem_exec_schedule@submit-early-slice@vcs0:
    - shard-skl:          NOTRUN -> [INCOMPLETE][76] ([i915#3797])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-skl3/igt@gem_exec_schedule@submit-early-slice@vcs0.html

  * igt@gem_lmem_swapping@heavy-random:
    - shard-kbl:          NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#4613])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-kbl4/igt@gem_lmem_swapping@heavy-random.html

  * igt@gem_lmem_swapping@heavy-verify-random:
    - shard-apl:          NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#4613])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-apl2/igt@gem_lmem_swapping@heavy-verify-random.html

  * igt@gem_lmem_swapping@smem-oom:
    - shard-iclb:         NOTRUN -> [SKIP][79] ([i915#4613])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-iclb8/igt@gem_lmem_swapping@smem-oom.html

  * igt@gem_lmem_swapping@verify:
    - shard-skl:          NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#4613])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-skl7/igt@gem_lmem_swapping@verify.html

  * igt@gem_pread@exhaustion:
    - shard-tglb:         NOTRUN -> [WARN][81] ([i915#2658])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-tglb7/igt@gem_pread@exhaustion.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-iclb:         NOTRUN -> [WARN][82] ([i915#2658])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-iclb7/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_pxp@verify-pxp-execution-after-suspend-resume:
    - shard-iclb:         NOTRUN -> [SKIP][83] ([i915#4270]) +1 similar issue
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-iclb8/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html

  * igt@gem_render_copy@yf-tiled-to-vebox-y-tiled:
    - shard-iclb:         NOTRUN -> [SKIP][84] ([i915#768])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-iclb1/igt@gem_render_copy@yf-tiled-to-vebox-y-tiled.html

  * igt@gem_userptr_blits@unsync-unmap-cycles:
    - shard-iclb:         NOTRUN -> [SKIP][85] ([i915#3297])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-iclb8/igt@gem_userptr_blits@unsync-unmap-cycles.html

  * igt@gem_userptr_blits@vma-merge:
    - shard-skl:          NOTRUN -> [FAIL][86] ([i915#3318])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-skl7/igt@gem_userptr_blits@vma-merge.html

  * igt@gen3_render_linear_blits:
    - shard-iclb:         NOTRUN -> [SKIP][87] ([fdo#109289])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-iclb1/igt@gen3_render_linear_blits.html

  * igt@gen9_exec_parse@bb-start-out:
    - shard-iclb:         NOTRUN -> [SKIP][88] ([i915#2856])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-iclb8/igt@gen9_exec_parse@bb-start-out.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-iclb:         [PASS][89] -> [FAIL][90] ([i915#454])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-iclb5/igt@i915_pm_dc@dc6-psr.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-iclb6/igt@i915_pm_dc@dc6-psr.html

  * igt@kms_async_flips@alternate-sync-async-flip:
    - shard-glk:          [PASS][91] -> [FAIL][92] ([i915#2521])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk8/igt@kms_async_flips@alternate-sync-async-flip.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-glk1/igt@kms_async_flips@alternate-sync-async-flip.html

  * igt@kms_atomic_transition@modeset-transition-fencing:
    - shard-snb:          NOTRUN -> [SKIP][93] ([fdo#109271])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-snb2/igt@kms_atomic_transition@modeset-transition-fencing.html

  * igt@kms_atomic_transition@plane-all-modeset-transition:
    - shard-iclb:         NOTRUN -> [SKIP][94] ([i915#1769])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-iclb7/igt@kms_atomic_transition@plane-all-modeset-transition.html

  * igt@kms_big_fb@linear-32bpp-rotate-90:
    - shard-iclb:         NOTRUN -> [SKIP][95] ([fdo#110725] / [fdo#111614]) +1 similar issue
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-iclb8/igt@kms_big_fb@linear-32bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-skl:          NOTRUN -> [SKIP][96] ([fdo#109271] / [i915#3777]) +1 similar issue
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-skl7/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
    - shard-skl:          NOTRUN -> [FAIL][97] ([i915#3743])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-skl7/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@yf-tiled-8bpp-rotate-270:
    - shard-iclb:         NOTRUN -> [SKIP][98] ([fdo#110723])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-iclb8/igt@kms_big_fb@yf-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
    - shard-tglb:         NOTRUN -> [SKIP][99] ([fdo#111615])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-tglb7/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-kbl:          NOTRUN -> [SKIP][100] ([fdo#109271] / [i915#3777])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-kbl4/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_mc_ccs:
    - shard-apl:          NOTRUN -> [SKIP][101] ([fdo#109271] / [i915#3886])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-apl2/igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
    - shard-iclb:         NOTRUN -> [SKIP][102] ([fdo#109278] / [i915#3886]) +3 similar issues
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-iclb8/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs_cc:
    - shard-kbl:          NOTRUN -> [SKIP][103] ([fdo#109271] / [i915#3886]) +2 similar issues
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-kbl7/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
    - shard-skl:          NOTRUN -> [SKIP][104] ([fdo#109271] / [i915#3886]) +1 similar issue
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-skl7/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_chamelium@dp-hpd-enable-disable-mode:
    - shard-tglb:         NOTRUN -> [SKIP][105] ([fdo#109284] / [fdo#111827]) +1 similar issue
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-tglb7/igt@kms_chamelium@dp-hpd-enable-disable-mode.html

  * igt@kms_chamelium@dp-hpd-storm-disable:
    - shard-apl:          NOTRUN -> [SKIP][106] ([fdo#109271] / [fdo#111827]) +3 similar issues
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-apl3/igt@kms_chamelium@dp-hpd-storm-disable.html

  * igt@kms_chamelium@vga-hpd-enable-disable-mode:
    - shard-kbl:          NOTRUN -> [SKIP][107] ([fdo#109271] / [fdo#111827]) +9 similar issues
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-kbl7/igt@kms_chamelium@vga-hpd-enable-disable-mode.html

  * igt@kms_color_chamelium@pipe-a-ctm-red-to-blue:
    - shard-iclb:         NOTRUN -> [SKIP][108] ([fdo#109284] / [fdo#111827]) +5 similar issues
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-iclb7/igt@kms_color_chamelium@pipe-a-ctm-red-to-blue.html

  * igt@kms_color_chamelium@pipe-d-ctm-blue-to-red:
    - shard-iclb:         NOTRUN -> [SKIP][109] ([fdo#109278] / [fdo#109284] / [fdo#111827])
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-iclb8/igt@kms_color_chamelium@pipe-d-ctm-blue-to-red.html

  * igt@kms_color_chamelium@pipe-d-ctm-red-to-blue:
    - shard-skl:          NOTRUN -> [SKIP][110] ([fdo#109271] / [fdo#111827]) +3 similar issues
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-skl7/igt@kms_color_chamelium@pipe-d-ctm-red-to-blue.html

  * igt@kms_content_protection@content_type_change:
    - shard-iclb:         NOTRUN -> [SKIP][111] ([fdo#109300] / [fdo#111066])
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-iclb8/igt@kms_content_protection@content_type_change.html

  * igt@kms_cursor_crc@pipe-a-cursor-32x32-random:
    - shard-iclb:         NOTRUN -> [SKIP][112] ([fdo#109278]) +17 similar issues
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-iclb8/igt@kms_cursor_crc@pipe-a-cursor-32x32-random.html

  * igt@kms_cursor_crc@pipe-a-cursor-512x512-sliding:
    - shard-iclb:         NOTRUN -> [SKIP][113] ([fdo#109278] / [fdo#109279]) +2 similar issues
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-iclb7/igt@kms_cursor_crc@pipe-a-cursor-512x512-sliding.html

  * igt@kms_cursor_crc@pipe-c-cursor-32x10-onscreen:
    - shard-kbl:          NOTRUN -> [SKIP][114] ([fdo#109271]) +71 similar issues
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-kbl7/igt@kms_cursor_crc@pipe-c-cursor-32x10-onscreen.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
    - shard-iclb:         NOTRUN -> [SKIP][115] ([fdo#109274] / [fdo#109278]) +3 similar issues
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-iclb8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions:
    - shard-tglb:         NOTRUN -> [SKIP][116] ([fdo#109274] / [fdo#111825])
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-tglb7/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-skl:          [PASS][117] -> [FAIL][118] ([i915#2346])
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_flip@2x-blocking-wf_vblank:
    - shard-iclb:         NOTRUN -> [SKIP][119] ([fdo#109274]) +2 similar issues
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-iclb8/igt@kms_flip@2x-blocking-wf_vblank.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
    - shard-iclb:         [PASS][120] -> [SKIP][121] ([i915#3701])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-iclb3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt:
    - shard-skl:          NOTRUN -> [SKIP][122] ([fdo#109271]) +32 similar issues
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-skl7/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-pgflip-blt:
    - shard-apl:          NOTRUN -> [SKIP][123] ([fdo#109271]) +38 similar issues
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-apl3/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt:
    - shard-tglb:         NOTRUN -> [SKIP][124] ([fdo#109280] / [fdo#111825]) +2 similar issues
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-wc:
    - shard-iclb:         NOTRUN -> [SKIP][125] ([fdo#109280]) +9 similar issues
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-skl:          [PASS][126] -> [FAIL][127] ([i915#1188])
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-skl3/igt@kms_hdr@bpc-switch-dpms.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-skl3/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_hdr@static-swap:
    - shard-iclb:         NOTRUN -> [SKIP][128] ([i915#1187])
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-iclb7/igt@kms_hdr@static-swap.html

  * igt@kms_hdr@static-toggle-suspend:
    - shard-tglb:         NOTRUN -> [SKIP][129] ([i915#1187])
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-tglb7/igt@kms_hdr@static-toggle-suspend.html

  * igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d:
    - shard-kbl:          NOTRUN -> [SKIP][130] ([fdo#109271] / [i915#533])
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-kbl4/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
    - shard-skl:          NOTRUN -> [SKIP][131] ([fdo#109271] / [i915#533])
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-skl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
    - shard-skl:          [PASS][132] -> [INCOMPLETE][133] ([i915#4939])
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-skl8/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-skl4/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
    - shard-kbl:          NOTRUN -> [FAIL][134] ([fdo#108145] / [i915#265])
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-kbl1/igt@kms_plane_alpha_blend@pipe-b-alpha-7efc.html
    - shard-apl:          NOTRUN -> [FAIL][135] ([fdo#108145] / [i915#265])
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-apl3/igt@kms_plane_alpha_blend@pipe-b-alpha-7efc.html

  * igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
    - shard-kbl:          NOTRUN -> [SKIP][136] ([fdo#109271] / [i915#658])
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-kbl4/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-iclb:         NOTRUN -> [SKIP][137] ([fdo#109642] / [fdo#111068] / [i915#658])
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-iclb7/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@kms_psr@psr2_cursor_blt:
    - shard-iclb:         [PASS][138] -> [SKIP][139] ([fdo#109441])
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-iclb3/igt@kms_psr@psr2_cursor_blt.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         NOTRUN -> [SKIP][140] ([fdo#109441])
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-iclb8/igt@kms_psr@psr2_cursor_render.html

  * igt@kms_vrr@flip-dpms:
    - shard-iclb:         NOTRUN -> [SKIP][141] ([fdo#109502]) +1 similar issue
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-iclb1/igt@kms_vrr@flip-dpms.html

  * igt@kms_writeback@writeback-pixel-formats:
    - shard-skl:          NOTRUN -> [SKIP][142] ([fdo#109271] / [i915#2437])
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-skl7/igt@kms_writeback@writeback-pixel-formats.html

  * igt@nouveau_crc@pipe-a-source-outp-inactive:
    - shard-tglb:         NOTRUN -> [SKIP][143] ([i915#2530]) +1 similar issue
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-tglb7/igt@nouveau_crc@pipe-a-source-outp-inactive.html

  * igt@perf@gen8-unprivileged-single-ctx-counters:
    - shard-tglb:         NOTRUN -> [SKIP][144] ([fdo#109289])
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-tglb7/igt@perf@gen8-unprivileged-single-ctx-counters.html

  * igt@prime_nv_api@i915_nv_import_twice:
    - shard-tglb:         NOTRUN -> [SKIP][145] ([fdo#109291])
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-tglb2/igt@prime_nv_api@i915_nv_import_twice.html

  * igt@prime_nv_pcopy@test3_4:
    - shard-iclb:         NOTRUN -> [SKIP][146] ([fdo#109291]) +1 similar issue
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-iclb8/igt@prime_nv_pcopy@test3_4.html

  * igt@syncobj_timeline@invalid-transfer-non-existent-point:
    - shard-iclb:         NOTRUN -> [DMESG-WARN][147] ([i915#5084])
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-iclb7/igt@syncobj_timeline@invalid-transfer-non-existent-point.html

  * igt@sysfs_clients@pidname:
    - shard-iclb:         NOTRUN -> [SKIP][148] ([i915#2994])
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-iclb8/igt@sysfs_clients@pidname.html

  
#### Possible fixes ####

  * igt@gem_eio@kms:
    - shard-tglb:         [FAIL][149] ([i915#232]) -> [PASS][150]
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-tglb1/igt@gem_eio@kms.html
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-tglb7/igt@gem_eio@kms.html

  * igt@gem_exec_capture@pi@vcs0:
    - shard-iclb:         [INCOMPLETE][151] ([i915#3371]) -> [PASS][152]
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-iclb1/igt@gem_exec_capture@pi@vcs0.html
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-iclb1/igt@gem_exec_capture@pi@vcs0.html

  * igt@gem_exec_fair@basic-none@vcs0:
    - shard-kbl:          [FAIL][153] ([i915#2842]) -> [PASS][154]
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-kbl7/igt@gem_exec_fair@basic-none@vcs0.html
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-kbl6/igt@gem_exec_fair@basic-none@vcs0.html

  * igt@gem_exec_parallel@contexts@rcs0:
    - shard-iclb:         [INCOMPLETE][155] ([i915#1895]) -> [PASS][156]
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-iclb8/igt@gem_exec_parallel@contexts@rcs0.html
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/shard-iclb8/igt@gem_exec_parallel@contexts@rcs0.html

  * igt@gem_ppgtt@flink-and-close-vma-leak:
    - shard-apl:          [FAIL][157] ([i915#644]) -> [PASS][158]
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-apl1/igt@gem_ppgtt

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22221/index.html

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Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/7] drm/i915: Move vblank waits out from IPS code

[Ville Syrjälä]

On Wed, Feb 09, 2022 at 05:36:17PM -0000, Patchwork wrote:
> == Series Details ==
> 
> Series: series starting with [1/7] drm/i915: Move vblank waits out from IPS code
> URL   : https://patchwork.freedesktop.org/series/99898/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_11207_full -> Patchwork_22221_full
> ====================================================
> 
> Summary
> -------
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_22221_full absolutely need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_22221_full, please notify your bug team to allow them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   
> 
> Participating hosts (11 -> 12)
> ------------------------------
> 
>   Additional (1): shard-rkl 
> 
> Possible new issues
> -------------------
> 
>   Here are the unknown changes that may have been introduced in Patchwork_22221_full:
> 
> ### IGT changes ###
> 
> #### Possible regressions ####
> 
>   * igt@kms_plane_cursor@pipe-a-viewport-size-64:
>     - shard-snb:          [PASS][1] -> [FAIL][2]

That looks like a real thing due to the ilk+ wm code being a bit
mouldy atm. I'll need to fix that first before I can push
that vblank consolidation patch :/ But on the plus side that has
given me another idea how to refactor the cxsr disable stuff into
a slightly nicer shape...

-- 
Ville Syrjälä
Intel