All of lore.kernel.org
 help / color / mirror / Atom feed
From: Michael Cheng <michael.cheng@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: tvrtko.ursulin@linux.intel.com, michael.cheng@intel.com,
	balasubramani.vivekanandan@intel.com, wayne.boyer@intel.com,
	casey.g.bowman@intel.com, lucas.demarchi@intel.com,
	dri-devel@lists.freedesktop.org
Subject: [PATCH v9 1/6] drm: Add arch arm64 for drm_clflush_virt_range
Date: Wed,  9 Feb 2022 17:26:12 -0800	[thread overview]
Message-ID: <20220210012617.1061641-2-michael.cheng@intel.com> (raw)
In-Reply-To: <20220210012617.1061641-1-michael.cheng@intel.com>

Add arm64 support for drm_clflush_virt_range. dcache_clean_inval_poc
performs a flush by first performing a clean, follow by an invalidation
operation.

v2 (Michael Cheng): Use correct macro for cleaning and invalidation the
		    dcache.

v3 (Michael Cheng): Remove ifdef for asm/cacheflush.h

v4 (Michael Cheng): Rebase

Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
 drivers/gpu/drm/drm_cache.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
index 66597e411764..ec8d91b088ff 100644
--- a/drivers/gpu/drm/drm_cache.c
+++ b/drivers/gpu/drm/drm_cache.c
@@ -28,6 +28,7 @@
  * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
  */
 
+#include <asm/cacheflush.h>
 #include <linux/cc_platform.h>
 #include <linux/export.h>
 #include <linux/highmem.h>
@@ -174,6 +175,10 @@ drm_clflush_virt_range(void *addr, unsigned long length)
 
 	if (wbinvd_on_all_cpus())
 		pr_err("Timed out waiting for cache flush\n");
+
+#elif defined(CONFIG_ARM64)
+	void *end = addr + length;
+	dcache_clean_inval_poc((unsigned long)addr, (unsigned long)end);
 #else
 	WARN_ONCE(1, "Architecture has no drm_cache.c support\n");
 #endif
-- 
2.25.1


WARNING: multiple messages have this Message-ID (diff)
From: Michael Cheng <michael.cheng@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: michael.cheng@intel.com, lucas.demarchi@intel.com,
	dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v9 1/6] drm: Add arch arm64 for drm_clflush_virt_range
Date: Wed,  9 Feb 2022 17:26:12 -0800	[thread overview]
Message-ID: <20220210012617.1061641-2-michael.cheng@intel.com> (raw)
In-Reply-To: <20220210012617.1061641-1-michael.cheng@intel.com>

Add arm64 support for drm_clflush_virt_range. dcache_clean_inval_poc
performs a flush by first performing a clean, follow by an invalidation
operation.

v2 (Michael Cheng): Use correct macro for cleaning and invalidation the
		    dcache.

v3 (Michael Cheng): Remove ifdef for asm/cacheflush.h

v4 (Michael Cheng): Rebase

Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
 drivers/gpu/drm/drm_cache.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
index 66597e411764..ec8d91b088ff 100644
--- a/drivers/gpu/drm/drm_cache.c
+++ b/drivers/gpu/drm/drm_cache.c
@@ -28,6 +28,7 @@
  * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
  */
 
+#include <asm/cacheflush.h>
 #include <linux/cc_platform.h>
 #include <linux/export.h>
 #include <linux/highmem.h>
@@ -174,6 +175,10 @@ drm_clflush_virt_range(void *addr, unsigned long length)
 
 	if (wbinvd_on_all_cpus())
 		pr_err("Timed out waiting for cache flush\n");
+
+#elif defined(CONFIG_ARM64)
+	void *end = addr + length;
+	dcache_clean_inval_poc((unsigned long)addr, (unsigned long)end);
 #else
 	WARN_ONCE(1, "Architecture has no drm_cache.c support\n");
 #endif
-- 
2.25.1


  reply	other threads:[~2022-02-10  1:26 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-10  1:26 [PATCH v9 0/6] Use drm_clflush* instead of clflush Michael Cheng
2022-02-10  1:26 ` [Intel-gfx] " Michael Cheng
2022-02-10  1:26 ` Michael Cheng [this message]
2022-02-10  1:26   ` [Intel-gfx] [PATCH v9 1/6] drm: Add arch arm64 for drm_clflush_virt_range Michael Cheng
2022-02-10 10:31   ` Tvrtko Ursulin
2022-02-10 10:31     ` Tvrtko Ursulin
2022-02-10  1:26 ` [PATCH v9 2/6] drm/i915/gt: Re-work intel_write_status_page Michael Cheng
2022-02-10  1:26   ` [Intel-gfx] " Michael Cheng
2022-02-10  1:26 ` [PATCH v9 3/6] drm/i915/gt: Drop invalidate_csb_entries Michael Cheng
2022-02-10  1:26   ` [Intel-gfx] " Michael Cheng
2022-02-10  1:26 ` [PATCH v9 4/6] drm/i915/gt: Re-work reset_csb Michael Cheng
2022-02-10  1:26   ` [Intel-gfx] " Michael Cheng
2022-02-10  1:26 ` [PATCH v9 5/6] drm/i915/: Re-work clflush_write32 Michael Cheng
2022-02-10  1:26   ` [Intel-gfx] " Michael Cheng
2022-02-10  1:26 ` [PATCH v9 6/6] drm/i915/gt: replace cache_clflush_range Michael Cheng
2022-02-10  1:26   ` [Intel-gfx] " Michael Cheng
2022-02-10  1:38 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Use drm_clflush* instead of clflush (rev8) Patchwork
2022-02-10  1:39 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-02-10  2:12 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20220210012617.1061641-2-michael.cheng@intel.com \
    --to=michael.cheng@intel.com \
    --cc=balasubramani.vivekanandan@intel.com \
    --cc=casey.g.bowman@intel.com \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=lucas.demarchi@intel.com \
    --cc=tvrtko.ursulin@linux.intel.com \
    --cc=wayne.boyer@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.