* [PATCH 1/2] pinctrl: qcom: sm8450: Add egpio support
@ 2022-02-10 13:12 Jonathan Marek
2022-02-10 13:12 ` [PATCH 2/2] pinctrl: qcom: print egpio mode in debugfs Jonathan Marek
2022-02-19 0:54 ` [PATCH 1/2] pinctrl: qcom: sm8450: Add egpio support Linus Walleij
0 siblings, 2 replies; 4+ messages in thread
From: Jonathan Marek @ 2022-02-10 13:12 UTC (permalink / raw)
To: linux-arm-msm
Cc: dmitry.baryshkov, Andy Gross, Bjorn Andersson, Linus Walleij,
open list:PIN CONTROL SUBSYSTEM, open list
This mirrors egpio support added for sc7280. This change is necessary for
gpios 165 to 209 to be driven by APSS.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
drivers/pinctrl/qcom/pinctrl-sm8450.c | 106 +++++++++++++++-----------
1 file changed, 61 insertions(+), 45 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8450.c b/drivers/pinctrl/qcom/pinctrl-sm8450.c
index c6fa3dbc14a1e..3110d7bf5698a 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8450.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8450.c
@@ -46,6 +46,8 @@
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
+ .egpio_enable = 12, \
+ .egpio_present = 11, \
.oe_bit = 9, \
.in_bit = 0, \
.out_bit = 1, \
@@ -567,6 +569,7 @@ enum sm8450_functions {
msm_mux_ddr_pxi2,
msm_mux_ddr_pxi3,
msm_mux_dp_hot,
+ msm_mux_egpio,
msm_mux_gcc_gp1,
msm_mux_gcc_gp2,
msm_mux_gcc_gp3,
@@ -719,6 +722,17 @@ static const char * const gpio_groups[] = {
"gpio207", "gpio208", "gpio209",
};
+static const char * const egpio_groups[] = {
+ "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170",
+ "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176",
+ "gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182",
+ "gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188",
+ "gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194",
+ "gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200",
+ "gpio201", "gpio202", "gpio203", "gpio204", "gpio205", "gpio206",
+ "gpio207", "gpio208", "gpio209",
+};
+
static const char * const aon_cam_groups[] = {
"gpio108",
};
@@ -1285,6 +1299,7 @@ static const struct msm_function sm8450_functions[] = {
FUNCTION(ddr_pxi2),
FUNCTION(ddr_pxi3),
FUNCTION(dp_hot),
+ FUNCTION(egpio),
FUNCTION(gcc_gp1),
FUNCTION(gcc_gp2),
FUNCTION(gcc_gp3),
@@ -1571,51 +1586,51 @@ static const struct msm_pingroup sm8450_groups[] = {
[162] = PINGROUP(162, qlink2_request, _, _, _, _, _, _, _, _),
[163] = PINGROUP(163, qlink2_enable, _, _, _, _, _, _, _, _),
[164] = PINGROUP(164, qlink2_wmss, _, _, _, _, _, _, _, _),
- [165] = PINGROUP(165, _, _, _, _, _, _, _, _, _),
- [166] = PINGROUP(166, _, _, _, _, _, _, _, _, _),
- [167] = PINGROUP(167, _, _, _, _, _, _, _, _, _),
- [168] = PINGROUP(168, _, _, _, _, _, _, _, _, _),
- [169] = PINGROUP(169, _, _, _, _, _, _, _, _, _),
- [170] = PINGROUP(170, _, _, _, _, _, _, _, _, _),
- [171] = PINGROUP(171, _, _, _, _, _, _, _, _, _),
- [172] = PINGROUP(172, _, _, _, _, _, _, _, _, _),
- [173] = PINGROUP(173, _, _, _, _, _, _, _, _, _),
- [174] = PINGROUP(174, _, _, _, _, _, _, _, _, _),
- [175] = PINGROUP(175, _, _, _, _, _, _, _, _, _),
- [176] = PINGROUP(176, _, _, _, _, _, _, _, _, _),
- [177] = PINGROUP(177, _, _, _, _, _, _, _, _, _),
- [178] = PINGROUP(178, _, _, _, _, _, _, _, _, _),
- [179] = PINGROUP(179, _, _, _, _, _, _, _, _, _),
- [180] = PINGROUP(180, _, _, _, _, _, _, _, _, _),
- [181] = PINGROUP(181, _, _, _, _, _, _, _, _, _),
- [182] = PINGROUP(182, _, _, _, _, _, _, _, _, _),
- [183] = PINGROUP(183, _, _, _, _, _, _, _, _, _),
- [184] = PINGROUP(184, _, _, _, _, _, _, _, _, _),
- [185] = PINGROUP(185, _, _, _, _, _, _, _, _, _),
- [186] = PINGROUP(186, _, _, _, _, _, _, _, _, _),
- [187] = PINGROUP(187, _, _, _, _, _, _, _, _, _),
- [188] = PINGROUP(188, _, qdss_gpio, _, _, _, _, _, _, _),
- [189] = PINGROUP(189, _, qdss_gpio, _, _, _, _, _, _, _),
- [190] = PINGROUP(190, qdss_gpio, _, _, _, _, _, _, _, _),
- [191] = PINGROUP(191, qdss_gpio, _, _, _, _, _, _, _, _),
- [192] = PINGROUP(192, _, qdss_gpio, _, _, _, _, _, _, _),
- [193] = PINGROUP(193, _, qdss_gpio, _, _, _, _, _, _, _),
- [194] = PINGROUP(194, _, qdss_gpio, _, _, _, _, _, _, _),
- [195] = PINGROUP(195, _, qdss_gpio, _, _, _, _, _, _, _),
- [196] = PINGROUP(196, _, qdss_gpio, _, _, _, _, _, _, _),
- [197] = PINGROUP(197, _, qdss_gpio, _, _, _, _, _, _, _),
- [198] = PINGROUP(198, _, qdss_gpio, _, _, _, _, _, _, _),
- [199] = PINGROUP(199, _, qdss_gpio, _, _, _, _, _, _, _),
- [200] = PINGROUP(200, _, qdss_gpio, _, _, _, _, _, _, _),
- [201] = PINGROUP(201, _, qdss_gpio, _, _, _, _, _, _, _),
- [202] = PINGROUP(202, qdss_gpio, _, _, _, _, _, _, _, _),
- [203] = PINGROUP(203, qdss_gpio, _, _, _, _, _, _, _, _),
- [204] = PINGROUP(204, qdss_gpio, _, _, _, _, _, _, _, _),
- [205] = PINGROUP(205, qdss_gpio, _, _, _, _, _, _, _, _),
- [206] = PINGROUP(206, qup5, _, _, _, _, _, _, _, _),
- [207] = PINGROUP(207, qup5, _, _, _, _, _, _, _, _),
- [208] = PINGROUP(208, cci_i2c, _, _, _, _, _, _, _, _),
- [209] = PINGROUP(209, cci_i2c, _, _, _, _, _, _, _, _),
+ [165] = PINGROUP(165, _, _, _, _, _, _, _, _, egpio),
+ [166] = PINGROUP(166, _, _, _, _, _, _, _, _, egpio),
+ [167] = PINGROUP(167, _, _, _, _, _, _, _, _, egpio),
+ [168] = PINGROUP(168, _, _, _, _, _, _, _, _, egpio),
+ [169] = PINGROUP(169, _, _, _, _, _, _, _, _, egpio),
+ [170] = PINGROUP(170, _, _, _, _, _, _, _, _, egpio),
+ [171] = PINGROUP(171, _, _, _, _, _, _, _, _, egpio),
+ [172] = PINGROUP(172, _, _, _, _, _, _, _, _, egpio),
+ [173] = PINGROUP(173, _, _, _, _, _, _, _, _, egpio),
+ [174] = PINGROUP(174, _, _, _, _, _, _, _, _, egpio),
+ [175] = PINGROUP(175, _, _, _, _, _, _, _, _, egpio),
+ [176] = PINGROUP(176, _, _, _, _, _, _, _, _, egpio),
+ [177] = PINGROUP(177, _, _, _, _, _, _, _, _, egpio),
+ [178] = PINGROUP(178, _, _, _, _, _, _, _, _, egpio),
+ [179] = PINGROUP(179, _, _, _, _, _, _, _, _, egpio),
+ [180] = PINGROUP(180, _, _, _, _, _, _, _, _, egpio),
+ [181] = PINGROUP(181, _, _, _, _, _, _, _, _, egpio),
+ [182] = PINGROUP(182, _, _, _, _, _, _, _, _, egpio),
+ [183] = PINGROUP(183, _, _, _, _, _, _, _, _, egpio),
+ [184] = PINGROUP(184, _, _, _, _, _, _, _, _, egpio),
+ [185] = PINGROUP(185, _, _, _, _, _, _, _, _, egpio),
+ [186] = PINGROUP(186, _, _, _, _, _, _, _, _, egpio),
+ [187] = PINGROUP(187, _, _, _, _, _, _, _, _, egpio),
+ [188] = PINGROUP(188, _, qdss_gpio, _, _, _, _, _, _, egpio),
+ [189] = PINGROUP(189, _, qdss_gpio, _, _, _, _, _, _, egpio),
+ [190] = PINGROUP(190, qdss_gpio, _, _, _, _, _, _, _, egpio),
+ [191] = PINGROUP(191, qdss_gpio, _, _, _, _, _, _, _, egpio),
+ [192] = PINGROUP(192, _, qdss_gpio, _, _, _, _, _, _, egpio),
+ [193] = PINGROUP(193, _, qdss_gpio, _, _, _, _, _, _, egpio),
+ [194] = PINGROUP(194, _, qdss_gpio, _, _, _, _, _, _, egpio),
+ [195] = PINGROUP(195, _, qdss_gpio, _, _, _, _, _, _, egpio),
+ [196] = PINGROUP(196, _, qdss_gpio, _, _, _, _, _, _, egpio),
+ [197] = PINGROUP(197, _, qdss_gpio, _, _, _, _, _, _, egpio),
+ [198] = PINGROUP(198, _, qdss_gpio, _, _, _, _, _, _, egpio),
+ [199] = PINGROUP(199, _, qdss_gpio, _, _, _, _, _, _, egpio),
+ [200] = PINGROUP(200, _, qdss_gpio, _, _, _, _, _, _, egpio),
+ [201] = PINGROUP(201, _, qdss_gpio, _, _, _, _, _, _, egpio),
+ [202] = PINGROUP(202, qdss_gpio, _, _, _, _, _, _, _, egpio),
+ [203] = PINGROUP(203, qdss_gpio, _, _, _, _, _, _, _, egpio),
+ [204] = PINGROUP(204, qdss_gpio, _, _, _, _, _, _, _, egpio),
+ [205] = PINGROUP(205, qdss_gpio, _, _, _, _, _, _, _, egpio),
+ [206] = PINGROUP(206, qup5, _, _, _, _, _, _, _, egpio),
+ [207] = PINGROUP(207, qup5, _, _, _, _, _, _, _, egpio),
+ [208] = PINGROUP(208, cci_i2c, _, _, _, _, _, _, _, egpio),
+ [209] = PINGROUP(209, cci_i2c, _, _, _, _, _, _, _, egpio),
[210] = UFS_RESET(ufs_reset, 0xde000),
[211] = SDC_QDSD_PINGROUP(sdc2_clk, 0xd6000, 14, 6),
[212] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xd6000, 11, 3),
@@ -1651,6 +1666,7 @@ static const struct msm_pinctrl_soc_data sm8450_tlmm = {
.ngpios = 211,
.wakeirq_map = sm8450_pdc_map,
.nwakeirq_map = ARRAY_SIZE(sm8450_pdc_map),
+ .egpio_func = 9,
};
static int sm8450_tlmm_probe(struct platform_device *pdev)
--
2.26.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] pinctrl: qcom: print egpio mode in debugfs
2022-02-10 13:12 [PATCH 1/2] pinctrl: qcom: sm8450: Add egpio support Jonathan Marek
@ 2022-02-10 13:12 ` Jonathan Marek
2022-02-19 0:55 ` Linus Walleij
2022-02-19 0:54 ` [PATCH 1/2] pinctrl: qcom: sm8450: Add egpio support Linus Walleij
1 sibling, 1 reply; 4+ messages in thread
From: Jonathan Marek @ 2022-02-10 13:12 UTC (permalink / raw)
To: linux-arm-msm
Cc: dmitry.baryshkov, Bjorn Andersson, Andy Gross, Linus Walleij,
open list:PIN CONTROL SUBSYSTEM, open list
When egpio_enable bit is cleared, the gpio is driven by SSC/LPASS TLMM and
the APSS TLMM settings are ignored. Reflect that in the debugfs dump.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
drivers/pinctrl/qcom/pinctrl-msm.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index 780878dede9e0..27c19a206502d 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -615,6 +615,7 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
int drive;
int pull;
int val;
+ int egpio_enable;
u32 ctl_reg, io_reg;
static const char * const pulls_keeper[] = {
@@ -641,12 +642,20 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
func = (ctl_reg >> g->mux_bit) & 7;
drive = (ctl_reg >> g->drv_bit) & 7;
pull = (ctl_reg >> g->pull_bit) & 3;
+ egpio_enable = 0;
+ if (pctrl->soc->egpio_func && ctl_reg & BIT(g->egpio_present))
+ egpio_enable = !(ctl_reg & BIT(g->egpio_enable));
if (is_out)
val = !!(io_reg & BIT(g->out_bit));
else
val = !!(io_reg & BIT(g->in_bit));
+ if (egpio_enable) {
+ seq_printf(s, " %-8s: egpio\n", g->name);
+ return;
+ }
+
seq_printf(s, " %-8s: %-3s", g->name, is_out ? "out" : "in");
seq_printf(s, " %-4s func%d", val ? "high" : "low", func);
seq_printf(s, " %dmA", msm_regval_to_drive(drive));
--
2.26.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 1/2] pinctrl: qcom: sm8450: Add egpio support
2022-02-10 13:12 [PATCH 1/2] pinctrl: qcom: sm8450: Add egpio support Jonathan Marek
2022-02-10 13:12 ` [PATCH 2/2] pinctrl: qcom: print egpio mode in debugfs Jonathan Marek
@ 2022-02-19 0:54 ` Linus Walleij
1 sibling, 0 replies; 4+ messages in thread
From: Linus Walleij @ 2022-02-19 0:54 UTC (permalink / raw)
To: Jonathan Marek
Cc: linux-arm-msm, dmitry.baryshkov, Andy Gross, Bjorn Andersson,
open list:PIN CONTROL SUBSYSTEM, open list
On Thu, Feb 10, 2022 at 2:14 PM Jonathan Marek <jonathan@marek.ca> wrote:
> This mirrors egpio support added for sc7280. This change is necessary for
> gpios 165 to 209 to be driven by APSS.
>
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Haven't heard anything for over a week so I just applied the
patches. I assume you know what you're doing.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 2/2] pinctrl: qcom: print egpio mode in debugfs
2022-02-10 13:12 ` [PATCH 2/2] pinctrl: qcom: print egpio mode in debugfs Jonathan Marek
@ 2022-02-19 0:55 ` Linus Walleij
0 siblings, 0 replies; 4+ messages in thread
From: Linus Walleij @ 2022-02-19 0:55 UTC (permalink / raw)
To: Jonathan Marek
Cc: linux-arm-msm, dmitry.baryshkov, Bjorn Andersson, Andy Gross,
open list:PIN CONTROL SUBSYSTEM, open list
On Thu, Feb 10, 2022 at 2:14 PM Jonathan Marek <jonathan@marek.ca> wrote:
> When egpio_enable bit is cleared, the gpio is driven by SSC/LPASS TLMM and
> the APSS TLMM settings are ignored. Reflect that in the debugfs dump.
>
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2022-02-19 0:55 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-02-10 13:12 [PATCH 1/2] pinctrl: qcom: sm8450: Add egpio support Jonathan Marek
2022-02-10 13:12 ` [PATCH 2/2] pinctrl: qcom: print egpio mode in debugfs Jonathan Marek
2022-02-19 0:55 ` Linus Walleij
2022-02-19 0:54 ` [PATCH 1/2] pinctrl: qcom: sm8450: Add egpio support Linus Walleij
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.