* [PATCH v10 0/6] Use drm_clflush* instead of clflush
@ 2022-02-10 18:36 ` Michael Cheng
0 siblings, 0 replies; 30+ messages in thread
From: Michael Cheng @ 2022-02-10 18:36 UTC (permalink / raw)
To: intel-gfx
Cc: tvrtko.ursulin, michael.cheng, balasubramani.vivekanandan,
wayne.boyer, casey.g.bowman, lucas.demarchi, dri-devel
This patch series re-work a few i915 functions to use drm_clflush_virt_range
instead of calling clflush or clflushopt directly. This will prevent errors
when building for non-x86 architectures.
v2: s/PAGE_SIZE/sizeof(value) for Re-work intel_write_status_page and added
more patches to convert additional clflush/clflushopt to use drm_clflush*.
(Michael Cheng)
v3: Drop invalidate_csb_entries and directly invoke drm_clflush_virt_ran
v4: Remove extra memory barriers
v5: s/cache_clflush_range/drm_clflush_virt_range
v6: Fix up "Drop invalidate_csb_entries" to use correct parameters. Also
added in arm64 support for drm_clflush_virt_range.
v7: Re-order patches, and use correct macro for dcache flush for arm64.
v8: Remove ifdef for asm/cacheflush.
v9: Rebased
v10: Replaced asm/cacheflush with linux/cacheflush
Michael Cheng (6):
drm: Add arch arm64 for drm_clflush_virt_range
drm/i915/gt: Re-work intel_write_status_page
drm/i915/gt: Drop invalidate_csb_entries
drm/i915/gt: Re-work reset_csb
drm/i915/: Re-work clflush_write32
drm/i915/gt: replace cache_clflush_range
drivers/gpu/drm/drm_cache.c | 6 ++++++
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-----
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 12 +++++------
drivers/gpu/drm/i915/gt/intel_engine.h | 13 ++++--------
.../drm/i915/gt/intel_execlists_submission.c | 20 +++++++------------
drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 2 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
8 files changed, 29 insertions(+), 36 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 30+ messages in thread
* [Intel-gfx] [PATCH v10 0/6] Use drm_clflush* instead of clflush
@ 2022-02-10 18:36 ` Michael Cheng
0 siblings, 0 replies; 30+ messages in thread
From: Michael Cheng @ 2022-02-10 18:36 UTC (permalink / raw)
To: intel-gfx; +Cc: michael.cheng, lucas.demarchi, dri-devel
This patch series re-work a few i915 functions to use drm_clflush_virt_range
instead of calling clflush or clflushopt directly. This will prevent errors
when building for non-x86 architectures.
v2: s/PAGE_SIZE/sizeof(value) for Re-work intel_write_status_page and added
more patches to convert additional clflush/clflushopt to use drm_clflush*.
(Michael Cheng)
v3: Drop invalidate_csb_entries and directly invoke drm_clflush_virt_ran
v4: Remove extra memory barriers
v5: s/cache_clflush_range/drm_clflush_virt_range
v6: Fix up "Drop invalidate_csb_entries" to use correct parameters. Also
added in arm64 support for drm_clflush_virt_range.
v7: Re-order patches, and use correct macro for dcache flush for arm64.
v8: Remove ifdef for asm/cacheflush.
v9: Rebased
v10: Replaced asm/cacheflush with linux/cacheflush
Michael Cheng (6):
drm: Add arch arm64 for drm_clflush_virt_range
drm/i915/gt: Re-work intel_write_status_page
drm/i915/gt: Drop invalidate_csb_entries
drm/i915/gt: Re-work reset_csb
drm/i915/: Re-work clflush_write32
drm/i915/gt: replace cache_clflush_range
drivers/gpu/drm/drm_cache.c | 6 ++++++
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-----
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 12 +++++------
drivers/gpu/drm/i915/gt/intel_engine.h | 13 ++++--------
.../drm/i915/gt/intel_execlists_submission.c | 20 +++++++------------
drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 2 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
8 files changed, 29 insertions(+), 36 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v10 1/6] drm: Add arch arm64 for drm_clflush_virt_range
2022-02-10 18:36 ` [Intel-gfx] " Michael Cheng
@ 2022-02-10 18:36 ` Michael Cheng
-1 siblings, 0 replies; 30+ messages in thread
From: Michael Cheng @ 2022-02-10 18:36 UTC (permalink / raw)
To: intel-gfx
Cc: tvrtko.ursulin, michael.cheng, balasubramani.vivekanandan,
wayne.boyer, casey.g.bowman, lucas.demarchi, dri-devel
Add arm64 support for drm_clflush_virt_range. dcache_clean_inval_poc
performs a flush by first performing a clean, follow by an invalidation
operation.
v2 (Michael Cheng): Use correct macro for cleaning and invalidation the
dcache.
v3 (Michael Cheng): Remove ifdef for asm/cacheflush.h
v4 (Michael Cheng): Rebase
v5 (Michael Cheng): Replace asm/cacheflush.h with linux/cacheflush.h
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
drivers/gpu/drm/drm_cache.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
index 66597e411764..2e233f53331e 100644
--- a/drivers/gpu/drm/drm_cache.c
+++ b/drivers/gpu/drm/drm_cache.c
@@ -28,6 +28,7 @@
* Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
*/
+#include <linux/cacheflush.h>
#include <linux/cc_platform.h>
#include <linux/export.h>
#include <linux/highmem.h>
@@ -174,6 +175,11 @@ drm_clflush_virt_range(void *addr, unsigned long length)
if (wbinvd_on_all_cpus())
pr_err("Timed out waiting for cache flush\n");
+
+#elif defined(CONFIG_ARM64)
+ void *end = addr + length;
+ dcache_clean_inval_poc((unsigned long)addr, (unsigned long)end);
+
#else
WARN_ONCE(1, "Architecture has no drm_cache.c support\n");
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [Intel-gfx] [PATCH v10 1/6] drm: Add arch arm64 for drm_clflush_virt_range
@ 2022-02-10 18:36 ` Michael Cheng
0 siblings, 0 replies; 30+ messages in thread
From: Michael Cheng @ 2022-02-10 18:36 UTC (permalink / raw)
To: intel-gfx; +Cc: michael.cheng, lucas.demarchi, dri-devel
Add arm64 support for drm_clflush_virt_range. dcache_clean_inval_poc
performs a flush by first performing a clean, follow by an invalidation
operation.
v2 (Michael Cheng): Use correct macro for cleaning and invalidation the
dcache.
v3 (Michael Cheng): Remove ifdef for asm/cacheflush.h
v4 (Michael Cheng): Rebase
v5 (Michael Cheng): Replace asm/cacheflush.h with linux/cacheflush.h
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
drivers/gpu/drm/drm_cache.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
index 66597e411764..2e233f53331e 100644
--- a/drivers/gpu/drm/drm_cache.c
+++ b/drivers/gpu/drm/drm_cache.c
@@ -28,6 +28,7 @@
* Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
*/
+#include <linux/cacheflush.h>
#include <linux/cc_platform.h>
#include <linux/export.h>
#include <linux/highmem.h>
@@ -174,6 +175,11 @@ drm_clflush_virt_range(void *addr, unsigned long length)
if (wbinvd_on_all_cpus())
pr_err("Timed out waiting for cache flush\n");
+
+#elif defined(CONFIG_ARM64)
+ void *end = addr + length;
+ dcache_clean_inval_poc((unsigned long)addr, (unsigned long)end);
+
#else
WARN_ONCE(1, "Architecture has no drm_cache.c support\n");
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v10 2/6] drm/i915/gt: Re-work intel_write_status_page
2022-02-10 18:36 ` [Intel-gfx] " Michael Cheng
@ 2022-02-10 18:36 ` Michael Cheng
-1 siblings, 0 replies; 30+ messages in thread
From: Michael Cheng @ 2022-02-10 18:36 UTC (permalink / raw)
To: intel-gfx
Cc: tvrtko.ursulin, michael.cheng, balasubramani.vivekanandan,
wayne.boyer, casey.g.bowman, lucas.demarchi, dri-devel
Re-work intel_write_status_page to use drm_clflush_virt_range. This
will prevent compiler errors when building for non-x86 architectures.
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine.h | 13 ++++---------
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index 0e353d8c2bc8..986777c2430d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -4,6 +4,7 @@
#include <asm/cacheflush.h>
#include <drm/drm_util.h>
+#include <drm/drm_cache.h>
#include <linux/hashtable.h>
#include <linux/irq_work.h>
@@ -143,15 +144,9 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
* of extra paranoia to try and ensure that the HWS takes the value
* we give and that it doesn't end up trapped inside the CPU!
*/
- if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
- mb();
- clflush(&engine->status_page.addr[reg]);
- engine->status_page.addr[reg] = value;
- clflush(&engine->status_page.addr[reg]);
- mb();
- } else {
- WRITE_ONCE(engine->status_page.addr[reg], value);
- }
+ drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value));
+ WRITE_ONCE(engine->status_page.addr[reg], value);
+ drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value));
}
/*
--
2.25.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [Intel-gfx] [PATCH v10 2/6] drm/i915/gt: Re-work intel_write_status_page
@ 2022-02-10 18:36 ` Michael Cheng
0 siblings, 0 replies; 30+ messages in thread
From: Michael Cheng @ 2022-02-10 18:36 UTC (permalink / raw)
To: intel-gfx; +Cc: michael.cheng, lucas.demarchi, dri-devel
Re-work intel_write_status_page to use drm_clflush_virt_range. This
will prevent compiler errors when building for non-x86 architectures.
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine.h | 13 ++++---------
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index 0e353d8c2bc8..986777c2430d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -4,6 +4,7 @@
#include <asm/cacheflush.h>
#include <drm/drm_util.h>
+#include <drm/drm_cache.h>
#include <linux/hashtable.h>
#include <linux/irq_work.h>
@@ -143,15 +144,9 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
* of extra paranoia to try and ensure that the HWS takes the value
* we give and that it doesn't end up trapped inside the CPU!
*/
- if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
- mb();
- clflush(&engine->status_page.addr[reg]);
- engine->status_page.addr[reg] = value;
- clflush(&engine->status_page.addr[reg]);
- mb();
- } else {
- WRITE_ONCE(engine->status_page.addr[reg], value);
- }
+ drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value));
+ WRITE_ONCE(engine->status_page.addr[reg], value);
+ drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value));
}
/*
--
2.25.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v10 3/6] drm/i915/gt: Drop invalidate_csb_entries
2022-02-10 18:36 ` [Intel-gfx] " Michael Cheng
@ 2022-02-10 18:36 ` Michael Cheng
-1 siblings, 0 replies; 30+ messages in thread
From: Michael Cheng @ 2022-02-10 18:36 UTC (permalink / raw)
To: intel-gfx
Cc: tvrtko.ursulin, michael.cheng, balasubramani.vivekanandan,
wayne.boyer, casey.g.bowman, lucas.demarchi, dri-devel
Drop invalidate_csb_entries and directly call drm_clflush_virt_range.
This allows for one less function call, and prevent complier errors when
building for non-x86 architectures.
v2(Michael Cheng): Drop invalidate_csb_entries function and directly
invoke drm_clflush_virt_range. Thanks to Tvrtko for the
sugguestion.
v3(Michael Cheng): Use correct parameters for drm_clflush_virt_range.
Thanks to Tvrtko for pointing this out.
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
.../gpu/drm/i915/gt/intel_execlists_submission.c | 13 ++++---------
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 9bb7c863172f..6186a5e4b191 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1646,12 +1646,6 @@ cancel_port_requests(struct intel_engine_execlists * const execlists,
return inactive;
}
-static void invalidate_csb_entries(const u64 *first, const u64 *last)
-{
- clflush((void *)first);
- clflush((void *)last);
-}
-
/*
* Starting with Gen12, the status has a new format:
*
@@ -1999,7 +1993,7 @@ process_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
* the wash as hardware, working or not, will need to do the
* invalidation before.
*/
- invalidate_csb_entries(&buf[0], &buf[num_entries - 1]);
+ drm_clflush_virt_range(&buf[0], num_entries * sizeof(buf[0]));
/*
* We assume that any event reflects a change in context flow
@@ -2783,8 +2777,9 @@ static void reset_csb_pointers(struct intel_engine_cs *engine)
/* Check that the GPU does indeed update the CSB entries! */
memset(execlists->csb_status, -1, (reset_value + 1) * sizeof(u64));
- invalidate_csb_entries(&execlists->csb_status[0],
- &execlists->csb_status[reset_value]);
+ drm_clflush_virt_range(&execlists->csb_status[0],
+ execlists->csb_size *
+ sizeof(execlists->csb_status[0]));
/* Once more for luck and our trusty paranoia */
ENGINE_WRITE(engine, RING_CONTEXT_STATUS_PTR,
--
2.25.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [Intel-gfx] [PATCH v10 3/6] drm/i915/gt: Drop invalidate_csb_entries
@ 2022-02-10 18:36 ` Michael Cheng
0 siblings, 0 replies; 30+ messages in thread
From: Michael Cheng @ 2022-02-10 18:36 UTC (permalink / raw)
To: intel-gfx; +Cc: michael.cheng, lucas.demarchi, dri-devel
Drop invalidate_csb_entries and directly call drm_clflush_virt_range.
This allows for one less function call, and prevent complier errors when
building for non-x86 architectures.
v2(Michael Cheng): Drop invalidate_csb_entries function and directly
invoke drm_clflush_virt_range. Thanks to Tvrtko for the
sugguestion.
v3(Michael Cheng): Use correct parameters for drm_clflush_virt_range.
Thanks to Tvrtko for pointing this out.
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
.../gpu/drm/i915/gt/intel_execlists_submission.c | 13 ++++---------
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 9bb7c863172f..6186a5e4b191 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1646,12 +1646,6 @@ cancel_port_requests(struct intel_engine_execlists * const execlists,
return inactive;
}
-static void invalidate_csb_entries(const u64 *first, const u64 *last)
-{
- clflush((void *)first);
- clflush((void *)last);
-}
-
/*
* Starting with Gen12, the status has a new format:
*
@@ -1999,7 +1993,7 @@ process_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
* the wash as hardware, working or not, will need to do the
* invalidation before.
*/
- invalidate_csb_entries(&buf[0], &buf[num_entries - 1]);
+ drm_clflush_virt_range(&buf[0], num_entries * sizeof(buf[0]));
/*
* We assume that any event reflects a change in context flow
@@ -2783,8 +2777,9 @@ static void reset_csb_pointers(struct intel_engine_cs *engine)
/* Check that the GPU does indeed update the CSB entries! */
memset(execlists->csb_status, -1, (reset_value + 1) * sizeof(u64));
- invalidate_csb_entries(&execlists->csb_status[0],
- &execlists->csb_status[reset_value]);
+ drm_clflush_virt_range(&execlists->csb_status[0],
+ execlists->csb_size *
+ sizeof(execlists->csb_status[0]));
/* Once more for luck and our trusty paranoia */
ENGINE_WRITE(engine, RING_CONTEXT_STATUS_PTR,
--
2.25.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v10 4/6] drm/i915/gt: Re-work reset_csb
2022-02-10 18:36 ` [Intel-gfx] " Michael Cheng
@ 2022-02-10 18:36 ` Michael Cheng
-1 siblings, 0 replies; 30+ messages in thread
From: Michael Cheng @ 2022-02-10 18:36 UTC (permalink / raw)
To: intel-gfx
Cc: tvrtko.ursulin, michael.cheng, balasubramani.vivekanandan,
wayne.boyer, casey.g.bowman, lucas.demarchi, dri-devel
Use drm_clflush_virt_range instead of directly invoking clflush. This
will prevent compiler errors when building for non-x86 architectures.
v2(Michael Cheng): Remove extra clflush
v3(Michael Cheng): Remove memory barrier since drm_clflush_virt_range
takes care of it.
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 6186a5e4b191..11b864fd68a5 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2945,9 +2945,8 @@ reset_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
- mb(); /* paranoia: read the CSB pointers from after the reset */
- clflush(execlists->csb_write);
- mb();
+ drm_clflush_virt_range(execlists->csb_write,
+ sizeof(execlists->csb_write));
inactive = process_csb(engine, inactive); /* drain preemption events */
--
2.25.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [Intel-gfx] [PATCH v10 4/6] drm/i915/gt: Re-work reset_csb
@ 2022-02-10 18:36 ` Michael Cheng
0 siblings, 0 replies; 30+ messages in thread
From: Michael Cheng @ 2022-02-10 18:36 UTC (permalink / raw)
To: intel-gfx; +Cc: michael.cheng, lucas.demarchi, dri-devel
Use drm_clflush_virt_range instead of directly invoking clflush. This
will prevent compiler errors when building for non-x86 architectures.
v2(Michael Cheng): Remove extra clflush
v3(Michael Cheng): Remove memory barrier since drm_clflush_virt_range
takes care of it.
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 6186a5e4b191..11b864fd68a5 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2945,9 +2945,8 @@ reset_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
- mb(); /* paranoia: read the CSB pointers from after the reset */
- clflush(execlists->csb_write);
- mb();
+ drm_clflush_virt_range(execlists->csb_write,
+ sizeof(execlists->csb_write));
inactive = process_csb(engine, inactive); /* drain preemption events */
--
2.25.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v10 5/6] drm/i915/: Re-work clflush_write32
2022-02-10 18:36 ` [Intel-gfx] " Michael Cheng
@ 2022-02-10 18:36 ` Michael Cheng
-1 siblings, 0 replies; 30+ messages in thread
From: Michael Cheng @ 2022-02-10 18:36 UTC (permalink / raw)
To: intel-gfx
Cc: tvrtko.ursulin, michael.cheng, balasubramani.vivekanandan,
wayne.boyer, casey.g.bowman, lucas.demarchi, dri-devel
Use drm_clflush_virt_range instead of clflushopt and remove the memory
barrier, since drm_clflush_virt_range takes care of that.
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 498b458fd784..0854276ff7ba 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1332,10 +1332,8 @@ static void *reloc_vaddr(struct i915_vma *vma,
static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
{
if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
- if (flushes & CLFLUSH_BEFORE) {
- clflushopt(addr);
- mb();
- }
+ if (flushes & CLFLUSH_BEFORE)
+ drm_clflush_virt_range(addr, sizeof(addr));
*addr = value;
@@ -1347,7 +1345,7 @@ static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
* to ensure ordering of clflush wrt to the system.
*/
if (flushes & CLFLUSH_AFTER)
- clflushopt(addr);
+ drm_clflush_virt_range(addr, sizeof(addr));
} else
*addr = value;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [Intel-gfx] [PATCH v10 5/6] drm/i915/: Re-work clflush_write32
@ 2022-02-10 18:36 ` Michael Cheng
0 siblings, 0 replies; 30+ messages in thread
From: Michael Cheng @ 2022-02-10 18:36 UTC (permalink / raw)
To: intel-gfx; +Cc: michael.cheng, lucas.demarchi, dri-devel
Use drm_clflush_virt_range instead of clflushopt and remove the memory
barrier, since drm_clflush_virt_range takes care of that.
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 498b458fd784..0854276ff7ba 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1332,10 +1332,8 @@ static void *reloc_vaddr(struct i915_vma *vma,
static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
{
if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
- if (flushes & CLFLUSH_BEFORE) {
- clflushopt(addr);
- mb();
- }
+ if (flushes & CLFLUSH_BEFORE)
+ drm_clflush_virt_range(addr, sizeof(addr));
*addr = value;
@@ -1347,7 +1345,7 @@ static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
* to ensure ordering of clflush wrt to the system.
*/
if (flushes & CLFLUSH_AFTER)
- clflushopt(addr);
+ drm_clflush_virt_range(addr, sizeof(addr));
} else
*addr = value;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v10 6/6] drm/i915/gt: replace cache_clflush_range
2022-02-10 18:36 ` [Intel-gfx] " Michael Cheng
@ 2022-02-10 18:36 ` Michael Cheng
-1 siblings, 0 replies; 30+ messages in thread
From: Michael Cheng @ 2022-02-10 18:36 UTC (permalink / raw)
To: intel-gfx
Cc: tvrtko.ursulin, michael.cheng, balasubramani.vivekanandan,
wayne.boyer, casey.g.bowman, lucas.demarchi, dri-devel
Replace all occurrence of cache_clflush_range with drm_clflush_virt_range.
This will prevent compile errors on non-x86 platforms.
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 12 ++++++------
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
5 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index c43e724afa9f..d0999e92621b 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -444,11 +444,11 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
pd = pdp->entry[gen8_pd_index(idx, 2)];
}
- clflush_cache_range(vaddr, PAGE_SIZE);
+ drm_clflush_virt_range(vaddr, PAGE_SIZE);
vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
}
} while (1);
- clflush_cache_range(vaddr, PAGE_SIZE);
+ drm_clflush_virt_range(vaddr, PAGE_SIZE);
return idx;
}
@@ -532,7 +532,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm,
}
} while (rem >= page_size && index < I915_PDES);
- clflush_cache_range(vaddr, PAGE_SIZE);
+ drm_clflush_virt_range(vaddr, PAGE_SIZE);
/*
* Is it safe to mark the 2M block as 64K? -- Either we have
@@ -548,7 +548,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm,
I915_GTT_PAGE_SIZE_2M)))) {
vaddr = px_vaddr(pd);
vaddr[maybe_64K] |= GEN8_PDE_IPS_64K;
- clflush_cache_range(vaddr, PAGE_SIZE);
+ drm_clflush_virt_range(vaddr, PAGE_SIZE);
page_size = I915_GTT_PAGE_SIZE_64K;
/*
@@ -569,7 +569,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm,
for (i = 1; i < index; i += 16)
memset64(vaddr + i, encode, 15);
- clflush_cache_range(vaddr, PAGE_SIZE);
+ drm_clflush_virt_range(vaddr, PAGE_SIZE);
}
}
@@ -617,7 +617,7 @@ static void gen8_ppgtt_insert_entry(struct i915_address_space *vm,
vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
vaddr[gen8_pd_index(idx, 0)] = gen8_pte_encode(addr, level, flags);
- clflush_cache_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));
+ drm_clflush_virt_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));
}
static int gen8_init_scratch(struct i915_address_space *vm)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 11b864fd68a5..67dd4b1fc185 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2823,7 +2823,7 @@ static void execlists_sanitize(struct intel_engine_cs *engine)
sanitize_hwsp(engine);
/* And scrub the dirty cachelines for the HWSP */
- clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
+ drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE);
intel_engine_reset_pinned_contexts(engine);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 0d6bbc8c57f2..9b594be9102f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -255,7 +255,7 @@ fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count)
void *vaddr = __px_vaddr(p);
memset64(vaddr, val, count);
- clflush_cache_range(vaddr, PAGE_SIZE);
+ drm_clflush_virt_range(vaddr, PAGE_SIZE);
}
static void poison_scratch_page(struct drm_i915_gem_object *scratch)
diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
index 48e6e2f87700..bd474a5123cb 100644
--- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
@@ -90,7 +90,7 @@ write_dma_entry(struct drm_i915_gem_object * const pdma,
u64 * const vaddr = __px_vaddr(pdma);
vaddr[idx] = encoded_entry;
- clflush_cache_range(&vaddr[idx], sizeof(u64));
+ drm_clflush_virt_range(&vaddr[idx], sizeof(u64));
}
void
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index b3a429a92c0d..89020706adc4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -3573,7 +3573,7 @@ static void guc_sanitize(struct intel_engine_cs *engine)
sanitize_hwsp(engine);
/* And scrub the dirty cachelines for the HWSP */
- clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
+ drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE);
intel_engine_reset_pinned_contexts(engine);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [Intel-gfx] [PATCH v10 6/6] drm/i915/gt: replace cache_clflush_range
@ 2022-02-10 18:36 ` Michael Cheng
0 siblings, 0 replies; 30+ messages in thread
From: Michael Cheng @ 2022-02-10 18:36 UTC (permalink / raw)
To: intel-gfx; +Cc: michael.cheng, lucas.demarchi, dri-devel
Replace all occurrence of cache_clflush_range with drm_clflush_virt_range.
This will prevent compile errors on non-x86 platforms.
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 12 ++++++------
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
5 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index c43e724afa9f..d0999e92621b 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -444,11 +444,11 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
pd = pdp->entry[gen8_pd_index(idx, 2)];
}
- clflush_cache_range(vaddr, PAGE_SIZE);
+ drm_clflush_virt_range(vaddr, PAGE_SIZE);
vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
}
} while (1);
- clflush_cache_range(vaddr, PAGE_SIZE);
+ drm_clflush_virt_range(vaddr, PAGE_SIZE);
return idx;
}
@@ -532,7 +532,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm,
}
} while (rem >= page_size && index < I915_PDES);
- clflush_cache_range(vaddr, PAGE_SIZE);
+ drm_clflush_virt_range(vaddr, PAGE_SIZE);
/*
* Is it safe to mark the 2M block as 64K? -- Either we have
@@ -548,7 +548,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm,
I915_GTT_PAGE_SIZE_2M)))) {
vaddr = px_vaddr(pd);
vaddr[maybe_64K] |= GEN8_PDE_IPS_64K;
- clflush_cache_range(vaddr, PAGE_SIZE);
+ drm_clflush_virt_range(vaddr, PAGE_SIZE);
page_size = I915_GTT_PAGE_SIZE_64K;
/*
@@ -569,7 +569,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm,
for (i = 1; i < index; i += 16)
memset64(vaddr + i, encode, 15);
- clflush_cache_range(vaddr, PAGE_SIZE);
+ drm_clflush_virt_range(vaddr, PAGE_SIZE);
}
}
@@ -617,7 +617,7 @@ static void gen8_ppgtt_insert_entry(struct i915_address_space *vm,
vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
vaddr[gen8_pd_index(idx, 0)] = gen8_pte_encode(addr, level, flags);
- clflush_cache_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));
+ drm_clflush_virt_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));
}
static int gen8_init_scratch(struct i915_address_space *vm)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 11b864fd68a5..67dd4b1fc185 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2823,7 +2823,7 @@ static void execlists_sanitize(struct intel_engine_cs *engine)
sanitize_hwsp(engine);
/* And scrub the dirty cachelines for the HWSP */
- clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
+ drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE);
intel_engine_reset_pinned_contexts(engine);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 0d6bbc8c57f2..9b594be9102f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -255,7 +255,7 @@ fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count)
void *vaddr = __px_vaddr(p);
memset64(vaddr, val, count);
- clflush_cache_range(vaddr, PAGE_SIZE);
+ drm_clflush_virt_range(vaddr, PAGE_SIZE);
}
static void poison_scratch_page(struct drm_i915_gem_object *scratch)
diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
index 48e6e2f87700..bd474a5123cb 100644
--- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
@@ -90,7 +90,7 @@ write_dma_entry(struct drm_i915_gem_object * const pdma,
u64 * const vaddr = __px_vaddr(pdma);
vaddr[idx] = encoded_entry;
- clflush_cache_range(&vaddr[idx], sizeof(u64));
+ drm_clflush_virt_range(&vaddr[idx], sizeof(u64));
}
void
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index b3a429a92c0d..89020706adc4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -3573,7 +3573,7 @@ static void guc_sanitize(struct intel_engine_cs *engine)
sanitize_hwsp(engine);
/* And scrub the dirty cachelines for the HWSP */
- clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
+ drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE);
intel_engine_reset_pinned_contexts(engine);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Use drm_clflush* instead of clflush (rev9)
2022-02-10 18:36 ` [Intel-gfx] " Michael Cheng
` (6 preceding siblings ...)
(?)
@ 2022-02-10 19:07 ` Patchwork
-1 siblings, 0 replies; 30+ messages in thread
From: Patchwork @ 2022-02-10 19:07 UTC (permalink / raw)
To: Michael Cheng; +Cc: intel-gfx
== Series Details ==
Series: Use drm_clflush* instead of clflush (rev9)
URL : https://patchwork.freedesktop.org/series/99450/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ea63269ee004 drm: Add arch arm64 for drm_clflush_virt_range
-:40: WARNING:LINE_SPACING: Missing a blank line after declarations
#40: FILE: drivers/gpu/drm/drm_cache.c:181:
+ void *end = addr + length;
+ dcache_clean_inval_poc((unsigned long)addr, (unsigned long)end);
total: 0 errors, 1 warnings, 0 checks, 18 lines checked
e83ef112b20c drm/i915/gt: Re-work intel_write_status_page
3272afe74b53 drm/i915/gt: Drop invalidate_csb_entries
87e71bff36de drm/i915/gt: Re-work reset_csb
4037c1b12325 drm/i915/: Re-work clflush_write32
ea5ae2247f97 drm/i915/gt: replace cache_clflush_range
^ permalink raw reply [flat|nested] 30+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Use drm_clflush* instead of clflush (rev9)
2022-02-10 18:36 ` [Intel-gfx] " Michael Cheng
` (7 preceding siblings ...)
(?)
@ 2022-02-10 19:08 ` Patchwork
-1 siblings, 0 replies; 30+ messages in thread
From: Patchwork @ 2022-02-10 19:08 UTC (permalink / raw)
To: Michael Cheng; +Cc: intel-gfx
== Series Details ==
Series: Use drm_clflush* instead of clflush (rev9)
URL : https://patchwork.freedesktop.org/series/99450/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 30+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Use drm_clflush* instead of clflush (rev9)
2022-02-10 18:36 ` [Intel-gfx] " Michael Cheng
` (8 preceding siblings ...)
(?)
@ 2022-02-10 19:34 ` Patchwork
-1 siblings, 0 replies; 30+ messages in thread
From: Patchwork @ 2022-02-10 19:34 UTC (permalink / raw)
To: Michael Cheng; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 7855 bytes --]
== Series Details ==
Series: Use drm_clflush* instead of clflush (rev9)
URL : https://patchwork.freedesktop.org/series/99450/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11214 -> Patchwork_22244
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/index.html
Participating hosts (48 -> 42)
------------------------------
Additional (2): fi-icl-u2 fi-adl-ddr4
Missing (8): shard-tglu fi-hsw-4200u fi-bsw-cyan fi-cfl-guc fi-ctg-p8600 shard-rkl shard-dg1 fi-bdw-samus
Known issues
------------
Here are the changes found in Patchwork_22244 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/fi-icl-u2/igt@amdgpu/amd_cs_nop@fork-gfx0.html
* igt@gem_exec_suspend@basic-s3@smem:
- fi-skl-6600u: [PASS][2] -> [INCOMPLETE][3] ([i915#4547])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/fi-skl-6600u/igt@gem_exec_suspend@basic-s3@smem.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/fi-skl-6600u/igt@gem_exec_suspend@basic-s3@smem.html
* igt@gem_huc_copy@huc-copy:
- fi-icl-u2: NOTRUN -> [SKIP][4] ([i915#2190])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/fi-icl-u2/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2: NOTRUN -> [SKIP][5] ([i915#4613]) +3 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/fi-icl-u2/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [PASS][6] -> [DMESG-FAIL][7] ([i915#4494] / [i915#4957])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: NOTRUN -> [SKIP][8] ([fdo#111827]) +8 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-icl-u2: NOTRUN -> [SKIP][9] ([fdo#109278]) +2 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2: NOTRUN -> [SKIP][10] ([fdo#109285])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/fi-icl-u2/igt@kms_force_connector_basic@force-load-detect.html
* igt@prime_vgem@basic-userptr:
- fi-icl-u2: NOTRUN -> [SKIP][11] ([i915#3301])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/fi-icl-u2/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-bdw-5557u: NOTRUN -> [FAIL][12] ([i915#2426] / [i915#4312])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/fi-bdw-5557u/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3@smem:
- {bat-rpls-2}: [INCOMPLETE][13] ([i915#4898]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/bat-rpls-2/igt@gem_exec_suspend@basic-s3@smem.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/bat-rpls-2/igt@gem_exec_suspend@basic-s3@smem.html
* igt@i915_selftest@live@workarounds:
- {bat-adlp-6}: [DMESG-WARN][15] ([i915#5068]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/bat-adlp-6/igt@i915_selftest@live@workarounds.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/bat-adlp-6/igt@i915_selftest@live@workarounds.html
#### Warnings ####
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770: [INCOMPLETE][17] ([i915#4785]) -> [INCOMPLETE][18] ([i915#3303])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
* igt@runner@aborted:
- fi-skl-6600u: [FAIL][19] ([i915#1436] / [i915#4312]) -> [FAIL][20] ([i915#4312])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/fi-skl-6600u/igt@runner@aborted.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/fi-skl-6600u/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3138]: https://gitlab.freedesktop.org/drm/intel/issues/3138
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4897]: https://gitlab.freedesktop.org/drm/intel/issues/4897
[i915#4898]: https://gitlab.freedesktop.org/drm/intel/issues/4898
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#5068]: https://gitlab.freedesktop.org/drm/intel/issues/5068
Build changes
-------------
* Linux: CI_DRM_11214 -> Patchwork_22244
CI-20190529: 20190529
CI_DRM_11214: b9ddf3cdcb94017765655d8d31adc1bb70b11046 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6342: 1bd167a3af9e8f6168ac89c64c64b929694d9be7 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22244: ea5ae2247f97608a67c03be719ab83e3ee88fa7f @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
ea5ae2247f97 drm/i915/gt: replace cache_clflush_range
4037c1b12325 drm/i915/: Re-work clflush_write32
87e71bff36de drm/i915/gt: Re-work reset_csb
3272afe74b53 drm/i915/gt: Drop invalidate_csb_entries
e83ef112b20c drm/i915/gt: Re-work intel_write_status_page
ea63269ee004 drm: Add arch arm64 for drm_clflush_virt_range
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/index.html
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^ permalink raw reply [flat|nested] 30+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for Use drm_clflush* instead of clflush (rev9)
2022-02-10 18:36 ` [Intel-gfx] " Michael Cheng
` (9 preceding siblings ...)
(?)
@ 2022-02-10 23:22 ` Patchwork
-1 siblings, 0 replies; 30+ messages in thread
From: Patchwork @ 2022-02-10 23:22 UTC (permalink / raw)
To: Michael Cheng; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30265 bytes --]
== Series Details ==
Series: Use drm_clflush* instead of clflush (rev9)
URL : https://patchwork.freedesktop.org/series/99450/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11214_full -> Patchwork_22244_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in Patchwork_22244_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_eio@kms:
- shard-tglb: [PASS][1] -> [FAIL][2] ([i915#232])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-tglb7/igt@gem_eio@kms.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-tglb8/igt@gem_eio@kms.html
* igt@gem_exec_balancer@parallel-out-fence:
- shard-kbl: NOTRUN -> [DMESG-WARN][3] ([i915#5076])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-kbl1/igt@gem_exec_balancer@parallel-out-fence.html
* igt@gem_exec_capture@pi@rcs0:
- shard-skl: NOTRUN -> [INCOMPLETE][4] ([i915#4547])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-skl9/igt@gem_exec_capture@pi@rcs0.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][5] -> [FAIL][6] ([i915#2842])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-tglb2/igt@gem_exec_fair@basic-flow@rcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-tglb5/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl: NOTRUN -> [FAIL][7] ([i915#2842])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-kbl1/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-kbl: [PASS][8] -> [FAIL][9] ([i915#2842]) +1 similar issue
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-kbl1/igt@gem_exec_fair@basic-none@vecs0.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-kbl6/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-iclb: [PASS][10] -> [FAIL][11] ([i915#2842])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-iclb3/igt@gem_exec_fair@basic-pace@rcs0.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-iclb5/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_schedule@submit-early-slice@vcs0:
- shard-skl: NOTRUN -> [INCOMPLETE][12] ([i915#3797])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-skl6/igt@gem_exec_schedule@submit-early-slice@vcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-apl: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#2190])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-apl8/igt@gem_huc_copy@huc-copy.html
- shard-kbl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#2190])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-kbl6/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- shard-skl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613]) +2 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-skl8/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@heavy-random:
- shard-apl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-apl8/igt@gem_lmem_swapping@heavy-random.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-glk: [PASS][17] -> [FAIL][18] ([i915#644])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-glk7/igt@gem_ppgtt@flink-and-close-vma-leak.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-glk3/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@gem_pread@exhaustion:
- shard-tglb: NOTRUN -> [WARN][19] ([i915#2658])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-tglb1/igt@gem_pread@exhaustion.html
* igt@gem_userptr_blits@vma-merge:
- shard-skl: NOTRUN -> [FAIL][20] ([i915#3318])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-skl2/igt@gem_userptr_blits@vma-merge.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [PASS][21] -> [DMESG-WARN][22] ([i915#1436] / [i915#716])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-skl4/igt@gen9_exec_parse@allowed-single.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-skl3/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_dc@dc9-dpms:
- shard-iclb: [PASS][23] -> [SKIP][24] ([i915#4281])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-iclb6/igt@i915_pm_dc@dc9-dpms.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-kbl: [PASS][25] -> [DMESG-WARN][26] ([i915#180])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-kbl6/igt@i915_suspend@fence-restore-tiled2untiled.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-kbl7/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@i915_suspend@forcewake:
- shard-skl: [PASS][27] -> [INCOMPLETE][28] ([i915#636])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-skl6/igt@i915_suspend@forcewake.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-skl7/igt@i915_suspend@forcewake.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-skl: NOTRUN -> [FAIL][29] ([i915#3743]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-skl1/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-tglb: NOTRUN -> [SKIP][30] ([fdo#111615])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-tglb1/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-apl: NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#3777]) +2 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-apl8/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-kbl: NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#3777]) +2 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-kbl6/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-skl: NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#3777]) +4 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-skl1/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][34] ([fdo#109271] / [i915#3886]) +7 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-skl1/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#3886]) +4 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-kbl6/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
- shard-apl: NOTRUN -> [SKIP][36] ([fdo#109271] / [i915#3886]) +3 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-apl8/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_chamelium@dp-hpd-enable-disable-mode:
- shard-tglb: NOTRUN -> [SKIP][37] ([fdo#109284] / [fdo#111827]) +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-tglb1/igt@kms_chamelium@dp-hpd-enable-disable-mode.html
* igt@kms_chamelium@hdmi-hpd-for-each-pipe:
- shard-kbl: NOTRUN -> [SKIP][38] ([fdo#109271] / [fdo#111827]) +8 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-kbl4/igt@kms_chamelium@hdmi-hpd-for-each-pipe.html
* igt@kms_color_chamelium@pipe-a-ctm-0-5:
- shard-apl: NOTRUN -> [SKIP][39] ([fdo#109271] / [fdo#111827]) +6 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-apl8/igt@kms_color_chamelium@pipe-a-ctm-0-5.html
* igt@kms_color_chamelium@pipe-d-degamma:
- shard-skl: NOTRUN -> [SKIP][40] ([fdo#109271] / [fdo#111827]) +13 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-skl1/igt@kms_color_chamelium@pipe-d-degamma.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-skl: NOTRUN -> [INCOMPLETE][41] ([i915#300])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-skl2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_crc@pipe-d-cursor-256x256-rapid-movement:
- shard-iclb: NOTRUN -> [SKIP][42] ([fdo#109278]) +1 similar issue
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-iclb8/igt@kms_cursor_crc@pipe-d-cursor-256x256-rapid-movement.html
* igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions:
- shard-tglb: NOTRUN -> [SKIP][43] ([fdo#109274] / [fdo#111825])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-tglb1/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [PASS][44] -> [INCOMPLETE][45] ([i915#180] / [i915#1982])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-apl8/igt@kms_fbcon_fbt@fbc-suspend.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-apl3/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-edp1:
- shard-skl: [PASS][46] -> [FAIL][47] ([i915#2122])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-skl8/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-edp1.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-skl1/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-apl: [PASS][48] -> [DMESG-WARN][49] ([i915#180]) +1 similar issue
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-apl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
- shard-iclb: [PASS][50] -> [SKIP][51] ([i915#3701])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-iclb8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-skl: NOTRUN -> [SKIP][52] ([fdo#109271]) +165 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-skl1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt:
- shard-tglb: NOTRUN -> [SKIP][53] ([fdo#109280] / [fdo#111825]) +2 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt.html
* igt@kms_hdr@bpc-switch:
- shard-skl: NOTRUN -> [FAIL][54] ([i915#1188])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-skl1/igt@kms_hdr@bpc-switch.html
* igt@kms_hdr@static-toggle-suspend:
- shard-tglb: NOTRUN -> [SKIP][55] ([i915#1187])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-tglb1/igt@kms_hdr@static-toggle-suspend.html
* igt@kms_panel_fitting@legacy:
- shard-kbl: NOTRUN -> [SKIP][56] ([fdo#109271]) +101 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-kbl1/igt@kms_panel_fitting@legacy.html
* igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d:
- shard-apl: NOTRUN -> [SKIP][57] ([fdo#109271] / [i915#533])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-apl8/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
- shard-skl: NOTRUN -> [SKIP][58] ([fdo#109271] / [i915#533]) +2 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-skl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-apl: NOTRUN -> [FAIL][59] ([fdo#108145] / [i915#265])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-apl8/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-skl: NOTRUN -> [FAIL][60] ([fdo#108145] / [i915#265]) +2 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-skl: NOTRUN -> [FAIL][61] ([i915#265])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-kbl: NOTRUN -> [FAIL][62] ([fdo#108145] / [i915#265]) +2 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-kbl4/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
- shard-apl: NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#2733])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-apl8/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
- shard-kbl: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#2733])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-kbl6/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
* igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
- shard-apl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#658])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-apl8/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-skl: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#658])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-skl1/igt@kms_psr2_su@page_flip-nv12.html
* igt@kms_psr@psr2_cursor_blt:
- shard-iclb: [PASS][67] -> [SKIP][68] ([fdo#109441]) +1 similar issue
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-iclb1/igt@kms_psr@psr2_cursor_blt.html
* igt@kms_psr@psr2_sprite_blt:
- shard-iclb: NOTRUN -> [SKIP][69] ([fdo#109441])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-iclb7/igt@kms_psr@psr2_sprite_blt.html
* igt@kms_sysfs_edid_timing:
- shard-apl: NOTRUN -> [FAIL][70] ([IGT#2])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-apl8/igt@kms_sysfs_edid_timing.html
- shard-kbl: NOTRUN -> [FAIL][71] ([IGT#2])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-kbl6/igt@kms_sysfs_edid_timing.html
* igt@kms_vblank@pipe-d-wait-forked-hang:
- shard-apl: NOTRUN -> [SKIP][72] ([fdo#109271]) +71 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-apl8/igt@kms_vblank@pipe-d-wait-forked-hang.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-skl: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#2437])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-skl1/igt@kms_writeback@writeback-invalid-parameters.html
- shard-kbl: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#2437])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-kbl4/igt@kms_writeback@writeback-invalid-parameters.html
* igt@nouveau_crc@ctx-flip-threshold-reset-after-capture:
- shard-iclb: NOTRUN -> [SKIP][75] ([i915#2530])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-iclb8/igt@nouveau_crc@ctx-flip-threshold-reset-after-capture.html
* igt@nouveau_crc@pipe-a-source-outp-inactive:
- shard-tglb: NOTRUN -> [SKIP][76] ([i915#2530]) +1 similar issue
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-tglb1/igt@nouveau_crc@pipe-a-source-outp-inactive.html
* igt@perf@gen8-unprivileged-single-ctx-counters:
- shard-tglb: NOTRUN -> [SKIP][77] ([fdo#109289])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-tglb1/igt@perf@gen8-unprivileged-single-ctx-counters.html
* igt@perf@polling-parameterized:
- shard-glk: [PASS][78] -> [FAIL][79] ([i915#1542])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-glk2/igt@perf@polling-parameterized.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-glk5/igt@perf@polling-parameterized.html
* igt@prime_nv_api@i915_nv_import_twice:
- shard-tglb: NOTRUN -> [SKIP][80] ([fdo#109291])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-tglb2/igt@prime_nv_api@i915_nv_import_twice.html
* igt@sysfs_clients@create:
- shard-apl: NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#2994])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-apl8/igt@sysfs_clients@create.html
- shard-kbl: NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#2994])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-kbl6/igt@sysfs_clients@create.html
* igt@sysfs_clients@fair-1:
- shard-skl: NOTRUN -> [SKIP][83] ([fdo#109271] / [i915#2994])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-skl1/igt@sysfs_clients@fair-1.html
#### Possible fixes ####
* igt@gem_exec_balancer@parallel-balancer:
- shard-iclb: [SKIP][84] ([i915#4525]) -> [PASS][85]
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-iclb3/igt@gem_exec_balancer@parallel-balancer.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-iclb1/igt@gem_exec_balancer@parallel-balancer.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [FAIL][86] ([i915#2842]) -> [PASS][87] +1 similar issue
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-kbl1/igt@gem_exec_fair@basic-none@vcs0.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-kbl6/igt@gem_exec_fair@basic-none@vcs0.html
- shard-apl: [FAIL][88] ([i915#2842]) -> [PASS][89] +1 similar issue
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-apl4/igt@gem_exec_fair@basic-none@vcs0.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-apl1/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- {shard-tglu}: [FAIL][90] ([i915#2842]) -> [PASS][91]
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-tglu-1/igt@gem_exec_fair@basic-pace-share@rcs0.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-tglu-1/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][92] ([i915#2849]) -> [PASS][93]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-iclb8/igt@gem_exec_fair@basic-throttle@rcs0.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-iclb1/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_whisper@basic-queues-forked-all:
- shard-glk: [DMESG-WARN][94] ([i915#118]) -> [PASS][95] +2 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-glk7/igt@gem_exec_whisper@basic-queues-forked-all.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-glk9/igt@gem_exec_whisper@basic-queues-forked-all.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [SKIP][96] ([i915#2190]) -> [PASS][97]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-tglb6/igt@gem_huc_copy@huc-copy.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-tglb8/igt@gem_huc_copy@huc-copy.html
* igt@gem_workarounds@suspend-resume:
- shard-skl: [INCOMPLETE][98] ([i915#4939]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-skl3/igt@gem_workarounds@suspend-resume.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-skl8/igt@gem_workarounds@suspend-resume.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: [DMESG-WARN][100] ([i915#180]) -> [PASS][101] +3 similar issues
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-apl7/igt@i915_suspend@fence-restore-tiled2untiled.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-apl8/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: [FAIL][102] ([i915#2346] / [i915#533]) -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [INCOMPLETE][104] ([i915#180] / [i915#636]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-kbl6/igt@kms_fbcon_fbt@fbc-suspend.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-expired-vblank@b-edp1:
- shard-skl: [FAIL][106] ([i915#79]) -> [PASS][107]
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-skl9/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-skl6/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1:
- shard-glk: [FAIL][108] ([i915#79]) -> [PASS][109]
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-glk1/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-glk4/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl: [DMESG-WARN][110] ([i915#180]) -> [PASS][111] +1 similar issue
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt:
- shard-iclb: [FAIL][112] ([i915#1888] / [i915#2546]) -> [PASS][113]
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt:
- shard-iclb: [FAIL][114] ([i915#1888]) -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-iclb5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-iclb6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [FAIL][116] ([i915#1188]) -> [PASS][117]
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-skl9/igt@kms_hdr@bpc-switch-dpms.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-skl6/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [FAIL][118] ([fdo#108145] / [i915#265]) -> [PASS][119]
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-iclb: [SKIP][120] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [PASS][121]
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-iclb1/igt@kms_psr2_su@frontbuffer-xrgb8888.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-iclb2/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: [SKIP][122] ([fdo#109441]) -> [PASS][123]
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-iclb8/igt@kms_psr@psr2_cursor_plane_move.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-iclb: [SKIP][124] ([i915#4525]) -> [DMESG-WARN][125] ([i915#5076])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-iclb8/igt@gem_exec_balancer@parallel-keep-in-fence.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-iclb1/igt@gem_exec_balancer@parallel-keep-in-fence.html
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [SKIP][126] ([i915#4525]) -> [DMESG-FAIL][127] ([i915#5076])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-iclb6/igt@gem_exec_balancer@parallel-ordering.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-iclb2/igt@gem_exec_balancer@parallel-ordering.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][128], [FAIL][129], [FAIL][130], [FAIL][131], [FAIL][132], [FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136], [FAIL][137], [FAIL][138], [FAIL][139], [FAIL][140]) ([fdo#109271] / [i915#180] / [i915#1814] / [i915#3002] / [i915#4312] / [i915#602] / [i915#92]) -> ([FAIL][141], [FAIL][142], [FAIL][143], [FAIL][144], [FAIL][145], [FAIL][146], [FAIL][147], [FAIL][148], [FAIL][149], [FAIL][150], [FAIL][151]) ([i915#180] / [i915#3002] / [i915#4312])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-kbl1/igt@runner@aborted.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-kbl1/igt@runner@aborted.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-kbl3/igt@runner@aborted.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-kbl6/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-kbl6/igt@runner@aborted.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-kbl7/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-kbl4/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-kbl7/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-kbl7/igt@runner@aborted.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-kbl6/igt@runner@aborted.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-kbl6/igt@runner@aborted.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-kbl4/igt@runner@aborted.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/shard-kbl6/igt@runner@aborted.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-kbl6/igt@runner@aborted.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-kbl6/igt@runner@aborted.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-kbl6/igt@runner@aborted.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-kbl7/igt@runner@aborted.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-kbl7/igt@runner@aborted.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-kbl7/igt@runner@aborted.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-kbl4/igt@runner@aborted.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-kbl1/igt@runner@aborted.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-kbl1/igt@runner@aborted.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/shard-kb
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22244/index.html
[-- Attachment #2: Type: text/html, Size: 33840 bytes --]
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v10 1/6] drm: Add arch arm64 for drm_clflush_virt_range
2022-02-10 18:36 ` [Intel-gfx] " Michael Cheng
@ 2022-02-22 21:49 ` Matt Roper
-1 siblings, 0 replies; 30+ messages in thread
From: Matt Roper @ 2022-02-22 21:49 UTC (permalink / raw)
To: Michael Cheng
Cc: tvrtko.ursulin, balasubramani.vivekanandan, wayne.boyer,
intel-gfx, casey.g.bowman, lucas.demarchi, dri-devel
On Thu, Feb 10, 2022 at 10:36:31AM -0800, Michael Cheng wrote:
> Add arm64 support for drm_clflush_virt_range. dcache_clean_inval_poc
> performs a flush by first performing a clean, follow by an invalidation
> operation.
>
> v2 (Michael Cheng): Use correct macro for cleaning and invalidation the
> dcache.
>
> v3 (Michael Cheng): Remove ifdef for asm/cacheflush.h
>
> v4 (Michael Cheng): Rebase
>
> v5 (Michael Cheng): Replace asm/cacheflush.h with linux/cacheflush.h
Note that you only really need to indicate that you're the one making
these updates in cases where you're picking up someone else's patch and
carrying it forward; otherwise it's pretty clear that you were also the
author of v2-v5.
However when possible it is a good idea to indicate who suggested
various changes you're making. E.g., I think a lot of these were based
on feedback from Tvrtko?
>
> Signed-off-by: Michael Cheng <michael.cheng@intel.com>
Change appears to accurately implement the same type of cache flush as
what we have on the x86 backend.
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/drm_cache.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
> index 66597e411764..2e233f53331e 100644
> --- a/drivers/gpu/drm/drm_cache.c
> +++ b/drivers/gpu/drm/drm_cache.c
> @@ -28,6 +28,7 @@
> * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
> */
>
> +#include <linux/cacheflush.h>
> #include <linux/cc_platform.h>
> #include <linux/export.h>
> #include <linux/highmem.h>
> @@ -174,6 +175,11 @@ drm_clflush_virt_range(void *addr, unsigned long length)
>
> if (wbinvd_on_all_cpus())
> pr_err("Timed out waiting for cache flush\n");
> +
> +#elif defined(CONFIG_ARM64)
> + void *end = addr + length;
> + dcache_clean_inval_poc((unsigned long)addr, (unsigned long)end);
> +
> #else
> WARN_ONCE(1, "Architecture has no drm_cache.c support\n");
> #endif
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Intel-gfx] [PATCH v10 1/6] drm: Add arch arm64 for drm_clflush_virt_range
@ 2022-02-22 21:49 ` Matt Roper
0 siblings, 0 replies; 30+ messages in thread
From: Matt Roper @ 2022-02-22 21:49 UTC (permalink / raw)
To: Michael Cheng; +Cc: intel-gfx, lucas.demarchi, dri-devel
On Thu, Feb 10, 2022 at 10:36:31AM -0800, Michael Cheng wrote:
> Add arm64 support for drm_clflush_virt_range. dcache_clean_inval_poc
> performs a flush by first performing a clean, follow by an invalidation
> operation.
>
> v2 (Michael Cheng): Use correct macro for cleaning and invalidation the
> dcache.
>
> v3 (Michael Cheng): Remove ifdef for asm/cacheflush.h
>
> v4 (Michael Cheng): Rebase
>
> v5 (Michael Cheng): Replace asm/cacheflush.h with linux/cacheflush.h
Note that you only really need to indicate that you're the one making
these updates in cases where you're picking up someone else's patch and
carrying it forward; otherwise it's pretty clear that you were also the
author of v2-v5.
However when possible it is a good idea to indicate who suggested
various changes you're making. E.g., I think a lot of these were based
on feedback from Tvrtko?
>
> Signed-off-by: Michael Cheng <michael.cheng@intel.com>
Change appears to accurately implement the same type of cache flush as
what we have on the x86 backend.
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/drm_cache.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
> index 66597e411764..2e233f53331e 100644
> --- a/drivers/gpu/drm/drm_cache.c
> +++ b/drivers/gpu/drm/drm_cache.c
> @@ -28,6 +28,7 @@
> * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
> */
>
> +#include <linux/cacheflush.h>
> #include <linux/cc_platform.h>
> #include <linux/export.h>
> #include <linux/highmem.h>
> @@ -174,6 +175,11 @@ drm_clflush_virt_range(void *addr, unsigned long length)
>
> if (wbinvd_on_all_cpus())
> pr_err("Timed out waiting for cache flush\n");
> +
> +#elif defined(CONFIG_ARM64)
> + void *end = addr + length;
> + dcache_clean_inval_poc((unsigned long)addr, (unsigned long)end);
> +
> #else
> WARN_ONCE(1, "Architecture has no drm_cache.c support\n");
> #endif
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Intel-gfx] [PATCH v10 2/6] drm/i915/gt: Re-work intel_write_status_page
2022-02-10 18:36 ` [Intel-gfx] " Michael Cheng
@ 2022-02-22 22:04 ` Matt Roper
-1 siblings, 0 replies; 30+ messages in thread
From: Matt Roper @ 2022-02-22 22:04 UTC (permalink / raw)
To: Michael Cheng; +Cc: intel-gfx, lucas.demarchi, dri-devel
On Thu, Feb 10, 2022 at 10:36:32AM -0800, Michael Cheng wrote:
> Re-work intel_write_status_page to use drm_clflush_virt_range. This
> will prevent compiler errors when building for non-x86 architectures.
>
It looks like this will also cause old x86 cpu's that don't have clflush
to do an extra wbinvd that they didn't do before; based on commit
9a29dd85a09d ("drm/i915: Fixup intel_write_status_page() for old CPUs
without clflush") we were just hoping that they were sufficiently
coherent that we can get away without extra flushing.
As far as I can see, this function is only used from a selftest, not
from real driver codepaths, so the extra flushing shouldn't have any
negative impact on end users.
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Michael Cheng <michael.cheng@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine.h | 13 ++++---------
> 1 file changed, 4 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
> index 0e353d8c2bc8..986777c2430d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> @@ -4,6 +4,7 @@
>
> #include <asm/cacheflush.h>
> #include <drm/drm_util.h>
> +#include <drm/drm_cache.h>
>
> #include <linux/hashtable.h>
> #include <linux/irq_work.h>
> @@ -143,15 +144,9 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
> * of extra paranoia to try and ensure that the HWS takes the value
> * we give and that it doesn't end up trapped inside the CPU!
> */
> - if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
> - mb();
> - clflush(&engine->status_page.addr[reg]);
> - engine->status_page.addr[reg] = value;
> - clflush(&engine->status_page.addr[reg]);
> - mb();
> - } else {
> - WRITE_ONCE(engine->status_page.addr[reg], value);
> - }
> + drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value));
> + WRITE_ONCE(engine->status_page.addr[reg], value);
> + drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value));
> }
>
> /*
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v10 2/6] drm/i915/gt: Re-work intel_write_status_page
@ 2022-02-22 22:04 ` Matt Roper
0 siblings, 0 replies; 30+ messages in thread
From: Matt Roper @ 2022-02-22 22:04 UTC (permalink / raw)
To: Michael Cheng
Cc: tvrtko.ursulin, balasubramani.vivekanandan, wayne.boyer,
intel-gfx, casey.g.bowman, lucas.demarchi, dri-devel
On Thu, Feb 10, 2022 at 10:36:32AM -0800, Michael Cheng wrote:
> Re-work intel_write_status_page to use drm_clflush_virt_range. This
> will prevent compiler errors when building for non-x86 architectures.
>
It looks like this will also cause old x86 cpu's that don't have clflush
to do an extra wbinvd that they didn't do before; based on commit
9a29dd85a09d ("drm/i915: Fixup intel_write_status_page() for old CPUs
without clflush") we were just hoping that they were sufficiently
coherent that we can get away without extra flushing.
As far as I can see, this function is only used from a selftest, not
from real driver codepaths, so the extra flushing shouldn't have any
negative impact on end users.
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Michael Cheng <michael.cheng@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine.h | 13 ++++---------
> 1 file changed, 4 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
> index 0e353d8c2bc8..986777c2430d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> @@ -4,6 +4,7 @@
>
> #include <asm/cacheflush.h>
> #include <drm/drm_util.h>
> +#include <drm/drm_cache.h>
>
> #include <linux/hashtable.h>
> #include <linux/irq_work.h>
> @@ -143,15 +144,9 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
> * of extra paranoia to try and ensure that the HWS takes the value
> * we give and that it doesn't end up trapped inside the CPU!
> */
> - if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
> - mb();
> - clflush(&engine->status_page.addr[reg]);
> - engine->status_page.addr[reg] = value;
> - clflush(&engine->status_page.addr[reg]);
> - mb();
> - } else {
> - WRITE_ONCE(engine->status_page.addr[reg], value);
> - }
> + drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value));
> + WRITE_ONCE(engine->status_page.addr[reg], value);
> + drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value));
> }
>
> /*
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v10 3/6] drm/i915/gt: Drop invalidate_csb_entries
2022-02-10 18:36 ` [Intel-gfx] " Michael Cheng
@ 2022-02-22 22:31 ` Matt Roper
-1 siblings, 0 replies; 30+ messages in thread
From: Matt Roper @ 2022-02-22 22:31 UTC (permalink / raw)
To: Michael Cheng
Cc: tvrtko.ursulin, balasubramani.vivekanandan, wayne.boyer,
intel-gfx, casey.g.bowman, lucas.demarchi, dri-devel
On Thu, Feb 10, 2022 at 10:36:33AM -0800, Michael Cheng wrote:
> Drop invalidate_csb_entries and directly call drm_clflush_virt_range.
> This allows for one less function call, and prevent complier errors when
> building for non-x86 architectures.
>
> v2(Michael Cheng): Drop invalidate_csb_entries function and directly
> invoke drm_clflush_virt_range. Thanks to Tvrtko for the
> sugguestion.
>
> v3(Michael Cheng): Use correct parameters for drm_clflush_virt_range.
> Thanks to Tvrtko for pointing this out.
>
> Signed-off-by: Michael Cheng <michael.cheng@intel.com>
> ---
> .../gpu/drm/i915/gt/intel_execlists_submission.c | 13 ++++---------
> 1 file changed, 4 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 9bb7c863172f..6186a5e4b191 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -1646,12 +1646,6 @@ cancel_port_requests(struct intel_engine_execlists * const execlists,
> return inactive;
> }
>
> -static void invalidate_csb_entries(const u64 *first, const u64 *last)
> -{
> - clflush((void *)first);
> - clflush((void *)last);
> -}
> -
> /*
> * Starting with Gen12, the status has a new format:
> *
> @@ -1999,7 +1993,7 @@ process_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
> * the wash as hardware, working or not, will need to do the
> * invalidation before.
> */
> - invalidate_csb_entries(&buf[0], &buf[num_entries - 1]);
> + drm_clflush_virt_range(&buf[0], num_entries * sizeof(buf[0]));
>
> /*
> * We assume that any event reflects a change in context flow
> @@ -2783,8 +2777,9 @@ static void reset_csb_pointers(struct intel_engine_cs *engine)
>
> /* Check that the GPU does indeed update the CSB entries! */
> memset(execlists->csb_status, -1, (reset_value + 1) * sizeof(u64));
> - invalidate_csb_entries(&execlists->csb_status[0],
> - &execlists->csb_status[reset_value]);
> + drm_clflush_virt_range(&execlists->csb_status[0],
I think you could simplify the parameter slightly by just writing it as
'execlists->csb_status'
> + execlists->csb_size *
> + sizeof(execlists->csb_status[0]));
The existing code only issues a clflush for the first and last entries
rather than the range from 0..reset_value, but since there are only a
maximum of 12 u64 entries, which fits into two cachelines, the end
result should be the same either way.
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>
> /* Once more for luck and our trusty paranoia */
> ENGINE_WRITE(engine, RING_CONTEXT_STATUS_PTR,
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Intel-gfx] [PATCH v10 3/6] drm/i915/gt: Drop invalidate_csb_entries
@ 2022-02-22 22:31 ` Matt Roper
0 siblings, 0 replies; 30+ messages in thread
From: Matt Roper @ 2022-02-22 22:31 UTC (permalink / raw)
To: Michael Cheng; +Cc: intel-gfx, lucas.demarchi, dri-devel
On Thu, Feb 10, 2022 at 10:36:33AM -0800, Michael Cheng wrote:
> Drop invalidate_csb_entries and directly call drm_clflush_virt_range.
> This allows for one less function call, and prevent complier errors when
> building for non-x86 architectures.
>
> v2(Michael Cheng): Drop invalidate_csb_entries function and directly
> invoke drm_clflush_virt_range. Thanks to Tvrtko for the
> sugguestion.
>
> v3(Michael Cheng): Use correct parameters for drm_clflush_virt_range.
> Thanks to Tvrtko for pointing this out.
>
> Signed-off-by: Michael Cheng <michael.cheng@intel.com>
> ---
> .../gpu/drm/i915/gt/intel_execlists_submission.c | 13 ++++---------
> 1 file changed, 4 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 9bb7c863172f..6186a5e4b191 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -1646,12 +1646,6 @@ cancel_port_requests(struct intel_engine_execlists * const execlists,
> return inactive;
> }
>
> -static void invalidate_csb_entries(const u64 *first, const u64 *last)
> -{
> - clflush((void *)first);
> - clflush((void *)last);
> -}
> -
> /*
> * Starting with Gen12, the status has a new format:
> *
> @@ -1999,7 +1993,7 @@ process_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
> * the wash as hardware, working or not, will need to do the
> * invalidation before.
> */
> - invalidate_csb_entries(&buf[0], &buf[num_entries - 1]);
> + drm_clflush_virt_range(&buf[0], num_entries * sizeof(buf[0]));
>
> /*
> * We assume that any event reflects a change in context flow
> @@ -2783,8 +2777,9 @@ static void reset_csb_pointers(struct intel_engine_cs *engine)
>
> /* Check that the GPU does indeed update the CSB entries! */
> memset(execlists->csb_status, -1, (reset_value + 1) * sizeof(u64));
> - invalidate_csb_entries(&execlists->csb_status[0],
> - &execlists->csb_status[reset_value]);
> + drm_clflush_virt_range(&execlists->csb_status[0],
I think you could simplify the parameter slightly by just writing it as
'execlists->csb_status'
> + execlists->csb_size *
> + sizeof(execlists->csb_status[0]));
The existing code only issues a clflush for the first and last entries
rather than the range from 0..reset_value, but since there are only a
maximum of 12 u64 entries, which fits into two cachelines, the end
result should be the same either way.
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>
> /* Once more for luck and our trusty paranoia */
> ENGINE_WRITE(engine, RING_CONTEXT_STATUS_PTR,
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v10 4/6] drm/i915/gt: Re-work reset_csb
2022-02-10 18:36 ` [Intel-gfx] " Michael Cheng
@ 2022-02-22 22:35 ` Matt Roper
-1 siblings, 0 replies; 30+ messages in thread
From: Matt Roper @ 2022-02-22 22:35 UTC (permalink / raw)
To: Michael Cheng
Cc: tvrtko.ursulin, balasubramani.vivekanandan, wayne.boyer,
intel-gfx, casey.g.bowman, lucas.demarchi, dri-devel
On Thu, Feb 10, 2022 at 10:36:34AM -0800, Michael Cheng wrote:
> Use drm_clflush_virt_range instead of directly invoking clflush. This
> will prevent compiler errors when building for non-x86 architectures.
>
> v2(Michael Cheng): Remove extra clflush
>
> v3(Michael Cheng): Remove memory barrier since drm_clflush_virt_range
> takes care of it.
>
> Signed-off-by: Michael Cheng <michael.cheng@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 6186a5e4b191..11b864fd68a5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -2945,9 +2945,8 @@ reset_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
> {
> struct intel_engine_execlists * const execlists = &engine->execlists;
>
> - mb(); /* paranoia: read the CSB pointers from after the reset */
> - clflush(execlists->csb_write);
> - mb();
> + drm_clflush_virt_range(execlists->csb_write,
> + sizeof(execlists->csb_write));
I think you technically want sizeof(execlists->csb_write[0]) here,
right? I.e., the size of the value (32-bits), not the size of the
pointer (32 or 64 depending on architecture). Not that it will really
change the behavior since it all works out to a single cacheline in the
end.
Aside from that,
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>
> inactive = process_csb(engine, inactive); /* drain preemption events */
>
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Intel-gfx] [PATCH v10 4/6] drm/i915/gt: Re-work reset_csb
@ 2022-02-22 22:35 ` Matt Roper
0 siblings, 0 replies; 30+ messages in thread
From: Matt Roper @ 2022-02-22 22:35 UTC (permalink / raw)
To: Michael Cheng; +Cc: intel-gfx, lucas.demarchi, dri-devel
On Thu, Feb 10, 2022 at 10:36:34AM -0800, Michael Cheng wrote:
> Use drm_clflush_virt_range instead of directly invoking clflush. This
> will prevent compiler errors when building for non-x86 architectures.
>
> v2(Michael Cheng): Remove extra clflush
>
> v3(Michael Cheng): Remove memory barrier since drm_clflush_virt_range
> takes care of it.
>
> Signed-off-by: Michael Cheng <michael.cheng@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 6186a5e4b191..11b864fd68a5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -2945,9 +2945,8 @@ reset_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
> {
> struct intel_engine_execlists * const execlists = &engine->execlists;
>
> - mb(); /* paranoia: read the CSB pointers from after the reset */
> - clflush(execlists->csb_write);
> - mb();
> + drm_clflush_virt_range(execlists->csb_write,
> + sizeof(execlists->csb_write));
I think you technically want sizeof(execlists->csb_write[0]) here,
right? I.e., the size of the value (32-bits), not the size of the
pointer (32 or 64 depending on architecture). Not that it will really
change the behavior since it all works out to a single cacheline in the
end.
Aside from that,
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>
> inactive = process_csb(engine, inactive); /* drain preemption events */
>
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v10 5/6] drm/i915/: Re-work clflush_write32
2022-02-10 18:36 ` [Intel-gfx] " Michael Cheng
@ 2022-02-22 22:37 ` Matt Roper
-1 siblings, 0 replies; 30+ messages in thread
From: Matt Roper @ 2022-02-22 22:37 UTC (permalink / raw)
To: Michael Cheng
Cc: tvrtko.ursulin, balasubramani.vivekanandan, wayne.boyer,
intel-gfx, casey.g.bowman, lucas.demarchi, dri-devel
On Thu, Feb 10, 2022 at 10:36:35AM -0800, Michael Cheng wrote:
> Use drm_clflush_virt_range instead of clflushopt and remove the memory
> barrier, since drm_clflush_virt_range takes care of that.
>
> Signed-off-by: Michael Cheng <michael.cheng@intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-----
> 1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index 498b458fd784..0854276ff7ba 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -1332,10 +1332,8 @@ static void *reloc_vaddr(struct i915_vma *vma,
> static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
> {
> if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
> - if (flushes & CLFLUSH_BEFORE) {
> - clflushopt(addr);
> - mb();
> - }
> + if (flushes & CLFLUSH_BEFORE)
> + drm_clflush_virt_range(addr, sizeof(addr));
This is another case where it should technically be sizeof(*addr),
although in practice it won't change the behavior.
>
> *addr = value;
>
> @@ -1347,7 +1345,7 @@ static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
> * to ensure ordering of clflush wrt to the system.
> */
> if (flushes & CLFLUSH_AFTER)
> - clflushopt(addr);
> + drm_clflush_virt_range(addr, sizeof(addr));
Ditto.
Aside from those,
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> } else
> *addr = value;
> }
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Intel-gfx] [PATCH v10 5/6] drm/i915/: Re-work clflush_write32
@ 2022-02-22 22:37 ` Matt Roper
0 siblings, 0 replies; 30+ messages in thread
From: Matt Roper @ 2022-02-22 22:37 UTC (permalink / raw)
To: Michael Cheng; +Cc: intel-gfx, lucas.demarchi, dri-devel
On Thu, Feb 10, 2022 at 10:36:35AM -0800, Michael Cheng wrote:
> Use drm_clflush_virt_range instead of clflushopt and remove the memory
> barrier, since drm_clflush_virt_range takes care of that.
>
> Signed-off-by: Michael Cheng <michael.cheng@intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-----
> 1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index 498b458fd784..0854276ff7ba 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -1332,10 +1332,8 @@ static void *reloc_vaddr(struct i915_vma *vma,
> static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
> {
> if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
> - if (flushes & CLFLUSH_BEFORE) {
> - clflushopt(addr);
> - mb();
> - }
> + if (flushes & CLFLUSH_BEFORE)
> + drm_clflush_virt_range(addr, sizeof(addr));
This is another case where it should technically be sizeof(*addr),
although in practice it won't change the behavior.
>
> *addr = value;
>
> @@ -1347,7 +1345,7 @@ static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
> * to ensure ordering of clflush wrt to the system.
> */
> if (flushes & CLFLUSH_AFTER)
> - clflushopt(addr);
> + drm_clflush_virt_range(addr, sizeof(addr));
Ditto.
Aside from those,
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> } else
> *addr = value;
> }
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v10 6/6] drm/i915/gt: replace cache_clflush_range
2022-02-10 18:36 ` [Intel-gfx] " Michael Cheng
@ 2022-02-22 22:40 ` Matt Roper
-1 siblings, 0 replies; 30+ messages in thread
From: Matt Roper @ 2022-02-22 22:40 UTC (permalink / raw)
To: Michael Cheng
Cc: tvrtko.ursulin, balasubramani.vivekanandan, wayne.boyer,
intel-gfx, casey.g.bowman, lucas.demarchi, dri-devel
On Thu, Feb 10, 2022 at 10:36:36AM -0800, Michael Cheng wrote:
> Replace all occurrence of cache_clflush_range with drm_clflush_virt_range.
> This will prevent compile errors on non-x86 platforms.
>
> Signed-off-by: Michael Cheng <michael.cheng@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 12 ++++++------
> drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_ppgtt.c | 2 +-
> drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
> 5 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> index c43e724afa9f..d0999e92621b 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> @@ -444,11 +444,11 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
> pd = pdp->entry[gen8_pd_index(idx, 2)];
> }
>
> - clflush_cache_range(vaddr, PAGE_SIZE);
> + drm_clflush_virt_range(vaddr, PAGE_SIZE);
> vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
> }
> } while (1);
> - clflush_cache_range(vaddr, PAGE_SIZE);
> + drm_clflush_virt_range(vaddr, PAGE_SIZE);
>
> return idx;
> }
> @@ -532,7 +532,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm,
> }
> } while (rem >= page_size && index < I915_PDES);
>
> - clflush_cache_range(vaddr, PAGE_SIZE);
> + drm_clflush_virt_range(vaddr, PAGE_SIZE);
>
> /*
> * Is it safe to mark the 2M block as 64K? -- Either we have
> @@ -548,7 +548,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm,
> I915_GTT_PAGE_SIZE_2M)))) {
> vaddr = px_vaddr(pd);
> vaddr[maybe_64K] |= GEN8_PDE_IPS_64K;
> - clflush_cache_range(vaddr, PAGE_SIZE);
> + drm_clflush_virt_range(vaddr, PAGE_SIZE);
> page_size = I915_GTT_PAGE_SIZE_64K;
>
> /*
> @@ -569,7 +569,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm,
> for (i = 1; i < index; i += 16)
> memset64(vaddr + i, encode, 15);
>
> - clflush_cache_range(vaddr, PAGE_SIZE);
> + drm_clflush_virt_range(vaddr, PAGE_SIZE);
> }
> }
>
> @@ -617,7 +617,7 @@ static void gen8_ppgtt_insert_entry(struct i915_address_space *vm,
>
> vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
> vaddr[gen8_pd_index(idx, 0)] = gen8_pte_encode(addr, level, flags);
> - clflush_cache_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));
> + drm_clflush_virt_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));
> }
>
> static int gen8_init_scratch(struct i915_address_space *vm)
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 11b864fd68a5..67dd4b1fc185 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -2823,7 +2823,7 @@ static void execlists_sanitize(struct intel_engine_cs *engine)
> sanitize_hwsp(engine);
>
> /* And scrub the dirty cachelines for the HWSP */
> - clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
> + drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE);
>
> intel_engine_reset_pinned_contexts(engine);
> }
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
> index 0d6bbc8c57f2..9b594be9102f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
> @@ -255,7 +255,7 @@ fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count)
> void *vaddr = __px_vaddr(p);
>
> memset64(vaddr, val, count);
> - clflush_cache_range(vaddr, PAGE_SIZE);
> + drm_clflush_virt_range(vaddr, PAGE_SIZE);
> }
>
> static void poison_scratch_page(struct drm_i915_gem_object *scratch)
> diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> index 48e6e2f87700..bd474a5123cb 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> @@ -90,7 +90,7 @@ write_dma_entry(struct drm_i915_gem_object * const pdma,
> u64 * const vaddr = __px_vaddr(pdma);
>
> vaddr[idx] = encoded_entry;
> - clflush_cache_range(&vaddr[idx], sizeof(u64));
> + drm_clflush_virt_range(&vaddr[idx], sizeof(u64));
> }
>
> void
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index b3a429a92c0d..89020706adc4 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -3573,7 +3573,7 @@ static void guc_sanitize(struct intel_engine_cs *engine)
> sanitize_hwsp(engine);
>
> /* And scrub the dirty cachelines for the HWSP */
> - clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
> + drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE);
>
> intel_engine_reset_pinned_contexts(engine);
> }
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Intel-gfx] [PATCH v10 6/6] drm/i915/gt: replace cache_clflush_range
@ 2022-02-22 22:40 ` Matt Roper
0 siblings, 0 replies; 30+ messages in thread
From: Matt Roper @ 2022-02-22 22:40 UTC (permalink / raw)
To: Michael Cheng; +Cc: intel-gfx, lucas.demarchi, dri-devel
On Thu, Feb 10, 2022 at 10:36:36AM -0800, Michael Cheng wrote:
> Replace all occurrence of cache_clflush_range with drm_clflush_virt_range.
> This will prevent compile errors on non-x86 platforms.
>
> Signed-off-by: Michael Cheng <michael.cheng@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 12 ++++++------
> drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_ppgtt.c | 2 +-
> drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
> 5 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> index c43e724afa9f..d0999e92621b 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> @@ -444,11 +444,11 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
> pd = pdp->entry[gen8_pd_index(idx, 2)];
> }
>
> - clflush_cache_range(vaddr, PAGE_SIZE);
> + drm_clflush_virt_range(vaddr, PAGE_SIZE);
> vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
> }
> } while (1);
> - clflush_cache_range(vaddr, PAGE_SIZE);
> + drm_clflush_virt_range(vaddr, PAGE_SIZE);
>
> return idx;
> }
> @@ -532,7 +532,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm,
> }
> } while (rem >= page_size && index < I915_PDES);
>
> - clflush_cache_range(vaddr, PAGE_SIZE);
> + drm_clflush_virt_range(vaddr, PAGE_SIZE);
>
> /*
> * Is it safe to mark the 2M block as 64K? -- Either we have
> @@ -548,7 +548,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm,
> I915_GTT_PAGE_SIZE_2M)))) {
> vaddr = px_vaddr(pd);
> vaddr[maybe_64K] |= GEN8_PDE_IPS_64K;
> - clflush_cache_range(vaddr, PAGE_SIZE);
> + drm_clflush_virt_range(vaddr, PAGE_SIZE);
> page_size = I915_GTT_PAGE_SIZE_64K;
>
> /*
> @@ -569,7 +569,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm,
> for (i = 1; i < index; i += 16)
> memset64(vaddr + i, encode, 15);
>
> - clflush_cache_range(vaddr, PAGE_SIZE);
> + drm_clflush_virt_range(vaddr, PAGE_SIZE);
> }
> }
>
> @@ -617,7 +617,7 @@ static void gen8_ppgtt_insert_entry(struct i915_address_space *vm,
>
> vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
> vaddr[gen8_pd_index(idx, 0)] = gen8_pte_encode(addr, level, flags);
> - clflush_cache_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));
> + drm_clflush_virt_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));
> }
>
> static int gen8_init_scratch(struct i915_address_space *vm)
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 11b864fd68a5..67dd4b1fc185 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -2823,7 +2823,7 @@ static void execlists_sanitize(struct intel_engine_cs *engine)
> sanitize_hwsp(engine);
>
> /* And scrub the dirty cachelines for the HWSP */
> - clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
> + drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE);
>
> intel_engine_reset_pinned_contexts(engine);
> }
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
> index 0d6bbc8c57f2..9b594be9102f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
> @@ -255,7 +255,7 @@ fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count)
> void *vaddr = __px_vaddr(p);
>
> memset64(vaddr, val, count);
> - clflush_cache_range(vaddr, PAGE_SIZE);
> + drm_clflush_virt_range(vaddr, PAGE_SIZE);
> }
>
> static void poison_scratch_page(struct drm_i915_gem_object *scratch)
> diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> index 48e6e2f87700..bd474a5123cb 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> @@ -90,7 +90,7 @@ write_dma_entry(struct drm_i915_gem_object * const pdma,
> u64 * const vaddr = __px_vaddr(pdma);
>
> vaddr[idx] = encoded_entry;
> - clflush_cache_range(&vaddr[idx], sizeof(u64));
> + drm_clflush_virt_range(&vaddr[idx], sizeof(u64));
> }
>
> void
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index b3a429a92c0d..89020706adc4 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -3573,7 +3573,7 @@ static void guc_sanitize(struct intel_engine_cs *engine)
> sanitize_hwsp(engine);
>
> /* And scrub the dirty cachelines for the HWSP */
> - clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
> + drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE);
>
> intel_engine_reset_pinned_contexts(engine);
> }
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 30+ messages in thread
end of thread, other threads:[~2022-02-22 22:40 UTC | newest]
Thread overview: 30+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-02-10 18:36 [PATCH v10 0/6] Use drm_clflush* instead of clflush Michael Cheng
2022-02-10 18:36 ` [Intel-gfx] " Michael Cheng
2022-02-10 18:36 ` [PATCH v10 1/6] drm: Add arch arm64 for drm_clflush_virt_range Michael Cheng
2022-02-10 18:36 ` [Intel-gfx] " Michael Cheng
2022-02-22 21:49 ` Matt Roper
2022-02-22 21:49 ` [Intel-gfx] " Matt Roper
2022-02-10 18:36 ` [PATCH v10 2/6] drm/i915/gt: Re-work intel_write_status_page Michael Cheng
2022-02-10 18:36 ` [Intel-gfx] " Michael Cheng
2022-02-22 22:04 ` Matt Roper
2022-02-22 22:04 ` Matt Roper
2022-02-10 18:36 ` [PATCH v10 3/6] drm/i915/gt: Drop invalidate_csb_entries Michael Cheng
2022-02-10 18:36 ` [Intel-gfx] " Michael Cheng
2022-02-22 22:31 ` Matt Roper
2022-02-22 22:31 ` [Intel-gfx] " Matt Roper
2022-02-10 18:36 ` [PATCH v10 4/6] drm/i915/gt: Re-work reset_csb Michael Cheng
2022-02-10 18:36 ` [Intel-gfx] " Michael Cheng
2022-02-22 22:35 ` Matt Roper
2022-02-22 22:35 ` [Intel-gfx] " Matt Roper
2022-02-10 18:36 ` [PATCH v10 5/6] drm/i915/: Re-work clflush_write32 Michael Cheng
2022-02-10 18:36 ` [Intel-gfx] " Michael Cheng
2022-02-22 22:37 ` Matt Roper
2022-02-22 22:37 ` [Intel-gfx] " Matt Roper
2022-02-10 18:36 ` [PATCH v10 6/6] drm/i915/gt: replace cache_clflush_range Michael Cheng
2022-02-10 18:36 ` [Intel-gfx] " Michael Cheng
2022-02-22 22:40 ` Matt Roper
2022-02-22 22:40 ` [Intel-gfx] " Matt Roper
2022-02-10 19:07 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Use drm_clflush* instead of clflush (rev9) Patchwork
2022-02-10 19:08 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-02-10 19:34 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-02-10 23:22 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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