From: Atish Patra <atishp@rivosinc.com> To: linux-kernel@vger.kernel.org Cc: Atish Patra <atishp@rivosinc.com>, Albert Ou <aou@eecs.berkeley.edu>, Atish Patra <atishp@atishpatra.org>, Anup Patel <anup@brainfault.org>, Damien Le Moal <damien.lemoal@wdc.com>, devicetree@vger.kernel.org, Jisheng Zhang <jszhang@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>, linux-riscv@lists.infradead.org, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Rob Herring <robh+dt@kernel.org> Subject: [PATCH v2 6/6] RISC-V: Improve /proc/cpuinfo output for ISA extensions Date: Thu, 10 Feb 2022 13:40:18 -0800 [thread overview] Message-ID: <20220210214018.55739-7-atishp@rivosinc.com> (raw) In-Reply-To: <20220210214018.55739-1-atishp@rivosinc.com> Currently, the /proc/cpuinfo outputs the entire riscv,isa string which is not ideal when we have multiple ISA extensions present in the ISA string. Some of them may not be enabled in kernel as well. Parse only the enabled ISA extension and print them in a separate row. Signed-off-by: Atish Patra <atishp@rivosinc.com> --- arch/riscv/include/asm/hwcap.h | 7 ++++++ arch/riscv/kernel/cpu.c | 44 ++++++++++++++++++++++++++++++++-- 2 files changed, 49 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 170bd80da520..691fc9c8099b 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -54,6 +54,13 @@ enum riscv_isa_ext_id { RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, }; +struct riscv_isa_ext_data { + /* Name of the extension displayed to userspace via /proc/cpuinfo */ + char uprop[RISCV_ISA_EXT_NAME_LEN_MAX]; + /* The logical ISA extension ID */ + unsigned int isa_ext_id; +}; + unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index ad0a7e9f828b..ced7e5be8641 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -6,6 +6,7 @@ #include <linux/init.h> #include <linux/seq_file.h> #include <linux/of.h> +#include <asm/hwcap.h> #include <asm/smp.h> #include <asm/pgtable.h> @@ -63,12 +64,50 @@ int riscv_of_parent_hartid(struct device_node *node) } #ifdef CONFIG_PROC_FS +#define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \ + { \ + .uprop = #UPROP, \ + .isa_ext_id = EXTID, \ + } + +static struct riscv_isa_ext_data isa_ext_arr[] = { + __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), +}; + +static void print_isa_ext(struct seq_file *f) +{ + struct riscv_isa_ext_data *edata; + int i = 0, arr_sz; + + arr_sz = ARRAY_SIZE(isa_ext_arr) - 1; + + /* No extension support available */ + if (arr_sz <= 0) + return; + + seq_puts(f, "isa-ext\t\t: "); + for (i = 0; i <= arr_sz; i++) { + edata = &isa_ext_arr[i]; + if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id)) + continue; + seq_printf(f, "%s ", edata->uprop); + } + seq_puts(f, "\n"); +} static void print_isa(struct seq_file *f, const char *isa) { - /* Print the entire ISA as it is */ + char *ext_start; + int isa_len = strlen(isa); + int base_isa_len = isa_len; + + ext_start = strnchr(isa, isa_len, '_'); + if (ext_start) + base_isa_len = isa_len - strlen(ext_start); + + /* Print only the base ISA as it is */ seq_puts(f, "isa\t\t: "); - seq_write(f, isa, strlen(isa)); + seq_write(f, isa, base_isa_len); seq_puts(f, "\n"); } @@ -115,6 +154,7 @@ static int c_show(struct seq_file *m, void *v) seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id)); if (!of_property_read_string(node, "riscv,isa", &isa)) print_isa(m, isa); + print_isa_ext(m); print_mmu(m); if (!of_property_read_string(node, "compatible", &compat) && strcmp(compat, "riscv")) -- 2.30.2
WARNING: multiple messages have this Message-ID (diff)
From: Atish Patra <atishp@rivosinc.com> To: linux-kernel@vger.kernel.org Cc: Atish Patra <atishp@rivosinc.com>, Albert Ou <aou@eecs.berkeley.edu>, Atish Patra <atishp@atishpatra.org>, Anup Patel <anup@brainfault.org>, Damien Le Moal <damien.lemoal@wdc.com>, devicetree@vger.kernel.org, Jisheng Zhang <jszhang@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>, linux-riscv@lists.infradead.org, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Rob Herring <robh+dt@kernel.org> Subject: [PATCH v2 6/6] RISC-V: Improve /proc/cpuinfo output for ISA extensions Date: Thu, 10 Feb 2022 13:40:18 -0800 [thread overview] Message-ID: <20220210214018.55739-7-atishp@rivosinc.com> (raw) In-Reply-To: <20220210214018.55739-1-atishp@rivosinc.com> Currently, the /proc/cpuinfo outputs the entire riscv,isa string which is not ideal when we have multiple ISA extensions present in the ISA string. Some of them may not be enabled in kernel as well. Parse only the enabled ISA extension and print them in a separate row. Signed-off-by: Atish Patra <atishp@rivosinc.com> --- arch/riscv/include/asm/hwcap.h | 7 ++++++ arch/riscv/kernel/cpu.c | 44 ++++++++++++++++++++++++++++++++-- 2 files changed, 49 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 170bd80da520..691fc9c8099b 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -54,6 +54,13 @@ enum riscv_isa_ext_id { RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, }; +struct riscv_isa_ext_data { + /* Name of the extension displayed to userspace via /proc/cpuinfo */ + char uprop[RISCV_ISA_EXT_NAME_LEN_MAX]; + /* The logical ISA extension ID */ + unsigned int isa_ext_id; +}; + unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index ad0a7e9f828b..ced7e5be8641 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -6,6 +6,7 @@ #include <linux/init.h> #include <linux/seq_file.h> #include <linux/of.h> +#include <asm/hwcap.h> #include <asm/smp.h> #include <asm/pgtable.h> @@ -63,12 +64,50 @@ int riscv_of_parent_hartid(struct device_node *node) } #ifdef CONFIG_PROC_FS +#define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \ + { \ + .uprop = #UPROP, \ + .isa_ext_id = EXTID, \ + } + +static struct riscv_isa_ext_data isa_ext_arr[] = { + __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), +}; + +static void print_isa_ext(struct seq_file *f) +{ + struct riscv_isa_ext_data *edata; + int i = 0, arr_sz; + + arr_sz = ARRAY_SIZE(isa_ext_arr) - 1; + + /* No extension support available */ + if (arr_sz <= 0) + return; + + seq_puts(f, "isa-ext\t\t: "); + for (i = 0; i <= arr_sz; i++) { + edata = &isa_ext_arr[i]; + if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id)) + continue; + seq_printf(f, "%s ", edata->uprop); + } + seq_puts(f, "\n"); +} static void print_isa(struct seq_file *f, const char *isa) { - /* Print the entire ISA as it is */ + char *ext_start; + int isa_len = strlen(isa); + int base_isa_len = isa_len; + + ext_start = strnchr(isa, isa_len, '_'); + if (ext_start) + base_isa_len = isa_len - strlen(ext_start); + + /* Print only the base ISA as it is */ seq_puts(f, "isa\t\t: "); - seq_write(f, isa, strlen(isa)); + seq_write(f, isa, base_isa_len); seq_puts(f, "\n"); } @@ -115,6 +154,7 @@ static int c_show(struct seq_file *m, void *v) seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id)); if (!of_property_read_string(node, "riscv,isa", &isa)) print_isa(m, isa); + print_isa_ext(m); print_mmu(m); if (!of_property_read_string(node, "compatible", &compat) && strcmp(compat, "riscv")) -- 2.30.2 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-02-10 21:40 UTC|newest] Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-02-10 21:40 [PATCH v2 0/6] Provide a fraemework for RISC-V ISA extensions Atish Patra 2022-02-10 21:40 ` Atish Patra 2022-02-10 21:40 ` [PATCH v2 1/6] RISC-V: Correctly print supported extensions Atish Patra 2022-02-10 21:40 ` Atish Patra 2022-02-10 21:40 ` [PATCH v2 2/6] RISC-V: Minimal parser for "riscv, isa" strings Atish Patra 2022-02-10 21:40 ` Atish Patra 2022-02-12 6:25 ` Tsukasa OI 2022-02-12 6:29 ` [PATCH v3 1/3] RISC-V: Correctly print supported extensions Tsukasa OI 2022-02-14 20:04 ` Heiko Stübner 2022-02-12 6:30 ` [PATCH v3 2/3] RISC-V: Minimal parser for "riscv, isa" strings Tsukasa OI 2022-02-14 20:04 ` Heiko Stübner 2022-02-12 6:30 ` [PATCH v3 3/3] RISC-V: Extract multi-letter extension names from "riscv, isa" Tsukasa OI 2022-02-14 20:04 ` Heiko Stübner 2022-02-14 20:07 ` [PATCH v2 2/6] RISC-V: Minimal parser for "riscv, isa" strings Atish Patra 2022-02-15 3:27 ` Tsukasa OI 2022-02-15 7:36 ` Atish Patra 2022-02-10 21:40 ` [PATCH v2 3/6] RISC-V: Extract multi-letter extension names from "riscv,isa" Atish Patra 2022-02-10 21:40 ` [PATCH v2 3/6] RISC-V: Extract multi-letter extension names from "riscv, isa" Atish Patra 2022-02-10 21:40 ` [PATCH v2 4/6] RISC-V: Implement multi-letter ISA extension probing framework Atish Patra 2022-02-10 21:40 ` Atish Patra 2022-02-14 20:05 ` Heiko Stübner 2022-02-14 20:05 ` Heiko Stübner 2022-02-14 20:14 ` Atish Patra 2022-02-14 20:14 ` Atish Patra 2022-02-14 20:24 ` Heiko Stübner 2022-02-14 20:24 ` Heiko Stübner 2022-02-14 20:42 ` Atish Patra 2022-02-14 20:42 ` Atish Patra 2022-02-14 22:22 ` Heiko Stübner 2022-02-14 22:22 ` Heiko Stübner 2022-02-14 23:22 ` Atish Kumar Patra 2022-02-14 23:22 ` Atish Kumar Patra 2022-02-15 9:12 ` Atish Kumar Patra 2022-02-15 9:12 ` Atish Kumar Patra 2022-02-15 9:48 ` Heiko Stübner 2022-02-15 9:48 ` Heiko Stübner 2022-02-15 9:50 ` Heiko Stübner 2022-02-15 9:50 ` Heiko Stübner 2022-02-16 0:47 ` Atish Kumar Patra 2022-02-16 0:47 ` Atish Kumar Patra 2022-02-10 21:40 ` [PATCH v2 5/6] RISC-V: Do no continue isa string parsing without correct XLEN Atish Patra 2022-02-10 21:40 ` Atish Patra 2022-02-10 21:58 ` Andreas Schwab 2022-02-10 21:58 ` Andreas Schwab 2022-02-11 12:52 ` Geert Uytterhoeven 2022-02-11 12:52 ` Geert Uytterhoeven 2022-02-14 20:15 ` Atish Patra 2022-02-14 20:15 ` Atish Patra 2022-02-14 20:06 ` Heiko Stübner 2022-02-14 20:06 ` Heiko Stübner 2022-02-10 21:40 ` Atish Patra [this message] 2022-02-10 21:40 ` [PATCH v2 6/6] RISC-V: Improve /proc/cpuinfo output for ISA extensions Atish Patra 2022-02-14 20:07 ` Heiko Stübner 2022-02-14 20:07 ` Heiko Stübner
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