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From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Weiwei Li <liweiwei@iscas.ac.cn>,
	Junqiang Wang <wangjunqiang@iscas.ac.cn>,
	Anup Patel <anup@brainfault.org>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 39/40] target/riscv: add support for svpbmt extension
Date: Sat, 12 Feb 2022 10:00:30 +1000	[thread overview]
Message-ID: <20220212000031.3946524-40-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220212000031.3946524-1-alistair.francis@opensource.wdc.com>

From: Weiwei Li <liweiwei@iscas.ac.cn>

- add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently
- add PTE_PBMT bit check for inner PTE

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220204022658.18097-6-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_bits.h   | 2 ++
 target/riscv/cpu.c        | 1 +
 target/riscv/cpu_helper.c | 4 +++-
 3 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 37ed4da72c..0fe01d7da5 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -561,7 +561,9 @@ typedef enum {
 #define PTE_A               0x040 /* Accessed */
 #define PTE_D               0x080 /* Dirty */
 #define PTE_SOFT            0x300 /* Reserved for Software */
+#define PTE_PBMT            0x6000000000000000ULL /* Page-based memory types */
 #define PTE_N               0x8000000000000000ULL /* NAPOT translation */
+#define PTE_ATTR            (PTE_N | PTE_PBMT) /* All attributes bits */
 
 /* Page table PPN shift amount */
 #define PTE_PPN_SHIFT       10
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e5676b40d1..b0a40b83e7 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -776,6 +776,7 @@ static Property riscv_cpu_properties[] = {
 
     DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
     DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
+    DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
 
     DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
     DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 437c9488a6..746335bfd6 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -937,9 +937,11 @@ restart:
         if (!(pte & PTE_V)) {
             /* Invalid PTE */
             return TRANSLATE_FAIL;
+        } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) {
+            return TRANSLATE_FAIL;
         } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
             /* Inner PTE, continue walking */
-            if (pte & (PTE_D | PTE_A | PTE_U | PTE_N)) {
+            if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) {
                 return TRANSLATE_FAIL;
             }
             base = ppn << PGSHIFT;
-- 
2.34.1



  parent reply	other threads:[~2022-02-12  1:14 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-11 23:59 [PULL 00/40] riscv-to-apply queue Alistair Francis
2022-02-11 23:59 ` [PULL 01/40] include: hw: remove ibex_plic.h Alistair Francis
2022-02-11 23:59 ` [PULL 02/40] Allow setting up to 8 bytes with the generic loader Alistair Francis
2022-02-11 23:59 ` [PULL 03/40] target/riscv: correct "code should not be reached" for x-rv128 Alistair Francis
2022-02-11 23:59 ` [PULL 04/40] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' Alistair Francis
2022-02-11 23:59 ` [PULL 05/40] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr Alistair Francis
2022-02-11 23:59 ` [PULL 06/40] target/riscv: access configuration through cfg_ptr in DisasContext Alistair Francis
2022-02-11 23:59 ` [PULL 07/40] target/riscv: access cfg structure through DisasContext Alistair Francis
2022-02-11 23:59 ` [PULL 08/40] target/riscv: iterate over a table of decoders Alistair Francis
2022-02-12  0:00 ` [PULL 09/40] target/riscv: Add XVentanaCondOps custom extension Alistair Francis
2022-02-12  0:00 ` [PULL 10/40] target/riscv: add a MAINTAINERS entry for XVentanaCondOps Alistair Francis
2022-02-12  0:00 ` [PULL 11/40] target/riscv: Fix vill field write in vtype Alistair Francis
2022-02-12  0:00 ` [PULL 12/40] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode Alistair Francis
2022-02-12  0:00 ` [PULL 13/40] target/riscv: Implement SGEIP bit in hip and hie CSRs Alistair Francis
2022-02-12  0:00 ` [PULL 14/40] target/riscv: Implement hgeie and hgeip CSRs Alistair Francis
2022-02-12  0:00 ` [PULL 15/40] target/riscv: Improve delivery of guest external interrupts Alistair Francis
2022-02-12  0:00 ` [PULL 16/40] target/riscv: Allow setting CPU feature from machine/device emulation Alistair Francis
2022-02-12  0:00 ` [PULL 17/40] target/riscv: Add AIA cpu feature Alistair Francis
2022-02-12  0:00 ` [PULL 18/40] target/riscv: Add defines for AIA CSRs Alistair Francis
2022-02-12  0:00 ` [PULL 19/40] target/riscv: Allow AIA device emulation to set ireg rmw callback Alistair Francis
2022-02-12  0:00 ` [PULL 20/40] target/riscv: Implement AIA local interrupt priorities Alistair Francis
2022-02-12  0:00 ` [PULL 21/40] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 Alistair Francis
2022-02-12  0:00 ` [PULL 22/40] target/riscv: Implement AIA hvictl and hviprioX CSRs Alistair Francis
2022-02-12  0:00 ` [PULL 23/40] target/riscv: Implement AIA interrupt filtering CSRs Alistair Francis
2022-02-12  0:00 ` [PULL 24/40] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs Alistair Francis
2022-02-12  0:00 ` [PULL 25/40] target/riscv: Implement AIA xiselect and xireg CSRs Alistair Francis
2022-02-12  0:00 ` [PULL 26/40] target/riscv: Implement AIA IMSIC interface CSRs Alistair Francis
2022-02-12  0:00 ` [PULL 27/40] hw/riscv: virt: Use AIA INTC compatible string when available Alistair Francis
2022-02-12  0:00 ` [PULL 28/40] target/riscv: Allow users to force enable AIA CSRs in HART Alistair Francis
2022-02-12  0:00 ` [PULL 29/40] hw/intc: Add RISC-V AIA APLIC device emulation Alistair Francis
2022-02-12  0:00 ` [PULL 30/40] hw/riscv: virt: Add optional AIA APLIC support to virt machine Alistair Francis
2022-02-12  0:00 ` [PULL 31/40] hw/intc: Add RISC-V AIA IMSIC device emulation Alistair Francis
2022-02-12  0:00 ` [PULL 32/40] hw/riscv: virt: Add optional AIA IMSIC support to virt machine Alistair Francis
2022-02-12  0:00 ` [PULL 33/40] docs/system: riscv: Document AIA options for " Alistair Francis
2022-02-12  0:00 ` [PULL 34/40] hw/riscv: virt: Increase maximum number of allowed CPUs Alistair Francis
2022-02-12  0:00 ` [PULL 35/40] target/riscv: Ignore reserved bits in PTE for RV64 Alistair Francis
2022-02-12  0:00 ` [PULL 36/40] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE Alistair Francis
2022-02-12  0:00 ` [PULL 37/40] target/riscv: add support for svnapot extension Alistair Francis
2022-02-12  0:00 ` [PULL 38/40] target/riscv: add support for svinval extension Alistair Francis
2022-02-12  0:00 ` Alistair Francis [this message]
2022-02-12  0:00 ` [PULL 40/40] docs/system: riscv: Update description of CPU Alistair Francis
2022-02-15 11:39 ` [PULL 00/40] riscv-to-apply queue Peter Maydell
2022-02-16  6:28   ` Alistair Francis
2022-02-16  6:45     ` Anup Patel

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