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From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Yu Li <liyu.yukiteru@bytedance.com>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 40/40] docs/system: riscv: Update description of CPU
Date: Sat, 12 Feb 2022 10:00:31 +1000	[thread overview]
Message-ID: <20220212000031.3946524-41-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220212000031.3946524-1-alistair.francis@opensource.wdc.com>

From: Yu Li <liyu.yukiteru@bytedance.com>

Since the hypervisor extension been non experimental and enabled for
default CPU, the previous command is no longer available and the
option `x-h=true` or `h=true` is also no longer required.

Signed-off-by: Yu Li <liyu.yukiteru@bytedance.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <9040401e-8f87-ef4a-d840-6703f08d068c@bytedance.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 docs/system/riscv/virt.rst | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst
index 373645513a..1272b6659e 100644
--- a/docs/system/riscv/virt.rst
+++ b/docs/system/riscv/virt.rst
@@ -23,9 +23,9 @@ The ``virt`` machine supports the following devices:
 * 1 generic PCIe host bridge
 * The fw_cfg device that allows a guest to obtain data from QEMU
 
-Note that the default CPU is a generic RV32GC/RV64GC. Optional extensions
-can be enabled via command line parameters, e.g.: ``-cpu rv64,x-h=true``
-enables the hypervisor extension for RV64.
+The hypervisor extension has been enabled for the default CPU, so virtual
+machines with hypervisor extension can simply be used without explicitly
+declaring.
 
 Hardware configuration information
 ----------------------------------
-- 
2.34.1



  parent reply	other threads:[~2022-02-12  1:15 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-11 23:59 [PULL 00/40] riscv-to-apply queue Alistair Francis
2022-02-11 23:59 ` [PULL 01/40] include: hw: remove ibex_plic.h Alistair Francis
2022-02-11 23:59 ` [PULL 02/40] Allow setting up to 8 bytes with the generic loader Alistair Francis
2022-02-11 23:59 ` [PULL 03/40] target/riscv: correct "code should not be reached" for x-rv128 Alistair Francis
2022-02-11 23:59 ` [PULL 04/40] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' Alistair Francis
2022-02-11 23:59 ` [PULL 05/40] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr Alistair Francis
2022-02-11 23:59 ` [PULL 06/40] target/riscv: access configuration through cfg_ptr in DisasContext Alistair Francis
2022-02-11 23:59 ` [PULL 07/40] target/riscv: access cfg structure through DisasContext Alistair Francis
2022-02-11 23:59 ` [PULL 08/40] target/riscv: iterate over a table of decoders Alistair Francis
2022-02-12  0:00 ` [PULL 09/40] target/riscv: Add XVentanaCondOps custom extension Alistair Francis
2022-02-12  0:00 ` [PULL 10/40] target/riscv: add a MAINTAINERS entry for XVentanaCondOps Alistair Francis
2022-02-12  0:00 ` [PULL 11/40] target/riscv: Fix vill field write in vtype Alistair Francis
2022-02-12  0:00 ` [PULL 12/40] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode Alistair Francis
2022-02-12  0:00 ` [PULL 13/40] target/riscv: Implement SGEIP bit in hip and hie CSRs Alistair Francis
2022-02-12  0:00 ` [PULL 14/40] target/riscv: Implement hgeie and hgeip CSRs Alistair Francis
2022-02-12  0:00 ` [PULL 15/40] target/riscv: Improve delivery of guest external interrupts Alistair Francis
2022-02-12  0:00 ` [PULL 16/40] target/riscv: Allow setting CPU feature from machine/device emulation Alistair Francis
2022-02-12  0:00 ` [PULL 17/40] target/riscv: Add AIA cpu feature Alistair Francis
2022-02-12  0:00 ` [PULL 18/40] target/riscv: Add defines for AIA CSRs Alistair Francis
2022-02-12  0:00 ` [PULL 19/40] target/riscv: Allow AIA device emulation to set ireg rmw callback Alistair Francis
2022-02-12  0:00 ` [PULL 20/40] target/riscv: Implement AIA local interrupt priorities Alistair Francis
2022-02-12  0:00 ` [PULL 21/40] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 Alistair Francis
2022-02-12  0:00 ` [PULL 22/40] target/riscv: Implement AIA hvictl and hviprioX CSRs Alistair Francis
2022-02-12  0:00 ` [PULL 23/40] target/riscv: Implement AIA interrupt filtering CSRs Alistair Francis
2022-02-12  0:00 ` [PULL 24/40] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs Alistair Francis
2022-02-12  0:00 ` [PULL 25/40] target/riscv: Implement AIA xiselect and xireg CSRs Alistair Francis
2022-02-12  0:00 ` [PULL 26/40] target/riscv: Implement AIA IMSIC interface CSRs Alistair Francis
2022-02-12  0:00 ` [PULL 27/40] hw/riscv: virt: Use AIA INTC compatible string when available Alistair Francis
2022-02-12  0:00 ` [PULL 28/40] target/riscv: Allow users to force enable AIA CSRs in HART Alistair Francis
2022-02-12  0:00 ` [PULL 29/40] hw/intc: Add RISC-V AIA APLIC device emulation Alistair Francis
2022-02-12  0:00 ` [PULL 30/40] hw/riscv: virt: Add optional AIA APLIC support to virt machine Alistair Francis
2022-02-12  0:00 ` [PULL 31/40] hw/intc: Add RISC-V AIA IMSIC device emulation Alistair Francis
2022-02-12  0:00 ` [PULL 32/40] hw/riscv: virt: Add optional AIA IMSIC support to virt machine Alistair Francis
2022-02-12  0:00 ` [PULL 33/40] docs/system: riscv: Document AIA options for " Alistair Francis
2022-02-12  0:00 ` [PULL 34/40] hw/riscv: virt: Increase maximum number of allowed CPUs Alistair Francis
2022-02-12  0:00 ` [PULL 35/40] target/riscv: Ignore reserved bits in PTE for RV64 Alistair Francis
2022-02-12  0:00 ` [PULL 36/40] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE Alistair Francis
2022-02-12  0:00 ` [PULL 37/40] target/riscv: add support for svnapot extension Alistair Francis
2022-02-12  0:00 ` [PULL 38/40] target/riscv: add support for svinval extension Alistair Francis
2022-02-12  0:00 ` [PULL 39/40] target/riscv: add support for svpbmt extension Alistair Francis
2022-02-12  0:00 ` Alistair Francis [this message]
2022-02-15 11:39 ` [PULL 00/40] riscv-to-apply queue Peter Maydell
2022-02-16  6:28   ` Alistair Francis
2022-02-16  6:45     ` Anup Patel

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