* [PATCH 1/2] opensbi: Upgrade to 1.0
@ 2022-02-14 23:37 Khem Raj
2022-02-14 23:37 ` [PATCH 2/2] u-boot: Fix RISCV build with binutils 2.38 Khem Raj
2022-02-15 22:27 ` [OE-core] [PATCH 1/2] opensbi: Upgrade to 1.0 Alistair Francis
0 siblings, 2 replies; 3+ messages in thread
From: Khem Raj @ 2022-02-14 23:37 UTC (permalink / raw)
To: openembedded-core; +Cc: Khem Raj, Alistair Francis
Drop OE specific patch to shunt march/mabi
this seems to work fine now.
unset CLANG_TARGET so it can compile with OE produced clang toolchain
which provides --target itself
Signed-off-by: Khem Raj <raj.khem@gmail.com>
Cc: Alistair Francis <alistair.francis@wdc.com>
---
...Makefile-Don-t-specify-mabi-or-march.patch | 36 -------------------
.../{opensbi_0.9.bb => opensbi_1.0.bb} | 5 ++-
2 files changed, 2 insertions(+), 39 deletions(-)
delete mode 100644 meta/recipes-bsp/opensbi/files/0001-Makefile-Don-t-specify-mabi-or-march.patch
rename meta/recipes-bsp/opensbi/{opensbi_0.9.bb => opensbi_1.0.bb} (91%)
diff --git a/meta/recipes-bsp/opensbi/files/0001-Makefile-Don-t-specify-mabi-or-march.patch b/meta/recipes-bsp/opensbi/files/0001-Makefile-Don-t-specify-mabi-or-march.patch
deleted file mode 100644
index d2a8048e87e..00000000000
--- a/meta/recipes-bsp/opensbi/files/0001-Makefile-Don-t-specify-mabi-or-march.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From fe9860fd85e49a75bef545e5d9914070491e8002 Mon Sep 17 00:00:00 2001
-From: Alistair Francis <alistair.francis@wdc.com>
-Date: Fri, 15 Feb 2019 14:57:41 -0800
-Subject: [PATCH] Makefile: Don't specify mabi or march
-
-To avoid
- can't link double-float modules with soft-float modules
-errors when building 32-bit openSBI don't specify mabi or march.
-
-Upstream-Status: Inappropriate [Fixes a 32-bit OE flow bug]
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-
----
- Makefile | 2 --
- 1 file changed, 2 deletions(-)
-
-diff --git a/Makefile b/Makefile
-index ccf8ea3..69e5b38 100644
---- a/Makefile
-+++ b/Makefile
-@@ -169,7 +169,6 @@ GENFLAGS += $(firmware-genflags-y)
- CFLAGS = -g -Wall -Werror -ffreestanding -nostdlib -fno-strict-aliasing -O2
- CFLAGS += -fno-omit-frame-pointer -fno-optimize-sibling-calls
- CFLAGS += -mno-save-restore -mstrict-align
--CFLAGS += -mabi=$(PLATFORM_RISCV_ABI) -march=$(PLATFORM_RISCV_ISA)
- CFLAGS += -mcmodel=$(PLATFORM_RISCV_CODE_MODEL)
- CFLAGS += $(GENFLAGS)
- CFLAGS += $(platform-cflags-y)
-@@ -183,7 +182,6 @@ CPPFLAGS += $(firmware-cppflags-y)
- ASFLAGS = -g -Wall -nostdlib -D__ASSEMBLY__
- ASFLAGS += -fno-omit-frame-pointer -fno-optimize-sibling-calls
- ASFLAGS += -mno-save-restore -mstrict-align
--ASFLAGS += -mabi=$(PLATFORM_RISCV_ABI) -march=$(PLATFORM_RISCV_ISA)
- ASFLAGS += -mcmodel=$(PLATFORM_RISCV_CODE_MODEL)
- ASFLAGS += $(GENFLAGS)
- ASFLAGS += $(platform-asflags-y)
diff --git a/meta/recipes-bsp/opensbi/opensbi_0.9.bb b/meta/recipes-bsp/opensbi/opensbi_1.0.bb
similarity index 91%
rename from meta/recipes-bsp/opensbi/opensbi_0.9.bb
rename to meta/recipes-bsp/opensbi/opensbi_1.0.bb
index 1956fbf9ffc..8430f62543a 100644
--- a/meta/recipes-bsp/opensbi/opensbi_0.9.bb
+++ b/meta/recipes-bsp/opensbi/opensbi_1.0.bb
@@ -8,14 +8,13 @@ require opensbi-payloads.inc
inherit autotools-brokensep deploy
-SRCREV = "234ed8e427f4d92903123199f6590d144e0d9351"
+SRCREV = "ce4c0188d96b2c20c2e08d24646a5e517fe15a4b"
SRC_URI = "git://github.com/riscv/opensbi.git;branch=master;protocol=https \
- file://0001-Makefile-Don-t-specify-mabi-or-march.patch \
"
S = "${WORKDIR}/git"
-EXTRA_OEMAKE += "PLATFORM=${RISCV_SBI_PLAT} I=${D} FW_PIC=n"
+EXTRA_OEMAKE += "PLATFORM=${RISCV_SBI_PLAT} I=${D} FW_PIC=n CLANG_TARGET= "
# If RISCV_SBI_PAYLOAD is set then include it as a payload
EXTRA_OEMAKE:append = " ${@riscv_get_extra_oemake_image(d)}"
EXTRA_OEMAKE:append = " ${@riscv_get_extra_oemake_fdt(d)}"
--
2.35.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH 2/2] u-boot: Fix RISCV build with binutils 2.38
2022-02-14 23:37 [PATCH 1/2] opensbi: Upgrade to 1.0 Khem Raj
@ 2022-02-14 23:37 ` Khem Raj
2022-02-15 22:27 ` [OE-core] [PATCH 1/2] opensbi: Upgrade to 1.0 Alistair Francis
1 sibling, 0 replies; 3+ messages in thread
From: Khem Raj @ 2022-02-14 23:37 UTC (permalink / raw)
To: openembedded-core; +Cc: Khem Raj
Ensure right ABI and march is used which matches OE core settings
Signed-off-by: Khem Raj <raj.khem@gmail.com>
---
...1-riscv-fix-build-with-binutils-2.38.patch | 40 +++++++++++++++++++
...iscv32-Use-double-float-ABI-for-rv32.patch | 16 ++++----
meta/recipes-bsp/u-boot/u-boot_2022.01.bb | 4 +-
3 files changed, 52 insertions(+), 8 deletions(-)
create mode 100644 meta/recipes-bsp/u-boot/files/0001-riscv-fix-build-with-binutils-2.38.patch
diff --git a/meta/recipes-bsp/u-boot/files/0001-riscv-fix-build-with-binutils-2.38.patch b/meta/recipes-bsp/u-boot/files/0001-riscv-fix-build-with-binutils-2.38.patch
new file mode 100644
index 00000000000..3598329b99d
--- /dev/null
+++ b/meta/recipes-bsp/u-boot/files/0001-riscv-fix-build-with-binutils-2.38.patch
@@ -0,0 +1,40 @@
+From 26a7f6b1e4c5f715c03e59a623f0d620498b92cf Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Sun, 13 Feb 2022 21:11:31 -0800
+Subject: [PATCH] riscv: fix build with binutils 2.38
+
+From version 2.38, binutils default to ISA spec version 20191213. This
+means that the csr read/write (csrr*/csrw*) instructions and fence.i
+instruction has separated from the `I` extension, become two standalone
+extensions: Zicsr and Zifencei.
+
+The fix is to specify those extensions explicitely in -march. However as
+older binutils version do not support this, we first need to detect
+that.
+
+Fixes
+arch/riscv/lib/cache.c: Assembler messages:
+arch/riscv/lib/cache.c:12: Error: unrecognized opcode `fence.i'
+
+Upstream-Status: Submitted []
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ arch/riscv/Makefile | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+--- a/arch/riscv/Makefile
++++ b/arch/riscv/Makefile
+@@ -28,7 +28,12 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y)
+ CMODEL = medany
+ endif
+
+-ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_F)$(ARCH_D)$(ARCH_C) -mabi=$(ABI) \
++# Newer binutils versions default to ISA spec version 20191213 which moves some
++# instructions from the I extension to the Zicsr and Zifencei extensions.
++toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_F)$(ARCH_D)$(ARCH_C)_zicsr_zifencei)
++zicsr_zifencei-$(toolchain-need-zicsr-zifencei) := _zicsr_zifencei
++
++ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_F)$(ARCH_D)$(ARCH_C)$(zicsr_zifencei-y) -mabi=$(ABI) \
+ -mcmodel=$(CMODEL)
+
+ PLATFORM_CPPFLAGS += $(ARCH_FLAGS)
diff --git a/meta/recipes-bsp/u-boot/files/0001-riscv32-Use-double-float-ABI-for-rv32.patch b/meta/recipes-bsp/u-boot/files/0001-riscv32-Use-double-float-ABI-for-rv32.patch
index 0ed3de4914e..0bf1bef2c99 100644
--- a/meta/recipes-bsp/u-boot/files/0001-riscv32-Use-double-float-ABI-for-rv32.patch
+++ b/meta/recipes-bsp/u-boot/files/0001-riscv32-Use-double-float-ABI-for-rv32.patch
@@ -13,11 +13,16 @@ Upstream-Status: Inappropriate [embedded specific]
arch/riscv/Makefile | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
-diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
-index 0b80eb8d86..7324946f48 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
-@@ -9,7 +9,9 @@ ifeq ($(CONFIG_ARCH_RV64I),y)
+@@ -5,11 +5,15 @@
+
+ ifeq ($(CONFIG_ARCH_RV64I),y)
+ ARCH_BASE = rv64im
+- ABI = lp64
++ ABI = lp64d
++ ARCH_D = d
++ ARCH_F = f
endif
ifeq ($(CONFIG_ARCH_RV32I),y)
ARCH_BASE = rv32im
@@ -28,7 +33,7 @@ index 0b80eb8d86..7324946f48 100644
endif
ifeq ($(CONFIG_RISCV_ISA_A),y)
ARCH_A = a
-@@ -24,7 +26,7 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y)
+@@ -24,7 +28,7 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y)
CMODEL = medany
endif
@@ -37,6 +42,3 @@ index 0b80eb8d86..7324946f48 100644
-mcmodel=$(CMODEL)
PLATFORM_CPPFLAGS += $(ARCH_FLAGS)
---
-2.30.0
-
diff --git a/meta/recipes-bsp/u-boot/u-boot_2022.01.bb b/meta/recipes-bsp/u-boot/u-boot_2022.01.bb
index 617827ff083..0d2464d74bd 100644
--- a/meta/recipes-bsp/u-boot/u-boot_2022.01.bb
+++ b/meta/recipes-bsp/u-boot/u-boot_2022.01.bb
@@ -1,7 +1,9 @@
require u-boot-common.inc
require u-boot.inc
-SRC_URI:append = " file://0001-riscv32-Use-double-float-ABI-for-rv32.patch"
+SRC_URI:append = " file://0001-riscv32-Use-double-float-ABI-for-rv32.patch \
+ file://0001-riscv-fix-build-with-binutils-2.38.patch \
+ "
DEPENDS += "bc-native dtc-native python3-setuptools-native"
--
2.35.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [OE-core] [PATCH 1/2] opensbi: Upgrade to 1.0
2022-02-14 23:37 [PATCH 1/2] opensbi: Upgrade to 1.0 Khem Raj
2022-02-14 23:37 ` [PATCH 2/2] u-boot: Fix RISCV build with binutils 2.38 Khem Raj
@ 2022-02-15 22:27 ` Alistair Francis
1 sibling, 0 replies; 3+ messages in thread
From: Alistair Francis @ 2022-02-15 22:27 UTC (permalink / raw)
To: Khem Raj; +Cc: OE-core, Alistair Francis
On Tue, Feb 15, 2022 at 9:37 AM Khem Raj <raj.khem@gmail.com> wrote:
>
> Drop OE specific patch to shunt march/mabi
> this seems to work fine now.
>
> unset CLANG_TARGET so it can compile with OE produced clang toolchain
> which provides --target itself
>
> Signed-off-by: Khem Raj <raj.khem@gmail.com>
> Cc: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> ...Makefile-Don-t-specify-mabi-or-march.patch | 36 -------------------
> .../{opensbi_0.9.bb => opensbi_1.0.bb} | 5 ++-
> 2 files changed, 2 insertions(+), 39 deletions(-)
> delete mode 100644 meta/recipes-bsp/opensbi/files/0001-Makefile-Don-t-specify-mabi-or-march.patch
> rename meta/recipes-bsp/opensbi/{opensbi_0.9.bb => opensbi_1.0.bb} (91%)
>
> diff --git a/meta/recipes-bsp/opensbi/files/0001-Makefile-Don-t-specify-mabi-or-march.patch b/meta/recipes-bsp/opensbi/files/0001-Makefile-Don-t-specify-mabi-or-march.patch
> deleted file mode 100644
> index d2a8048e87e..00000000000
> --- a/meta/recipes-bsp/opensbi/files/0001-Makefile-Don-t-specify-mabi-or-march.patch
> +++ /dev/null
> @@ -1,36 +0,0 @@
> -From fe9860fd85e49a75bef545e5d9914070491e8002 Mon Sep 17 00:00:00 2001
> -From: Alistair Francis <alistair.francis@wdc.com>
> -Date: Fri, 15 Feb 2019 14:57:41 -0800
> -Subject: [PATCH] Makefile: Don't specify mabi or march
> -
> -To avoid
> - can't link double-float modules with soft-float modules
> -errors when building 32-bit openSBI don't specify mabi or march.
> -
> -Upstream-Status: Inappropriate [Fixes a 32-bit OE flow bug]
> -Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> -
> ----
> - Makefile | 2 --
> - 1 file changed, 2 deletions(-)
> -
> -diff --git a/Makefile b/Makefile
> -index ccf8ea3..69e5b38 100644
> ---- a/Makefile
> -+++ b/Makefile
> -@@ -169,7 +169,6 @@ GENFLAGS += $(firmware-genflags-y)
> - CFLAGS = -g -Wall -Werror -ffreestanding -nostdlib -fno-strict-aliasing -O2
> - CFLAGS += -fno-omit-frame-pointer -fno-optimize-sibling-calls
> - CFLAGS += -mno-save-restore -mstrict-align
> --CFLAGS += -mabi=$(PLATFORM_RISCV_ABI) -march=$(PLATFORM_RISCV_ISA)
> - CFLAGS += -mcmodel=$(PLATFORM_RISCV_CODE_MODEL)
> - CFLAGS += $(GENFLAGS)
> - CFLAGS += $(platform-cflags-y)
> -@@ -183,7 +182,6 @@ CPPFLAGS += $(firmware-cppflags-y)
> - ASFLAGS = -g -Wall -nostdlib -D__ASSEMBLY__
> - ASFLAGS += -fno-omit-frame-pointer -fno-optimize-sibling-calls
> - ASFLAGS += -mno-save-restore -mstrict-align
> --ASFLAGS += -mabi=$(PLATFORM_RISCV_ABI) -march=$(PLATFORM_RISCV_ISA)
> - ASFLAGS += -mcmodel=$(PLATFORM_RISCV_CODE_MODEL)
> - ASFLAGS += $(GENFLAGS)
> - ASFLAGS += $(platform-asflags-y)
> diff --git a/meta/recipes-bsp/opensbi/opensbi_0.9.bb b/meta/recipes-bsp/opensbi/opensbi_1.0.bb
> similarity index 91%
> rename from meta/recipes-bsp/opensbi/opensbi_0.9.bb
> rename to meta/recipes-bsp/opensbi/opensbi_1.0.bb
> index 1956fbf9ffc..8430f62543a 100644
> --- a/meta/recipes-bsp/opensbi/opensbi_0.9.bb
> +++ b/meta/recipes-bsp/opensbi/opensbi_1.0.bb
> @@ -8,14 +8,13 @@ require opensbi-payloads.inc
>
> inherit autotools-brokensep deploy
>
> -SRCREV = "234ed8e427f4d92903123199f6590d144e0d9351"
> +SRCREV = "ce4c0188d96b2c20c2e08d24646a5e517fe15a4b"
> SRC_URI = "git://github.com/riscv/opensbi.git;branch=master;protocol=https \
> - file://0001-Makefile-Don-t-specify-mabi-or-march.patch \
> "
>
> S = "${WORKDIR}/git"
>
> -EXTRA_OEMAKE += "PLATFORM=${RISCV_SBI_PLAT} I=${D} FW_PIC=n"
> +EXTRA_OEMAKE += "PLATFORM=${RISCV_SBI_PLAT} I=${D} FW_PIC=n CLANG_TARGET= "
> # If RISCV_SBI_PAYLOAD is set then include it as a payload
> EXTRA_OEMAKE:append = " ${@riscv_get_extra_oemake_image(d)}"
> EXTRA_OEMAKE:append = " ${@riscv_get_extra_oemake_fdt(d)}"
> --
> 2.35.1
>
>
> -=-=-=-=-=-=-=-=-=-=-=-
> Links: You receive all messages sent to this group.
> View/Reply Online (#161733): https://lists.openembedded.org/g/openembedded-core/message/161733
> Mute This Topic: https://lists.openembedded.org/mt/89150183/3619028
> Group Owner: openembedded-core+owner@lists.openembedded.org
> Unsubscribe: https://lists.openembedded.org/g/openembedded-core/unsub [alistair23@gmail.com]
> -=-=-=-=-=-=-=-=-=-=-=-
>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2022-02-15 22:28 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-02-14 23:37 [PATCH 1/2] opensbi: Upgrade to 1.0 Khem Raj
2022-02-14 23:37 ` [PATCH 2/2] u-boot: Fix RISCV build with binutils 2.38 Khem Raj
2022-02-15 22:27 ` [OE-core] [PATCH 1/2] opensbi: Upgrade to 1.0 Alistair Francis
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.