From: Nishanth Menon <nm@ti.com> To: Tero Kristo <kristo@kernel.org>, Vignesh Raghavendra <vigneshr@ti.com>, Marc Zyngier <maz@kernel.org> Cc: <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>, Rob Herring <robh+dt@kernel.org>, Nishanth Menon <nm@ti.com>, <stable@vger.kernel.org> Subject: [PATCH 5/5] arm64: dts: ti: k3-j721s2: Fix gic-v3 compatible regs Date: Tue, 15 Feb 2022 14:10:08 -0600 [thread overview] Message-ID: <20220215201008.15235-6-nm@ti.com> (raw) In-Reply-To: <20220215201008.15235-1-nm@ti.com> Though GIC ARE option is disabled for no GIC-v2 compatibility, Cortex-A72 is free to implement the CPU interface as long as it communicates with the GIC using the stream protocol. This requires that the SoC integration mark out the PERIPHBASE[1] as reserved area within the SoC. See longer discussion in [2] for further information. Update the GIC register map to indicate offsets from PERIPHBASE based on [3]. Without doing this, systems like kvm will not function with gic-v2 emulation. [1] https://developer.arm.com/documentation/100095/0002/system-control/aarch64-register-descriptions/configuration-base-address-register--el1 [2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/ [3] https://developer.arm.com/documentation/100095/0002/way1382452674438 Fixes: b8545f9d3a54 ("arm64: dts: ti: Add initial support for J721S2 SoC") Cc: stable@vger.kernel.org Reported-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> --- Testing: based on next-20220215 J721s2-evm Log: https://gist.github.com/nmenon/302b0bcfbb1b5b8743fa5c242eb7d15f arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 5 ++++- arch/arm64/boot/dts/ti/k3-j721s2.dtsi | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index b04db1d3ab61..be7f39299894 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -34,7 +34,10 @@ gic500: interrupt-controller@1800000 { #interrupt-cells = <3>; interrupt-controller; reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */ - <0x00 0x01900000 0x00 0x100000>; /* GICR */ + <0x00 0x01900000 0x00 0x100000>, /* GICR */ + <0x00 0x6f000000 0x00 0x2000>, /* GICC */ + <0x00 0x6f010000 0x00 0x1000>, /* GICH */ + <0x00 0x6f020000 0x00 0x2000>; /* GICV */ /* vcpumntirq: virtual CPU interface maintenance interrupt */ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi index fe5234c40f6c..7b930a85a29d 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi @@ -119,6 +119,7 @@ cbass_main: bus@100000 { <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ <0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */ <0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */ + <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */ <0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */ <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */ -- 2.31.1
WARNING: multiple messages have this Message-ID (diff)
From: Nishanth Menon <nm@ti.com> To: Tero Kristo <kristo@kernel.org>, Vignesh Raghavendra <vigneshr@ti.com>, Marc Zyngier <maz@kernel.org> Cc: <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>, Rob Herring <robh+dt@kernel.org>, Nishanth Menon <nm@ti.com>, <stable@vger.kernel.org> Subject: [PATCH 5/5] arm64: dts: ti: k3-j721s2: Fix gic-v3 compatible regs Date: Tue, 15 Feb 2022 14:10:08 -0600 [thread overview] Message-ID: <20220215201008.15235-6-nm@ti.com> (raw) In-Reply-To: <20220215201008.15235-1-nm@ti.com> Though GIC ARE option is disabled for no GIC-v2 compatibility, Cortex-A72 is free to implement the CPU interface as long as it communicates with the GIC using the stream protocol. This requires that the SoC integration mark out the PERIPHBASE[1] as reserved area within the SoC. See longer discussion in [2] for further information. Update the GIC register map to indicate offsets from PERIPHBASE based on [3]. Without doing this, systems like kvm will not function with gic-v2 emulation. [1] https://developer.arm.com/documentation/100095/0002/system-control/aarch64-register-descriptions/configuration-base-address-register--el1 [2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/ [3] https://developer.arm.com/documentation/100095/0002/way1382452674438 Fixes: b8545f9d3a54 ("arm64: dts: ti: Add initial support for J721S2 SoC") Cc: stable@vger.kernel.org Reported-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> --- Testing: based on next-20220215 J721s2-evm Log: https://gist.github.com/nmenon/302b0bcfbb1b5b8743fa5c242eb7d15f arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 5 ++++- arch/arm64/boot/dts/ti/k3-j721s2.dtsi | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index b04db1d3ab61..be7f39299894 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -34,7 +34,10 @@ gic500: interrupt-controller@1800000 { #interrupt-cells = <3>; interrupt-controller; reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */ - <0x00 0x01900000 0x00 0x100000>; /* GICR */ + <0x00 0x01900000 0x00 0x100000>, /* GICR */ + <0x00 0x6f000000 0x00 0x2000>, /* GICC */ + <0x00 0x6f010000 0x00 0x1000>, /* GICH */ + <0x00 0x6f020000 0x00 0x2000>; /* GICV */ /* vcpumntirq: virtual CPU interface maintenance interrupt */ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi index fe5234c40f6c..7b930a85a29d 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi @@ -119,6 +119,7 @@ cbass_main: bus@100000 { <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ <0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */ <0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */ + <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */ <0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */ <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */ -- 2.31.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-02-15 20:10 UTC|newest] Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-02-15 20:10 [PATCH 0/5] arm64: dts: ti: k3*: Fix gic-v3 compatible regs Nishanth Menon 2022-02-15 20:10 ` Nishanth Menon 2022-02-15 20:10 ` [PATCH 1/5] arm64: dts: ti: k3-am65: " Nishanth Menon 2022-02-15 20:10 ` Nishanth Menon 2022-02-15 20:10 ` [PATCH 2/5] arm64: dts: ti: k3-j721e: " Nishanth Menon 2022-02-15 20:10 ` Nishanth Menon 2022-02-15 20:10 ` [PATCH 3/5] arm64: dts: ti: k3-j7200: " Nishanth Menon 2022-02-15 20:10 ` Nishanth Menon 2022-02-15 20:10 ` [PATCH 4/5] arm64: dts: ti: k3-am64: " Nishanth Menon 2022-02-15 20:10 ` Nishanth Menon 2022-02-15 20:10 ` Nishanth Menon [this message] 2022-02-15 20:10 ` [PATCH 5/5] arm64: dts: ti: k3-j721s2: " Nishanth Menon 2022-02-16 9:16 ` [PATCH 0/5] arm64: dts: ti: k3*: " Marc Zyngier 2022-02-16 9:16 ` Marc Zyngier 2022-02-22 19:31 ` Nishanth Menon 2022-02-22 19:31 ` Nishanth Menon
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