[PATCH 0/3] gpio: Add AST2[456]00 GPIO driver

[PATCH 0/3] gpio: Add AST2[456]00 GPIO driver

[Andrew Jeffery]

Hello,

This series adds support for the GPIO controller found in Aspeed's
AST2400, AST2500 and AST2600 BMC SoCs.

By and large I've just extracted the work from Aspeed's SDK and
submitted it. However, the driver as found in the SDK was in-turn
extracted from Linux, cut down and adapted to u-boot. I've adjusted the
copyright to reflect this (as found in Linux) after discussion with Troy
and Ryan.

From there I've polished the patch in accordance with checkpatch and
done some tweaks to improve consistency with the kernel driver (mainly
the file name).

I've lightly tested the driver as-presented under qemu. That said, as
the code has been lifted from Aspeed's SDK (and in-turn from Linux) the
implementation has seen much wider testing.

Please review!

Andrew

Andrew Jeffery (3):
  gpio: Add Aspeed GPIO driver
  ARM: dts: ast2500: Add ngpios property to GPIO node
  configs: evb-ast2[56]00: Enable GPIO control

 arch/arm/dts/ast2500.dtsi     |   1 +
 configs/evb-ast2500_defconfig |   3 +
 configs/evb-ast2600_defconfig |   3 +
 drivers/gpio/Kconfig          |   7 +
 drivers/gpio/Makefile         |   1 +
 drivers/gpio/gpio-aspeed.c    | 299 ++++++++++++++++++++++++++++++++++
 6 files changed, 314 insertions(+)
 create mode 100644 drivers/gpio/gpio-aspeed.c

-- 
2.32.0

[PATCH 1/3] gpio: Add Aspeed GPIO driver

[Andrew Jeffery]

The Aspeed GPIO driver supports the GPIO controllers found in the
AST2400, AST2500 and AST2600 BMC SoCs. The implementation is a cut-down
copy of the upstream Linux kernel driver, adapted for u-boot.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
 drivers/gpio/Kconfig       |   7 +
 drivers/gpio/Makefile      |   1 +
 drivers/gpio/gpio-aspeed.c | 299 +++++++++++++++++++++++++++++++++++++
 3 files changed, 307 insertions(+)
 create mode 100644 drivers/gpio/gpio-aspeed.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 8d0e47c67d9e..f7fb8b519eca 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -126,6 +126,13 @@ config ATMEL_PIO4
 	  may be dedicated as a general purpose I/O or be assigned to
 	  a function of an embedded peripheral.
 
+config ASPEED_GPIO
+	bool "Aspeed GPIO Driver"
+	help
+	  Say yes here to support the Aspeed GPIO driver. The controller
+	  is found in the AST2400, AST2500 and AST2600 BMC SoCs and
+	  provides access to over 200 GPIOs on each chip.
+
 config DA8XX_GPIO
 	bool "DA8xx GPIO Driver"
 	help
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 63e9be6034f2..720297952cdd 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_$(SPL_TPL_)DM_GPIO) += gpio-uclass.o
 
 obj-$(CONFIG_$(SPL_)DM_PCA953X)	+= pca953x_gpio.o
 
+obj-$(CONFIG_ASPEED_GPIO)	+= gpio-aspeed.o
 obj-$(CONFIG_AT91_GPIO)	+= at91_gpio.o
 obj-$(CONFIG_ATMEL_PIO4)	+= atmel_pio4.o
 obj-$(CONFIG_BCM6345_GPIO)	+= bcm6345_gpio.o
diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c
new file mode 100644
index 000000000000..a8a2afcb5c85
--- /dev/null
+++ b/drivers/gpio/gpio-aspeed.c
@@ -0,0 +1,299 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2015 IBM Corp.
+ * Joel Stanley <joel@jms.id.au>
+ * Ryan Chen <ryan_chen@aspeedtech.com>
+ *
+ * Implementation extracted from the Linux kernel and adapted for u-boot.
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+#include <config.h>
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <linux/bug.h>
+#include <linux/sizes.h>
+
+struct aspeed_gpio_priv {
+	void *regs;
+};
+
+struct aspeed_gpio_bank {
+	u16		val_regs;	/* +0: Rd: read input value, Wr: set write latch
+					 * +4: Rd/Wr: Direction (0=in, 1=out)
+					 */
+	u16		rdata_reg;	/*     Rd: read write latch, Wr: <none>  */
+	u16		irq_regs;
+	u16		debounce_regs;
+	u16		tolerance_regs;
+	u16		cmdsrc_regs;
+	const char	names[4][3];
+};
+
+static const struct aspeed_gpio_bank aspeed_gpio_banks[] = {
+	{
+		.val_regs = 0x0000,
+		.rdata_reg = 0x00c0,
+		.irq_regs = 0x0008,
+		.debounce_regs = 0x0040,
+		.tolerance_regs = 0x001c,
+		.cmdsrc_regs = 0x0060,
+		.names = { "A", "B", "C", "D" },
+	},
+	{
+		.val_regs = 0x0020,
+		.rdata_reg = 0x00c4,
+		.irq_regs = 0x0028,
+		.debounce_regs = 0x0048,
+		.tolerance_regs = 0x003c,
+		.cmdsrc_regs = 0x0068,
+		.names = { "E", "F", "G", "H" },
+	},
+	{
+		.val_regs = 0x0070,
+		.rdata_reg = 0x00c8,
+		.irq_regs = 0x0098,
+		.debounce_regs = 0x00b0,
+		.tolerance_regs = 0x00ac,
+		.cmdsrc_regs = 0x0090,
+		.names = { "I", "J", "K", "L" },
+	},
+	{
+		.val_regs = 0x0078,
+		.rdata_reg = 0x00cc,
+		.irq_regs = 0x00e8,
+		.debounce_regs = 0x0100,
+		.tolerance_regs = 0x00fc,
+		.cmdsrc_regs = 0x00e0,
+		.names = { "M", "N", "O", "P" },
+	},
+	{
+		.val_regs = 0x0080,
+		.rdata_reg = 0x00d0,
+		.irq_regs = 0x0118,
+		.debounce_regs = 0x0130,
+		.tolerance_regs = 0x012c,
+		.cmdsrc_regs = 0x0110,
+		.names = { "Q", "R", "S", "T" },
+	},
+	{
+		.val_regs = 0x0088,
+		.rdata_reg = 0x00d4,
+		.irq_regs = 0x0148,
+		.debounce_regs = 0x0160,
+		.tolerance_regs = 0x015c,
+		.cmdsrc_regs = 0x0140,
+		.names = { "U", "V", "W", "X" },
+	},
+	{
+		.val_regs = 0x01E0,
+		.rdata_reg = 0x00d8,
+		.irq_regs = 0x0178,
+		.debounce_regs = 0x0190,
+		.tolerance_regs = 0x018c,
+		.cmdsrc_regs = 0x0170,
+		.names = { "Y", "Z", "AA", "AB" },
+	},
+	{
+		.val_regs = 0x01e8,
+		.rdata_reg = 0x00dc,
+		.irq_regs = 0x01a8,
+		.debounce_regs = 0x01c0,
+		.tolerance_regs = 0x01bc,
+		.cmdsrc_regs = 0x01a0,
+		.names = { "AC", "", "", "" },
+	},
+};
+
+enum aspeed_gpio_reg {
+	reg_val,
+	reg_rdata,
+	reg_dir,
+	reg_irq_enable,
+	reg_irq_type0,
+	reg_irq_type1,
+	reg_irq_type2,
+	reg_irq_status,
+	reg_debounce_sel1,
+	reg_debounce_sel2,
+	reg_tolerance,
+	reg_cmdsrc0,
+	reg_cmdsrc1,
+};
+
+#define GPIO_VAL_VALUE	0x00
+#define GPIO_VAL_DIR	0x04
+
+#define GPIO_IRQ_ENABLE	0x00
+#define GPIO_IRQ_TYPE0	0x04
+#define GPIO_IRQ_TYPE1	0x08
+#define GPIO_IRQ_TYPE2	0x0c
+#define GPIO_IRQ_STATUS	0x10
+
+#define GPIO_DEBOUNCE_SEL1 0x00
+#define GPIO_DEBOUNCE_SEL2 0x04
+
+#define GPIO_CMDSRC_0	0x00
+#define GPIO_CMDSRC_1	0x04
+#define  GPIO_CMDSRC_ARM		0
+#define  GPIO_CMDSRC_LPC		1
+#define  GPIO_CMDSRC_COLDFIRE		2
+#define  GPIO_CMDSRC_RESERVED		3
+
+/* This will be resolved at compile time */
+static inline void __iomem *bank_reg(struct aspeed_gpio_priv *gpio,
+				     const struct aspeed_gpio_bank *bank,
+				     const enum aspeed_gpio_reg reg)
+{
+	switch (reg) {
+	case reg_val:
+		return gpio->regs + bank->val_regs + GPIO_VAL_VALUE;
+	case reg_rdata:
+		return gpio->regs + bank->rdata_reg;
+	case reg_dir:
+		return gpio->regs + bank->val_regs + GPIO_VAL_DIR;
+	case reg_irq_enable:
+		return gpio->regs + bank->irq_regs + GPIO_IRQ_ENABLE;
+	case reg_irq_type0:
+		return gpio->regs + bank->irq_regs + GPIO_IRQ_TYPE0;
+	case reg_irq_type1:
+		return gpio->regs + bank->irq_regs + GPIO_IRQ_TYPE1;
+	case reg_irq_type2:
+		return gpio->regs + bank->irq_regs + GPIO_IRQ_TYPE2;
+	case reg_irq_status:
+		return gpio->regs + bank->irq_regs + GPIO_IRQ_STATUS;
+	case reg_debounce_sel1:
+		return gpio->regs + bank->debounce_regs + GPIO_DEBOUNCE_SEL1;
+	case reg_debounce_sel2:
+		return gpio->regs + bank->debounce_regs + GPIO_DEBOUNCE_SEL2;
+	case reg_tolerance:
+		return gpio->regs + bank->tolerance_regs;
+	case reg_cmdsrc0:
+		return gpio->regs + bank->cmdsrc_regs + GPIO_CMDSRC_0;
+	case reg_cmdsrc1:
+		return gpio->regs + bank->cmdsrc_regs + GPIO_CMDSRC_1;
+	}
+	BUG();
+}
+
+#define GPIO_BANK(x)	((x) >> 5)
+#define GPIO_OFFSET(x)	((x) & 0x1f)
+#define GPIO_BIT(x)	BIT(GPIO_OFFSET(x))
+
+static const struct aspeed_gpio_bank *to_bank(unsigned int offset)
+{
+	unsigned int bank = GPIO_BANK(offset);
+
+	WARN_ON(bank >= ARRAY_SIZE(aspeed_gpio_banks));
+	return &aspeed_gpio_banks[bank];
+}
+
+static int
+aspeed_gpio_direction_input(struct udevice *dev, unsigned int offset)
+{
+	struct aspeed_gpio_priv *priv = dev_get_priv(dev);
+	const struct aspeed_gpio_bank *bank = to_bank(offset);
+	u32 dir = readl(bank_reg(priv, bank, reg_dir));
+
+	dir &= ~GPIO_BIT(offset);
+	writel(dir, bank_reg(priv, bank, reg_dir));
+
+	return 0;
+}
+
+static int aspeed_gpio_direction_output(struct udevice *dev, unsigned int offset,
+					int value)
+{
+	struct aspeed_gpio_priv *priv = dev_get_priv(dev);
+	const struct aspeed_gpio_bank *bank = to_bank(offset);
+	u32 dir = readl(bank_reg(priv, bank, reg_dir));
+	u32 output = readl(bank_reg(priv, bank, reg_val));
+
+	dir |= GPIO_BIT(offset);
+	writel(dir, bank_reg(priv, bank, reg_dir));
+
+	if (value)
+		output |= GPIO_BIT(offset);
+	else
+		output &= ~GPIO_BIT(offset);
+
+	writel(output, bank_reg(priv, bank, reg_val));
+
+	return 0;
+}
+
+static int aspeed_gpio_get_value(struct udevice *dev, unsigned int offset)
+{
+	struct aspeed_gpio_priv *priv = dev_get_priv(dev);
+	const struct aspeed_gpio_bank *bank = to_bank(offset);
+
+	return !!(readl(bank_reg(priv, bank, reg_val)) & GPIO_BIT(offset));
+}
+
+static int
+aspeed_gpio_set_value(struct udevice *dev, unsigned int offset, int value)
+{
+	struct aspeed_gpio_priv *priv = dev_get_priv(dev);
+	const struct aspeed_gpio_bank *bank = to_bank(offset);
+	u32 data = readl(bank_reg(priv, bank, reg_val));
+
+	if (value)
+		data |= GPIO_BIT(offset);
+	else
+		data &= ~GPIO_BIT(offset);
+
+	writel(data, bank_reg(priv, bank, reg_val));
+
+	return 0;
+}
+
+static int aspeed_gpio_get_function(struct udevice *dev, unsigned int offset)
+{
+	struct aspeed_gpio_priv *priv = dev_get_priv(dev);
+	const struct aspeed_gpio_bank *bank = to_bank(offset);
+
+	if (readl(bank_reg(priv, bank, reg_dir)) & GPIO_BIT(offset))
+		return GPIOF_OUTPUT;
+
+	return GPIOF_INPUT;
+}
+
+static const struct dm_gpio_ops aspeed_gpio_ops = {
+	.direction_input	= aspeed_gpio_direction_input,
+	.direction_output	= aspeed_gpio_direction_output,
+	.get_value		= aspeed_gpio_get_value,
+	.set_value		= aspeed_gpio_set_value,
+	.get_function		= aspeed_gpio_get_function,
+};
+
+static int aspeed_gpio_probe(struct udevice *dev)
+{
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct aspeed_gpio_priv *priv = dev_get_priv(dev);
+
+	uc_priv->bank_name = dev->name;
+	ofnode_read_u32(dev_ofnode(dev), "ngpios", &uc_priv->gpio_count);
+	priv->regs = devfdt_get_addr_ptr(dev);
+
+	return 0;
+}
+
+static const struct udevice_id aspeed_gpio_ids[] = {
+	{ .compatible = "aspeed,ast2400-gpio",  },
+	{ .compatible = "aspeed,ast2500-gpio",	},
+	{ .compatible = "aspeed,ast2600-gpio",	},
+	{ }
+};
+
+U_BOOT_DRIVER(gpio_aspeed) = {
+	.name   = "gpio-aspeed",
+	.id     = UCLASS_GPIO,
+	.of_match = aspeed_gpio_ids,
+	.ops    = &aspeed_gpio_ops,
+	.probe  = aspeed_gpio_probe,
+	.priv_auto = sizeof(struct aspeed_gpio_priv),
+};
-- 
2.32.0

[PATCH 2/3] ARM: dts: ast2500: Add ngpios property to GPIO node

[Andrew Jeffery]

Populate gpio_count in the gpio subsystem for the AST2500.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
 arch/arm/dts/ast2500.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/ast2500.dtsi b/arch/arm/dts/ast2500.dtsi
index 98359bf92425..ee66ef67042b 100644
--- a/arch/arm/dts/ast2500.dtsi
+++ b/arch/arm/dts/ast2500.dtsi
@@ -214,6 +214,7 @@
 				reg = <0x1e780000 0x1000>;
 				interrupts = <20>;
 				gpio-ranges = <&pinctrl 0 0 220>;
+				ngpios = <228>;
 				interrupt-controller;
 			};
 
-- 
2.32.0

[PATCH 3/3] configs: evb-ast2[56]00: Enable GPIO control

[Andrew Jeffery]

Build in the driver for the Aspeed GPIO controller and turn on the
`gpio` shell command.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
 configs/evb-ast2500_defconfig | 3 +++
 configs/evb-ast2600_defconfig | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig
index ea001851cac1..26743fc8f5a6 100644
--- a/configs/evb-ast2500_defconfig
+++ b/configs/evb-ast2500_defconfig
@@ -7,6 +7,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_EVB_AST2500=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_SIZE=0x20000
+CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ast2500-evb"
 CONFIG_PRE_CON_BUF_ADDR=0x1e720000
 CONFIG_SYS_LOAD_ADDR=0x83000000
@@ -18,6 +19,7 @@ CONFIG_PRE_CONSOLE_BUFFER=y
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_HUSH_PARSER=y
 # CONFIG_AUTO_COMPLETE is not set
+CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_DHCP=y
@@ -28,6 +30,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_REGMAP=y
 CONFIG_CLK=y
+CONFIG_ASPEED_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_ASPEED=y
 CONFIG_MMC_SDHCI=y
diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index 172b08e63ccb..1c58f34079e3 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -11,6 +11,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_SIZE=0x10000
+CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ast2600-evb"
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK_R_ADDR=0x83000000
@@ -39,6 +40,7 @@ CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_DHCP=y
@@ -57,6 +59,7 @@ CONFIG_SPL_CLK=y
 CONFIG_DM_HASH=y
 CONFIG_HASH_ASPEED=y
 CONFIG_ASPEED_ACRY=y
+CONFIG_ASPEED_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_MISC=y
 CONFIG_SPL_MISC=y
-- 
2.32.0

RE: [PATCH 0/3] gpio: Add AST2[456]00 GPIO driver

[Ryan Chen]

Hello Andrew,
This patch series are ok, Please help add Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>

> -----Original Message-----
> From: Andrew Jeffery <andrew@aj.id.au>
> Sent: Wednesday, February 16, 2022 7:57 AM
> To: u-boot@lists.denx.de
> Cc: maxims@google.com; ChiaWei Wang <chiawei_wang@aspeedtech.com>;
> Ryan Chen <ryan_chen@aspeedtech.com>; Troy Lee
> <troy_lee@aspeedtech.com>; BMC-SW <BMC-SW@aspeedtech.com>;
> joel@jms.id.au; eajames@linux.ibm.com
> Subject: [PATCH 0/3] gpio: Add AST2[456]00 GPIO driver
> 
> Hello,
> 
> This series adds support for the GPIO controller found in Aspeed's AST2400,
> AST2500 and AST2600 BMC SoCs.
> 
> By and large I've just extracted the work from Aspeed's SDK and submitted it.
> However, the driver as found in the SDK was in-turn extracted from Linux, cut
> down and adapted to u-boot. I've adjusted the copyright to reflect this (as
> found in Linux) after discussion with Troy and Ryan.
> 
> From there I've polished the patch in accordance with checkpatch and done
> some tweaks to improve consistency with the kernel driver (mainly the file
> name).
> 
> I've lightly tested the driver as-presented under qemu. That said, as the code
> has been lifted from Aspeed's SDK (and in-turn from Linux) the implementation
> has seen much wider testing.
> 
> Please review!
> 
> Andrew
> 
> Andrew Jeffery (3):
>   gpio: Add Aspeed GPIO driver
>   ARM: dts: ast2500: Add ngpios property to GPIO node
>   configs: evb-ast2[56]00: Enable GPIO control
> 
>  arch/arm/dts/ast2500.dtsi     |   1 +
>  configs/evb-ast2500_defconfig |   3 +
>  configs/evb-ast2600_defconfig |   3 +
>  drivers/gpio/Kconfig          |   7 +
>  drivers/gpio/Makefile         |   1 +
>  drivers/gpio/gpio-aspeed.c    | 299
> ++++++++++++++++++++++++++++++++++
>  6 files changed, 314 insertions(+)
>  create mode 100644 drivers/gpio/gpio-aspeed.c
> 
> --
> 2.32.0

Re: [PATCH 0/3] gpio: Add AST2[456]00 GPIO driver

[Andrew Jeffery]

On Wed, 16 Feb 2022, at 19:02, Ryan Chen wrote:
> Hello Andrew,
> This patch series are ok, Please help add Reviewed-by: Ryan Chen 
> <ryan_chen@aspeedtech.com>

Thanks Ryan. This is all that's necessary!

Andrew

Re: [PATCH 1/3] gpio: Add Aspeed GPIO driver

[Tom Rini]

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On Wed, Feb 16, 2022 at 10:26:56AM +1030, Andrew Jeffery wrote:

> The Aspeed GPIO driver supports the GPIO controllers found in the
> AST2400, AST2500 and AST2600 BMC SoCs. The implementation is a cut-down
> copy of the upstream Linux kernel driver, adapted for u-boot.
> 
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>

Applied to u-boot/next, thanks!

-- 
Tom

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Re: [PATCH 2/3] ARM: dts: ast2500: Add ngpios property to GPIO node

[Tom Rini]

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On Wed, Feb 16, 2022 at 10:26:57AM +1030, Andrew Jeffery wrote:

> Populate gpio_count in the gpio subsystem for the AST2500.
> 
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>

Applied to u-boot/next, thanks!

-- 
Tom

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Re: [PATCH 3/3] configs: evb-ast2[56]00: Enable GPIO control

[Tom Rini]

[-- Attachment #1: Type: text/plain, Size: 264 bytes --]

On Wed, Feb 16, 2022 at 10:26:58AM +1030, Andrew Jeffery wrote:

> Build in the driver for the Aspeed GPIO controller and turn on the
> `gpio` shell command.
> 
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>

Applied to u-boot/next, thanks!

-- 
Tom

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