[PATCH v2,0/2] Add mmsys reset control for MT8186

[PATCH v2,0/2] Add mmsys reset control for MT8186

[Rex-BC Chen]

v2:
1. Change variable type from unsigned int to u16.

v1:
1. Add a new variable in mmsys driver data to control different register
   offset for different SoCs.
2. Add MT8183 reset register offset.
3. Add mmsys reset control for MT8186.

This series is based on mmsys patch for MT8186 on [1].
[1]: https://patchwork.kernel.org/project/linux-mediatek/patch/20220216084831.14883-4-rex-bc.chen@mediatek.com/

Rex-BC Chen (2):
  soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data
  soc: mediatek: mmsys: add mmsys reset control for MT8186

 drivers/soc/mediatek/mt8183-mmsys.h | 2 ++
 drivers/soc/mediatek/mt8186-mmsys.h | 2 ++
 drivers/soc/mediatek/mtk-mmsys.c    | 7 +++++--
 drivers/soc/mediatek/mtk-mmsys.h    | 3 +--
 4 files changed, 10 insertions(+), 4 deletions(-)

-- 
2.18.0

[PATCH v2,0/2] Add mmsys reset control for MT8186

[Rex-BC Chen]

v2:
1. Change variable type from unsigned int to u16.

v1:
1. Add a new variable in mmsys driver data to control different register
   offset for different SoCs.
2. Add MT8183 reset register offset.
3. Add mmsys reset control for MT8186.

This series is based on mmsys patch for MT8186 on [1].
[1]: https://patchwork.kernel.org/project/linux-mediatek/patch/20220216084831.14883-4-rex-bc.chen@mediatek.com/

Rex-BC Chen (2):
  soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data
  soc: mediatek: mmsys: add mmsys reset control for MT8186

 drivers/soc/mediatek/mt8183-mmsys.h | 2 ++
 drivers/soc/mediatek/mt8186-mmsys.h | 2 ++
 drivers/soc/mediatek/mtk-mmsys.c    | 7 +++++--
 drivers/soc/mediatek/mtk-mmsys.h    | 3 +--
 4 files changed, 10 insertions(+), 4 deletions(-)

-- 
2.18.0


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[PATCH v2,0/2] Add mmsys reset control for MT8186

[Rex-BC Chen]

v2:
1. Change variable type from unsigned int to u16.

v1:
1. Add a new variable in mmsys driver data to control different register
   offset for different SoCs.
2. Add MT8183 reset register offset.
3. Add mmsys reset control for MT8186.

This series is based on mmsys patch for MT8186 on [1].
[1]: https://patchwork.kernel.org/project/linux-mediatek/patch/20220216084831.14883-4-rex-bc.chen@mediatek.com/

Rex-BC Chen (2):
  soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data
  soc: mediatek: mmsys: add mmsys reset control for MT8186

 drivers/soc/mediatek/mt8183-mmsys.h | 2 ++
 drivers/soc/mediatek/mt8186-mmsys.h | 2 ++
 drivers/soc/mediatek/mtk-mmsys.c    | 7 +++++--
 drivers/soc/mediatek/mtk-mmsys.h    | 3 +--
 4 files changed, 10 insertions(+), 4 deletions(-)

-- 
2.18.0


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[PATCH v2,1/2] soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data

[Rex-BC Chen]

There are different software reset registers for difference MTK SoCs.
Therefore, we add a new variable "sw0_rst_offset" to control it.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/soc/mediatek/mt8183-mmsys.h | 2 ++
 drivers/soc/mediatek/mtk-mmsys.c    | 6 ++++--
 drivers/soc/mediatek/mtk-mmsys.h    | 3 +--
 3 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h
index 9dee485807c9..0c021f4b76d2 100644
--- a/drivers/soc/mediatek/mt8183-mmsys.h
+++ b/drivers/soc/mediatek/mt8183-mmsys.h
@@ -25,6 +25,8 @@
 #define MT8183_RDMA0_SOUT_COLOR0		0x1
 #define MT8183_RDMA1_SOUT_DSI0			0x1
 
+#define MT8183_MMSYS_SW0_RST_B			0x140
+
 static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
 	{
 		DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 0da25069ffb3..cab62c3eac05 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -49,12 +49,14 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
 	.clk_driver = "clk-mt8173-mm",
 	.routes = mmsys_default_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
+	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
 };
 
 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
 	.clk_driver = "clk-mt8183-mm",
 	.routes = mmsys_mt8183_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
+	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
 };
 
 static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
@@ -128,14 +130,14 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l
 
 	spin_lock_irqsave(&mmsys->lock, flags);
 
-	reg = readl_relaxed(mmsys->regs + MMSYS_SW0_RST_B);
+	reg = readl_relaxed(mmsys->regs + mmsys->data->sw0_rst_offset);
 
 	if (assert)
 		reg &= ~BIT(id);
 	else
 		reg |= BIT(id);
 
-	writel_relaxed(reg, mmsys->regs + MMSYS_SW0_RST_B);
+	writel_relaxed(reg, mmsys->regs + mmsys->data->sw0_rst_offset);
 
 	spin_unlock_irqrestore(&mmsys->lock, flags);
 
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 8b0ed05117ea..77f37f8c715b 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -78,8 +78,6 @@
 #define DSI_SEL_IN_RDMA				0x1
 #define DSI_SEL_IN_MASK				0x1
 
-#define MMSYS_SW0_RST_B				0x140
-
 struct mtk_mmsys_routes {
 	u32 from_comp;
 	u32 to_comp;
@@ -92,6 +90,7 @@ struct mtk_mmsys_driver_data {
 	const char *clk_driver;
 	const struct mtk_mmsys_routes *routes;
 	const unsigned int num_routes;
+	const u16 sw0_rst_offset;
 };
 
 /*
-- 
2.18.0

[PATCH v2, 1/2] soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data

[Rex-BC Chen]

There are different software reset registers for difference MTK SoCs.
Therefore, we add a new variable "sw0_rst_offset" to control it.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/soc/mediatek/mt8183-mmsys.h | 2 ++
 drivers/soc/mediatek/mtk-mmsys.c    | 6 ++++--
 drivers/soc/mediatek/mtk-mmsys.h    | 3 +--
 3 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h
index 9dee485807c9..0c021f4b76d2 100644
--- a/drivers/soc/mediatek/mt8183-mmsys.h
+++ b/drivers/soc/mediatek/mt8183-mmsys.h
@@ -25,6 +25,8 @@
 #define MT8183_RDMA0_SOUT_COLOR0		0x1
 #define MT8183_RDMA1_SOUT_DSI0			0x1
 
+#define MT8183_MMSYS_SW0_RST_B			0x140
+
 static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
 	{
 		DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 0da25069ffb3..cab62c3eac05 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -49,12 +49,14 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
 	.clk_driver = "clk-mt8173-mm",
 	.routes = mmsys_default_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
+	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
 };
 
 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
 	.clk_driver = "clk-mt8183-mm",
 	.routes = mmsys_mt8183_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
+	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
 };
 
 static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
@@ -128,14 +130,14 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l
 
 	spin_lock_irqsave(&mmsys->lock, flags);
 
-	reg = readl_relaxed(mmsys->regs + MMSYS_SW0_RST_B);
+	reg = readl_relaxed(mmsys->regs + mmsys->data->sw0_rst_offset);
 
 	if (assert)
 		reg &= ~BIT(id);
 	else
 		reg |= BIT(id);
 
-	writel_relaxed(reg, mmsys->regs + MMSYS_SW0_RST_B);
+	writel_relaxed(reg, mmsys->regs + mmsys->data->sw0_rst_offset);
 
 	spin_unlock_irqrestore(&mmsys->lock, flags);
 
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 8b0ed05117ea..77f37f8c715b 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -78,8 +78,6 @@
 #define DSI_SEL_IN_RDMA				0x1
 #define DSI_SEL_IN_MASK				0x1
 
-#define MMSYS_SW0_RST_B				0x140
-
 struct mtk_mmsys_routes {
 	u32 from_comp;
 	u32 to_comp;
@@ -92,6 +90,7 @@ struct mtk_mmsys_driver_data {
 	const char *clk_driver;
 	const struct mtk_mmsys_routes *routes;
 	const unsigned int num_routes;
+	const u16 sw0_rst_offset;
 };
 
 /*
-- 
2.18.0


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[PATCH v2, 1/2] soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data

[Rex-BC Chen]

There are different software reset registers for difference MTK SoCs.
Therefore, we add a new variable "sw0_rst_offset" to control it.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/soc/mediatek/mt8183-mmsys.h | 2 ++
 drivers/soc/mediatek/mtk-mmsys.c    | 6 ++++--
 drivers/soc/mediatek/mtk-mmsys.h    | 3 +--
 3 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h
index 9dee485807c9..0c021f4b76d2 100644
--- a/drivers/soc/mediatek/mt8183-mmsys.h
+++ b/drivers/soc/mediatek/mt8183-mmsys.h
@@ -25,6 +25,8 @@
 #define MT8183_RDMA0_SOUT_COLOR0		0x1
 #define MT8183_RDMA1_SOUT_DSI0			0x1
 
+#define MT8183_MMSYS_SW0_RST_B			0x140
+
 static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
 	{
 		DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 0da25069ffb3..cab62c3eac05 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -49,12 +49,14 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
 	.clk_driver = "clk-mt8173-mm",
 	.routes = mmsys_default_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
+	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
 };
 
 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
 	.clk_driver = "clk-mt8183-mm",
 	.routes = mmsys_mt8183_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
+	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
 };
 
 static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
@@ -128,14 +130,14 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l
 
 	spin_lock_irqsave(&mmsys->lock, flags);
 
-	reg = readl_relaxed(mmsys->regs + MMSYS_SW0_RST_B);
+	reg = readl_relaxed(mmsys->regs + mmsys->data->sw0_rst_offset);
 
 	if (assert)
 		reg &= ~BIT(id);
 	else
 		reg |= BIT(id);
 
-	writel_relaxed(reg, mmsys->regs + MMSYS_SW0_RST_B);
+	writel_relaxed(reg, mmsys->regs + mmsys->data->sw0_rst_offset);
 
 	spin_unlock_irqrestore(&mmsys->lock, flags);
 
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 8b0ed05117ea..77f37f8c715b 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -78,8 +78,6 @@
 #define DSI_SEL_IN_RDMA				0x1
 #define DSI_SEL_IN_MASK				0x1
 
-#define MMSYS_SW0_RST_B				0x140
-
 struct mtk_mmsys_routes {
 	u32 from_comp;
 	u32 to_comp;
@@ -92,6 +90,7 @@ struct mtk_mmsys_driver_data {
 	const char *clk_driver;
 	const struct mtk_mmsys_routes *routes;
 	const unsigned int num_routes;
+	const u16 sw0_rst_offset;
 };
 
 /*
-- 
2.18.0


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[PATCH v2,2/2] soc: mediatek: mmsys: add mmsys reset control for MT8186

[Rex-BC Chen]

Add mmsys reset control register 0x160 for MT8186.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/soc/mediatek/mt8186-mmsys.h | 2 ++
 drivers/soc/mediatek/mtk-mmsys.c    | 1 +
 2 files changed, 3 insertions(+)

diff --git a/drivers/soc/mediatek/mt8186-mmsys.h b/drivers/soc/mediatek/mt8186-mmsys.h
index 7de329f2d729..c72ccf86ea28 100644
--- a/drivers/soc/mediatek/mt8186-mmsys.h
+++ b/drivers/soc/mediatek/mt8186-mmsys.h
@@ -52,6 +52,8 @@
 #define MT8186_DPI0_FROM_DITHER0			1
 #define MT8186_DPI0_FROM_RDMA0				2
 
+#define MT8186_MMSYS_SW0_RST_B				0x160
+
 static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = {
 	{
 		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index cab62c3eac05..4fc4c2c9ea20 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -63,6 +63,7 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
 	.clk_driver = "clk-mt8186-mm",
 	.routes = mmsys_mt8186_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table),
+	.sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
 };
 
 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
-- 
2.18.0

[PATCH v2, 2/2] soc: mediatek: mmsys: add mmsys reset control for MT8186

[Rex-BC Chen]

Add mmsys reset control register 0x160 for MT8186.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/soc/mediatek/mt8186-mmsys.h | 2 ++
 drivers/soc/mediatek/mtk-mmsys.c    | 1 +
 2 files changed, 3 insertions(+)

diff --git a/drivers/soc/mediatek/mt8186-mmsys.h b/drivers/soc/mediatek/mt8186-mmsys.h
index 7de329f2d729..c72ccf86ea28 100644
--- a/drivers/soc/mediatek/mt8186-mmsys.h
+++ b/drivers/soc/mediatek/mt8186-mmsys.h
@@ -52,6 +52,8 @@
 #define MT8186_DPI0_FROM_DITHER0			1
 #define MT8186_DPI0_FROM_RDMA0				2
 
+#define MT8186_MMSYS_SW0_RST_B				0x160
+
 static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = {
 	{
 		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index cab62c3eac05..4fc4c2c9ea20 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -63,6 +63,7 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
 	.clk_driver = "clk-mt8186-mm",
 	.routes = mmsys_mt8186_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table),
+	.sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
 };
 
 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
-- 
2.18.0


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[PATCH v2, 2/2] soc: mediatek: mmsys: add mmsys reset control for MT8186

[Rex-BC Chen]

Add mmsys reset control register 0x160 for MT8186.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/soc/mediatek/mt8186-mmsys.h | 2 ++
 drivers/soc/mediatek/mtk-mmsys.c    | 1 +
 2 files changed, 3 insertions(+)

diff --git a/drivers/soc/mediatek/mt8186-mmsys.h b/drivers/soc/mediatek/mt8186-mmsys.h
index 7de329f2d729..c72ccf86ea28 100644
--- a/drivers/soc/mediatek/mt8186-mmsys.h
+++ b/drivers/soc/mediatek/mt8186-mmsys.h
@@ -52,6 +52,8 @@
 #define MT8186_DPI0_FROM_DITHER0			1
 #define MT8186_DPI0_FROM_RDMA0				2
 
+#define MT8186_MMSYS_SW0_RST_B				0x160
+
 static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = {
 	{
 		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index cab62c3eac05..4fc4c2c9ea20 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -63,6 +63,7 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
 	.clk_driver = "clk-mt8186-mm",
 	.routes = mmsys_mt8186_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table),
+	.sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
 };
 
 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
-- 
2.18.0


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Re: [PATCH v2,1/2] soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data

[AngeloGioacchino Del Regno]

Il 17/02/22 09:26, Rex-BC Chen ha scritto:
> There are different software reset registers for difference MTK SoCs.
> Therefore, we add a new variable "sw0_rst_offset" to control it.
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   drivers/soc/mediatek/mt8183-mmsys.h | 2 ++
>   drivers/soc/mediatek/mtk-mmsys.c    | 6 ++++--
>   drivers/soc/mediatek/mtk-mmsys.h    | 3 +--
>   3 files changed, 7 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h
> index 9dee485807c9..0c021f4b76d2 100644
> --- a/drivers/soc/mediatek/mt8183-mmsys.h
> +++ b/drivers/soc/mediatek/mt8183-mmsys.h
> @@ -25,6 +25,8 @@
>   #define MT8183_RDMA0_SOUT_COLOR0		0x1
>   #define MT8183_RDMA1_SOUT_DSI0			0x1
>   
> +#define MT8183_MMSYS_SW0_RST_B			0x140
> +
>   static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
>   	{
>   		DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 0da25069ffb3..cab62c3eac05 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -49,12 +49,14 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
>   	.clk_driver = "clk-mt8173-mm",
>   	.routes = mmsys_default_routing_table,
>   	.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
> +	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
>   };
>   
>   static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
>   	.clk_driver = "clk-mt8183-mm",
>   	.routes = mmsys_mt8183_routing_table,
>   	.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
> +	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
>   };
>   
>   static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
> @@ -128,14 +130,14 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l
>   
>   	spin_lock_irqsave(&mmsys->lock, flags);
>   
> -	reg = readl_relaxed(mmsys->regs + MMSYS_SW0_RST_B);
> +	reg = readl_relaxed(mmsys->regs + mmsys->data->sw0_rst_offset);
>   
>   	if (assert)
>   		reg &= ~BIT(id);
>   	else
>   		reg |= BIT(id);
>   
> -	writel_relaxed(reg, mmsys->regs + MMSYS_SW0_RST_B);
> +	writel_relaxed(reg, mmsys->regs + mmsys->data->sw0_rst_offset);
>   
>   	spin_unlock_irqrestore(&mmsys->lock, flags);
>   
> diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
> index 8b0ed05117ea..77f37f8c715b 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.h
> +++ b/drivers/soc/mediatek/mtk-mmsys.h
> @@ -78,8 +78,6 @@
>   #define DSI_SEL_IN_RDMA				0x1
>   #define DSI_SEL_IN_MASK				0x1
>   
> -#define MMSYS_SW0_RST_B				0x140
> -
>   struct mtk_mmsys_routes {
>   	u32 from_comp;
>   	u32 to_comp;
> @@ -92,6 +90,7 @@ struct mtk_mmsys_driver_data {
>   	const char *clk_driver;
>   	const struct mtk_mmsys_routes *routes;
>   	const unsigned int num_routes;
> +	const u16 sw0_rst_offset;
>   };
>   
>   /*

Re: [PATCH v2, 1/2] soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data

[AngeloGioacchino Del Regno]

Il 17/02/22 09:26, Rex-BC Chen ha scritto:
> There are different software reset registers for difference MTK SoCs.
> Therefore, we add a new variable "sw0_rst_offset" to control it.
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   drivers/soc/mediatek/mt8183-mmsys.h | 2 ++
>   drivers/soc/mediatek/mtk-mmsys.c    | 6 ++++--
>   drivers/soc/mediatek/mtk-mmsys.h    | 3 +--
>   3 files changed, 7 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h
> index 9dee485807c9..0c021f4b76d2 100644
> --- a/drivers/soc/mediatek/mt8183-mmsys.h
> +++ b/drivers/soc/mediatek/mt8183-mmsys.h
> @@ -25,6 +25,8 @@
>   #define MT8183_RDMA0_SOUT_COLOR0		0x1
>   #define MT8183_RDMA1_SOUT_DSI0			0x1
>   
> +#define MT8183_MMSYS_SW0_RST_B			0x140
> +
>   static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
>   	{
>   		DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 0da25069ffb3..cab62c3eac05 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -49,12 +49,14 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
>   	.clk_driver = "clk-mt8173-mm",
>   	.routes = mmsys_default_routing_table,
>   	.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
> +	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
>   };
>   
>   static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
>   	.clk_driver = "clk-mt8183-mm",
>   	.routes = mmsys_mt8183_routing_table,
>   	.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
> +	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
>   };
>   
>   static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
> @@ -128,14 +130,14 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l
>   
>   	spin_lock_irqsave(&mmsys->lock, flags);
>   
> -	reg = readl_relaxed(mmsys->regs + MMSYS_SW0_RST_B);
> +	reg = readl_relaxed(mmsys->regs + mmsys->data->sw0_rst_offset);
>   
>   	if (assert)
>   		reg &= ~BIT(id);
>   	else
>   		reg |= BIT(id);
>   
> -	writel_relaxed(reg, mmsys->regs + MMSYS_SW0_RST_B);
> +	writel_relaxed(reg, mmsys->regs + mmsys->data->sw0_rst_offset);
>   
>   	spin_unlock_irqrestore(&mmsys->lock, flags);
>   
> diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
> index 8b0ed05117ea..77f37f8c715b 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.h
> +++ b/drivers/soc/mediatek/mtk-mmsys.h
> @@ -78,8 +78,6 @@
>   #define DSI_SEL_IN_RDMA				0x1
>   #define DSI_SEL_IN_MASK				0x1
>   
> -#define MMSYS_SW0_RST_B				0x140
> -
>   struct mtk_mmsys_routes {
>   	u32 from_comp;
>   	u32 to_comp;
> @@ -92,6 +90,7 @@ struct mtk_mmsys_driver_data {
>   	const char *clk_driver;
>   	const struct mtk_mmsys_routes *routes;
>   	const unsigned int num_routes;
> +	const u16 sw0_rst_offset;
>   };
>   
>   /*

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Re: [PATCH v2, 1/2] soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data

[AngeloGioacchino Del Regno]

Il 17/02/22 09:26, Rex-BC Chen ha scritto:
> There are different software reset registers for difference MTK SoCs.
> Therefore, we add a new variable "sw0_rst_offset" to control it.
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   drivers/soc/mediatek/mt8183-mmsys.h | 2 ++
>   drivers/soc/mediatek/mtk-mmsys.c    | 6 ++++--
>   drivers/soc/mediatek/mtk-mmsys.h    | 3 +--
>   3 files changed, 7 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h
> index 9dee485807c9..0c021f4b76d2 100644
> --- a/drivers/soc/mediatek/mt8183-mmsys.h
> +++ b/drivers/soc/mediatek/mt8183-mmsys.h
> @@ -25,6 +25,8 @@
>   #define MT8183_RDMA0_SOUT_COLOR0		0x1
>   #define MT8183_RDMA1_SOUT_DSI0			0x1
>   
> +#define MT8183_MMSYS_SW0_RST_B			0x140
> +
>   static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
>   	{
>   		DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 0da25069ffb3..cab62c3eac05 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -49,12 +49,14 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
>   	.clk_driver = "clk-mt8173-mm",
>   	.routes = mmsys_default_routing_table,
>   	.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
> +	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
>   };
>   
>   static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
>   	.clk_driver = "clk-mt8183-mm",
>   	.routes = mmsys_mt8183_routing_table,
>   	.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
> +	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
>   };
>   
>   static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
> @@ -128,14 +130,14 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l
>   
>   	spin_lock_irqsave(&mmsys->lock, flags);
>   
> -	reg = readl_relaxed(mmsys->regs + MMSYS_SW0_RST_B);
> +	reg = readl_relaxed(mmsys->regs + mmsys->data->sw0_rst_offset);
>   
>   	if (assert)
>   		reg &= ~BIT(id);
>   	else
>   		reg |= BIT(id);
>   
> -	writel_relaxed(reg, mmsys->regs + MMSYS_SW0_RST_B);
> +	writel_relaxed(reg, mmsys->regs + mmsys->data->sw0_rst_offset);
>   
>   	spin_unlock_irqrestore(&mmsys->lock, flags);
>   
> diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
> index 8b0ed05117ea..77f37f8c715b 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.h
> +++ b/drivers/soc/mediatek/mtk-mmsys.h
> @@ -78,8 +78,6 @@
>   #define DSI_SEL_IN_RDMA				0x1
>   #define DSI_SEL_IN_MASK				0x1
>   
> -#define MMSYS_SW0_RST_B				0x140
> -
>   struct mtk_mmsys_routes {
>   	u32 from_comp;
>   	u32 to_comp;
> @@ -92,6 +90,7 @@ struct mtk_mmsys_driver_data {
>   	const char *clk_driver;
>   	const struct mtk_mmsys_routes *routes;
>   	const unsigned int num_routes;
> +	const u16 sw0_rst_offset;
>   };
>   
>   /*

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Re: [PATCH v2,0/2] Add mmsys reset control for MT8186

[Matthias Brugger]

On 17/02/2022 09:26, Rex-BC Chen wrote:
> v2:
> 1. Change variable type from unsigned int to u16.
> 
> v1:
> 1. Add a new variable in mmsys driver data to control different register
>     offset for different SoCs.
> 2. Add MT8183 reset register offset.
> 3. Add mmsys reset control for MT8186.
> 
> This series is based on mmsys patch for MT8186 on [1].
> [1]: https://patchwork.kernel.org/project/linux-mediatek/patch/20220216084831.14883-4-rex-bc.chen@mediatek.com/
> 
> Rex-BC Chen (2):
>    soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data
>    soc: mediatek: mmsys: add mmsys reset control for MT8186
> 
>   drivers/soc/mediatek/mt8183-mmsys.h | 2 ++
>   drivers/soc/mediatek/mt8186-mmsys.h | 2 ++
>   drivers/soc/mediatek/mtk-mmsys.c    | 7 +++++--
>   drivers/soc/mediatek/mtk-mmsys.h    | 3 +--
>   4 files changed, 10 insertions(+), 4 deletions(-)
> 

Series applied, thanks!

Re: [PATCH v2,0/2] Add mmsys reset control for MT8186

[Matthias Brugger]

On 17/02/2022 09:26, Rex-BC Chen wrote:
> v2:
> 1. Change variable type from unsigned int to u16.
> 
> v1:
> 1. Add a new variable in mmsys driver data to control different register
>     offset for different SoCs.
> 2. Add MT8183 reset register offset.
> 3. Add mmsys reset control for MT8186.
> 
> This series is based on mmsys patch for MT8186 on [1].
> [1]: https://patchwork.kernel.org/project/linux-mediatek/patch/20220216084831.14883-4-rex-bc.chen@mediatek.com/
> 
> Rex-BC Chen (2):
>    soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data
>    soc: mediatek: mmsys: add mmsys reset control for MT8186
> 
>   drivers/soc/mediatek/mt8183-mmsys.h | 2 ++
>   drivers/soc/mediatek/mt8186-mmsys.h | 2 ++
>   drivers/soc/mediatek/mtk-mmsys.c    | 7 +++++--
>   drivers/soc/mediatek/mtk-mmsys.h    | 3 +--
>   4 files changed, 10 insertions(+), 4 deletions(-)
> 

Series applied, thanks!

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Re: [PATCH v2,0/2] Add mmsys reset control for MT8186

[Matthias Brugger]

On 17/02/2022 09:26, Rex-BC Chen wrote:
> v2:
> 1. Change variable type from unsigned int to u16.
> 
> v1:
> 1. Add a new variable in mmsys driver data to control different register
>     offset for different SoCs.
> 2. Add MT8183 reset register offset.
> 3. Add mmsys reset control for MT8186.
> 
> This series is based on mmsys patch for MT8186 on [1].
> [1]: https://patchwork.kernel.org/project/linux-mediatek/patch/20220216084831.14883-4-rex-bc.chen@mediatek.com/
> 
> Rex-BC Chen (2):
>    soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data
>    soc: mediatek: mmsys: add mmsys reset control for MT8186
> 
>   drivers/soc/mediatek/mt8183-mmsys.h | 2 ++
>   drivers/soc/mediatek/mt8186-mmsys.h | 2 ++
>   drivers/soc/mediatek/mtk-mmsys.c    | 7 +++++--
>   drivers/soc/mediatek/mtk-mmsys.h    | 3 +--
>   4 files changed, 10 insertions(+), 4 deletions(-)
> 

Series applied, thanks!

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Re: [PATCH v2,0/2] Add mmsys reset control for MT8186

[Rex-BC Chen]

Hello Matthias,

Thanks for accepting my patches, but I didn't see this patch [1]
in v5.17-next/soc.
There will be build error if [1] is not included while [2] is applied.
The sw0_rst_offset is declared in [2].

If I have mistake, please let me know.
Thanks!

[1]:
https://patchwork.kernel.org/project/linux-mediatek/patch/20220217082626.15728-2-rex-bc.chen@mediatek.com/

[2]:
https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/commit/?h=v5.17-next/soc&id=831785f0e5b919c29e1bc5f9a74e9ebd38289e24

BRs,
Rex
On Tue, 2022-03-01 at 08:35 +0100, Matthias Brugger wrote:
> 
> On 17/02/2022 09:26, Rex-BC Chen wrote:
> > v2:
> > 1. Change variable type from unsigned int to u16.
> > 
> > v1:
> > 1. Add a new variable in mmsys driver data to control different
> > register
> >     offset for different SoCs.
> > 2. Add MT8183 reset register offset.
> > 3. Add mmsys reset control for MT8186.
> > 
> > This series is based on mmsys patch for MT8186 on [1].
> > [1]: 
> > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20220216084831.14883-4-rex-bc.chen@mediatek.com/__;!!CTRNKA9wMg0ARbw!wp2uW6phbST6ySpYRlb7iwmATAVkkCL1JBau9dCwhXj8KRasrAWnLd1EUT9gLE-oF9Yq$
> >  
> > 
> > Rex-BC Chen (2):
> >    soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data
> >    soc: mediatek: mmsys: add mmsys reset control for MT8186
> > 
> >   drivers/soc/mediatek/mt8183-mmsys.h | 2 ++
> >   drivers/soc/mediatek/mt8186-mmsys.h | 2 ++
> >   drivers/soc/mediatek/mtk-mmsys.c    | 7 +++++--
> >   drivers/soc/mediatek/mtk-mmsys.h    | 3 +--
> >   4 files changed, 10 insertions(+), 4 deletions(-)
> > 
> 
> Series applied, thanks!

Re: [PATCH v2,0/2] Add mmsys reset control for MT8186

[Rex-BC Chen]

Hello Matthias,

Thanks for accepting my patches, but I didn't see this patch [1]
in v5.17-next/soc.
There will be build error if [1] is not included while [2] is applied.
The sw0_rst_offset is declared in [2].

If I have mistake, please let me know.
Thanks!

[1]:
https://patchwork.kernel.org/project/linux-mediatek/patch/20220217082626.15728-2-rex-bc.chen@mediatek.com/

[2]:
https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/commit/?h=v5.17-next/soc&id=831785f0e5b919c29e1bc5f9a74e9ebd38289e24

BRs,
Rex
On Tue, 2022-03-01 at 08:35 +0100, Matthias Brugger wrote:
> 
> On 17/02/2022 09:26, Rex-BC Chen wrote:
> > v2:
> > 1. Change variable type from unsigned int to u16.
> > 
> > v1:
> > 1. Add a new variable in mmsys driver data to control different
> > register
> >     offset for different SoCs.
> > 2. Add MT8183 reset register offset.
> > 3. Add mmsys reset control for MT8186.
> > 
> > This series is based on mmsys patch for MT8186 on [1].
> > [1]: 
> > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20220216084831.14883-4-rex-bc.chen@mediatek.com/__;!!CTRNKA9wMg0ARbw!wp2uW6phbST6ySpYRlb7iwmATAVkkCL1JBau9dCwhXj8KRasrAWnLd1EUT9gLE-oF9Yq$
> >  
> > 
> > Rex-BC Chen (2):
> >    soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data
> >    soc: mediatek: mmsys: add mmsys reset control for MT8186
> > 
> >   drivers/soc/mediatek/mt8183-mmsys.h | 2 ++
> >   drivers/soc/mediatek/mt8186-mmsys.h | 2 ++
> >   drivers/soc/mediatek/mtk-mmsys.c    | 7 +++++--
> >   drivers/soc/mediatek/mtk-mmsys.h    | 3 +--
> >   4 files changed, 10 insertions(+), 4 deletions(-)
> > 
> 
> Series applied, thanks!


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Re: [PATCH v2,0/2] Add mmsys reset control for MT8186

[Rex-BC Chen]

Hello Matthias,

Thanks for accepting my patches, but I didn't see this patch [1]
in v5.17-next/soc.
There will be build error if [1] is not included while [2] is applied.
The sw0_rst_offset is declared in [2].

If I have mistake, please let me know.
Thanks!

[1]:
https://patchwork.kernel.org/project/linux-mediatek/patch/20220217082626.15728-2-rex-bc.chen@mediatek.com/

[2]:
https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/commit/?h=v5.17-next/soc&id=831785f0e5b919c29e1bc5f9a74e9ebd38289e24

BRs,
Rex
On Tue, 2022-03-01 at 08:35 +0100, Matthias Brugger wrote:
> 
> On 17/02/2022 09:26, Rex-BC Chen wrote:
> > v2:
> > 1. Change variable type from unsigned int to u16.
> > 
> > v1:
> > 1. Add a new variable in mmsys driver data to control different
> > register
> >     offset for different SoCs.
> > 2. Add MT8183 reset register offset.
> > 3. Add mmsys reset control for MT8186.
> > 
> > This series is based on mmsys patch for MT8186 on [1].
> > [1]: 
> > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20220216084831.14883-4-rex-bc.chen@mediatek.com/__;!!CTRNKA9wMg0ARbw!wp2uW6phbST6ySpYRlb7iwmATAVkkCL1JBau9dCwhXj8KRasrAWnLd1EUT9gLE-oF9Yq$
> >  
> > 
> > Rex-BC Chen (2):
> >    soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data
> >    soc: mediatek: mmsys: add mmsys reset control for MT8186
> > 
> >   drivers/soc/mediatek/mt8183-mmsys.h | 2 ++
> >   drivers/soc/mediatek/mt8186-mmsys.h | 2 ++
> >   drivers/soc/mediatek/mtk-mmsys.c    | 7 +++++--
> >   drivers/soc/mediatek/mtk-mmsys.h    | 3 +--
> >   4 files changed, 10 insertions(+), 4 deletions(-)
> > 
> 
> Series applied, thanks!


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Re: [PATCH v2,0/2] Add mmsys reset control for MT8186

[Matthias Brugger]

Hi Rex,

On 01/03/2022 12:13, Rex-BC Chen wrote:
> Hello Matthias,
> 
> Thanks for accepting my patches, but I didn't see this patch [1]
> in v5.17-next/soc.
> There will be build error if [1] is not included while [2] is applied.
> The sw0_rst_offset is declared in [2].
> 
> If I have mistake, please let me know.

Thanks for the info. That was actually my mistake. Should be fixed by now.

Thanks a lot!
Matthias

> Thanks!
> 
> [1]:
> https://patchwork.kernel.org/project/linux-mediatek/patch/20220217082626.15728-2-rex-bc.chen@mediatek.com/
> 
> [2]:
> https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/commit/?h=v5.17-next/soc&id=831785f0e5b919c29e1bc5f9a74e9ebd38289e24
> 
> BRs,
> Rex
> On Tue, 2022-03-01 at 08:35 +0100, Matthias Brugger wrote:
>>
>> On 17/02/2022 09:26, Rex-BC Chen wrote:
>>> v2:
>>> 1. Change variable type from unsigned int to u16.
>>>
>>> v1:
>>> 1. Add a new variable in mmsys driver data to control different
>>> register
>>>      offset for different SoCs.
>>> 2. Add MT8183 reset register offset.
>>> 3. Add mmsys reset control for MT8186.
>>>
>>> This series is based on mmsys patch for MT8186 on [1].
>>> [1]:
>>> https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20220216084831.14883-4-rex-bc.chen@mediatek.com/__;!!CTRNKA9wMg0ARbw!wp2uW6phbST6ySpYRlb7iwmATAVkkCL1JBau9dCwhXj8KRasrAWnLd1EUT9gLE-oF9Yq$
>>>   
>>>
>>> Rex-BC Chen (2):
>>>     soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data
>>>     soc: mediatek: mmsys: add mmsys reset control for MT8186
>>>
>>>    drivers/soc/mediatek/mt8183-mmsys.h | 2 ++
>>>    drivers/soc/mediatek/mt8186-mmsys.h | 2 ++
>>>    drivers/soc/mediatek/mtk-mmsys.c    | 7 +++++--
>>>    drivers/soc/mediatek/mtk-mmsys.h    | 3 +--
>>>    4 files changed, 10 insertions(+), 4 deletions(-)
>>>
>>
>> Series applied, thanks!
> 

Re: [PATCH v2,0/2] Add mmsys reset control for MT8186

[Matthias Brugger]

Hi Rex,

On 01/03/2022 12:13, Rex-BC Chen wrote:
> Hello Matthias,
> 
> Thanks for accepting my patches, but I didn't see this patch [1]
> in v5.17-next/soc.
> There will be build error if [1] is not included while [2] is applied.
> The sw0_rst_offset is declared in [2].
> 
> If I have mistake, please let me know.

Thanks for the info. That was actually my mistake. Should be fixed by now.

Thanks a lot!
Matthias

> Thanks!
> 
> [1]:
> https://patchwork.kernel.org/project/linux-mediatek/patch/20220217082626.15728-2-rex-bc.chen@mediatek.com/
> 
> [2]:
> https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/commit/?h=v5.17-next/soc&id=831785f0e5b919c29e1bc5f9a74e9ebd38289e24
> 
> BRs,
> Rex
> On Tue, 2022-03-01 at 08:35 +0100, Matthias Brugger wrote:
>>
>> On 17/02/2022 09:26, Rex-BC Chen wrote:
>>> v2:
>>> 1. Change variable type from unsigned int to u16.
>>>
>>> v1:
>>> 1. Add a new variable in mmsys driver data to control different
>>> register
>>>      offset for different SoCs.
>>> 2. Add MT8183 reset register offset.
>>> 3. Add mmsys reset control for MT8186.
>>>
>>> This series is based on mmsys patch for MT8186 on [1].
>>> [1]:
>>> https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20220216084831.14883-4-rex-bc.chen@mediatek.com/__;!!CTRNKA9wMg0ARbw!wp2uW6phbST6ySpYRlb7iwmATAVkkCL1JBau9dCwhXj8KRasrAWnLd1EUT9gLE-oF9Yq$
>>>   
>>>
>>> Rex-BC Chen (2):
>>>     soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data
>>>     soc: mediatek: mmsys: add mmsys reset control for MT8186
>>>
>>>    drivers/soc/mediatek/mt8183-mmsys.h | 2 ++
>>>    drivers/soc/mediatek/mt8186-mmsys.h | 2 ++
>>>    drivers/soc/mediatek/mtk-mmsys.c    | 7 +++++--
>>>    drivers/soc/mediatek/mtk-mmsys.h    | 3 +--
>>>    4 files changed, 10 insertions(+), 4 deletions(-)
>>>
>>
>> Series applied, thanks!
> 

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Linux-mediatek@lists.infradead.org
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Re: [PATCH v2,0/2] Add mmsys reset control for MT8186

[Matthias Brugger]

Hi Rex,

On 01/03/2022 12:13, Rex-BC Chen wrote:
> Hello Matthias,
> 
> Thanks for accepting my patches, but I didn't see this patch [1]
> in v5.17-next/soc.
> There will be build error if [1] is not included while [2] is applied.
> The sw0_rst_offset is declared in [2].
> 
> If I have mistake, please let me know.

Thanks for the info. That was actually my mistake. Should be fixed by now.

Thanks a lot!
Matthias

> Thanks!
> 
> [1]:
> https://patchwork.kernel.org/project/linux-mediatek/patch/20220217082626.15728-2-rex-bc.chen@mediatek.com/
> 
> [2]:
> https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/commit/?h=v5.17-next/soc&id=831785f0e5b919c29e1bc5f9a74e9ebd38289e24
> 
> BRs,
> Rex
> On Tue, 2022-03-01 at 08:35 +0100, Matthias Brugger wrote:
>>
>> On 17/02/2022 09:26, Rex-BC Chen wrote:
>>> v2:
>>> 1. Change variable type from unsigned int to u16.
>>>
>>> v1:
>>> 1. Add a new variable in mmsys driver data to control different
>>> register
>>>      offset for different SoCs.
>>> 2. Add MT8183 reset register offset.
>>> 3. Add mmsys reset control for MT8186.
>>>
>>> This series is based on mmsys patch for MT8186 on [1].
>>> [1]:
>>> https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20220216084831.14883-4-rex-bc.chen@mediatek.com/__;!!CTRNKA9wMg0ARbw!wp2uW6phbST6ySpYRlb7iwmATAVkkCL1JBau9dCwhXj8KRasrAWnLd1EUT9gLE-oF9Yq$
>>>   
>>>
>>> Rex-BC Chen (2):
>>>     soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data
>>>     soc: mediatek: mmsys: add mmsys reset control for MT8186
>>>
>>>    drivers/soc/mediatek/mt8183-mmsys.h | 2 ++
>>>    drivers/soc/mediatek/mt8186-mmsys.h | 2 ++
>>>    drivers/soc/mediatek/mtk-mmsys.c    | 7 +++++--
>>>    drivers/soc/mediatek/mtk-mmsys.h    | 3 +--
>>>    4 files changed, 10 insertions(+), 4 deletions(-)
>>>
>>
>> Series applied, thanks!
> 

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