[PATCH v2 0/7] arm64: dts: phyCORE-i.MX8MP SoM updates

[PATCH v2 0/7] arm64: dts: phyCORE-i.MX8MP SoM updates

[Teresa Remmet]

second version of several small changes for the phyCORE-i.MX8MP
SoM device tree. Including drive strength updates of different 
interfaces and PMIC configuration changes.

Changes in v2:
- Updated commit message of patch [7/7] as suggested 
  by Haibo
- Added Reviewed-by from Haibo

Regards,
Teresa

Jonas Kuenstler (1):
  arm64: dts: imx8mp-phycore-som: Set usdhc root clock for eMMC

Teresa Remmet (6):
  arm64: dts: imx8mp-phycore-som: Set minimum output impedance for eth
    phy
  arm64: dts: imx8mp-phycore-som: Adapt eMMC drive strength
  arm64: dts: imx8mp-phycore-som: Reduce drive strength for fec tx lines
  arm64: dts: imx8mp-phycore-som: Update WDOG muxing
  arm64: dts: imx8mp-phycore-som: Set VDD_ARM run and standby voltage
  arm64: dts: imx8mp-phycore-som: LDO5 needs to be enabled instead of
    LDO4

 .../dts/freescale/imx8mp-phycore-som.dtsi     | 39 +++++++++++--------
 1 file changed, 22 insertions(+), 17 deletions(-)

-- 
2.25.1


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[PATCH v2 1/7] arm64: dts: imx8mp-phycore-som: Set minimum output impedance for eth phy

[Teresa Remmet]

To fit spec requirements set minimum output impedance for dp83867
ethernet phy.

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
---
 arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
index fc178eebf8aa..778f601a0119 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
@@ -60,6 +60,7 @@ ethphy1: ethernet-phy@0 {
 			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 			ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+			ti,min-output-impedance;
 			enet-phy-lane-no-swap;
 		};
 	};
-- 
2.25.1


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[PATCH v2 2/7] arm64: dts: imx8mp-phycore-som: Adapt eMMC drive strength

[Teresa Remmet]

Set eMMC drive strength for USDHC3_DATA lines (200Mhz)
to X4 for signal improvement.

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
---
Changes in v2:
- Added Reviewed-by tag

 .../boot/dts/freescale/imx8mp-phycore-som.dtsi   | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
index 778f601a0119..927290990d02 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
@@ -299,14 +299,14 @@ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
 		fsl,pins = <
 			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196
 			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6
-			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d6
-			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d6
-			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d6
-			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d6
-			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d6
-			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d6
-			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d6
-			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d6
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d2
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d2
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d2
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d2
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d2
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d2
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d2
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d2
 			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196
 		>;
 	};
-- 
2.25.1


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[PATCH v2 3/7] arm64: dts: imx8mp-phycore-som: Reduce drive strength for fec tx lines

[Teresa Remmet]

Reduce drive strength on fec tx lines for signal quality improvements.
Measurements showed that TD0 and TD1 require X4 and the other lines
X2 for optimized settings.

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
---
 .../arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
index 927290990d02..06e94f6e1702 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
@@ -222,12 +222,12 @@ MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91
 			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91
 			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91
 			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91
-			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f
-			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f
-			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f
-			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f
-			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f
-			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f
+			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x12
+			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x12
+			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x14
+			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x14
+			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x14
+			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x14
 			MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15		0x11
 		>;
 	};
-- 
2.25.1


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[PATCH v2 4/7] arm64: dts: imx8mp-phycore-som: Update WDOG muxing

[Teresa Remmet]

To be able to trigger a reset also from an external source we
need to configure the WDOG pin as open drain.

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
---
 arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
index 06e94f6e1702..fb84032e529f 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
@@ -313,7 +313,7 @@ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196
 
 	pinctrl_wdog: wdoggrp {
 		fsl,pins = <
-			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0xc6
+			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0xe6
 		>;
 	};
 };
-- 
2.25.1


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[PATCH v2 5/7] arm64: dts: imx8mp-phycore-som: Set VDD_ARM run and standby voltage

[Teresa Remmet]

Add bindings for VDD_ARM (BUCK2) run and standby voltage.

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
---
 arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
index fb84032e529f..4855bfc9e6a3 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
@@ -114,6 +114,8 @@ buck2: BUCK2 {
 				regulator-boot-on;
 				regulator-always-on;
 				regulator-ramp-delay = <3125>;
+				nxp,dvs-run-voltage = <950000>;
+				nxp,dvs-standby-voltage = <850000>;
 			};
 
 			buck4: BUCK4 {
-- 
2.25.1


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[PATCH v2 6/7] arm64: dts: imx8mp-phycore-som: LDO5 needs to be enabled instead of LDO4

[Teresa Remmet]

LDO4 is not connected so disable it. And LDO5 is used for VSEL of
the NVCC_SD2 SD-Card bus. Having it disabled seems not to have an
impact on the functionality. We enable it, as it is used.

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
---
Changes in v2:
- Added Reviewed-by tag

 arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
index 4855bfc9e6a3..c471ab252a69 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
@@ -170,14 +170,14 @@ ldo4: LDO4 {
 				regulator-compatible = "LDO4";
 				regulator-min-microvolt = <800000>;
 				regulator-max-microvolt = <3300000>;
-				regulator-boot-on;
-				regulator-always-on;
 			};
 
 			ldo5: LDO5 {
 				regulator-compatible = "LDO5";
 				regulator-min-microvolt = <1800000>;
 				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
 			};
 		};
 	};
-- 
2.25.1


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[PATCH v2 7/7] arm64: dts: imx8mp-phycore-som: Set usdhc root clock for eMMC

[Teresa Remmet]

From: Jonas Kuenstler <j.kuenstler@phytec.de>

Set the usdhc root clock to 400MHz to be able to support
HS400/HS400ES modes for eMMC on phyCORE-i.MX8MP SoM.

Signed-off-by: Jonas Kuenstler <j.kuenstler@phytec.de>
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
---
Changes in v2:
- Updated commit message
- Added Reviewed-by tag

 arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
index c471ab252a69..79b290a002c1 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
@@ -197,6 +197,8 @@ rv3028: rtc@52 {
 
 /* eMMC */
 &usdhc3 {
+	assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>;
+	assigned-clock-rates = <400000000>;
 	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 	pinctrl-0 = <&pinctrl_usdhc3>;
 	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
-- 
2.25.1


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Re: [PATCH v2 0/7] arm64: dts: phyCORE-i.MX8MP SoM updates

[Shawn Guo]

On Fri, Feb 18, 2022 at 01:04:51PM +0100, Teresa Remmet wrote:
> second version of several small changes for the phyCORE-i.MX8MP
> SoM device tree. Including drive strength updates of different 
> interfaces and PMIC configuration changes.
> 
> Changes in v2:
> - Updated commit message of patch [7/7] as suggested 
>   by Haibo
> - Added Reviewed-by from Haibo
> 
> Regards,
> Teresa
> 
> Jonas Kuenstler (1):
>   arm64: dts: imx8mp-phycore-som: Set usdhc root clock for eMMC
> 
> Teresa Remmet (6):
>   arm64: dts: imx8mp-phycore-som: Set minimum output impedance for eth
>     phy
>   arm64: dts: imx8mp-phycore-som: Adapt eMMC drive strength
>   arm64: dts: imx8mp-phycore-som: Reduce drive strength for fec tx lines
>   arm64: dts: imx8mp-phycore-som: Update WDOG muxing
>   arm64: dts: imx8mp-phycore-som: Set VDD_ARM run and standby voltage
>   arm64: dts: imx8mp-phycore-som: LDO5 needs to be enabled instead of
>     LDO4

Applied, thanks!

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