* [PATCH v2 1/2] clk: qcom: clk-rcg2: Update logic to calculate D value for RCG
@ 2022-02-21 18:13 Taniya Das
2022-02-21 18:13 ` [PATCH v2 2/2] clk: qcom: clk-rcg2: Update the frac table for pixel clock Taniya Das
2022-02-24 22:27 ` [PATCH v2 1/2] clk: qcom: clk-rcg2: Update logic to calculate D value for RCG Stephen Boyd
0 siblings, 2 replies; 6+ messages in thread
From: Taniya Das @ 2022-02-21 18:13 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette
Cc: Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, Taniya Das
The display pixel clock has a requirement on certain newer platforms to
support M/N as (2/3) and the final D value calculated results in
underflow errors.
As the current implementation does not check for D value is within
the accepted range for a given M & N value. Update the logic to
calculate the final D value based on the range.
Fixes: 99cbd064b059f ("clk: qcom: Support display RCG clocks")
Signed-off-by: Taniya Das <tdas@codeaurora.org>
---
[v2]
* Update the if else check with clamp.
* Typecast the f->m to u32.
drivers/clk/qcom/clk-rcg2.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index e1b1b426fae4..3a78a2a16cf8 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -264,7 +264,7 @@ static int clk_rcg2_determine_floor_rate(struct clk_hw *hw,
static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
{
- u32 cfg, mask;
+ u32 cfg, mask, d_val, not2d_val, n_minus_m;
struct clk_hw *hw = &rcg->clkr.hw;
int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src);
@@ -283,8 +283,17 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
if (ret)
return ret;
+ /* Calculate 2d value */
+ d_val = f->n;
+
+ n_minus_m = f->n - f->m;
+ n_minus_m *= 2;
+
+ d_val = clamp(d_val, (u32)f->m, n_minus_m);
+ not2d_val = ~d_val & mask;
+
ret = regmap_update_bits(rcg->clkr.regmap,
- RCG_D_OFFSET(rcg), mask, ~f->n);
+ RCG_D_OFFSET(rcg), mask, not2d_val);
if (ret)
return ret;
}
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the Linux Foundation.
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 2/2] clk: qcom: clk-rcg2: Update the frac table for pixel clock
2022-02-21 18:13 [PATCH v2 1/2] clk: qcom: clk-rcg2: Update logic to calculate D value for RCG Taniya Das
@ 2022-02-21 18:13 ` Taniya Das
2022-02-24 22:28 ` Stephen Boyd
2022-02-24 22:27 ` [PATCH v2 1/2] clk: qcom: clk-rcg2: Update logic to calculate D value for RCG Stephen Boyd
1 sibling, 1 reply; 6+ messages in thread
From: Taniya Das @ 2022-02-21 18:13 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette
Cc: Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, Taniya Das
Support the new numerator and denominator for pixel clock.
Fixes: 99cbd064b059f ("clk: qcom: Support display RCG clocks")
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
---
drivers/clk/qcom/clk-rcg2.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 3a78a2a16cf8..cb5610c46882 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -729,6 +729,7 @@ static const struct frac_entry frac_table_pixel[] = {
{ 2, 9 },
{ 4, 9 },
{ 1, 1 },
+ { 2, 3 },
{ }
};
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the Linux Foundation.
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2 1/2] clk: qcom: clk-rcg2: Update logic to calculate D value for RCG
2022-02-21 18:13 [PATCH v2 1/2] clk: qcom: clk-rcg2: Update logic to calculate D value for RCG Taniya Das
2022-02-21 18:13 ` [PATCH v2 2/2] clk: qcom: clk-rcg2: Update the frac table for pixel clock Taniya Das
@ 2022-02-24 22:27 ` Stephen Boyd
1 sibling, 0 replies; 6+ messages in thread
From: Stephen Boyd @ 2022-02-24 22:27 UTC (permalink / raw)
To: Michael Turquette, Taniya Das
Cc: Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, Taniya Das
Quoting Taniya Das (2022-02-21 10:13:21)
> The display pixel clock has a requirement on certain newer platforms to
> support M/N as (2/3) and the final D value calculated results in
> underflow errors.
> As the current implementation does not check for D value is within
> the accepted range for a given M & N value. Update the logic to
> calculate the final D value based on the range.
>
> Fixes: 99cbd064b059f ("clk: qcom: Support display RCG clocks")
> Signed-off-by: Taniya Das <tdas@codeaurora.org>
> ---
> [v2]
> * Update the if else check with clamp.
> * Typecast the f->m to u32.
>
> drivers/clk/qcom/clk-rcg2.c | 13 +++++++++++--
> 1 file changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
> index e1b1b426fae4..3a78a2a16cf8 100644
> --- a/drivers/clk/qcom/clk-rcg2.c
> +++ b/drivers/clk/qcom/clk-rcg2.c
> @@ -264,7 +264,7 @@ static int clk_rcg2_determine_floor_rate(struct clk_hw *hw,
>
> static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
> {
> - u32 cfg, mask;
> + u32 cfg, mask, d_val, not2d_val, n_minus_m;
> struct clk_hw *hw = &rcg->clkr.hw;
> int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src);
>
> @@ -283,8 +283,17 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
> if (ret)
> return ret;
>
> + /* Calculate 2d value */
> + d_val = f->n;
> +
> + n_minus_m = f->n - f->m;
> + n_minus_m *= 2;
> +
> + d_val = clamp(d_val, (u32)f->m, n_minus_m);
Use clamp_t(u32, d_val, f->m, n_minus_m)
> + not2d_val = ~d_val & mask;
> +
> ret = regmap_update_bits(rcg->clkr.regmap,
> - RCG_D_OFFSET(rcg), mask, ~f->n);
> + RCG_D_OFFSET(rcg), mask, not2d_val);
> if (ret)
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 2/2] clk: qcom: clk-rcg2: Update the frac table for pixel clock
2022-02-21 18:13 ` [PATCH v2 2/2] clk: qcom: clk-rcg2: Update the frac table for pixel clock Taniya Das
@ 2022-02-24 22:28 ` Stephen Boyd
0 siblings, 0 replies; 6+ messages in thread
From: Stephen Boyd @ 2022-02-24 22:28 UTC (permalink / raw)
To: Michael Turquette, Taniya Das
Cc: Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, Taniya Das
Quoting Taniya Das (2022-02-21 10:13:22)
> Support the new numerator and denominator for pixel clock.
What SoCs does this patch affect? It would be good to know if it's
fixing something wrong with existing SoC support or if it's only for
future SoCs that will want to set a 2/3 divide.
>
> Fixes: 99cbd064b059f ("clk: qcom: Support display RCG clocks")
> Signed-off-by: Taniya Das <tdas@codeaurora.org>
> Reviewed-by: Stephen Boyd <sboyd@kernel.org>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 1/2] clk: qcom: clk-rcg2: Update logic to calculate D value for RCG
2022-02-02 17:25 Taniya Das
@ 2022-02-17 23:05 ` Stephen Boyd
0 siblings, 0 replies; 6+ messages in thread
From: Stephen Boyd @ 2022-02-17 23:05 UTC (permalink / raw)
To: Michael Turquette, Taniya Das
Cc: Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, devicetree, robh, robh+dt, Taniya Das
Quoting Taniya Das (2022-02-02 09:25:39)
> The current implementation does not check for D value is within
> the accepted range for a given M & N value. Update the logic to
> calculate the final D value based on the range.
Is this fixing any SoC that's supported now? Or is it future work? This
is important to know if this needs to be merged this week or next merge
window.
>
> Fixes: 99cbd064b059f ("clk: qcom: Support display RCG clocks")
> Signed-off-by: Taniya Das <tdas@codeaurora.org>
> ---
> * Split the patch and update the Fixes tag.
>
> drivers/clk/qcom/clk-rcg2.c | 14 ++++++++++++--
> 1 file changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
> index e1b1b426fae4..34251ec98def 100644
> --- a/drivers/clk/qcom/clk-rcg2.c
> +++ b/drivers/clk/qcom/clk-rcg2.c
> @@ -264,7 +264,7 @@ static int clk_rcg2_determine_floor_rate(struct clk_hw *hw,
>
> static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
> {
> - u32 cfg, mask;
> + u32 cfg, mask, d_val, not2d_val;
> struct clk_hw *hw = &rcg->clkr.hw;
> int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src);
>
> @@ -283,8 +283,18 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
> if (ret)
> return ret;
>
> + /* Calculate 2d value */
> + d_val = f->n;
> +
> + if (d_val > ((f->n - f->m) * 2))
Please make another local variable for (f->n - f->m) * 2
u32 n_minus_m;
...
n_minus_m = f->n - f->m;
n_minus_m *= 2;
d_val = clamp(d_val, f->m, n_minus_m);
not2d_val = ~d_val & mask;
would be better than if else logic because the types are all verified to
be compatible.
> + d_val = (f->n - f->m) * 2;
> + else if (d_val < f->m)
> + d_val = f->m;
> +
> + not2d_val = ~d_val & mask;
> +
> ret = regmap_update_bits(rcg->clkr.regmap,
> - RCG_D_OFFSET(rcg), mask, ~f->n);
> + RCG_D_OFFSET(rcg), mask, not2d_val);
> if (ret)
> return ret;
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 1/2] clk: qcom: clk-rcg2: Update logic to calculate D value for RCG
@ 2022-02-02 17:25 Taniya Das
2022-02-17 23:05 ` Stephen Boyd
0 siblings, 1 reply; 6+ messages in thread
From: Taniya Das @ 2022-02-02 17:25 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette
Cc: Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk,
linux-kernel, devicetree, robh, robh+dt, Taniya Das
The current implementation does not check for D value is within
the accepted range for a given M & N value. Update the logic to
calculate the final D value based on the range.
Fixes: 99cbd064b059f ("clk: qcom: Support display RCG clocks")
Signed-off-by: Taniya Das <tdas@codeaurora.org>
---
* Split the patch and update the Fixes tag.
drivers/clk/qcom/clk-rcg2.c | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index e1b1b426fae4..34251ec98def 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -264,7 +264,7 @@ static int clk_rcg2_determine_floor_rate(struct clk_hw *hw,
static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
{
- u32 cfg, mask;
+ u32 cfg, mask, d_val, not2d_val;
struct clk_hw *hw = &rcg->clkr.hw;
int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src);
@@ -283,8 +283,18 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
if (ret)
return ret;
+ /* Calculate 2d value */
+ d_val = f->n;
+
+ if (d_val > ((f->n - f->m) * 2))
+ d_val = (f->n - f->m) * 2;
+ else if (d_val < f->m)
+ d_val = f->m;
+
+ not2d_val = ~d_val & mask;
+
ret = regmap_update_bits(rcg->clkr.regmap,
- RCG_D_OFFSET(rcg), mask, ~f->n);
+ RCG_D_OFFSET(rcg), mask, not2d_val);
if (ret)
return ret;
}
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the Linux Foundation.
^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-02-24 22:28 UTC | newest]
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2022-02-21 18:13 [PATCH v2 1/2] clk: qcom: clk-rcg2: Update logic to calculate D value for RCG Taniya Das
2022-02-21 18:13 ` [PATCH v2 2/2] clk: qcom: clk-rcg2: Update the frac table for pixel clock Taniya Das
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2022-02-24 22:27 ` [PATCH v2 1/2] clk: qcom: clk-rcg2: Update logic to calculate D value for RCG Stephen Boyd
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