[PATCH 0/2] clk: zynq: trivial fixes

[PATCH 0/2] clk: zynq: trivial fixes

[Shubhrajyoti Datta]

Trivial patches.
No functional change inteded.

Shubhrajyoti Datta (2):
  clk: zynq: trivial warning fix
  clk: zynq: Update the parameters to zynq_clk_register_periph_clk

 drivers/clk/zynq/clkc.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

-- 
2.17.1

[PATCH 1/2] clk: zynq: trivial warning fix

[Shubhrajyoti Datta]

Fix the below warning

WARNING: Missing a blank line after declarations
+               int enable = !!(fclk_enable & BIT(i - fclk0));
+               zynq_clk_register_fclk(i, clk_output_name[i],

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
---
 drivers/clk/zynq/clkc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c
index 204b83d911b9..434511dcf5cb 100644
--- a/drivers/clk/zynq/clkc.c
+++ b/drivers/clk/zynq/clkc.c
@@ -349,6 +349,7 @@ static void __init zynq_clk_setup(struct device_node *np)
 	/* Peripheral clocks */
 	for (i = fclk0; i <= fclk3; i++) {
 		int enable = !!(fclk_enable & BIT(i - fclk0));
+
 		zynq_clk_register_fclk(i, clk_output_name[i],
 				SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0),
 				periph_parents, enable);
-- 
2.17.1

[PATCH 2/2] clk: zynq: Update the parameters to zynq_clk_register_periph_clk

[Shubhrajyoti Datta]

In case there are only one gate or the two_gate is 0 the clk1 clock
passed is not used. We are passing 0 which is arm_pll.
Pass a invalid clock instead.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
---
 drivers/clk/zynq/clkc.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c
index 434511dcf5cb..7bdeaff2bfd6 100644
--- a/drivers/clk/zynq/clkc.c
+++ b/drivers/clk/zynq/clkc.c
@@ -355,14 +355,14 @@ static void __init zynq_clk_setup(struct device_node *np)
 				periph_parents, enable);
 	}
 
-	zynq_clk_register_periph_clk(lqspi, 0, clk_output_name[lqspi], NULL,
-			SLCR_LQSPI_CLK_CTRL, periph_parents, 0);
+	zynq_clk_register_periph_clk(lqspi, clk_max, clk_output_name[lqspi], NULL,
+				     SLCR_LQSPI_CLK_CTRL, periph_parents, 0);
 
-	zynq_clk_register_periph_clk(smc, 0, clk_output_name[smc], NULL,
-			SLCR_SMC_CLK_CTRL, periph_parents, 0);
+	zynq_clk_register_periph_clk(smc, clk_max, clk_output_name[smc], NULL,
+				     SLCR_SMC_CLK_CTRL, periph_parents, 0);
 
-	zynq_clk_register_periph_clk(pcap, 0, clk_output_name[pcap], NULL,
-			SLCR_PCAP_CLK_CTRL, periph_parents, 0);
+	zynq_clk_register_periph_clk(pcap, clk_max, clk_output_name[pcap], NULL,
+				     SLCR_PCAP_CLK_CTRL, periph_parents, 0);
 
 	zynq_clk_register_periph_clk(sdio0, sdio1, clk_output_name[sdio0],
 			clk_output_name[sdio1], SLCR_SDIO_CLK_CTRL,
-- 
2.17.1

Re: [PATCH 1/2] clk: zynq: trivial warning fix

[Stephen Boyd]

Quoting Shubhrajyoti Datta (2022-02-22 05:09:02)
> Fix the below warning
> 
> WARNING: Missing a blank line after declarations
> +               int enable = !!(fclk_enable & BIT(i - fclk0));
> +               zynq_clk_register_fclk(i, clk_output_name[i],
> 
> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
> ---

Applied to clk-next

Re: [PATCH 2/2] clk: zynq: Update the parameters to zynq_clk_register_periph_clk

[Stephen Boyd]

Quoting Shubhrajyoti Datta (2022-02-22 05:09:03)
> In case there are only one gate or the two_gate is 0 the clk1 clock
> passed is not used. We are passing 0 which is arm_pll.
> Pass a invalid clock instead.
> 
> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
> ---

Applied to clk-next