From: matheus.ferst@eldorado.org.br
To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Cc: danielhb413@gmail.com, richard.henderson@linaro.org,
groug@kaod.org, clg@kaod.org,
Matheus Ferst <matheus.ferst@eldorado.org.br>,
david@gibson.dropbear.id.au
Subject: [PATCH v4 09/47] target/ppc: Move Vector Compare Equal/Not Equal/Greater Than to decodetree
Date: Tue, 22 Feb 2022 11:36:07 -0300 [thread overview]
Message-ID: <20220222143646.1268606-10-matheus.ferst@eldorado.org.br> (raw)
In-Reply-To: <20220222143646.1268606-1-matheus.ferst@eldorado.org.br>
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/helper.h | 30 ----------
target/ppc/insn32.decode | 24 ++++++++
target/ppc/int_helper.c | 54 -----------------
target/ppc/translate/vmx-impl.c.inc | 89 ++++++++++++++++++++---------
target/ppc/translate/vmx-ops.c.inc | 15 +----
5 files changed, 88 insertions(+), 124 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 6ac72868bb..fb421dd343 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -140,46 +140,16 @@ DEF_HELPER_3(vabsduw, void, avr, avr, avr)
DEF_HELPER_3(vavgsb, void, avr, avr, avr)
DEF_HELPER_3(vavgsh, void, avr, avr, avr)
DEF_HELPER_3(vavgsw, void, avr, avr, avr)
-DEF_HELPER_4(vcmpequb, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpequh, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpequw, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpequd, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpneb, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpneh, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpnew, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpnezb, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpnezh, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpnezw, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpgtub, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpgtuh, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpgtuw, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpgtud, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpgtsb, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpgtsh, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpgtsw, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpgtsd, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpeqfp, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgefp, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtfp, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpbfp, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpequb_dot, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpequh_dot, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpequw_dot, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpequd_dot, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpneb_dot, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpneh_dot, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpnew_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpnezb_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpnezh_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpnezw_dot, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpgtub_dot, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpgtuh_dot, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpgtuw_dot, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpgtud_dot, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpgtsb_dot, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpgtsh_dot, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpgtsw_dot, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpgtsd_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpeqfp_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgefp_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtfp_dot, void, env, avr, avr, avr)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index cba680075b..5443ee0394 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -51,6 +51,9 @@
&VA vrt vra vrb rc
@VA ...... vrt:5 vra:5 vrb:5 rc:5 ...... &VA
+&VC vrt vra vrb rc:bool
+@VC ...... vrt:5 vra:5 vrb:5 rc:1 .......... &VC
+
&VN vrt vra vrb sh
@VN ...... vrt:5 vra:5 vrb:5 .. sh:3 ...... &VN
@@ -373,6 +376,27 @@ DSCLIQ 111111 ..... ..... ...... 001000010 . @Z22_tap_sh_rc
DSCRI 111011 ..... ..... ...... 001100010 . @Z22_ta_sh_rc
DSCRIQ 111111 ..... ..... ...... 001100010 . @Z22_tap_sh_rc
+## Vector Integer Instructions
+
+VCMPEQUB 000100 ..... ..... ..... . 0000000110 @VC
+VCMPEQUH 000100 ..... ..... ..... . 0001000110 @VC
+VCMPEQUW 000100 ..... ..... ..... . 0010000110 @VC
+VCMPEQUD 000100 ..... ..... ..... . 0011000111 @VC
+
+VCMPGTSB 000100 ..... ..... ..... . 1100000110 @VC
+VCMPGTSH 000100 ..... ..... ..... . 1101000110 @VC
+VCMPGTSW 000100 ..... ..... ..... . 1110000110 @VC
+VCMPGTSD 000100 ..... ..... ..... . 1111000111 @VC
+
+VCMPGTUB 000100 ..... ..... ..... . 1000000110 @VC
+VCMPGTUH 000100 ..... ..... ..... . 1001000110 @VC
+VCMPGTUW 000100 ..... ..... ..... . 1010000110 @VC
+VCMPGTUD 000100 ..... ..... ..... . 1011000111 @VC
+
+VCMPNEB 000100 ..... ..... ..... . 0000000111 @VC
+VCMPNEH 000100 ..... ..... ..... . 0001000111 @VC
+VCMPNEW 000100 ..... ..... ..... . 0010000111 @VC
+
## Vector Bit Manipulation Instruction
VCFUGED 000100 ..... ..... ..... 10101001101 @VX
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index ade2b28795..c9e64014dc 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -662,57 +662,6 @@ VCF(ux, uint32_to_float32, u32)
VCF(sx, int32_to_float32, s32)
#undef VCF
-#define VCMP_DO(suffix, compare, element, record) \
- void helper_vcmp##suffix(CPUPPCState *env, ppc_avr_t *r, \
- ppc_avr_t *a, ppc_avr_t *b) \
- { \
- uint64_t ones = (uint64_t)-1; \
- uint64_t all = ones; \
- uint64_t none = 0; \
- int i; \
- \
- for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
- uint64_t result = (a->element[i] compare b->element[i] ? \
- ones : 0x0); \
- switch (sizeof(a->element[0])) { \
- case 8: \
- r->u64[i] = result; \
- break; \
- case 4: \
- r->u32[i] = result; \
- break; \
- case 2: \
- r->u16[i] = result; \
- break; \
- case 1: \
- r->u8[i] = result; \
- break; \
- } \
- all &= result; \
- none |= result; \
- } \
- if (record) { \
- env->crf[6] = ((all != 0) << 3) | ((none == 0) << 1); \
- } \
- }
-#define VCMP(suffix, compare, element) \
- VCMP_DO(suffix, compare, element, 0) \
- VCMP_DO(suffix##_dot, compare, element, 1)
-VCMP(equb, ==, u8)
-VCMP(equh, ==, u16)
-VCMP(equw, ==, u32)
-VCMP(equd, ==, u64)
-VCMP(gtub, >, u8)
-VCMP(gtuh, >, u16)
-VCMP(gtuw, >, u32)
-VCMP(gtud, >, u64)
-VCMP(gtsb, >, s8)
-VCMP(gtsh, >, s16)
-VCMP(gtsw, >, s32)
-VCMP(gtsd, >, s64)
-#undef VCMP_DO
-#undef VCMP
-
#define VCMPNE_DO(suffix, element, etype, cmpzero, record) \
void helper_vcmpne##suffix(CPUPPCState *env, ppc_avr_t *r, \
ppc_avr_t *a, ppc_avr_t *b) \
@@ -751,9 +700,6 @@ void helper_vcmpne##suffix(CPUPPCState *env, ppc_avr_t *r, \
VCMPNE(zb, u8, uint8_t, 1)
VCMPNE(zh, u16, uint16_t, 1)
VCMPNE(zw, u32, uint32_t, 1)
-VCMPNE(b, u8, uint8_t, 0)
-VCMPNE(h, u16, uint16_t, 0)
-VCMPNE(w, u32, uint32_t, 0)
#undef VCMPNE_DO
#undef VCMPNE
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index cf69f4c412..e007003f14 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -985,41 +985,74 @@ static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
} \
}
-GEN_VXRFORM(vcmpequb, 3, 0)
-GEN_VXRFORM(vcmpequh, 3, 1)
-GEN_VXRFORM(vcmpequw, 3, 2)
-GEN_VXRFORM(vcmpequd, 3, 3)
GEN_VXRFORM(vcmpnezb, 3, 4)
GEN_VXRFORM(vcmpnezh, 3, 5)
GEN_VXRFORM(vcmpnezw, 3, 6)
-GEN_VXRFORM(vcmpgtsb, 3, 12)
-GEN_VXRFORM(vcmpgtsh, 3, 13)
-GEN_VXRFORM(vcmpgtsw, 3, 14)
-GEN_VXRFORM(vcmpgtsd, 3, 15)
-GEN_VXRFORM(vcmpgtub, 3, 8)
-GEN_VXRFORM(vcmpgtuh, 3, 9)
-GEN_VXRFORM(vcmpgtuw, 3, 10)
-GEN_VXRFORM(vcmpgtud, 3, 11)
+
+static void do_vcmp_rc(int vrt)
+{
+ TCGv_i64 tmp, set, clr;
+
+ tmp = tcg_temp_new_i64();
+ set = tcg_temp_new_i64();
+ clr = tcg_temp_new_i64();
+
+ get_avr64(tmp, vrt, true);
+ tcg_gen_mov_i64(set, tmp);
+ get_avr64(tmp, vrt, false);
+ tcg_gen_or_i64(clr, set, tmp);
+ tcg_gen_and_i64(set, set, tmp);
+
+ tcg_gen_setcondi_i64(TCG_COND_EQ, clr, clr, 0);
+ tcg_gen_shli_i64(clr, clr, 1);
+
+ tcg_gen_setcondi_i64(TCG_COND_EQ, set, set, -1);
+ tcg_gen_shli_i64(set, set, 3);
+
+ tcg_gen_or_i64(tmp, set, clr);
+ tcg_gen_extrl_i64_i32(cpu_crf[6], tmp);
+
+ tcg_temp_free_i64(tmp);
+ tcg_temp_free_i64(set);
+ tcg_temp_free_i64(clr);
+}
+
+static bool do_vcmp(DisasContext *ctx, arg_VC *a, TCGCond cond, int vece)
+{
+ REQUIRE_VECTOR(ctx);
+
+ tcg_gen_gvec_cmp(cond, vece, avr_full_offset(a->vrt),
+ avr_full_offset(a->vra), avr_full_offset(a->vrb), 16, 16);
+
+ if (a->rc) {
+ do_vcmp_rc(a->vrt);
+ }
+
+ return true;
+}
+
+TRANS_FLAGS(ALTIVEC, VCMPEQUB, do_vcmp, TCG_COND_EQ, MO_8)
+TRANS_FLAGS(ALTIVEC, VCMPEQUH, do_vcmp, TCG_COND_EQ, MO_16)
+TRANS_FLAGS(ALTIVEC, VCMPEQUW, do_vcmp, TCG_COND_EQ, MO_32)
+TRANS_FLAGS2(ALTIVEC_207, VCMPEQUD, do_vcmp, TCG_COND_EQ, MO_64)
+
+TRANS_FLAGS(ALTIVEC, VCMPGTSB, do_vcmp, TCG_COND_GT, MO_8)
+TRANS_FLAGS(ALTIVEC, VCMPGTSH, do_vcmp, TCG_COND_GT, MO_16)
+TRANS_FLAGS(ALTIVEC, VCMPGTSW, do_vcmp, TCG_COND_GT, MO_32)
+TRANS_FLAGS2(ALTIVEC_207, VCMPGTSD, do_vcmp, TCG_COND_GT, MO_64)
+TRANS_FLAGS(ALTIVEC, VCMPGTUB, do_vcmp, TCG_COND_GTU, MO_8)
+TRANS_FLAGS(ALTIVEC, VCMPGTUH, do_vcmp, TCG_COND_GTU, MO_16)
+TRANS_FLAGS(ALTIVEC, VCMPGTUW, do_vcmp, TCG_COND_GTU, MO_32)
+TRANS_FLAGS2(ALTIVEC_207, VCMPGTUD, do_vcmp, TCG_COND_GTU, MO_64)
+
+TRANS_FLAGS2(ISA300, VCMPNEB, do_vcmp, TCG_COND_NE, MO_8)
+TRANS_FLAGS2(ISA300, VCMPNEH, do_vcmp, TCG_COND_NE, MO_16)
+TRANS_FLAGS2(ISA300, VCMPNEW, do_vcmp, TCG_COND_NE, MO_32)
+
GEN_VXRFORM(vcmpeqfp, 3, 3)
GEN_VXRFORM(vcmpgefp, 3, 7)
GEN_VXRFORM(vcmpgtfp, 3, 11)
GEN_VXRFORM(vcmpbfp, 3, 15)
-GEN_VXRFORM(vcmpneb, 3, 0)
-GEN_VXRFORM(vcmpneh, 3, 1)
-GEN_VXRFORM(vcmpnew, 3, 2)
-
-GEN_VXRFORM_DUAL(vcmpequb, PPC_ALTIVEC, PPC_NONE, \
- vcmpneb, PPC_NONE, PPC2_ISA300)
-GEN_VXRFORM_DUAL(vcmpequh, PPC_ALTIVEC, PPC_NONE, \
- vcmpneh, PPC_NONE, PPC2_ISA300)
-GEN_VXRFORM_DUAL(vcmpequw, PPC_ALTIVEC, PPC_NONE, \
- vcmpnew, PPC_NONE, PPC2_ISA300)
-GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
- vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
-GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
- vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
-GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
- vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
static void gen_vsplti(DisasContext *ctx, int vece)
{
diff --git a/target/ppc/translate/vmx-ops.c.inc b/target/ppc/translate/vmx-ops.c.inc
index 6787327f56..80d460c34e 100644
--- a/target/ppc/translate/vmx-ops.c.inc
+++ b/target/ppc/translate/vmx-ops.c.inc
@@ -187,19 +187,10 @@ GEN_HANDLER2_E(name, str, 0x4, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA300),
GEN_VXRFORM_300(vcmpnezb, 3, 4)
GEN_VXRFORM_300(vcmpnezh, 3, 5)
GEN_VXRFORM_300(vcmpnezw, 3, 6)
-GEN_VXRFORM(vcmpgtsb, 3, 12)
-GEN_VXRFORM(vcmpgtsh, 3, 13)
-GEN_VXRFORM(vcmpgtsw, 3, 14)
-GEN_VXRFORM(vcmpgtub, 3, 8)
-GEN_VXRFORM(vcmpgtuh, 3, 9)
-GEN_VXRFORM(vcmpgtuw, 3, 10)
-GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE)
+GEN_VXRFORM(vcmpeqfp, 3, 3)
GEN_VXRFORM(vcmpgefp, 3, 7)
-GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE)
-GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE)
-GEN_VXRFORM_DUAL(vcmpequb, vcmpneb, 3, 0, PPC_ALTIVEC, PPC_NONE)
-GEN_VXRFORM_DUAL(vcmpequh, vcmpneh, 3, 1, PPC_ALTIVEC, PPC_NONE)
-GEN_VXRFORM_DUAL(vcmpequw, vcmpnew, 3, 2, PPC_ALTIVEC, PPC_NONE)
+GEN_VXRFORM(vcmpgtfp, 3, 11)
+GEN_VXRFORM(vcmpbfp, 3, 15)
#define GEN_VXFORM_DUAL_INV(name0, name1, opc2, opc3, inval0, inval1, type) \
GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, \
--
2.25.1
next prev parent reply other threads:[~2022-02-22 15:13 UTC|newest]
Thread overview: 97+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-22 14:35 [PATCH v4 00/47] target/ppc: PowerISA Vector/VSX instruction batch matheus.ferst
2022-02-22 14:35 ` [PATCH v4 01/47] target/ppc: Introduce TRANS*FLAGS macros matheus.ferst
2022-02-22 14:36 ` [PATCH v4 02/47] target/ppc: moved vector even and odd multiplication to decodetree matheus.ferst
2022-02-22 18:19 ` Richard Henderson
2022-02-22 14:36 ` [PATCH v4 03/47] target/ppc: Moved vector multiply high and low " matheus.ferst
2022-02-22 18:19 ` Richard Henderson
2022-02-22 14:36 ` [PATCH v4 04/47] target/ppc: vmulh* instructions without helpers matheus.ferst
2022-02-22 18:23 ` Richard Henderson
2022-02-22 14:36 ` [PATCH v4 05/47] target/ppc: Implement vmsumcud instruction matheus.ferst
2022-02-22 18:28 ` Richard Henderson
2022-02-22 14:36 ` [PATCH v4 06/47] target/ppc: Implement vmsumudm instruction matheus.ferst
2022-02-22 14:36 ` [PATCH v4 07/47] target/ppc: Move vexts[bhw]2[wd] to decodetree matheus.ferst
2022-02-22 18:34 ` Richard Henderson
2022-02-22 14:36 ` [PATCH v4 08/47] target/ppc: Implement vextsd2q matheus.ferst
2022-02-22 14:36 ` matheus.ferst [this message]
2022-02-22 18:37 ` [PATCH v4 09/47] target/ppc: Move Vector Compare Equal/Not Equal/Greater Than to decodetree Richard Henderson
2022-02-22 14:36 ` [PATCH v4 10/47] target/ppc: Move Vector Compare Not Equal or Zero " matheus.ferst
2022-02-22 19:04 ` Richard Henderson
2022-02-22 14:36 ` [PATCH v4 11/47] target/ppc: Implement Vector Compare Equal Quadword matheus.ferst
2022-02-22 19:05 ` Richard Henderson
2022-02-22 14:36 ` [PATCH v4 12/47] target/ppc: Implement Vector Compare Greater Than Quadword matheus.ferst
2022-02-22 19:07 ` Richard Henderson
2022-02-22 14:36 ` [PATCH v4 13/47] target/ppc: Implement Vector Compare Quadword matheus.ferst
2022-02-22 14:36 ` [PATCH v4 14/47] target/ppc: implement vstri[bh][lr] matheus.ferst
2022-02-22 19:13 ` Richard Henderson
2022-02-22 14:36 ` [PATCH v4 15/47] target/ppc: implement vclrlb matheus.ferst
2022-02-22 19:15 ` Richard Henderson
2022-02-22 14:36 ` [PATCH v4 16/47] target/ppc: implement vclrrb matheus.ferst
2022-02-22 19:17 ` Richard Henderson
2022-02-22 14:36 ` [PATCH v4 17/47] target/ppc: implement vcntmb[bhwd] matheus.ferst
2022-02-22 14:36 ` [PATCH v4 18/47] target/ppc: implement vgnb matheus.ferst
2022-02-22 21:58 ` Richard Henderson
2022-02-22 14:36 ` [PATCH v4 19/47] target/ppc: move vs[lr][a][bhwd] to decodetree matheus.ferst
2022-02-22 22:01 ` Richard Henderson
2022-02-22 14:36 ` [PATCH v4 20/47] target/ppc: implement vslq matheus.ferst
2022-02-22 22:14 ` Richard Henderson
2022-02-23 21:53 ` Matheus K. Ferst
2022-02-23 22:12 ` Richard Henderson
2022-02-22 14:36 ` [PATCH v4 21/47] target/ppc: implement vsrq matheus.ferst
2022-02-22 22:15 ` Richard Henderson
2022-02-22 14:36 ` [PATCH v4 22/47] target/ppc: implement vsraq matheus.ferst
2022-02-22 22:19 ` Richard Henderson
2022-02-22 14:36 ` [PATCH v4 23/47] target/ppc: move vrl[bhwd] to decodetree matheus.ferst
2022-02-22 22:20 ` Richard Henderson
2022-02-22 14:36 ` [PATCH v4 24/47] target/ppc: move vrl[bhwd]nm/vrl[bhwd]mi " matheus.ferst
2022-02-22 22:30 ` Richard Henderson
2022-02-23 21:43 ` Matheus K. Ferst
2022-02-23 22:19 ` Richard Henderson
2022-02-24 20:23 ` Matheus K. Ferst
2022-02-24 21:26 ` Richard Henderson
2022-02-22 14:36 ` [PATCH v4 25/47] target/ppc: implement vrlq matheus.ferst
2022-02-22 22:33 ` Richard Henderson
2022-02-22 14:36 ` [PATCH v4 26/47] target/ppc: Move vsel and vperm/vpermr to decodetree matheus.ferst
2022-02-22 22:37 ` Richard Henderson
2022-02-22 14:36 ` [PATCH v4 27/47] target/ppc: Move xxsel " matheus.ferst
2022-02-22 22:38 ` Richard Henderson
2022-02-22 14:36 ` [PATCH v4 28/47] target/ppc: move xxperm/xxpermr " matheus.ferst
2022-02-22 22:40 ` Richard Henderson
2022-02-22 14:36 ` [PATCH v4 29/47] target/ppc: Move xxpermdi " matheus.ferst
2022-02-22 22:42 ` Richard Henderson
2022-02-22 14:36 ` [PATCH v4 30/47] target/ppc: Implement xxpermx instruction matheus.ferst
2022-02-22 22:46 ` Richard Henderson
2022-02-22 14:36 ` [PATCH v4 31/47] tcg/tcg-op-gvec.c: Introduce tcg_gen_gvec_4i matheus.ferst
2022-02-22 23:04 ` Richard Henderson
2022-02-22 14:36 ` [PATCH v4 32/47] target/ppc: Implement xxeval matheus.ferst
2022-02-22 23:43 ` Richard Henderson
2022-02-22 14:36 ` [PATCH v4 33/47] target/ppc: Implement xxgenpcv[bhwd]m instruction matheus.ferst
2022-02-22 23:48 ` Richard Henderson
2022-02-22 14:36 ` [PATCH v4 34/47] target/ppc: move xs[n]madd[am][ds]p/xs[n]msub[am][ds]p to decodetree matheus.ferst
2022-02-22 23:52 ` Richard Henderson
2022-02-22 14:36 ` [PATCH v4 35/47] target/ppc: implement xs[n]maddqp[o]/xs[n]msubqp[o] matheus.ferst
2022-02-22 23:56 ` Richard Henderson
2022-02-22 14:36 ` [PATCH v4 36/47] target/ppc: Implement xvtlsbb instruction matheus.ferst
2022-02-23 0:07 ` Richard Henderson
2022-02-22 14:36 ` [PATCH v4 37/47] target/ppc: Remove xscmpnedp instruction matheus.ferst
2022-02-22 14:36 ` [PATCH v4 38/47] target/ppc: Refactor VSX_SCALAR_CMP_DP matheus.ferst
2022-02-23 0:20 ` Richard Henderson
2022-02-24 19:16 ` Víctor Colombo
2022-02-24 21:24 ` Richard Henderson
2022-02-22 14:36 ` [PATCH v4 39/47] target/ppc: Implement xscmp{eq,ge,gt}qp matheus.ferst
2022-02-23 0:21 ` Richard Henderson
2022-02-22 14:36 ` [PATCH v4 40/47] target/ppc: Move xscmp{eq,ge,gt}dp to decodetree matheus.ferst
2022-02-23 0:22 ` [PATCH v4 40/47] target/ppc: Move xscmp{eq, ge, gt}dp " Richard Henderson
2022-02-22 14:36 ` [PATCH v4 41/47] target/ppc: Move xs{max, min}[cj]dp to use do_helper_XX3 matheus.ferst
2022-02-23 0:23 ` Richard Henderson
2022-02-22 14:36 ` [PATCH v4 42/47] target/ppc: Refactor VSX_MAX_MINC helper matheus.ferst
2022-02-23 0:40 ` Richard Henderson
2022-02-22 14:36 ` [PATCH v4 43/47] target/ppc: Implement xs{max,min}cqp matheus.ferst
2022-02-23 0:41 ` Richard Henderson
2022-02-22 14:36 ` [PATCH v4 44/47] target/ppc: Implement xvcvbf16spn and xvcvspbf16 instructions matheus.ferst
2022-02-23 3:08 ` Richard Henderson
2022-02-22 14:36 ` [PATCH v4 45/47] target/ppc: implement plxsd/pstxsd matheus.ferst
2022-02-23 3:14 ` Richard Henderson
2022-02-22 14:36 ` [PATCH v4 46/47] target/ppc: implement plxssp/pstxssp matheus.ferst
2022-02-23 3:16 ` Richard Henderson
2022-02-22 14:36 ` [PATCH v4 47/47] target/ppc: implement lxvr[bhwd]/stxvr[bhwd]x matheus.ferst
2022-02-23 3:23 ` Richard Henderson
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