* [PATCH 1/2] drm/amd/pm: update message definition for smu 13.0.5
@ 2022-02-24 11:30 Yifan Zhang
2022-02-24 11:30 ` [PATCH 2/2] drm/amd/pm: refine smu 13.0.5 pp table code Yifan Zhang
0 siblings, 1 reply; 2+ messages in thread
From: Yifan Zhang @ 2022-02-24 11:30 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Yifan Zhang, Ray.Huang
this patch updates message definition for smu 13.0.5
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
---
.../inc/pmfw_if/smu13_driver_if_v13_0_5.h | 1 -
.../pm/swsmu/inc/pmfw_if/smu_v13_0_5_ppsmc.h | 56 +++++++++----------
.../drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c | 4 +-
3 files changed, 29 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_5.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_5.h
index aa971412b434..f3a22642c88b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_5.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_5.h
@@ -103,7 +103,6 @@ typedef struct {
uint16_t ThrottlerStatus;
uint16_t CurrentSocketPower; //[mW]
- uint16_t spare1;
} SmuMetrics_t;
//Freq in MHz
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_5_ppsmc.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_5_ppsmc.h
index c6238c74923a..fb483bd9e147 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_5_ppsmc.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_5_ppsmc.h
@@ -32,34 +32,34 @@
#define PPSMC_Result_CmdRejectedBusy 0xFC
-// Message Definitions:
-#define PPSMC_MSG_TestMessage 1
-#define PPSMC_MSG_GetSmuVersion 2
-#define PPSMC_MSG_EnableGfxOff 3 ///< Enable GFXOFF
-#define PPSMC_MSG_DisableGfxOff 4 ///< Disable GFXOFF
-#define PPSMC_MSG_PowerDownVcn 5 ///< Power down VCN
-#define PPSMC_MSG_PowerUpVcn 6 ///< Power up VCN; VCN is power gated by default
-#define PPSMC_MSG_SetHardMinVcn 7 ///< For wireless display
-#define PPSMC_MSG_SetSoftMinGfxclk 8 ///< Set SoftMin for GFXCLK, argument is frequency in MHz
-#define PPSMC_MSG_Spare0 9 ///< Spare
-#define PPSMC_MSG_GfxDeviceDriverReset 10 ///< Request GFX mode 2 reset
-#define PPSMC_MSG_SetDriverDramAddrHigh 11 ///< Set high 32 bits of DRAM address for Driver table transfer
-#define PPSMC_MSG_SetDriverDramAddrLow 12 ///< Set low 32 bits of DRAM address for Driver table transfer
-#define PPSMC_MSG_TransferTableSmu2Dram 13 ///< Transfer driver interface table from PMFW SRAM to DRAM
-#define PPSMC_MSG_TransferTableDram2Smu 14 ///< Transfer driver interface table from DRAM to PMFW SRAM
-#define PPSMC_MSG_GetGfxclkFrequency 15 ///< Get GFX clock frequency
-#define PPSMC_MSG_GetEnabledSmuFeatures 16 ///< Get enabled features in PMFW
-#define PPSMC_MSG_SetSoftMaxVcn 17 ///< Set soft max for VCN clocks (VCLK and DCLK)
-#define PPSMC_MSG_PowerDownJpeg 18 ///< Power down Jpeg
-#define PPSMC_MSG_PowerUpJpeg 19 ///< Power up Jpeg; VCN is power gated by default
-#define PPSMC_MSG_SetSoftMaxGfxClk 20
-#define PPSMC_MSG_SetHardMinGfxClk 21 ///< Set hard min for GFX CLK
-#define PPSMC_MSG_AllowGfxOff 22 ///< Inform PMFW of allowing GFXOFF entry
-#define PPSMC_MSG_DisallowGfxOff 23 ///< Inform PMFW of disallowing GFXOFF entry
-#define PPSMC_MSG_SetSoftMinVcn 24 ///< Set soft min for VCN clocks (VCLK and DCLK)
-#define PPSMC_MSG_GetDriverIfVersion 25 ///< Get PMFW_DRIVER_IF version
-#define PPSMC_MSG_PrepareMp1ForUnload 26 ///< Prepare PMFW for GFX driver unload
-#define PPSMC_Message_Count 27
+#define PPSMC_MSG_TestMessage 0x01 ///< To check if PMFW is alive and responding. Requirement specified by PMFW team
+#define PPSMC_MSG_GetSmuVersion 0x02 ///< Get PMFW version
+#define PPSMC_MSG_SPARE0 0x03 ///< SPARE
+#define PPSMC_MSG_SPARE1 0x04 ///< SPARE
+#define PPSMC_MSG_PowerDownVcn 0x05 ///< Power down VCN
+#define PPSMC_MSG_PowerUpVcn 0x06 ///< Power up VCN; VCN is power gated by default
+#define PPSMC_MSG_SetHardMinVcn 0x07 ///< For wireless display
+#define PPSMC_MSG_SetSoftMinGfxclk 0x08 ///< Set SoftMin for GFXCLK, argument is frequency in MHz
+#define PPSMC_MSG_SPARE2 0x09 ///< SPARE
+#define PPSMC_MSG_GfxDeviceDriverReset 0x0A ///< Request GFX mode 2 reset
+#define PPSMC_MSG_SetDriverDramAddrHigh 0x0B ///< Set high 32 bits of DRAM address for Driver table transfer
+#define PPSMC_MSG_SetDriverDramAddrLow 0x0C ///< Set low 32 bits of DRAM address for Driver table transfer
+#define PPSMC_MSG_TransferTableSmu2Dram 0x0D ///< Transfer driver interface table from PMFW SRAM to DRAM
+#define PPSMC_MSG_TransferTableDram2Smu 0x0E ///< Transfer driver interface table from DRAM to PMFW SRAM
+#define PPSMC_MSG_GetGfxclkFrequency 0x0F ///< Get GFX clock frequency
+#define PPSMC_MSG_GetEnabledSmuFeatures 0x10 ///< Get enabled features in PMFW
+#define PPSMC_MSG_SetSoftMaxVcn 0x11 ///< Set soft max for VCN clocks (VCLK and DCLK)
+#define PPSMC_MSG_PowerDownJpeg 0x12 ///< Power down Jpeg
+#define PPSMC_MSG_PowerUpJpeg 0x13 ///< Power up Jpeg; VCN is power gated by default
+#define PPSMC_MSG_SetSoftMaxGfxClk 0x14 ///< Set soft min for GFX CLK
+#define PPSMC_MSG_SetHardMinGfxClk 0x15 ///< Set hard min for GFX CLK
+#define PPSMC_MSG_AllowGfxOff 0x16 ///< Inform PMFW of allowing GFXOFF entry
+#define PPSMC_MSG_DisallowGfxOff 0x17 ///< Inform PMFW of disallowing GFXOFF entry
+#define PPSMC_MSG_SetSoftMinVcn 0x18 ///< Set soft min for VCN clocks (VCLK and DCLK)
+#define PPSMC_MSG_GetDriverIfVersion 0x19 ///< Get PMFW_DRIVER_IF version
+#define PPSMC_MSG_PrepareMp1ForUnload 0x1A ///< Prepare PMFW for GFX driver unload
+#define PPSMC_MSG_GetThermalControllerLimit 0x1B ///< Provide thermal limit
+#define PPSMC_Message_Count 0x1C ///< Total number of PPSMC messages
/** @enum Mode_Reset_e
* Mode reset type, argument for PPSMC_MSG_GfxDeviceDriverReset
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
index 8ee5bcb60370..0bc15ff822a5 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
@@ -57,13 +57,11 @@
static struct cmn2asic_msg_mapping smu_v13_0_5_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
- MSG_MAP(EnableGfxOff, PPSMC_MSG_EnableGfxOff, 1),
- MSG_MAP(DisableGfxOff, PPSMC_MSG_DisableGfxOff, 1),
MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1),
MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1),
MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1),
MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk, 1),
- MSG_MAP(Spare0, PPSMC_MSG_Spare0, 1),
+ MSG_MAP(Spare0, PPSMC_MSG_SPARE0, 1),
MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 1),
MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
--
2.25.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [PATCH 2/2] drm/amd/pm: refine smu 13.0.5 pp table code
2022-02-24 11:30 [PATCH 1/2] drm/amd/pm: update message definition for smu 13.0.5 Yifan Zhang
@ 2022-02-24 11:30 ` Yifan Zhang
0 siblings, 0 replies; 2+ messages in thread
From: Yifan Zhang @ 2022-02-24 11:30 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Yifan Zhang, Ray.Huang
Based on smu 13.0.5 features, refine pp table code.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
---
.../drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c | 131 ++++--------------
.../drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.h | 1 +
2 files changed, 27 insertions(+), 105 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
index 0bc15ff822a5..f938eb1809cc 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
@@ -225,22 +225,6 @@ static bool smu_v13_0_5_is_dpm_running(struct smu_context *smu)
return !!(feature_enabled & SMC_DPM_FEATURE);
}
-static int smu_v13_0_5_post_smu_init(struct smu_context *smu)
-{
- /*
- struct amdgpu_device *adev = smu->adev;
- */
- int ret = 0;
-
- /* allow message will be sent after enable gfxoff on smu 13.0.5 */
- /*
- ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxOff, NULL);
- if (ret)
- dev_err(adev->dev, "Failed to Enable GfxOff!\n");
- */
- return ret;
-}
-
static int smu_v13_0_5_mode_reset(struct smu_context *smu, int type)
{
int ret = 0;
@@ -312,30 +296,6 @@ static int smu_v13_0_5_get_smu_metrics_data(struct smu_context *smu,
case METRICS_VOLTAGE_VDDSOC:
*value = metrics->Voltage[1];
break;
-#if 0
- case METRICS_SS_APU_SHARE:
- /* return the percentage of APU power with respect to APU's power limit.
- * percentage is reported, this isn't boost value. Smartshift power
- * boost/shift is only when the percentage is more than 100.
- */
- if (metrics->StapmOpnLimit > 0)
- *value = (metrics->ApuPower * 100) / metrics->StapmOpnLimit;
- else
- *value = 0;
- break;
- case METRICS_SS_DGPU_SHARE:
- /* return the percentage of dGPU power with respect to dGPU's power limit.
- * percentage is reported, this isn't boost value. Smartshift power
- * boost/shift is only when the percentage is more than 100.
- */
- if ((metrics->dGpuPower > 0) &&
- (metrics->StapmCurrentLimit > metrics->StapmOpnLimit))
- *value = (metrics->dGpuPower * 100) /
- (metrics->StapmCurrentLimit - metrics->StapmOpnLimit);
- else
- *value = 0;
- break;
-#endif
default:
*value = UINT_MAX;
break;
@@ -501,12 +461,6 @@ static ssize_t smu_v13_0_5_get_gpu_metrics(struct smu_context *smu,
gpu_metrics->temperature_gfx = metrics.GfxTemperature;
gpu_metrics->temperature_soc = metrics.SocTemperature;
- /*
- memcpy(&gpu_metrics->temperature_core[0],
- &metrics.CoreTemperature[0],
- sizeof(uint16_t) * 8);
- gpu_metrics->temperature_l3[0] = metrics.L3Temperature;
- */
gpu_metrics->average_gfx_activity = metrics.GfxActivity;
gpu_metrics->average_mm_activity = metrics.UvdActivity;
@@ -514,28 +468,13 @@ static ssize_t smu_v13_0_5_get_gpu_metrics(struct smu_context *smu,
gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
gpu_metrics->average_gfx_power = metrics.Power[0];
gpu_metrics->average_soc_power = metrics.Power[1];
- /*
- memcpy(&gpu_metrics->average_core_power[0],
- &metrics.CorePower[0],
- sizeof(uint16_t) * 8);
- */
-
gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
-
- /*
- memcpy(&gpu_metrics->current_coreclk[0],
- &metrics.CoreFrequency[0],
- sizeof(uint16_t) * 8);
- gpu_metrics->current_l3clk[0] = metrics.L3Frequency;
- */
-
gpu_metrics->throttle_status = metrics.ThrottlerStatus;
-
gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
*table = (void *)gpu_metrics;
@@ -650,9 +589,11 @@ static int smu_v13_0_5_get_current_clk_freq(struct smu_context *smu,
case SMU_MCLK:
member_type = METRICS_AVERAGE_UCLK;
break;
- case SMU_FCLK:
+ case SMU_GFXCLK:
+ case SMU_SCLK:
return smu_cmn_send_smc_msg_with_param(smu,
- SMU_MSG_GetFclkFrequency, 0, value);
+ SMU_MSG_GetGfxclkFrequency, 0, value);
+ break;
default:
return -EINVAL;
}
@@ -889,14 +830,6 @@ static int smu_v13_0_5_set_soft_freq_limited_range(struct smu_context *smu,
msg_set_min = SMU_MSG_SetHardMinGfxClk;
msg_set_max = SMU_MSG_SetSoftMaxGfxClk;
break;
- case SMU_FCLK:
- msg_set_min = SMU_MSG_SetHardMinFclkByFreq;
- msg_set_max = SMU_MSG_SetSoftMaxFclkByFreq;
- break;
- case SMU_SOCCLK:
- msg_set_min = SMU_MSG_SetHardMinSocclkByFreq;
- msg_set_max = SMU_MSG_SetSoftMaxSocclkByFreq;
- break;
case SMU_VCLK:
case SMU_DCLK:
msg_set_min = SMU_MSG_SetHardMinVcn;
@@ -943,7 +876,6 @@ static int smu_v13_0_5_print_clk_levels(struct smu_context *smu,
case SMU_VCLK:
case SMU_DCLK:
case SMU_MCLK:
- case SMU_FCLK:
ret = smu_v13_0_5_get_current_clk_freq(smu, clk_type, &cur_value);
if (ret)
goto print_clk_out;
@@ -961,6 +893,27 @@ static int smu_v13_0_5_print_clk_levels(struct smu_context *smu,
cur_value == value ? "*" : "");
}
break;
+ case SMU_GFXCLK:
+ case SMU_SCLK:
+ ret = smu_v13_0_5_get_current_clk_freq(smu, clk_type, &cur_value);
+ if (ret)
+ goto print_clk_out;
+ min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
+ max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
+ if (cur_value == max)
+ i = 2;
+ else if (cur_value == min)
+ i = 0;
+ else
+ i = 1;
+ size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
+ i == 0 ? "*" : "");
+ size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
+ i == 1 ? cur_value : SMU_13_0_5_UMD_PSTATE_GFXCLK,
+ i == 1 ? "*" : "");
+ size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
+ i == 2 ? "*" : "");
+ break;
default:
break;
}
@@ -969,6 +922,7 @@ static int smu_v13_0_5_print_clk_levels(struct smu_context *smu,
return size;
}
+
static int smu_v13_0_5_force_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type, uint32_t mask)
{
@@ -980,8 +934,6 @@ static int smu_v13_0_5_force_clk_levels(struct smu_context *smu,
soft_max_level = mask ? (fls(mask) - 1) : 0;
switch (clk_type) {
- case SMU_SOCCLK:
- case SMU_FCLK:
case SMU_VCLK:
case SMU_DCLK:
ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
@@ -1010,31 +962,19 @@ static int smu_v13_0_5_set_performance_level(struct smu_context *smu,
{
struct amdgpu_device *adev = smu->adev;
uint32_t sclk_min = 0, sclk_max = 0;
- uint32_t fclk_min = 0, fclk_max = 0;
- uint32_t socclk_min = 0, socclk_max = 0;
int ret = 0;
switch (level) {
case AMD_DPM_FORCED_LEVEL_HIGH:
smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_max);
- smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_max);
- smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_max);
sclk_min = sclk_max;
- fclk_min = fclk_max;
- socclk_min = socclk_max;
break;
case AMD_DPM_FORCED_LEVEL_LOW:
smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, NULL);
- smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, NULL);
- smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, NULL);
sclk_max = sclk_min;
- fclk_max = fclk_min;
- socclk_max = socclk_min;
break;
case AMD_DPM_FORCED_LEVEL_AUTO:
smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, &sclk_max);
- smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, &fclk_max);
- smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, &socclk_max);
break;
case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
@@ -1062,24 +1002,6 @@ static int smu_v13_0_5_set_performance_level(struct smu_context *smu,
smu->gfx_actual_soft_max_freq = sclk_max;
}
- if (fclk_min && fclk_max) {
- ret = smu_v13_0_5_set_soft_freq_limited_range(smu,
- SMU_FCLK,
- fclk_min,
- fclk_max);
- if (ret)
- return ret;
- }
-
- if (socclk_min && socclk_max) {
- ret = smu_v13_0_5_set_soft_freq_limited_range(smu,
- SMU_SOCCLK,
- socclk_min,
- socclk_max);
- if (ret)
- return ret;
- }
-
return ret;
}
@@ -1115,7 +1037,6 @@ static const struct pptable_funcs smu_v13_0_5_ppt_funcs = {
.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
.set_driver_table_location = smu_v13_0_set_driver_table_location,
.gfx_off_control = smu_v13_0_gfx_off_control,
- .post_init = smu_v13_0_5_post_smu_init,
.mode2_reset = smu_v13_0_5_mode2_reset,
.get_dpm_ultimate_freq = smu_v13_0_5_get_dpm_ultimate_freq,
.od_edit_dpm_table = smu_v13_0_5_od_edit_dpm_table,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.h
index d2e872c93650..40bc0f8e6d61 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.h
@@ -24,5 +24,6 @@
#define __SMU_V13_0_5_PPT_H__
extern void smu_v13_0_5_set_ppt_funcs(struct smu_context *smu);
+#define SMU_13_0_5_UMD_PSTATE_GFXCLK 1100
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
end of thread, other threads:[~2022-02-24 11:31 UTC | newest]
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