[PATCH 1/2] ARM: imx: imx8m: Add 933 MHz PLL settings

[PATCH 1/2] ARM: imx: imx8m: Add 933 MHz PLL settings

[Marek Vasut]

Add settings for operating PLL at 933 MHz. This setting is useful in
case the LPDDR4 DRAM should operate at 1866 MHz or 3733 MT/s.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
---
 arch/arm/mach-imx/imx8m/clock_imx8mm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index 76132defc21..4db55f86081 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -48,6 +48,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 #ifdef CONFIG_SPL_BUILD
 static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
 	PLL_1443X_RATE(1000000000U, 250, 3, 1, 0),
+	PLL_1443X_RATE(933000000U, 311, 4, 1, 0),
 	PLL_1443X_RATE(800000000U, 300, 9, 0, 0),
 	PLL_1443X_RATE(750000000U, 250, 8, 0, 0),
 	PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
-- 
2.34.1

[PATCH 2/2] imx8m: ddrphy_utils: Add 3732 MT/s mode

[Marek Vasut]

Add entry for 3732 MT/s mode of operation of the LPDDR4, in
which case the DDR PLL has to be configured in 933 MHz mode.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
---
 drivers/ddr/imx/imx8m/ddrphy_utils.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/ddr/imx/imx8m/ddrphy_utils.c b/drivers/ddr/imx/imx8m/ddrphy_utils.c
index 0f8baefb1f8..a54449e5f14 100644
--- a/drivers/ddr/imx/imx8m/ddrphy_utils.c
+++ b/drivers/ddr/imx/imx8m/ddrphy_utils.c
@@ -117,6 +117,10 @@ void ddrphy_init_set_dfi_clk(unsigned int drate)
 		dram_pll_init(MHZ(1000));
 		dram_disable_bypass();
 		break;
+	case 3732:
+		dram_pll_init(MHZ(933));
+		dram_disable_bypass();
+		break;
 	case 3200:
 		dram_pll_init(MHZ(800));
 		dram_disable_bypass();
-- 
2.34.1

Re: [PATCH 1/2] ARM: imx: imx8m: Add 933 MHz PLL settings

[Fabio Estevam]

On 26/02/2022 00:37, Marek Vasut wrote:
> Add settings for operating PLL at 933 MHz. This setting is useful in
> case the LPDDR4 DRAM should operate at 1866 MHz or 3733 MT/s.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Fabio Estevam <festevam@denx.de>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Stefano Babic <sbabic@denx.de>

Reviewed-by: Fabio Estevam <festevam@denx.de>

Re: [PATCH 2/2] imx8m: ddrphy_utils: Add 3732 MT/s mode

[Fabio Estevam]

On 26/02/2022 00:37, Marek Vasut wrote:
> Add entry for 3732 MT/s mode of operation of the LPDDR4, in
> which case the DDR PLL has to be configured in 933 MHz mode.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Fabio Estevam <festevam@denx.de>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Stefano Babic <sbabic@denx.de>

Reviewed-by: Fabio Estevam <festevam@denx.de>

Re: [PATCH 1/2] ARM: imx: imx8m: Add 933 MHz PLL settings

[Peng Fan (OSS)]

On 2022/2/26 11:37, Marek Vasut wrote:
> Add settings for operating PLL at 933 MHz. This setting is useful in
> case the LPDDR4 DRAM should operate at 1866 MHz or 3733 MT/s.

Is the DDR operation value get from NXP DDR TOOL?

Thanks,
Peng.

> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Fabio Estevam <festevam@denx.de>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
>   arch/arm/mach-imx/imx8m/clock_imx8mm.c | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> index 76132defc21..4db55f86081 100644
> --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> @@ -48,6 +48,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
>   #ifdef CONFIG_SPL_BUILD
>   static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
>   	PLL_1443X_RATE(1000000000U, 250, 3, 1, 0),
> +	PLL_1443X_RATE(933000000U, 311, 4, 1, 0),
>   	PLL_1443X_RATE(800000000U, 300, 9, 0, 0),
>   	PLL_1443X_RATE(750000000U, 250, 8, 0, 0),
>   	PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
> 

Re: [PATCH 1/2] ARM: imx: imx8m: Add 933 MHz PLL settings

[Marek Vasut]

On 3/21/22 03:48, Peng Fan (OSS) wrote:
> 
> 
> On 2022/2/26 11:37, Marek Vasut wrote:
>> Add settings for operating PLL at 933 MHz. This setting is useful in
>> case the LPDDR4 DRAM should operate at 1866 MHz or 3733 MT/s.
> 
> Is the DDR operation value get from NXP DDR TOOL?

No, the DDR RPA supports like two PLL settings, it is very limited.
I had to derive the PLL settings myself and been using those since.

Do you expect any stability issues ? I don't observe any so far, and I 
tested it including LCDIFv3 and GPU (etnaviv), no funny behavior was 
observed.

[PATCH 1/2] ARM: imx: imx8m: Add 933 MHz PLL settings

[sbabic]

> Add settings for operating PLL at 933 MHz. This setting is useful in
> case the LPDDR4 DRAM should operate at 1866 MHz or 3733 MT/s.
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Fabio Estevam <festevam@denx.de>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Stefano Babic <sbabic@denx.de>
> Reviewed-by: Fabio Estevam <festevam@denx.de>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH 2/2] imx8m: ddrphy_utils: Add 3732 MT/s mode

[sbabic]

> Add entry for 3732 MT/s mode of operation of the LPDDR4, in
> which case the DDR PLL has to be configured in 933 MHz mode.
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Fabio Estevam <festevam@denx.de>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Stefano Babic <sbabic@denx.de>
> Reviewed-by: Fabio Estevam <festevam@denx.de>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================