* [PULL 1/7] arm: Remove swift-bmc machine
2022-02-28 7:12 [PULL 0/7] aspeed queue Cédric Le Goater
@ 2022-02-28 7:12 ` Cédric Le Goater
2022-02-28 7:12 ` [PULL 2/7] ast2600: Add Secure Boot Controller model Cédric Le Goater
` (6 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Cédric Le Goater @ 2022-02-28 7:12 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Andrew Jeffery, Peter Maydell, Joel Stanley, Cédric Le Goater
From: Joel Stanley <joel@jms.id.au>
It was scheduled for removal in 7.0.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
docs/about/deprecated.rst | 7 ----
docs/about/removed-features.rst | 5 +++
docs/system/arm/aspeed.rst | 1 -
hw/arm/aspeed.c | 64 ---------------------------------
4 files changed, 5 insertions(+), 72 deletions(-)
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index 26d00812ba94..85773db631c1 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -315,13 +315,6 @@ Use the more generic event ``DEVICE_UNPLUG_GUEST_ERROR`` instead.
System emulator machines
------------------------
-Aspeed ``swift-bmc`` machine (since 6.1)
-''''''''''''''''''''''''''''''''''''''''
-
-This machine is deprecated because we have enough AST2500 based OpenPOWER
-machines. It can be easily replaced by the ``witherspoon-bmc`` or the
-``romulus-bmc`` machines.
-
PPC 405 ``taihu`` machine (since 7.0)
'''''''''''''''''''''''''''''''''''''
diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.rst
index cb0575fd4975..4b831ea29176 100644
--- a/docs/about/removed-features.rst
+++ b/docs/about/removed-features.rst
@@ -588,6 +588,11 @@ The Raspberry Pi machines come in various models (A, A+, B, B+). To be able
to distinguish which model QEMU is implementing, the ``raspi2`` and ``raspi3``
machines have been renamed ``raspi2b`` and ``raspi3b``.
+Aspeed ``swift-bmc`` machine (removed in 7.0)
+'''''''''''''''''''''''''''''''''''''''''''''
+
+This machine was removed because it was unused. Alternative AST2500 based
+OpenPOWER machines are ``witherspoon-bmc`` and ``romulus-bmc``.
linux-user mode CPUs
--------------------
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index d8b102fa0ad0..60ed94f18759 100644
--- a/docs/system/arm/aspeed.rst
+++ b/docs/system/arm/aspeed.rst
@@ -22,7 +22,6 @@ AST2500 SoC based machines :
- ``romulus-bmc`` OpenPOWER Romulus POWER9 BMC
- ``witherspoon-bmc`` OpenPOWER Witherspoon POWER9 BMC
- ``sonorapass-bmc`` OCP SonoraPass BMC
-- ``swift-bmc`` OpenPOWER Swift BMC POWER9 (to be removed in v7.0)
- ``fp5280g2-bmc`` Inspur FP5280G2 BMC
- ``g220a-bmc`` Bytedance G220A BMC
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index d911dc904fb3..faf7a9fd6863 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -106,17 +106,6 @@ struct AspeedMachineState {
SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
SCU_AST2500_HW_STRAP_RESERVED1)
-/* Swift hardware value: 0xF11AD206 */
-#define SWIFT_BMC_HW_STRAP1 ( \
- AST2500_HW_STRAP1_DEFAULTS | \
- SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
- SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
- SCU_AST2500_HW_STRAP_UART_DEBUG | \
- SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
- SCU_H_PLL_BYPASS_EN | \
- SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
- SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
-
#define G220A_BMC_HW_STRAP1 ( \
SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
@@ -544,35 +533,6 @@ static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
}
-static void swift_bmc_i2c_init(AspeedMachineState *bmc)
-{
- AspeedSoCState *soc = &bmc->soc;
-
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "pca9552", 0x60);
-
- /* The swift board expects a TMP275 but a TMP105 is compatible */
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "tmp105", 0x48);
- /* The swift board expects a pca9551 but a pca9552 is compatible */
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x60);
-
- /* The swift board expects an Epson RX8900 RTC but a ds1338 is compatible */
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "ds1338", 0x32);
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60);
-
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
- /* The swift board expects a pca9539 but a pca9552 is compatible */
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "pca9552", 0x74);
-
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
- /* The swift board expects a pca9539 but a pca9552 is compatible */
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "pca9552",
- 0x74);
-
- /* The swift board expects a TMP275 but a TMP105 is compatible */
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x48);
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x4a);
-}
-
static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
{
AspeedSoCState *soc = &bmc->soc;
@@ -1102,26 +1062,6 @@ static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
aspeed_soc_num_cpus(amc->soc_name);
};
-static void aspeed_machine_swift_class_init(ObjectClass *oc, void *data)
-{
- MachineClass *mc = MACHINE_CLASS(oc);
- AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
-
- mc->desc = "OpenPOWER Swift BMC (ARM1176)";
- amc->soc_name = "ast2500-a1";
- amc->hw_strap1 = SWIFT_BMC_HW_STRAP1;
- amc->fmc_model = "mx66l1g45g";
- amc->spi_model = "mx66l1g45g";
- amc->num_cs = 2;
- amc->i2c_init = swift_bmc_i2c_init;
- mc->default_ram_size = 512 * MiB;
- mc->default_cpus = mc->min_cpus = mc->max_cpus =
- aspeed_soc_num_cpus(amc->soc_name);
-
- mc->deprecation_reason = "redundant system. Please use a similar "
- "OpenPOWER BMC, Witherspoon or Romulus.";
-};
-
static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -1277,10 +1217,6 @@ static const TypeInfo aspeed_machine_types[] = {
.name = MACHINE_TYPE_NAME("romulus-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_romulus_class_init,
- }, {
- .name = MACHINE_TYPE_NAME("swift-bmc"),
- .parent = TYPE_ASPEED_MACHINE,
- .class_init = aspeed_machine_swift_class_init,
}, {
.name = MACHINE_TYPE_NAME("sonorapass-bmc"),
.parent = TYPE_ASPEED_MACHINE,
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PULL 2/7] ast2600: Add Secure Boot Controller model
2022-02-28 7:12 [PULL 0/7] aspeed queue Cédric Le Goater
2022-02-28 7:12 ` [PULL 1/7] arm: Remove swift-bmc machine Cédric Le Goater
@ 2022-02-28 7:12 ` Cédric Le Goater
2022-02-28 7:12 ` [PULL 3/7] aspeed: rainier: Add i2c LED devices Cédric Le Goater
` (5 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Cédric Le Goater @ 2022-02-28 7:12 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Andrew Jeffery, Peter Maydell, Joel Stanley, Cédric Le Goater
From: Joel Stanley <joel@jms.id.au>
Just a stub that indicates the system has booted in secure boot mode.
Used for testing the driver:
https://lore.kernel.org/all/20211019080608.283324-1-joel@jms.id.au/
Signed-off-by: Joel Stanley <joel@jms.id.au>
[ clg: - Fixed typo
- Adjusted Copyright dates ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/arm/aspeed_soc.h | 3 +
include/hw/misc/aspeed_sbc.h | 32 ++++++++
hw/arm/aspeed_ast2600.c | 9 +++
hw/misc/aspeed_sbc.c | 141 +++++++++++++++++++++++++++++++++++
hw/misc/meson.build | 1 +
5 files changed, 186 insertions(+)
create mode 100644 include/hw/misc/aspeed_sbc.h
create mode 100644 hw/misc/aspeed_sbc.c
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index cae9906684cb..da043dcb454d 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -24,6 +24,7 @@
#include "hw/misc/aspeed_i3c.h"
#include "hw/ssi/aspeed_smc.h"
#include "hw/misc/aspeed_hace.h"
+#include "hw/misc/aspeed_sbc.h"
#include "hw/watchdog/wdt_aspeed.h"
#include "hw/net/ftgmac100.h"
#include "target/arm/cpu.h"
@@ -60,6 +61,7 @@ struct AspeedSoCState {
AspeedSMCState fmc;
AspeedSMCState spi[ASPEED_SPIS_NUM];
EHCISysBusState ehci[ASPEED_EHCIS_NUM];
+ AspeedSBCState sbc;
AspeedSDMCState sdmc;
AspeedWDTState wdt[ASPEED_WDTS_NUM];
FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
@@ -109,6 +111,7 @@ enum {
ASPEED_DEV_SDMC,
ASPEED_DEV_SCU,
ASPEED_DEV_ADC,
+ ASPEED_DEV_SBC,
ASPEED_DEV_VIDEO,
ASPEED_DEV_SRAM,
ASPEED_DEV_SDHCI,
diff --git a/include/hw/misc/aspeed_sbc.h b/include/hw/misc/aspeed_sbc.h
new file mode 100644
index 000000000000..651747e28f3a
--- /dev/null
+++ b/include/hw/misc/aspeed_sbc.h
@@ -0,0 +1,32 @@
+/*
+ * ASPEED Secure Boot Controller
+ *
+ * Copyright (C) 2021-2022 IBM Corp.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef ASPEED_SBC_H
+#define ASPEED_SBC_H
+
+#include "hw/sysbus.h"
+
+#define TYPE_ASPEED_SBC "aspeed.sbc"
+#define TYPE_ASPEED_AST2600_SBC TYPE_ASPEED_SBC "-ast2600"
+OBJECT_DECLARE_TYPE(AspeedSBCState, AspeedSBCClass, ASPEED_SBC)
+
+#define ASPEED_SBC_NR_REGS (0x93c >> 2)
+
+struct AspeedSBCState {
+ SysBusDevice parent;
+
+ MemoryRegion iomem;
+
+ uint32_t regs[ASPEED_SBC_NR_REGS];
+};
+
+struct AspeedSBCClass {
+ SysBusDeviceClass parent_class;
+};
+
+#endif /* _ASPEED_SBC_H_ */
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index 12f6edc081fd..21cd3342c578 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -47,6 +47,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
[ASPEED_DEV_XDMA] = 0x1E6E7000,
[ASPEED_DEV_ADC] = 0x1E6E9000,
[ASPEED_DEV_DP] = 0x1E6EB000,
+ [ASPEED_DEV_SBC] = 0x1E6F2000,
[ASPEED_DEV_VIDEO] = 0x1E700000,
[ASPEED_DEV_SDHCI] = 0x1E740000,
[ASPEED_DEV_EMMC] = 0x1E750000,
@@ -227,6 +228,8 @@ static void aspeed_soc_ast2600_init(Object *obj)
object_initialize_child(obj, "hace", &s->hace, typename);
object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C);
+
+ object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC);
}
/*
@@ -539,6 +542,12 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
/* The AST2600 I3C controller has one IRQ per bus. */
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
}
+
+ /* Secure Boot Controller */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) {
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]);
}
static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
diff --git a/hw/misc/aspeed_sbc.c b/hw/misc/aspeed_sbc.c
new file mode 100644
index 000000000000..40f2a8c6312f
--- /dev/null
+++ b/hw/misc/aspeed_sbc.c
@@ -0,0 +1,141 @@
+/*
+ * ASPEED Secure Boot Controller
+ *
+ * Copyright (C) 2021-2022 IBM Corp.
+ *
+ * Joel Stanley <joel@jms.id.au>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/error-report.h"
+#include "hw/misc/aspeed_sbc.h"
+#include "qapi/error.h"
+#include "migration/vmstate.h"
+
+#define R_PROT (0x000 / 4)
+#define R_STATUS (0x014 / 4)
+
+static uint64_t aspeed_sbc_read(void *opaque, hwaddr addr, unsigned int size)
+{
+ AspeedSBCState *s = ASPEED_SBC(opaque);
+
+ addr >>= 2;
+
+ if (addr >= ASPEED_SBC_NR_REGS) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
+ __func__, addr << 2);
+ return 0;
+ }
+
+ return s->regs[addr];
+}
+
+static void aspeed_sbc_write(void *opaque, hwaddr addr, uint64_t data,
+ unsigned int size)
+{
+ AspeedSBCState *s = ASPEED_SBC(opaque);
+
+ addr >>= 2;
+
+ if (addr >= ASPEED_SBC_NR_REGS) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
+ __func__, addr << 2);
+ return;
+ }
+
+ switch (addr) {
+ case R_STATUS:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: write to read only register 0x%" HWADDR_PRIx "\n",
+ __func__, addr << 2);
+ return;
+ default:
+ break;
+ }
+
+ s->regs[addr] = data;
+}
+
+static const MemoryRegionOps aspeed_sbc_ops = {
+ .read = aspeed_sbc_read,
+ .write = aspeed_sbc_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 4,
+ },
+};
+
+static void aspeed_sbc_reset(DeviceState *dev)
+{
+ struct AspeedSBCState *s = ASPEED_SBC(dev);
+
+ memset(s->regs, 0, sizeof(s->regs));
+
+ /* Set secure boot enabled, and boot from emmc/spi */
+ s->regs[R_STATUS] = 1 << 6 | 1 << 5;
+}
+
+static void aspeed_sbc_realize(DeviceState *dev, Error **errp)
+{
+ AspeedSBCState *s = ASPEED_SBC(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+
+ memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sbc_ops, s,
+ TYPE_ASPEED_SBC, 0x1000);
+
+ sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static const VMStateDescription vmstate_aspeed_sbc = {
+ .name = TYPE_ASPEED_SBC,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, AspeedSBCState, ASPEED_SBC_NR_REGS),
+ VMSTATE_END_OF_LIST(),
+ }
+};
+
+static void aspeed_sbc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = aspeed_sbc_realize;
+ dc->reset = aspeed_sbc_reset;
+ dc->vmsd = &vmstate_aspeed_sbc;
+}
+
+static const TypeInfo aspeed_sbc_info = {
+ .name = TYPE_ASPEED_SBC,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(AspeedSBCState),
+ .class_init = aspeed_sbc_class_init,
+ .class_size = sizeof(AspeedSBCClass)
+};
+
+static void aspeed_ast2600_sbc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "AST2600 Secure Boot Controller";
+}
+
+static const TypeInfo aspeed_ast2600_sbc_info = {
+ .name = TYPE_ASPEED_AST2600_SBC,
+ .parent = TYPE_ASPEED_SBC,
+ .class_init = aspeed_ast2600_sbc_class_init,
+};
+
+static void aspeed_sbc_register_types(void)
+{
+ type_register_static(&aspeed_ast2600_sbc_info);
+ type_register_static(&aspeed_sbc_info);
+}
+
+type_init(aspeed_sbc_register_types);
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index 6dcbe044f3f0..645585371a8b 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -111,6 +111,7 @@ softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
'aspeed_i3c.c',
'aspeed_lpc.c',
'aspeed_scu.c',
+ 'aspeed_sbc.c',
'aspeed_sdmc.c',
'aspeed_xdma.c'))
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PULL 3/7] aspeed: rainier: Add i2c LED devices
2022-02-28 7:12 [PULL 0/7] aspeed queue Cédric Le Goater
2022-02-28 7:12 ` [PULL 1/7] arm: Remove swift-bmc machine Cédric Le Goater
2022-02-28 7:12 ` [PULL 2/7] ast2600: Add Secure Boot Controller model Cédric Le Goater
@ 2022-02-28 7:12 ` Cédric Le Goater
2022-02-28 7:12 ` [PULL 4/7] aspeed: rainier: Add strap values taken from hardware Cédric Le Goater
` (4 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Cédric Le Goater @ 2022-02-28 7:12 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Andrew Jeffery, Peter Maydell, Cédric Le Goater,
Joel Stanley, Philippe Mathieu-Daudé
From: Joel Stanley <joel@jms.id.au>
This helps quieten booting the current Rainier kernel.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/arm/aspeed.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index faf7a9fd6863..7590b36bb017 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -712,6 +712,8 @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "pca9552", 0x61);
+
/* The rainier expects a TMP275 but a TMP105 is compatible */
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
0x48);
@@ -724,11 +726,14 @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x60);
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
0x48);
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
0x49);
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "pca9552", 0x60);
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "pca9552", 0x61);
i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
"pca9546", 0x70);
aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
@@ -747,7 +752,12 @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x30);
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x31);
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x32);
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x33);
/* Bus 7: TODO max31785@52 */
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x60);
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x61);
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76);
/* Bus 7: TODO si7021-a20@20 */
@@ -762,6 +772,7 @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
0x4a);
aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB);
aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB);
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60);
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61);
/* Bus 8: ucd90320@11 */
/* Bus 8: ucd90320@b */
@@ -783,13 +794,17 @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
"pca9546", 0x70);
aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "pca9552", 0x60);
aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13), "pca9552", 0x60);
aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 14), "pca9552", 0x60);
aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "pca9552", 0x60);
}
static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PULL 4/7] aspeed: rainier: Add strap values taken from hardware
2022-02-28 7:12 [PULL 0/7] aspeed queue Cédric Le Goater
` (2 preceding siblings ...)
2022-02-28 7:12 ` [PULL 3/7] aspeed: rainier: Add i2c LED devices Cédric Le Goater
@ 2022-02-28 7:12 ` Cédric Le Goater
2022-02-28 7:12 ` [PULL 5/7] aspeed: Introduce a create_pca9552() helper Cédric Le Goater
` (3 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Cédric Le Goater @ 2022-02-28 7:12 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Andrew Jeffery, Peter Maydell, Joel Stanley, Cédric Le Goater
From: Joel Stanley <joel@jms.id.au>
When time permits, we should introduce defines for the HW strapping
registers to cleanly decode the values.
SCU500 = 0x00422016
Disable ARM JTAG trusted world debug: 0x1
Disable ARM JTAG debug: 0x1
VGA Memory Size: 0x1 [16MB]
Cortex M3: 0x1 [Disabled]
Boot device: 0x1 [eMMC]
Reserved: 0x1
SCU510 = 0x80000848
Secure Boot Enable: 0x1
Enable boot SPI or eMMC ABR (second boot): 0x1
Enable LPC mode: 0x1 [LPC]
Disable LPC SuperIO 0x2e/0x4e: 0x1
Signed-off-by: Joel Stanley <joel@jms.id.au>
[ clg: rewrote the commit log ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/arm/aspeed.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 7590b36bb017..f71a5d87473f 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -160,8 +160,8 @@ struct AspeedMachineState {
#define TACOMA_BMC_HW_STRAP2 0x00000040
/* Rainier hardware value: (QEMU prototype) */
-#define RAINIER_BMC_HW_STRAP1 0x00000000
-#define RAINIER_BMC_HW_STRAP2 0x00000000
+#define RAINIER_BMC_HW_STRAP1 0x00422016
+#define RAINIER_BMC_HW_STRAP2 0x80000848
/* Fuji hardware value */
#define FUJI_BMC_HW_STRAP1 0x00000000
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PULL 5/7] aspeed: Introduce a create_pca9552() helper
2022-02-28 7:12 [PULL 0/7] aspeed queue Cédric Le Goater
` (3 preceding siblings ...)
2022-02-28 7:12 ` [PULL 4/7] aspeed: rainier: Add strap values taken from hardware Cédric Le Goater
@ 2022-02-28 7:12 ` Cédric Le Goater
2022-02-28 7:12 ` [PULL 6/7] aspeed/smc: Add an address mask on segment registers Cédric Le Goater
` (2 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Cédric Le Goater @ 2022-02-28 7:12 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Andrew Jeffery, Peter Maydell, Philippe Mathieu-Daudé,
Joel Stanley, Cédric Le Goater
This unifies the way we create the pca9552 devices on the different boards.
Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/arm/aspeed.c | 49 +++++++++++++++++++++++++++----------------------
1 file changed, 27 insertions(+), 22 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index f71a5d87473f..11558b327bc9 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -533,6 +533,12 @@ static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
}
+static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
+{
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id),
+ TYPE_PCA9552, addr);
+}
+
static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
{
AspeedSoCState *soc = &bmc->soc;
@@ -549,9 +555,9 @@ static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54,
eeprom4_54);
/* PCA9539 @ 0x76, but PCA9552 is compatible */
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x76);
+ create_pca9552(soc, 4, 0x76);
/* PCA9539 @ 0x77, but PCA9552 is compatible */
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x77);
+ create_pca9552(soc, 4, 0x77);
/* bus 6 : */
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48);
@@ -562,8 +568,8 @@ static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
uint8_t *eeprom8_56 = g_malloc0(8 * 1024);
smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56,
eeprom8_56);
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60);
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61);
+ create_pca9552(soc, 8, 0x60);
+ create_pca9552(soc, 8, 0x61);
/* bus 8 : adc128d818 @ 0x1d */
/* bus 8 : adc128d818 @ 0x1f */
@@ -701,8 +707,7 @@ static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68);
/* It expects a pca9555 but a pca9552 is compatible */
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_PCA9552,
- 0x20);
+ create_pca9552(soc, 8, 0x30);
}
static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
@@ -712,7 +717,7 @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "pca9552", 0x61);
+ create_pca9552(soc, 3, 0x61);
/* The rainier expects a TMP275 but a TMP105 is compatible */
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
@@ -726,14 +731,14 @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x60);
+ create_pca9552(soc, 4, 0x60);
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
0x48);
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
0x49);
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "pca9552", 0x60);
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "pca9552", 0x61);
+ create_pca9552(soc, 5, 0x60);
+ create_pca9552(soc, 5, 0x61);
i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
"pca9546", 0x70);
aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
@@ -752,13 +757,13 @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x30);
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x31);
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x32);
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x33);
+ create_pca9552(soc, 7, 0x30);
+ create_pca9552(soc, 7, 0x31);
+ create_pca9552(soc, 7, 0x32);
+ create_pca9552(soc, 7, 0x33);
/* Bus 7: TODO max31785@52 */
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x60);
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x61);
+ create_pca9552(soc, 7, 0x60);
+ create_pca9552(soc, 7, 0x61);
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76);
/* Bus 7: TODO si7021-a20@20 */
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
@@ -772,8 +777,8 @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
0x4a);
aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB);
aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB);
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60);
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61);
+ create_pca9552(soc, 8, 0x60);
+ create_pca9552(soc, 8, 0x61);
/* Bus 8: ucd90320@11 */
/* Bus 8: ucd90320@b */
/* Bus 8: ucd90320@c */
@@ -794,17 +799,17 @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
"pca9546", 0x70);
aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "pca9552", 0x60);
+ create_pca9552(soc, 11, 0x60);
aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13), "pca9552", 0x60);
+ create_pca9552(soc, 13, 0x60);
aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 14), "pca9552", 0x60);
+ create_pca9552(soc, 14, 0x60);
aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "pca9552", 0x60);
+ create_pca9552(soc, 15, 0x60);
}
static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PULL 6/7] aspeed/smc: Add an address mask on segment registers
2022-02-28 7:12 [PULL 0/7] aspeed queue Cédric Le Goater
` (4 preceding siblings ...)
2022-02-28 7:12 ` [PULL 5/7] aspeed: Introduce a create_pca9552() helper Cédric Le Goater
@ 2022-02-28 7:12 ` Cédric Le Goater
2022-02-28 7:12 ` [PULL 7/7] aspeed/sdmc: Add trace events Cédric Le Goater
2022-03-01 10:43 ` [PULL 0/7] aspeed queue Peter Maydell
7 siblings, 0 replies; 9+ messages in thread
From: Cédric Le Goater @ 2022-02-28 7:12 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Andrew Jeffery, Peter Maydell, Joel Stanley, Cédric Le Goater
Only a limited set of bits are used for decoding the Start and End
addresses of the mapping window of a flash device.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ssi/aspeed_smc.h | 1 +
hw/ssi/aspeed_smc.c | 11 +++++++++++
2 files changed, 12 insertions(+)
diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h
index e26555581996..cad73ddc13f2 100644
--- a/include/hw/ssi/aspeed_smc.h
+++ b/include/hw/ssi/aspeed_smc.h
@@ -99,6 +99,7 @@ struct AspeedSMCClass {
uint8_t max_peripherals;
const uint32_t *resets;
const AspeedSegments *segments;
+ uint32_t segment_addr_mask;
hwaddr flash_window_base;
uint32_t flash_window_size;
uint32_t features;
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index ff154eb84f85..d899be17fd71 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/aspeed_smc.c
@@ -259,6 +259,10 @@ static void aspeed_smc_flash_set_segment_region(AspeedSMCState *s, int cs,
memory_region_set_enabled(&fl->mmio, !!seg.size);
memory_region_transaction_commit();
+ if (asc->segment_addr_mask) {
+ regval &= asc->segment_addr_mask;
+ }
+
s->regs[R_SEG_ADDR0 + cs] = regval;
}
@@ -1364,6 +1368,7 @@ static void aspeed_2400_fmc_class_init(ObjectClass *klass, void *data)
asc->conf_enable_w0 = CONF_ENABLE_W0;
asc->max_peripherals = 5;
asc->segments = aspeed_2400_fmc_segments;
+ asc->segment_addr_mask = 0xffff0000;
asc->resets = aspeed_2400_fmc_resets;
asc->flash_window_base = 0x20000000;
asc->flash_window_size = 0x10000000;
@@ -1446,6 +1451,7 @@ static void aspeed_2500_fmc_class_init(ObjectClass *klass, void *data)
asc->conf_enable_w0 = CONF_ENABLE_W0;
asc->max_peripherals = 3;
asc->segments = aspeed_2500_fmc_segments;
+ asc->segment_addr_mask = 0xffff0000;
asc->resets = aspeed_2500_fmc_resets;
asc->flash_window_base = 0x20000000;
asc->flash_window_size = 0x10000000;
@@ -1483,6 +1489,7 @@ static void aspeed_2500_spi1_class_init(ObjectClass *klass, void *data)
asc->conf_enable_w0 = CONF_ENABLE_W0;
asc->max_peripherals = 2;
asc->segments = aspeed_2500_spi1_segments;
+ asc->segment_addr_mask = 0xffff0000;
asc->flash_window_base = 0x30000000;
asc->flash_window_size = 0x8000000;
asc->features = 0x0;
@@ -1517,6 +1524,7 @@ static void aspeed_2500_spi2_class_init(ObjectClass *klass, void *data)
asc->conf_enable_w0 = CONF_ENABLE_W0;
asc->max_peripherals = 2;
asc->segments = aspeed_2500_spi2_segments;
+ asc->segment_addr_mask = 0xffff0000;
asc->flash_window_base = 0x38000000;
asc->flash_window_size = 0x8000000;
asc->features = 0x0;
@@ -1598,6 +1606,7 @@ static void aspeed_2600_fmc_class_init(ObjectClass *klass, void *data)
asc->conf_enable_w0 = CONF_ENABLE_W0;
asc->max_peripherals = 3;
asc->segments = aspeed_2600_fmc_segments;
+ asc->segment_addr_mask = 0x0ff00ff0;
asc->resets = aspeed_2600_fmc_resets;
asc->flash_window_base = 0x20000000;
asc->flash_window_size = 0x10000000;
@@ -1636,6 +1645,7 @@ static void aspeed_2600_spi1_class_init(ObjectClass *klass, void *data)
asc->conf_enable_w0 = CONF_ENABLE_W0;
asc->max_peripherals = 2;
asc->segments = aspeed_2600_spi1_segments;
+ asc->segment_addr_mask = 0x0ff00ff0;
asc->flash_window_base = 0x30000000;
asc->flash_window_size = 0x10000000;
asc->features = ASPEED_SMC_FEATURE_DMA |
@@ -1674,6 +1684,7 @@ static void aspeed_2600_spi2_class_init(ObjectClass *klass, void *data)
asc->conf_enable_w0 = CONF_ENABLE_W0;
asc->max_peripherals = 3;
asc->segments = aspeed_2600_spi2_segments;
+ asc->segment_addr_mask = 0x0ff00ff0;
asc->flash_window_base = 0x50000000;
asc->flash_window_size = 0x10000000;
asc->features = ASPEED_SMC_FEATURE_DMA |
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PULL 7/7] aspeed/sdmc: Add trace events
2022-02-28 7:12 [PULL 0/7] aspeed queue Cédric Le Goater
` (5 preceding siblings ...)
2022-02-28 7:12 ` [PULL 6/7] aspeed/smc: Add an address mask on segment registers Cédric Le Goater
@ 2022-02-28 7:12 ` Cédric Le Goater
2022-03-01 10:43 ` [PULL 0/7] aspeed queue Peter Maydell
7 siblings, 0 replies; 9+ messages in thread
From: Cédric Le Goater @ 2022-02-28 7:12 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Andrew Jeffery, Peter Maydell, Philippe Mathieu-Daudé,
Joel Stanley, Cédric Le Goater
This is useful to analyze changes in the U-Boot RAM driver when SDRAM
training is performed.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/misc/aspeed_sdmc.c | 2 ++
hw/misc/trace-events | 4 ++++
2 files changed, 6 insertions(+)
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
index 08f856cbda7e..d2a3931033b3 100644
--- a/hw/misc/aspeed_sdmc.c
+++ b/hw/misc/aspeed_sdmc.c
@@ -130,6 +130,7 @@ static uint64_t aspeed_sdmc_read(void *opaque, hwaddr addr, unsigned size)
return 0;
}
+ trace_aspeed_sdmc_read(addr, s->regs[addr]);
return s->regs[addr];
}
@@ -148,6 +149,7 @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
return;
}
+ trace_aspeed_sdmc_write(addr, data);
asc->write(s, addr, data);
}
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index 1c373dd0a4c5..fb5a3897807f 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -205,6 +205,10 @@ aspeed_i3c_write(uint64_t offset, uint64_t data) "I3C write: offset 0x%" PRIx64
aspeed_i3c_device_read(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] read: offset 0x%" PRIx64 " data 0x%" PRIx64
aspeed_i3c_device_write(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] write: offset 0x%" PRIx64 " data 0x%" PRIx64
+# aspeed_sdmc.c
+aspeed_sdmc_write(uint64_t reg, uint64_t data) "reg @0x%" PRIx64 " data: 0x%" PRIx64
+aspeed_sdmc_read(uint64_t reg, uint64_t data) "reg @0x%" PRIx64 " data: 0x%" PRIx64
+
# bcm2835_property.c
bcm2835_mbox_property(uint32_t tag, uint32_t bufsize, size_t resplen) "mbox property tag:0x%08x in_sz:%u out_sz:%zu"
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PULL 0/7] aspeed queue
2022-02-28 7:12 [PULL 0/7] aspeed queue Cédric Le Goater
` (6 preceding siblings ...)
2022-02-28 7:12 ` [PULL 7/7] aspeed/sdmc: Add trace events Cédric Le Goater
@ 2022-03-01 10:43 ` Peter Maydell
7 siblings, 0 replies; 9+ messages in thread
From: Peter Maydell @ 2022-03-01 10:43 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: Andrew Jeffery, qemu-arm, qemu-devel, Joel Stanley
On Mon, 28 Feb 2022 at 07:12, Cédric Le Goater <clg@kaod.org> wrote:
>
> The following changes since commit c13b8e9973635f34f3ce4356af27a311c993729c:
>
> Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20220216' into staging (2022-02-16 09:57:11 +0000)
>
> are available in the Git repository at:
>
> https://github.com/legoater/qemu/ tags/pull-aspeed-20220227
>
> for you to fetch changes up to 3671342a38f21316a2bda62e7d607bbaedd60fd8:
>
> aspeed/sdmc: Add trace events (2022-02-26 18:40:51 +0100)
>
> ----------------------------------------------------------------
> aspeed queue:
>
> * Removal of the swift-bmc machine
> * New Secure Boot Controller model
> * Improvements on the rainier machine
> * Various small cleanups
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 9+ messages in thread