[igt-dev] [PATCH i-g-t 0/3] Use supported dma-buf regions in prime_mmap*

[igt-dev] [PATCH i-g-t 0/3] Use supported dma-buf regions in prime_mmap*

[Zbigniew Kempczyński]

Contains library helper + changes in prime_mmap*. Additionally removes
prime_mmap_coherency libdrm dependency.

v2: addressing review comments

Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>

Ch Sai Gowtham (1):
  tests/prime_mmap_coherency.c: Use intel_bb and intel_buf to remove
    libdrm dependency

Zbigniew Kempczyński (2):
  lib/intel_memory_regions: Add helper which creates supported dma-buf
    set
  tests/prime_mmap: Iterate over dma-buf supported memory regions

 lib/i915/intel_memory_region.c |  61 ++++++++++++++++
 lib/i915/intel_memory_region.h |   3 +
 tests/prime_mmap.c             |  34 ++-------
 tests/prime_mmap_coherency.c   | 128 ++++++++++++++++++++-------------
 4 files changed, 148 insertions(+), 78 deletions(-)

-- 
2.32.0

[igt-dev] [PATCH i-g-t 1/3] lib/intel_memory_regions: Add helper which creates supported dma-buf set

[Zbigniew Kempczyński]

As different systems support or not dma-buf add function helper which
will create set of supported by dma-buf memory regions.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 lib/i915/intel_memory_region.c | 61 ++++++++++++++++++++++++++++++++++
 lib/i915/intel_memory_region.h |  3 ++
 2 files changed, 64 insertions(+)

diff --git a/lib/i915/intel_memory_region.c b/lib/i915/intel_memory_region.c
index a8759e069..a2db74566 100644
--- a/lib/i915/intel_memory_region.c
+++ b/lib/i915/intel_memory_region.c
@@ -332,6 +332,67 @@ char *memregion_dynamic_subtest_name(struct igt_collection *set)
 	return name;
 }
 
+struct mmap_supported_region {
+	uint32_t region;
+	struct igt_list_head link;
+};
+
+/**
+ * get_dma_buf_mmap_supported_set:
+ * @i915: i915 drm file descriptor
+ * @set: memory regions set
+ *
+ * Function constructs set with regions which supports dma-buf mapping.
+ *
+ * Returns: set of regions which allows do dma-buf mmap or NULL otherwise.
+ *
+ * Note: set (igt_collection) need to be destroyed after use.
+ */
+struct igt_collection *
+get_dma_buf_mmap_supported_set(int i915, struct igt_collection *set)
+{
+	struct igt_collection *region, *supported_set = NULL;
+	uint32_t reg;
+	int dma_buf_fd;
+	char *ptr;
+	uint32_t handle, bosize = 4096;
+	int count = 0;
+	struct mmap_supported_region *mreg, *tmp;
+	IGT_LIST_HEAD(region_list);
+
+	for_each_combination(region, 1, set) {
+		reg = igt_collection_get_value(region, 0);
+		handle = gem_create_in_memory_regions(i915, bosize, reg);
+
+		dma_buf_fd = prime_handle_to_fd(i915, handle);
+		ptr = mmap(NULL, bosize, PROT_READ, MAP_SHARED, dma_buf_fd, 0);
+		if (ptr != MAP_FAILED) {
+			mreg = malloc(sizeof(*mreg));
+			igt_assert(mreg);
+			mreg->region = reg;
+			igt_list_add_tail(&mreg->link, &region_list);
+			count++;
+		}
+		munmap(ptr, bosize);
+		gem_close(i915, handle);
+		close(dma_buf_fd);
+	}
+
+	if (count) {
+		int i = 0;
+
+		supported_set = igt_collection_create(count);
+
+		igt_list_for_each_entry_safe(mreg, tmp, &region_list, link) {
+			igt_collection_set_value(supported_set, i++, mreg->region);
+			igt_list_del(&mreg->link);
+			free(mreg);
+		}
+	}
+
+	return supported_set;
+}
+
 /**
  * intel_dump_gpu_meminfo:
  * @info: pointer to drm_i915_query_memory_regions structure
diff --git a/lib/i915/intel_memory_region.h b/lib/i915/intel_memory_region.h
index 936e7d1c8..bd92267b6 100644
--- a/lib/i915/intel_memory_region.h
+++ b/lib/i915/intel_memory_region.h
@@ -111,6 +111,9 @@ __get_memory_region_set(struct drm_i915_query_memory_regions *regions,
 	__get_memory_region_set(regions, arr__, ARRAY_SIZE(arr__)); \
 })
 
+struct igt_collection *
+get_dma_buf_mmap_supported_set(int i915, struct igt_collection *set);
+
 char *memregion_dynamic_subtest_name(struct igt_collection *set);
 
 void intel_dump_gpu_meminfo(const struct drm_i915_query_memory_regions *info);
-- 
2.32.0

Re: [igt-dev] [PATCH i-g-t 1/3] lib/intel_memory_regions: Add helper which creates supported dma-buf set

[Gwan-gyeong Mun]

Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Tested-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>

If the https://patchwork.freedesktop.org/series/100737/ patch (currently 
under review) is applied to the i915, you can see that the 
igt@prime_mmap test works normally in dg1.

On 3/1/22 9:58 AM, Zbigniew Kempczyński wrote:
> As different systems support or not dma-buf add function helper which
> will create set of supported by dma-buf memory regions.
> 
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> ---
>   lib/i915/intel_memory_region.c | 61 ++++++++++++++++++++++++++++++++++
>   lib/i915/intel_memory_region.h |  3 ++
>   2 files changed, 64 insertions(+)
> 
> diff --git a/lib/i915/intel_memory_region.c b/lib/i915/intel_memory_region.c
> index a8759e069..a2db74566 100644
> --- a/lib/i915/intel_memory_region.c
> +++ b/lib/i915/intel_memory_region.c
> @@ -332,6 +332,67 @@ char *memregion_dynamic_subtest_name(struct igt_collection *set)
>   	return name;
>   }
>   
> +struct mmap_supported_region {
> +	uint32_t region;
> +	struct igt_list_head link;
> +};
> +
> +/**
> + * get_dma_buf_mmap_supported_set:
> + * @i915: i915 drm file descriptor
> + * @set: memory regions set
> + *
> + * Function constructs set with regions which supports dma-buf mapping.
> + *
> + * Returns: set of regions which allows do dma-buf mmap or NULL otherwise.
> + *
> + * Note: set (igt_collection) need to be destroyed after use.
> + */
> +struct igt_collection *
> +get_dma_buf_mmap_supported_set(int i915, struct igt_collection *set)
> +{
> +	struct igt_collection *region, *supported_set = NULL;
> +	uint32_t reg;
> +	int dma_buf_fd;
> +	char *ptr;
> +	uint32_t handle, bosize = 4096;
> +	int count = 0;
> +	struct mmap_supported_region *mreg, *tmp;
> +	IGT_LIST_HEAD(region_list);
> +
> +	for_each_combination(region, 1, set) {
> +		reg = igt_collection_get_value(region, 0);
> +		handle = gem_create_in_memory_regions(i915, bosize, reg);
> +
> +		dma_buf_fd = prime_handle_to_fd(i915, handle);
> +		ptr = mmap(NULL, bosize, PROT_READ, MAP_SHARED, dma_buf_fd, 0);
> +		if (ptr != MAP_FAILED) {
> +			mreg = malloc(sizeof(*mreg));
> +			igt_assert(mreg);
> +			mreg->region = reg;
> +			igt_list_add_tail(&mreg->link, &region_list);
> +			count++;
> +		}
> +		munmap(ptr, bosize);
> +		gem_close(i915, handle);
> +		close(dma_buf_fd);
> +	}
> +
> +	if (count) {
> +		int i = 0;
> +
> +		supported_set = igt_collection_create(count);
> +
> +		igt_list_for_each_entry_safe(mreg, tmp, &region_list, link) {
> +			igt_collection_set_value(supported_set, i++, mreg->region);
> +			igt_list_del(&mreg->link);
> +			free(mreg);
> +		}
> +	}
> +
> +	return supported_set;
> +}
> +
>   /**
>    * intel_dump_gpu_meminfo:
>    * @info: pointer to drm_i915_query_memory_regions structure
> diff --git a/lib/i915/intel_memory_region.h b/lib/i915/intel_memory_region.h
> index 936e7d1c8..bd92267b6 100644
> --- a/lib/i915/intel_memory_region.h
> +++ b/lib/i915/intel_memory_region.h
> @@ -111,6 +111,9 @@ __get_memory_region_set(struct drm_i915_query_memory_regions *regions,
>   	__get_memory_region_set(regions, arr__, ARRAY_SIZE(arr__)); \
>   })
>   
> +struct igt_collection *
> +get_dma_buf_mmap_supported_set(int i915, struct igt_collection *set);
> +
>   char *memregion_dynamic_subtest_name(struct igt_collection *set);
>   
>   void intel_dump_gpu_meminfo(const struct drm_i915_query_memory_regions *info);
> 

[igt-dev] [PATCH i-g-t 2/3] tests/prime_mmap: Iterate over dma-buf supported memory regions

[Zbigniew Kempczyński]

To avoid code duplication (prime_mmap_coherency uses similar code)
use helper function which returns dma-buf set of supported regions.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 tests/prime_mmap.c | 34 ++++++----------------------------
 1 file changed, 6 insertions(+), 28 deletions(-)

diff --git a/tests/prime_mmap.c b/tests/prime_mmap.c
index e0cb9a25b..d53185ff1 100644
--- a/tests/prime_mmap.c
+++ b/tests/prime_mmap.c
@@ -483,31 +483,6 @@ test_aperture_limit(uint32_t region, int size)
 	gem_close(fd, handle2);
 }
 
-static int
-check_for_dma_buf_mmap(struct igt_collection *set)
-{
-	struct igt_collection *region;
-	uint32_t reg;
-	int dma_buf_fd;
-	char *ptr;
-	uint32_t handle;
-	int ret = 1;
-
-	for_each_combination(region, 1, set) {
-		reg = igt_collection_get_value(region, 0);
-		handle = gem_create_in_memory_regions(fd, BO_SIZE, reg);
-
-		dma_buf_fd = prime_handle_to_fd(fd, handle);
-		ptr = mmap(NULL, BO_SIZE, PROT_READ, MAP_SHARED, dma_buf_fd, 0);
-		if (ptr != MAP_FAILED)
-			ret = 0;
-		munmap(ptr, BO_SIZE);
-		gem_close(fd, handle);
-		close(dma_buf_fd);
-	}
-	return ret;
-}
-
 #define SKIP_LMEM (1 << 0)
 #define SKIP_USERPTR (1 << 1)
 
@@ -527,7 +502,7 @@ static bool check_skip(uint32_t skip, uint32_t region)
 
 igt_main
 {
-	struct igt_collection *set, *regions;
+	struct igt_collection *set, *regions, *dma_buf_set;
 	struct drm_i915_query_memory_regions *query_info;
 	struct {
 		const char *name;
@@ -560,13 +535,15 @@ igt_main
 
 		set = get_memory_region_set(query_info, I915_SYSTEM_MEMORY,
 					    I915_DEVICE_MEMORY);
-		igt_assert(check_for_dma_buf_mmap(set) == 0);
+
+		dma_buf_set = get_dma_buf_mmap_supported_set(fd, set);
+		igt_require_f(dma_buf_set, "No dma-buf region supported\n");
 		errno = 0;
 	}
 
 	for (i = 0; i < ARRAY_SIZE(tests); i++)
 		igt_subtest_with_dynamic(tests[i].name) {
-			for_each_combination(regions, 1, set) {
+			for_each_combination(regions, 1, dma_buf_set) {
 				region = igt_collection_get_value(regions, 0);
 				size = gem_get_batch_size(fd, MEMORY_TYPE_FROM_REGION(region));
 				size = max(size, BO_SIZE);
@@ -582,6 +559,7 @@ igt_main
 	igt_fixture {
 		free(query_info);
 		igt_collection_destroy(set);
+		igt_collection_destroy(dma_buf_set);
 		close(fd);
 	}
 }
-- 
2.32.0

Re: [igt-dev] [PATCH i-g-t 2/3] tests/prime_mmap: Iterate over dma-buf supported memory regions

[Kamil Konieczny]

Dnia 2022-03-01 at 08:58:02 +0100, Zbigniew Kempczyński napisał(a):
> To avoid code duplication (prime_mmap_coherency uses similar code)
> use helper function which returns dma-buf set of supported regions.
> 
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> ---
>  tests/prime_mmap.c | 34 ++++++----------------------------
>  1 file changed, 6 insertions(+), 28 deletions(-)

Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>

> 
> diff --git a/tests/prime_mmap.c b/tests/prime_mmap.c
> index e0cb9a25b..d53185ff1 100644
> --- a/tests/prime_mmap.c
> +++ b/tests/prime_mmap.c
> @@ -483,31 +483,6 @@ test_aperture_limit(uint32_t region, int size)
>  	gem_close(fd, handle2);
>  }
>  
> -static int
> -check_for_dma_buf_mmap(struct igt_collection *set)
> -{
> -	struct igt_collection *region;
> -	uint32_t reg;
> -	int dma_buf_fd;
> -	char *ptr;
> -	uint32_t handle;
> -	int ret = 1;
> -
> -	for_each_combination(region, 1, set) {
> -		reg = igt_collection_get_value(region, 0);
> -		handle = gem_create_in_memory_regions(fd, BO_SIZE, reg);
> -
> -		dma_buf_fd = prime_handle_to_fd(fd, handle);
> -		ptr = mmap(NULL, BO_SIZE, PROT_READ, MAP_SHARED, dma_buf_fd, 0);
> -		if (ptr != MAP_FAILED)
> -			ret = 0;
> -		munmap(ptr, BO_SIZE);
> -		gem_close(fd, handle);
> -		close(dma_buf_fd);
> -	}
> -	return ret;
> -}
> -
>  #define SKIP_LMEM (1 << 0)
>  #define SKIP_USERPTR (1 << 1)
>  
> @@ -527,7 +502,7 @@ static bool check_skip(uint32_t skip, uint32_t region)
>  
>  igt_main
>  {
> -	struct igt_collection *set, *regions;
> +	struct igt_collection *set, *regions, *dma_buf_set;
>  	struct drm_i915_query_memory_regions *query_info;
>  	struct {
>  		const char *name;
> @@ -560,13 +535,15 @@ igt_main
>  
>  		set = get_memory_region_set(query_info, I915_SYSTEM_MEMORY,
>  					    I915_DEVICE_MEMORY);
> -		igt_assert(check_for_dma_buf_mmap(set) == 0);
> +
> +		dma_buf_set = get_dma_buf_mmap_supported_set(fd, set);
> +		igt_require_f(dma_buf_set, "No dma-buf region supported\n");
>  		errno = 0;
>  	}
>  
>  	for (i = 0; i < ARRAY_SIZE(tests); i++)
>  		igt_subtest_with_dynamic(tests[i].name) {
> -			for_each_combination(regions, 1, set) {
> +			for_each_combination(regions, 1, dma_buf_set) {
>  				region = igt_collection_get_value(regions, 0);
>  				size = gem_get_batch_size(fd, MEMORY_TYPE_FROM_REGION(region));
>  				size = max(size, BO_SIZE);
> @@ -582,6 +559,7 @@ igt_main
>  	igt_fixture {
>  		free(query_info);
>  		igt_collection_destroy(set);
> +		igt_collection_destroy(dma_buf_set);
>  		close(fd);
>  	}
>  }
> -- 
> 2.32.0
> 

Re: [igt-dev] [PATCH i-g-t 2/3] tests/prime_mmap: Iterate over dma-buf supported memory regions

[Gwan-gyeong Mun]

Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Tested-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>

If the https://patchwork.freedesktop.org/series/100737/ patch (currently 
under review) is applied to the i915, you can see that the 
igt@prime_mmap test works normally in dg1.

On 3/1/22 9:58 AM, Zbigniew Kempczyński wrote:
> To avoid code duplication (prime_mmap_coherency uses similar code)
> use helper function which returns dma-buf set of supported regions.
> 
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> ---
>   tests/prime_mmap.c | 34 ++++++----------------------------
>   1 file changed, 6 insertions(+), 28 deletions(-)
> 
> diff --git a/tests/prime_mmap.c b/tests/prime_mmap.c
> index e0cb9a25b..d53185ff1 100644
> --- a/tests/prime_mmap.c
> +++ b/tests/prime_mmap.c
> @@ -483,31 +483,6 @@ test_aperture_limit(uint32_t region, int size)
>   	gem_close(fd, handle2);
>   }
>   
> -static int
> -check_for_dma_buf_mmap(struct igt_collection *set)
> -{
> -	struct igt_collection *region;
> -	uint32_t reg;
> -	int dma_buf_fd;
> -	char *ptr;
> -	uint32_t handle;
> -	int ret = 1;
> -
> -	for_each_combination(region, 1, set) {
> -		reg = igt_collection_get_value(region, 0);
> -		handle = gem_create_in_memory_regions(fd, BO_SIZE, reg);
> -
> -		dma_buf_fd = prime_handle_to_fd(fd, handle);
> -		ptr = mmap(NULL, BO_SIZE, PROT_READ, MAP_SHARED, dma_buf_fd, 0);
> -		if (ptr != MAP_FAILED)
> -			ret = 0;
> -		munmap(ptr, BO_SIZE);
> -		gem_close(fd, handle);
> -		close(dma_buf_fd);
> -	}
> -	return ret;
> -}
> -
>   #define SKIP_LMEM (1 << 0)
>   #define SKIP_USERPTR (1 << 1)
>   
> @@ -527,7 +502,7 @@ static bool check_skip(uint32_t skip, uint32_t region)
>   
>   igt_main
>   {
> -	struct igt_collection *set, *regions;
> +	struct igt_collection *set, *regions, *dma_buf_set;
>   	struct drm_i915_query_memory_regions *query_info;
>   	struct {
>   		const char *name;
> @@ -560,13 +535,15 @@ igt_main
>   
>   		set = get_memory_region_set(query_info, I915_SYSTEM_MEMORY,
>   					    I915_DEVICE_MEMORY);
> -		igt_assert(check_for_dma_buf_mmap(set) == 0);
> +
> +		dma_buf_set = get_dma_buf_mmap_supported_set(fd, set);
> +		igt_require_f(dma_buf_set, "No dma-buf region supported\n");
>   		errno = 0;
>   	}
>   
>   	for (i = 0; i < ARRAY_SIZE(tests); i++)
>   		igt_subtest_with_dynamic(tests[i].name) {
> -			for_each_combination(regions, 1, set) {
> +			for_each_combination(regions, 1, dma_buf_set) {
>   				region = igt_collection_get_value(regions, 0);
>   				size = gem_get_batch_size(fd, MEMORY_TYPE_FROM_REGION(region));
>   				size = max(size, BO_SIZE);
> @@ -582,6 +559,7 @@ igt_main
>   	igt_fixture {
>   		free(query_info);
>   		igt_collection_destroy(set);
> +		igt_collection_destroy(dma_buf_set);
>   		close(fd);
>   	}
>   }
> 

Re: [igt-dev] [PATCH i-g-t 2/3] tests/prime_mmap: Iterate over dma-buf supported memory regions

[Gwan-gyeong Mun]

This is the result of igt@prime_mmap tests
  - mmap fix for lmem kernel patch was applied: 
https://patchwork.freedesktop.org/series/100737/

  - Tested HW: DG1,

IGT-Version: 1.26-g9458a2f1 (x86_64) (Linux: 5.17.0-rc5-drm-tip-test+ 
x86_64)
Starting subtest: test_correct
Starting dynamic subtest: test_correct-smem
Dynamic subtest test_correct-smem: SUCCESS (0.036s)
Starting dynamic subtest: test_correct-lmem0
Dynamic subtest test_correct-lmem0: SUCCESS (0.146s)
Subtest test_correct: SUCCESS (0.182s)
Starting subtest: test_map_unmap
Starting dynamic subtest: test_map_unmap-smem
Dynamic subtest test_map_unmap-smem: SUCCESS (0.036s)
Starting dynamic subtest: test_map_unmap-lmem0
Dynamic subtest test_map_unmap-lmem0: SUCCESS (0.142s)
Subtest test_map_unmap: SUCCESS (0.178s)
Starting subtest: test_reprime
Starting dynamic subtest: test_reprime-smem
Dynamic subtest test_reprime-smem: SUCCESS (0.036s)
Starting dynamic subtest: test_reprime-lmem0
Dynamic subtest test_reprime-lmem0: SUCCESS (0.143s)
Subtest test_reprime: SUCCESS (0.179s)
Starting subtest: test_forked
Starting dynamic subtest: test_forked-smem
Dynamic subtest test_forked-smem: SUCCESS (0.048s)
Starting dynamic subtest: test_forked-lmem0
Dynamic subtest test_forked-lmem0: SUCCESS (0.154s)
Subtest test_forked: SUCCESS (0.202s)
Starting subtest: test_correct_cpu_write
Starting dynamic subtest: test_correct_cpu_write-smem
Dynamic subtest test_correct_cpu_write-smem: SUCCESS (0.000s)
Starting dynamic subtest: test_correct_cpu_write-lmem0
Dynamic subtest test_correct_cpu_write-lmem0: SUCCESS (0.000s)
Subtest test_correct_cpu_write: SUCCESS (0.001s)
Starting subtest: test_forked_cpu_write
Starting dynamic subtest: test_forked_cpu_write-smem
Dynamic subtest test_forked_cpu_write-smem: SUCCESS (0.012s)
Starting dynamic subtest: test_forked_cpu_write-lmem0
Dynamic subtest test_forked_cpu_write-lmem0: SUCCESS (0.012s)
Subtest test_forked_cpu_write: SUCCESS (0.024s)
Starting subtest: test_refcounting
Starting dynamic subtest: test_refcounting-smem
Dynamic subtest test_refcounting-smem: SUCCESS (0.037s)
Starting dynamic subtest: test_refcounting-lmem0
Dynamic subtest test_refcounting-lmem0: SUCCESS (0.145s)
Subtest test_refcounting: SUCCESS (0.181s)
Starting subtest: test_dup
Starting dynamic subtest: test_dup-smem
Dynamic subtest test_dup-smem: SUCCESS (0.036s)
Starting dynamic subtest: test_dup-lmem0
Dynamic subtest test_dup-lmem0: SUCCESS (0.142s)
Subtest test_dup: SUCCESS (0.179s)
Starting subtest: test_userptr
Starting dynamic subtest: test_userptr-smem
Dynamic subtest test_userptr-smem: SUCCESS (0.000s)
Subtest test_userptr: SUCCESS (0.000s)
Starting subtest: test_errors
Starting dynamic subtest: test_errors-smem
Dynamic subtest test_errors-smem: SUCCESS (0.110s)
Starting dynamic subtest: test_errors-lmem0
Dynamic subtest test_errors-lmem0: SUCCESS (0.437s)
Subtest test_errors: SUCCESS (0.547s)
Starting subtest: test_invalid_sync_flags
Starting dynamic subtest: test_invalid_sync_flags-smem
Dynamic subtest test_invalid_sync_flags-smem: SUCCESS (0.000s)
Starting dynamic subtest: test_invalid_sync_flags-lmem0
Dynamic subtest test_invalid_sync_flags-lmem0: SUCCESS (0.000s)
Subtest test_invalid_sync_flags: SUCCESS (0.000s)
Starting subtest: test_aperture_limit
Starting dynamic subtest: test_aperture_limit-smem
Dynamic subtest test_aperture_limit-smem: SUCCESS (7.086s)
Subtest test_aperture_limit: SUCCESS (7.086s)


On 3/2/22 1:49 PM, Gwan-gyeong Mun wrote:
> Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Tested-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> 
> If the https://patchwork.freedesktop.org/series/100737/ patch (currently 
> under review) is applied to the i915, you can see that the 
> igt@prime_mmap test works normally in dg1.
> 
> On 3/1/22 9:58 AM, Zbigniew Kempczyński wrote:
>> To avoid code duplication (prime_mmap_coherency uses similar code)
>> use helper function which returns dma-buf set of supported regions.
>>
>> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
>> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
>> ---
>>   tests/prime_mmap.c | 34 ++++++----------------------------
>>   1 file changed, 6 insertions(+), 28 deletions(-)
>>
>> diff --git a/tests/prime_mmap.c b/tests/prime_mmap.c
>> index e0cb9a25b..d53185ff1 100644
>> --- a/tests/prime_mmap.c
>> +++ b/tests/prime_mmap.c
>> @@ -483,31 +483,6 @@ test_aperture_limit(uint32_t region, int size)
>>       gem_close(fd, handle2);
>>   }
>> -static int
>> -check_for_dma_buf_mmap(struct igt_collection *set)
>> -{
>> -    struct igt_collection *region;
>> -    uint32_t reg;
>> -    int dma_buf_fd;
>> -    char *ptr;
>> -    uint32_t handle;
>> -    int ret = 1;
>> -
>> -    for_each_combination(region, 1, set) {
>> -        reg = igt_collection_get_value(region, 0);
>> -        handle = gem_create_in_memory_regions(fd, BO_SIZE, reg);
>> -
>> -        dma_buf_fd = prime_handle_to_fd(fd, handle);
>> -        ptr = mmap(NULL, BO_SIZE, PROT_READ, MAP_SHARED, dma_buf_fd, 0);
>> -        if (ptr != MAP_FAILED)
>> -            ret = 0;
>> -        munmap(ptr, BO_SIZE);
>> -        gem_close(fd, handle);
>> -        close(dma_buf_fd);
>> -    }
>> -    return ret;
>> -}
>> -
>>   #define SKIP_LMEM (1 << 0)
>>   #define SKIP_USERPTR (1 << 1)
>> @@ -527,7 +502,7 @@ static bool check_skip(uint32_t skip, uint32_t 
>> region)
>>   igt_main
>>   {
>> -    struct igt_collection *set, *regions;
>> +    struct igt_collection *set, *regions, *dma_buf_set;
>>       struct drm_i915_query_memory_regions *query_info;
>>       struct {
>>           const char *name;
>> @@ -560,13 +535,15 @@ igt_main
>>           set = get_memory_region_set(query_info, I915_SYSTEM_MEMORY,
>>                           I915_DEVICE_MEMORY);
>> -        igt_assert(check_for_dma_buf_mmap(set) == 0);
>> +
>> +        dma_buf_set = get_dma_buf_mmap_supported_set(fd, set);
>> +        igt_require_f(dma_buf_set, "No dma-buf region supported\n");
>>           errno = 0;
>>       }
>>       for (i = 0; i < ARRAY_SIZE(tests); i++)
>>           igt_subtest_with_dynamic(tests[i].name) {
>> -            for_each_combination(regions, 1, set) {
>> +            for_each_combination(regions, 1, dma_buf_set) {
>>                   region = igt_collection_get_value(regions, 0);
>>                   size = gem_get_batch_size(fd, 
>> MEMORY_TYPE_FROM_REGION(region));
>>                   size = max(size, BO_SIZE);
>> @@ -582,6 +559,7 @@ igt_main
>>       igt_fixture {
>>           free(query_info);
>>           igt_collection_destroy(set);
>> +        igt_collection_destroy(dma_buf_set);
>>           close(fd);
>>       }
>>   }
>>

[igt-dev] [PATCH i-g-t 3/3] tests/prime_mmap_coherency.c: Use intel_bb and intel_buf to remove libdrm dependency

[Zbigniew Kempczyński]

From: Ch Sai Gowtham <sai.gowtham.ch@intel.com>

Using intel_bb and intel_buf to remove libdrm dependency.

v2: addressing review comments (Kamil)

Signed-off-by: Ch Sai Gowtham <sai.gowtham.ch@intel.com>
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
---
 tests/prime_mmap_coherency.c | 128 +++++++++++++++++++++--------------
 1 file changed, 78 insertions(+), 50 deletions(-)

diff --git a/tests/prime_mmap_coherency.c b/tests/prime_mmap_coherency.c
index 2a0749577..0238d9117 100644
--- a/tests/prime_mmap_coherency.c
+++ b/tests/prime_mmap_coherency.c
@@ -36,8 +36,8 @@ IGT_TEST_DESCRIPTION("Test dma-buf mmap on !llc platforms mostly and provoke"
 		" coherency bugs so we know for sure where we need the sync ioctls.");
 
 int fd;
-static drm_intel_bufmgr *bufmgr;
-struct intel_batchbuffer *batch;
+static struct buf_ops *bops;
+static struct intel_bb *batch;
 static int width = 1024, height = 1024;
 
 /*
@@ -49,29 +49,34 @@ static int width = 1024, height = 1024;
  */
 static int test_read_flush(void)
 {
-	drm_intel_bo *bo_1;
-	drm_intel_bo *bo_2;
+	struct intel_buf *buffer_1;
+	struct intel_buf *buffer_2;
 	uint32_t *ptr_cpu;
 	uint32_t *ptr_gtt;
 	int dma_buf_fd, i;
 	int stale = 0;
 
-	bo_1 = drm_intel_bo_alloc(bufmgr, "BO 1", width * height * 4, 4096);
+
+	buffer_1 = intel_buf_create(bops, width, height, 32, 4096,
+				    I915_TILING_NONE, I915_COMPRESSION_NONE);
 
 	/* STEP #1: put the BO 1 in GTT domain. We use the blitter to copy and fill
 	 * zeros to BO 1, so commands will be submitted and likely to place BO 1 in
 	 * the GTT domain. */
-	bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096);
-	intel_copy_bo(batch, bo_1, bo_2, width * height);
-	drm_intel_bo_unreference(bo_2);
 
+	buffer_2 = intel_buf_create(bops, width, height, 32, 4096,
+				    I915_TILING_NONE, I915_COMPRESSION_NONE);
+	intel_bb_copy_intel_buf(batch, buffer_2, buffer_1, width * height * 4);
+	intel_buf_destroy(buffer_2);
 	/* STEP #2: read BO 1 using the dma-buf CPU mmap. This dirties the CPU caches. */
-	dma_buf_fd = prime_handle_to_fd_for_mmap(fd, bo_1->handle);
+	dma_buf_fd = prime_handle_to_fd_for_mmap(fd, buffer_1->handle);
 
 	/* STEP #3: write 0x11 into BO 1. */
-	bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096);
-	ptr_gtt = gem_mmap__device_coherent(fd, bo_2->handle, 0, width * height, PROT_READ | PROT_WRITE);
-	gem_set_domain(fd, bo_2->handle,
+	buffer_2 = intel_buf_create(bops, width, height, 32, 4096,
+				    I915_TILING_NONE, I915_COMPRESSION_NONE);
+	ptr_gtt = gem_mmap__device_coherent(fd, buffer_2->handle, 0,
+					    width * height, PROT_READ | PROT_WRITE);
+	gem_set_domain(fd, buffer_2->handle,
 		       I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
 	memset(ptr_gtt, 0xc5, width * height);
 	munmap(ptr_gtt, width * height);
@@ -85,8 +90,8 @@ static int test_read_flush(void)
 		igt_assert_eq(ptr_cpu[i], 0);
 	prime_sync_end(dma_buf_fd, false);
 
-	intel_copy_bo(batch, bo_1, bo_2, width * height);
-	drm_intel_bo_unreference(bo_2);
+	intel_bb_copy_intel_buf(batch, buffer_2, buffer_1, width * height);
+	intel_buf_destroy(buffer_2);
 
 	/* STEP #4: read again using the CPU mmap. Doing #1 before #3 makes sure we
 	 * don't do a full CPU cache flush in step #3 again. That makes sure all the
@@ -99,7 +104,7 @@ static int test_read_flush(void)
 			stale++;
 	prime_sync_end(dma_buf_fd, false);
 
-	drm_intel_bo_unreference(bo_1);
+	intel_buf_destroy(buffer_1);
 	munmap(ptr_cpu, width * height);
 
 	close(dma_buf_fd);
@@ -116,24 +121,26 @@ static int test_read_flush(void)
  */
 static int test_write_flush(void)
 {
-	drm_intel_bo *bo_1;
-	drm_intel_bo *bo_2;
+	struct intel_buf *buffer_1;
+	struct intel_buf *buffer_2;
 	uint32_t *ptr_cpu;
 	uint32_t *ptr2_cpu;
 	int dma_buf_fd, dma_buf2_fd, i;
 	int stale = 0;
 
-	bo_1 = drm_intel_bo_alloc(bufmgr, "BO 1", width * height * 4, 4096);
+	buffer_1 = intel_buf_create(bops, width, height, 32, 4096,
+				    I915_TILING_NONE, I915_COMPRESSION_NONE);
 
 	/* STEP #1: Put the BO 1 in GTT domain. We use the blitter to copy and fill
 	 * zeros to BO 1, so commands will be submitted and likely to place BO 1 in
 	 * the GTT domain. */
-	bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096);
-	intel_copy_bo(batch, bo_1, bo_2, width * height);
-	drm_intel_bo_unreference(bo_2);
+	buffer_2 = intel_buf_create(bops, width, height, 32, 4096,
+				    I915_TILING_NONE, I915_COMPRESSION_NONE);
+	intel_bb_copy_intel_buf(batch, buffer_2, buffer_1, width * height * 4);
+	intel_buf_destroy(buffer_2);
 
 	/* STEP #2: Write '1's into BO 1 using the dma-buf CPU mmap. */
-	dma_buf_fd = prime_handle_to_fd_for_mmap(fd, bo_1->handle);
+	dma_buf_fd = prime_handle_to_fd_for_mmap(fd, buffer_1->handle);
 	igt_skip_on(errno == EINVAL);
 
 	ptr_cpu = mmap(NULL, width * height, PROT_READ | PROT_WRITE,
@@ -147,13 +154,14 @@ static int test_write_flush(void)
 	prime_sync_end(dma_buf_fd, true);
 
 	/* STEP #3: Copy BO 1 into BO 2, using blitter. */
-	bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096);
-	intel_copy_bo(batch, bo_2, bo_1, width * height);
+	buffer_2 = intel_buf_create(bops, width, height, 32, 4096,
+				    I915_TILING_NONE, I915_COMPRESSION_NONE);
+	intel_bb_copy_intel_buf(batch, buffer_1, buffer_2, width * height * 4);
 
 	/* STEP #4: compare BO 2 against written BO 1. In !llc hardware, there
 	 * should be some cache lines that didn't get flushed out and are still 0,
 	 * requiring cache flush before the write in step 2. */
-	dma_buf2_fd = prime_handle_to_fd_for_mmap(fd, bo_2->handle);
+	dma_buf2_fd = prime_handle_to_fd_for_mmap(fd, buffer_2->handle);
 	igt_skip_on(errno == EINVAL);
 
 	ptr2_cpu = mmap(NULL, width * height, PROT_READ | PROT_WRITE,
@@ -168,8 +176,8 @@ static int test_write_flush(void)
 
 	prime_sync_end(dma_buf2_fd, false);
 
-	drm_intel_bo_unreference(bo_1);
-	drm_intel_bo_unreference(bo_2);
+	intel_buf_destroy(buffer_1);
+	intel_buf_destroy(buffer_2);
 	munmap(ptr_cpu, width * height);
 
 	close(dma_buf2_fd);
@@ -180,33 +188,32 @@ static int test_write_flush(void)
 
 static void blit_and_cmp(void)
 {
-	drm_intel_bo *bo_1;
-	drm_intel_bo *bo_2;
+	struct intel_buf *buffer_1;
+	struct intel_buf *buffer_2;
 	uint32_t *ptr_cpu;
 	uint32_t *ptr2_cpu;
 	int dma_buf_fd, dma_buf2_fd, i;
 	int local_fd;
-	drm_intel_bufmgr *local_bufmgr;
-	struct intel_batchbuffer *local_batch;
-
+	struct buf_ops *local_bops;
+	struct intel_bb *local_batch;
 	/* recreate process local variables */
 	local_fd = drm_open_driver(DRIVER_INTEL);
-	local_bufmgr = drm_intel_bufmgr_gem_init(local_fd, 4096);
-	igt_assert(local_bufmgr);
+	local_bops = buf_ops_create(local_fd);
 
-	local_batch = intel_batchbuffer_alloc(local_bufmgr, intel_get_drm_devid(local_fd));
-	igt_assert(local_batch);
+	local_batch = intel_bb_create(local_fd, 4096);
 
-	bo_1 = drm_intel_bo_alloc(local_bufmgr, "BO 1", width * height * 4, 4096);
-	dma_buf_fd = prime_handle_to_fd_for_mmap(local_fd, bo_1->handle);
+	buffer_1 = intel_buf_create(local_bops, width, height, 32, 4096,
+				    I915_TILING_NONE, I915_COMPRESSION_NONE);
+	dma_buf_fd = prime_handle_to_fd_for_mmap(local_fd, buffer_1->handle);
 	igt_skip_on(errno == EINVAL);
 
 	ptr_cpu = mmap(NULL, width * height, PROT_READ | PROT_WRITE,
 		       MAP_SHARED, dma_buf_fd, 0);
 	igt_assert(ptr_cpu != MAP_FAILED);
 
-	bo_2 = drm_intel_bo_alloc(local_bufmgr, "BO 2", width * height * 4, 4096);
-	dma_buf2_fd = prime_handle_to_fd_for_mmap(local_fd, bo_2->handle);
+	buffer_2 = intel_buf_create(local_bops, width, height, 32, 4096,
+				    I915_TILING_NONE, I915_COMPRESSION_NONE);
+	dma_buf2_fd = prime_handle_to_fd_for_mmap(local_fd, buffer_2->handle);
 
 	ptr2_cpu = mmap(NULL, width * height, PROT_READ | PROT_WRITE,
 			MAP_SHARED, dma_buf2_fd, 0);
@@ -222,7 +229,7 @@ static void blit_and_cmp(void)
 	prime_sync_end(dma_buf2_fd, true);
 
 	/* Copy BO 1 into BO 2, using blitter. */
-	intel_copy_bo(local_batch, bo_2, bo_1, width * height);
+	intel_bb_copy_intel_buf(local_batch, buffer_1, buffer_2, width * height * 4);
 	usleep(0); /* let someone else claim the mutex */
 
 	/* Compare BOs. If prime_sync_* were executed properly, the caches
@@ -232,16 +239,16 @@ static void blit_and_cmp(void)
 		igt_fail_on_f(ptr2_cpu[i] != 0x11111111, "Found 0x%08x at offset 0x%08x\n", ptr2_cpu[i], i);
 	prime_sync_end(dma_buf2_fd, false);
 
-	drm_intel_bo_unreference(bo_1);
-	drm_intel_bo_unreference(bo_2);
+	intel_buf_destroy(buffer_1);
+	intel_buf_destroy(buffer_2);
 	munmap(ptr_cpu, width * height);
 	munmap(ptr2_cpu, width * height);
 
 	close(dma_buf_fd);
 	close(dma_buf2_fd);
 
-	intel_batchbuffer_free(local_batch);
-	drm_intel_bufmgr_destroy(local_bufmgr);
+	intel_bb_destroy(local_batch);
+	buf_ops_destroy(local_bops);
 	close(local_fd);
 }
 
@@ -274,49 +281,70 @@ static void test_ioctl_errors(void)
 			break;
 		}
 
-		igt_fork(child, num_children)
+		igt_fork(child, num_children) {
+			intel_allocator_init();
 			igt_while_interruptible(true) blit_and_cmp();
+		}
 		igt_waitchildren();
 	}
 }
 
 igt_main
 {
+	struct igt_collection *set, *dma_buf_set;
+	struct drm_i915_query_memory_regions *query_info;
+
 	igt_fixture {
 		fd = drm_open_driver(DRIVER_INTEL);
 		igt_require_gem(fd);
 
-		bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
-		batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
+		query_info = gem_get_query_memory_regions(fd);
+		igt_assert(query_info);
+
+		set = get_memory_region_set(query_info, I915_SYSTEM_MEMORY,
+					    I915_DEVICE_MEMORY);
+
+		dma_buf_set = get_dma_buf_mmap_supported_set(fd, set);
+		igt_require_f(dma_buf_set, "No dma-buf region supported\n");
+
+		igt_collection_destroy(set);
+		igt_collection_destroy(dma_buf_set);
+
+		bops = buf_ops_create(fd);
 	}
 
 	/* Cache coherency and the eviction are pretty much unpredictable, so
 	 * reproducing boils down to trial and error to hit different scenarios.
 	 * TODO: We may want to improve tests a bit by picking random subranges. */
 	igt_subtest("read") {
+		batch = intel_bb_create(fd, 4096);
 		igt_until_timeout(5) {
 			int stale = test_read_flush();
 			igt_fail_on_f(stale,
 				      "num of stale cache lines %d\n", stale);
 		}
+		intel_bb_destroy(batch);
 	}
 
 	igt_subtest("write") {
+		batch = intel_bb_create(fd, 4096);
 		igt_until_timeout(5) {
 			int stale = test_write_flush();
 			igt_fail_on_f(stale,
 				      "num of stale cache lines %d\n", stale);
 		}
+		intel_bb_destroy(batch);
 	}
 
 	igt_subtest("ioctl-errors") {
+		batch = intel_bb_create(fd, 4096);
 		igt_info("exercising concurrent blit to get ioctl errors\n");
 		test_ioctl_errors();
+		intel_bb_destroy(batch);
 	}
 
 	igt_fixture {
-		intel_batchbuffer_free(batch);
-		drm_intel_bufmgr_destroy(bufmgr);
+		buf_ops_destroy(bops);
 
 		close(fd);
 	}
-- 
2.32.0

[igt-dev] ✓ Fi.CI.BAT: success for Use supported dma-buf regions in prime_mmap* (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 6087 bytes --]

== Series Details ==

Series: Use supported dma-buf regions in prime_mmap* (rev2)
URL   : https://patchwork.freedesktop.org/series/100819/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11301 -> IGTPW_6720
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/index.html

Participating hosts (42 -> 41)
------------------------------

  Additional (1): fi-kbl-soraka 
  Missing    (2): fi-bsw-cyan fi-bdw-samus 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_6720:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_lmem_swapping@verify-random@lmem0:
    - {bat-dg2-9}:        [INCOMPLETE][1] ([i915#4936]) -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11301/bat-dg2-9/igt@gem_lmem_swapping@verify-random@lmem0.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/bat-dg2-9/igt@gem_lmem_swapping@verify-random@lmem0.html

  * igt@kms_addfb_basic@too-high:
    - {bat-dg2-9}:        [PASS][3] -> [DMESG-WARN][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11301/bat-dg2-9/igt@kms_addfb_basic@too-high.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/bat-dg2-9/igt@kms_addfb_basic@too-high.html

  
Known issues
------------

  Here are the changes found in IGTPW_6720 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_fence@basic-busy@bcs0:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][5] ([fdo#109271]) +8 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/fi-kbl-soraka/igt@gem_exec_fence@basic-busy@bcs0.html

  * igt@gem_huc_copy@huc-copy:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#2190])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@basic:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +3 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html

  * igt@i915_selftest@live@gt_pm:
    - fi-kbl-soraka:      NOTRUN -> [DMESG-FAIL][8] ([i915#1886] / [i915#2291])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/fi-kbl-soraka/igt@kms_chamelium@common-hpd-after-suspend.html

  * igt@kms_flip@basic-flip-vs-modeset@a-edp1:
    - bat-adlp-4:         [PASS][10] -> [DMESG-WARN][11] ([i915#3576])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11301/bat-adlp-4/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/bat-adlp-4/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#533])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/fi-kbl-soraka/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  
#### Possible fixes ####

  * igt@kms_busy@basic@modeset:
    - bat-adlp-4:         [DMESG-WARN][13] ([i915#3576]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11301/bat-adlp-4/igt@kms_busy@basic@modeset.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/bat-adlp-4/igt@kms_busy@basic@modeset.html

  * igt@kms_flip@basic-flip-vs-modeset@a-edp1:
    - {bat-adlp-6}:       [DMESG-WARN][15] ([i915#3576]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11301/bat-adlp-6/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/bat-adlp-6/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
    - fi-cfl-8109u:       [DMESG-WARN][17] ([i915#295]) -> [PASS][18] +12 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11301/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
  [i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
  [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4936]: https://gitlab.freedesktop.org/drm/intel/issues/4936
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#5127]: https://gitlab.freedesktop.org/drm/intel/issues/5127
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_6361 -> IGTPW_6720

  CI-20190529: 20190529
  CI_DRM_11301: 2993d5d1ab67bc47f6be438e163742bb8cd3004c @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_6720: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/index.html
  IGT_6361: 2372a4beb6a33c5f0799a4a8ccbb93794f52dbca @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/index.html

[-- Attachment #2: Type: text/html, Size: 7195 bytes --]

[igt-dev] ✗ Fi.CI.IGT: failure for Use supported dma-buf regions in prime_mmap* (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 30270 bytes --]

== Series Details ==

Series: Use supported dma-buf regions in prime_mmap* (rev2)
URL   : https://patchwork.freedesktop.org/series/100819/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11301_full -> IGTPW_6720_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_6720_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_6720_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/index.html

Participating hosts (13 -> 8)
------------------------------

  Missing    (5): pig-kbl-iris pig-glk-j5005 pig-skl-6260u shard-rkl shard-dg1 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_6720_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_exec_schedule@submit-golden-slice@rcs0:
    - shard-tglb:         [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11301/shard-tglb7/igt@gem_exec_schedule@submit-golden-slice@rcs0.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-tglb6/igt@gem_exec_schedule@submit-golden-slice@rcs0.html

  * {igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-25@pipe-d-edp-1-downscale-with-pixel-format} (NEW):
    - shard-tglb:         NOTRUN -> [SKIP][3]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-tglb5/igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-25@pipe-d-edp-1-downscale-with-pixel-format.html

  * {igt@kms_plane_scaling@downscale-with-rotation-factor-0-25@pipe-d-hdmi-a-1-downscale-with-rotation} (NEW):
    - {shard-tglu}:       NOTRUN -> [SKIP][4] +3 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-tglu-3/igt@kms_plane_scaling@downscale-with-rotation-factor-0-25@pipe-d-hdmi-a-1-downscale-with-rotation.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-25@pipe-a-edp-1-downscale-with-pixel-format}:
    - shard-iclb:         NOTRUN -> [SKIP][5] +2 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-iclb5/igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-25@pipe-a-edp-1-downscale-with-pixel-format.html

  * {igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-25@pipe-b-edp-1-downscale-with-pixel-format}:
    - shard-tglb:         NOTRUN -> [SKIP][6] +2 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-tglb5/igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-25@pipe-b-edp-1-downscale-with-pixel-format.html

  * {igt@kms_plane_scaling@upscale-with-rotation-20x20@pipe-c-hdmi-a-1-upscale-with-rotation}:
    - {shard-tglu}:       NOTRUN -> [SKIP][7] +7 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-tglu-3/igt@kms_plane_scaling@upscale-with-rotation-20x20@pipe-c-hdmi-a-1-upscale-with-rotation.html

  
New tests
---------

  New tests have been introduced between CI_DRM_11301_full and IGTPW_6720_full:

### New IGT tests (29) ###

  * igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-25@pipe-b-hdmi-a-1-downscale-with-pixel-format:
    - Statuses : 1 skip(s)
    - Exec time: [0.02] s

  * igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-25@pipe-d-edp-1-downscale-with-pixel-format:
    - Statuses : 1 skip(s)
    - Exec time: [0.02] s

  * igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-25@pipe-d-hdmi-a-1-downscale-with-pixel-format:
    - Statuses : 1 skip(s)
    - Exec time: [0.02] s

  * igt@kms_plane_scaling@downscale-with-rotation-factor-0-25@pipe-b-hdmi-a-1-downscale-with-rotation:
    - Statuses : 1 skip(s)
    - Exec time: [0.02] s

  * igt@kms_plane_scaling@downscale-with-rotation-factor-0-25@pipe-d-hdmi-a-1-downscale-with-rotation:
    - Statuses : 1 skip(s)
    - Exec time: [0.02] s

  * igt@kms_plane_scaling@invalid-num-scalers@pipe-d-edp-1-invalid-num-scalers:
    - Statuses : 1 pass(s)
    - Exec time: [0.02] s

  * igt@kms_plane_scaling@planes-downscale-factor-0-75@pipe-b-hdmi-a-1-planes-downscale:
    - Statuses : 1 pass(s)
    - Exec time: [0.14] s

  * igt@kms_plane_scaling@planes-downscale-factor-0-75@pipe-d-edp-1-planes-downscale:
    - Statuses : 1 pass(s)
    - Exec time: [1.28] s

  * igt@kms_plane_scaling@planes-downscale-factor-0-75@pipe-d-hdmi-a-1-planes-downscale:
    - Statuses : 1 pass(s)
    - Exec time: [0.14] s

  * igt@kms_plane_scaling@planes-scaling-unity-scaling@pipe-b-hdmi-a-1-planes-unity-scaling:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_plane_scaling@planes-scaling-unity-scaling@pipe-d-edp-1-planes-unity-scaling:
    - Statuses : 1 pass(s)
    - Exec time: [1.28] s

  * igt@kms_plane_scaling@planes-scaling-unity-scaling@pipe-d-hdmi-a-1-planes-unity-scaling:
    - Statuses : 1 pass(s)
    - Exec time: [0.11] s

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-b-hdmi-a-1-planes-upscale-downscale:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-d-edp-1-planes-upscale-downscale:
    - Statuses : 1 pass(s)
    - Exec time: [1.27] s

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-d-hdmi-a-1-planes-upscale-downscale:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_plane_scaling@planes-upscale-20x20@pipe-b-hdmi-a-1-planes-upscale:
    - Statuses : 1 pass(s)
    - Exec time: [0.10] s

  * igt@kms_plane_scaling@planes-upscale-20x20@pipe-d-edp-1-planes-upscale:
    - Statuses : 1 pass(s)
    - Exec time: [1.22] s

  * igt@kms_plane_scaling@planes-upscale-20x20@pipe-d-hdmi-a-1-planes-upscale:
    - Statuses : 1 pass(s)
    - Exec time: [0.10] s

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-a-edp-1-planes-upscale-downscale:
    - Statuses : 2 pass(s)
    - Exec time: [0.13, 0.18] s

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-a-hdmi-a-1-planes-upscale-downscale:
    - Statuses : 2 pass(s)
    - Exec time: [0.10, 0.36] s

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-a-vga-1-planes-upscale-downscale:
    - Statuses : 1 skip(s)
    - Exec time: [0.05] s

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-b-edp-1-planes-upscale-downscale:
    - Statuses : 2 pass(s)
    - Exec time: [1.23, 1.33] s

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-b-hdmi-a-1-planes-upscale-downscale:
    - Statuses : 1 pass(s)
    - Exec time: [0.11] s

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-b-hdmi-a-2-planes-upscale-downscale:
    - Statuses : 1 pass(s)
    - Exec time: [0.34] s

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-b-vga-1-planes-upscale-downscale:
    - Statuses : 1 skip(s)
    - Exec time: [0.03] s

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-c-edp-1-planes-upscale-downscale:
    - Statuses : 2 pass(s)
    - Exec time: [1.28, 1.34] s

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-c-hdmi-a-1-planes-upscale-downscale:
    - Statuses : 1 pass(s) 1 skip(s)
    - Exec time: [0.12, 0.13] s

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-d-edp-1-planes-upscale-downscale:
    - Statuses : 1 pass(s)
    - Exec time: [1.21] s

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-d-hdmi-a-1-planes-upscale-downscale:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  

Known issues
------------

  Here are the changes found in IGTPW_6720_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@feature_discovery@display-2x:
    - shard-tglb:         NOTRUN -> [SKIP][8] ([i915#1839])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-tglb3/igt@feature_discovery@display-2x.html
    - shard-iclb:         NOTRUN -> [SKIP][9] ([i915#1839])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-iclb4/igt@feature_discovery@display-2x.html

  * igt@gem_ctx_param@set-priority-not-supported:
    - shard-tglb:         NOTRUN -> [SKIP][10] ([fdo#109314])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-tglb2/igt@gem_ctx_param@set-priority-not-supported.html
    - shard-iclb:         NOTRUN -> [SKIP][11] ([fdo#109314])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-iclb4/igt@gem_ctx_param@set-priority-not-supported.html

  * igt@gem_ctx_persistence@legacy-engines-queued:
    - shard-snb:          NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#1099]) +2 similar issues
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-snb4/igt@gem_ctx_persistence@legacy-engines-queued.html

  * igt@gem_exec_balancer@parallel-keep-submit-fence:
    - shard-kbl:          NOTRUN -> [DMESG-WARN][13] ([i915#5076])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-kbl4/igt@gem_exec_balancer@parallel-keep-submit-fence.html

  * igt@gem_exec_fair@basic-none@vcs0:
    - shard-kbl:          NOTRUN -> [FAIL][14] ([i915#2842]) +2 similar issues
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-kbl1/igt@gem_exec_fair@basic-none@vcs0.html
    - shard-tglb:         NOTRUN -> [FAIL][15] ([i915#2842]) +4 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-tglb1/igt@gem_exec_fair@basic-none@vcs0.html

  * igt@gem_exec_fair@basic-none@vecs0:
    - shard-iclb:         NOTRUN -> [FAIL][16] ([i915#2842]) +3 similar issues
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-iclb8/igt@gem_exec_fair@basic-none@vecs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-tglb:         [PASS][17] -> [FAIL][18] ([i915#2842])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11301/shard-tglb8/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs0:
    - shard-kbl:          [PASS][19] -> [SKIP][20] ([fdo#109271])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11301/shard-kbl3/igt@gem_exec_fair@basic-pace@vcs0.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs0.html

  * igt@gem_exec_params@secure-non-root:
    - shard-tglb:         NOTRUN -> [SKIP][21] ([fdo#112283])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-tglb1/igt@gem_exec_params@secure-non-root.html
    - shard-iclb:         NOTRUN -> [SKIP][22] ([fdo#112283])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-iclb8/igt@gem_exec_params@secure-non-root.html

  * igt@gem_exec_schedule@submit-early-slice@vcs1:
    - shard-tglb:         [PASS][23] -> [INCOMPLETE][24] ([i915#3797])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11301/shard-tglb2/igt@gem_exec_schedule@submit-early-slice@vcs1.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-tglb2/igt@gem_exec_schedule@submit-early-slice@vcs1.html

  * igt@gem_exec_suspend@basic-s3@smem:
    - shard-apl:          [PASS][25] -> [DMESG-WARN][26] ([i915#180]) +1 similar issue
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11301/shard-apl2/igt@gem_exec_suspend@basic-s3@smem.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-apl8/igt@gem_exec_suspend@basic-s3@smem.html

  * igt@gem_lmem_swapping@heavy-random:
    - shard-iclb:         NOTRUN -> [SKIP][27] ([i915#4613]) +1 similar issue
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-iclb4/igt@gem_lmem_swapping@heavy-random.html
    - shard-apl:          NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#4613]) +1 similar issue
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-apl1/igt@gem_lmem_swapping@heavy-random.html
    - shard-glk:          NOTRUN -> [SKIP][29] ([fdo#109271] / [i915#4613])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-glk2/igt@gem_lmem_swapping@heavy-random.html

  * igt@gem_lmem_swapping@heavy-verify-random:
    - shard-kbl:          NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#4613]) +2 similar issues
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-kbl4/igt@gem_lmem_swapping@heavy-verify-random.html
    - shard-tglb:         NOTRUN -> [SKIP][31] ([i915#4613]) +2 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-tglb2/igt@gem_lmem_swapping@heavy-verify-random.html

  * igt@gem_pxp@create-protected-buffer:
    - shard-snb:          NOTRUN -> [SKIP][32] ([fdo#109271]) +152 similar issues
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-snb2/igt@gem_pxp@create-protected-buffer.html

  * igt@gem_pxp@create-regular-buffer:
    - shard-tglb:         NOTRUN -> [SKIP][33] ([i915#4270]) +5 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-tglb1/igt@gem_pxp@create-regular-buffer.html

  * igt@gem_pxp@reject-modify-context-protection-off-3:
    - shard-iclb:         NOTRUN -> [SKIP][34] ([i915#4270]) +3 similar issues
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-iclb7/igt@gem_pxp@reject-modify-context-protection-off-3.html

  * igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled:
    - shard-iclb:         NOTRUN -> [SKIP][35] ([i915#768])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-iclb8/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled.html

  * igt@gem_userptr_blits@create-destroy-unsync:
    - shard-tglb:         NOTRUN -> [SKIP][36] ([i915#3297])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-tglb8/igt@gem_userptr_blits@create-destroy-unsync.html

  * igt@gen3_render_tiledy_blits:
    - shard-tglb:         NOTRUN -> [SKIP][37] ([fdo#109289]) +3 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-tglb7/igt@gen3_render_tiledy_blits.html

  * igt@gen7_exec_parse@chained-batch:
    - shard-iclb:         NOTRUN -> [SKIP][38] ([fdo#109289]) +1 similar issue
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-iclb8/igt@gen7_exec_parse@chained-batch.html

  * igt@gen9_exec_parse@batch-without-end:
    - shard-iclb:         NOTRUN -> [SKIP][39] ([i915#2856]) +1 similar issue
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-iclb4/igt@gen9_exec_parse@batch-without-end.html

  * igt@gen9_exec_parse@shadow-peek:
    - shard-tglb:         NOTRUN -> [SKIP][40] ([i915#2527] / [i915#2856]) +3 similar issues
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-tglb8/igt@gen9_exec_parse@shadow-peek.html

  * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
    - shard-kbl:          NOTRUN -> [SKIP][41] ([fdo#109271] / [i915#1937])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-kbl3/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html
    - shard-apl:          NOTRUN -> [SKIP][42] ([fdo#109271] / [i915#1937])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-apl7/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html

  * igt@i915_pm_rc6_residency@rc6-idle:
    - shard-tglb:         NOTRUN -> [WARN][43] ([i915#2681] / [i915#2684])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-tglb8/igt@i915_pm_rc6_residency@rc6-idle.html

  * igt@i915_pm_rpm@gem-execbuf-stress-pc8:
    - shard-iclb:         NOTRUN -> [SKIP][44] ([fdo#109293] / [fdo#109506])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-iclb4/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html
    - shard-tglb:         NOTRUN -> [SKIP][45] ([fdo#109506] / [i915#2411])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-tglb1/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html

  * igt@i915_pm_sseu@full-enable:
    - shard-tglb:         NOTRUN -> [SKIP][46] ([i915#4387])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-tglb7/igt@i915_pm_sseu@full-enable.html

  * igt@i915_selftest@live@hangcheck:
    - shard-snb:          [PASS][47] -> [INCOMPLETE][48] ([i915#3921])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11301/shard-snb6/igt@i915_selftest@live@hangcheck.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-snb5/igt@i915_selftest@live@hangcheck.html

  * igt@kms_atomic_transition@plane-all-modeset-transition:
    - shard-iclb:         NOTRUN -> [SKIP][49] ([i915#1769])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-iclb1/igt@kms_atomic_transition@plane-all-modeset-transition.html
    - shard-tglb:         NOTRUN -> [SKIP][50] ([i915#1769])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-tglb7/igt@kms_atomic_transition@plane-all-modeset-transition.html

  * igt@kms_big_fb@linear-8bpp-rotate-270:
    - shard-tglb:         NOTRUN -> [SKIP][51] ([fdo#111614]) +3 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-tglb8/igt@kms_big_fb@linear-8bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - shard-apl:          NOTRUN -> [SKIP][52] ([fdo#109271] / [i915#3777]) +2 similar issues
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-apl1/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - shard-kbl:          NOTRUN -> [SKIP][53] ([fdo#109271] / [i915#3777]) +6 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-kbl7/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_fb@yf-tiled-64bpp-rotate-270:
    - shard-tglb:         NOTRUN -> [SKIP][54] ([fdo#111615]) +7 similar issues
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-tglb1/igt@kms_big_fb@yf-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
    - shard-apl:          NOTRUN -> [SKIP][55] ([fdo#109271]) +226 similar issues
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-apl7/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html
    - shard-iclb:         NOTRUN -> [SKIP][56] ([fdo#110723]) +3 similar issues
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-iclb5/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html

  * igt@kms_big_joiner@basic:
    - shard-tglb:         NOTRUN -> [SKIP][57] ([i915#2705])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-tglb6/igt@kms_big_joiner@basic.html
    - shard-iclb:         NOTRUN -> [SKIP][58] ([i915#2705])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-iclb5/igt@kms_big_joiner@basic.html

  * igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
    - shard-glk:          NOTRUN -> [SKIP][59] ([fdo#109271] / [i915#3886]) +7 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-glk3/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
    - shard-apl:          NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#3886]) +13 similar issues
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-apl4/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][61] ([i915#3689]) +6 similar issues
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-tglb1/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_ccs.html

  * igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][62] ([i915#3689] / [i915#3886]) +7 similar issues
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-tglb6/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs:
    - shard-kbl:          NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#3886]) +17 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-kbl6/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_mc_ccs:
    - shard-iclb:         NOTRUN -> [SKIP][64] ([fdo#109278] / [i915#3886]) +6 similar issues
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-iclb8/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-d-missing-ccs-buffer-yf_tiled_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][65] ([fdo#111615] / [i915#3689]) +6 similar issues
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-tglb3/igt@kms_ccs@pipe-d-missing-ccs-buffer-yf_tiled_ccs.html

  * igt@kms_cdclk@plane-scaling:
    - shard-tglb:         NOTRUN -> [SKIP][66] ([i915#3742])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-tglb7/igt@kms_cdclk@plane-scaling.html

  * igt@kms_chamelium@dp-mode-timings:
    - shard-apl:          NOTRUN -> [SKIP][67] ([fdo#109271] / [fdo#111827]) +25 similar issues
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-apl1/igt@kms_chamelium@dp-mode-timings.html

  * igt@kms_chamelium@hdmi-hpd:
    - shard-glk:          NOTRUN -> [SKIP][68] ([fdo#109271] / [fdo#111827]) +11 similar issues
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-glk1/igt@kms_chamelium@hdmi-hpd.html

  * igt@kms_chamelium@hdmi-hpd-after-suspend:
    - shard-iclb:         NOTRUN -> [SKIP][69] ([fdo#109284] / [fdo#111827]) +12 similar issues
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-iclb1/igt@kms_chamelium@hdmi-hpd-after-suspend.html

  * igt@kms_chamelium@vga-hpd-for-each-pipe:
    - shard-kbl:          NOTRUN -> [SKIP][70] ([fdo#109271] / [fdo#111827]) +26 similar issues
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-kbl1/igt@kms_chamelium@vga-hpd-for-each-pipe.html

  * igt@kms_color@pipe-d-ctm-negative:
    - shard-iclb:         NOTRUN -> [SKIP][71] ([fdo#109278] / [i915#1149])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-iclb7/igt@kms_color@pipe-d-ctm-negative.html

  * igt@kms_color_chamelium@pipe-b-ctm-limited-range:
    - shard-tglb:         NOTRUN -> [SKIP][72] ([fdo#109284] / [fdo#111827]) +20 similar issues
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-tglb1/igt@kms_color_chamelium@pipe-b-ctm-limited-range.html

  * igt@kms_color_chamelium@pipe-c-ctm-green-to-red:
    - shard-snb:          NOTRUN -> [SKIP][73] ([fdo#109271] / [fdo#111827]) +11 similar issues
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-snb7/igt@kms_color_chamelium@pipe-c-ctm-green-to-red.html

  * igt@kms_color_chamelium@pipe-d-ctm-limited-range:
    - shard-iclb:         NOTRUN -> [SKIP][74] ([fdo#109278] / [fdo#109284] / [fdo#111827])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-iclb7/igt@kms_color_chamelium@pipe-d-ctm-limited-range.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-tglb:         NOTRUN -> [SKIP][75] ([i915#1063]) +1 similar issue
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-tglb5/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@lic:
    - shard-kbl:          NOTRUN -> [TIMEOUT][76] ([i915#1319])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-kbl1/igt@kms_content_protection@lic.html

  * igt@kms_cursor_crc@pipe-a-cursor-32x10-offscreen:
    - shard-tglb:         NOTRUN -> [SKIP][77] ([i915#3359]) +10 similar issues
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-tglb3/igt@kms_cursor_crc@pipe-a-cursor-32x10-offscreen.html

  * igt@kms_cursor_crc@pipe-a-cursor-suspend:
    - shard-kbl:          NOTRUN -> [DMESG-WARN][78] ([i915#180]) +1 similar issue
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html

  * igt@kms_cursor_crc@pipe-b-cursor-32x32-sliding:
    - shard-tglb:         NOTRUN -> [SKIP][79] ([i915#3319]) +2 similar issues
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-tglb6/igt@kms_cursor_crc@pipe-b-cursor-32x32-sliding.html

  * igt@kms_cursor_crc@pipe-b-cursor-512x512-rapid-movement:
    - shard-iclb:         NOTRUN -> [SKIP][80] ([fdo#109278] / [fdo#109279]) +1 similar issue
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-iclb8/igt@kms_cursor_crc@pipe-b-cursor-512x512-rapid-movement.html

  * igt@kms_cursor_crc@pipe-c-cursor-512x512-random:
    - shard-tglb:         NOTRUN -> [SKIP][81] ([fdo#109279] / [i915#3359]) +4 similar issues
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-tglb6/igt@kms_cursor_crc@pipe-c-cursor-512x512-random.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-apl:          NOTRUN -> [DMESG-WARN][82] ([i915#180])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-apl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - shard-tglb:         NOTRUN -> [SKIP][83] ([i915#4103]) +1 similar issue
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-tglb3/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
    - shard-iclb:         NOTRUN -> [SKIP][84] ([fdo#109274] / [fdo#109278]) +1 similar issue
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-iclb8/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html

  * igt@kms_cursor_legacy@pipe-d-single-move:
    - shard-iclb:         NOTRUN -> [SKIP][85] ([fdo#109278]) +40 similar issues
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-iclb8/igt@kms_cursor_legacy@pipe-d-single-move.html

  * igt@kms_cursor_legacy@pipe-d-torture-bo:
    - shard-apl:          NOTRUN -> [SKIP][86] ([fdo#109271] / [i915#533]) +2 similar issues
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-apl1/igt@kms_cursor_legacy@pipe-d-torture-bo.html

  * igt@kms_flip@2x-absolute-wf_vblank:
    - shard-tglb:         NOTRUN -> [SKIP][87] ([fdo#109274] / [fdo#111825] / [i915#3966])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-tglb7/igt@kms_flip@2x-absolute-wf_vblank.html

  * igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2:
    - shard-glk:          [PASS][88] -> [FAIL][89] ([i915#79])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11301/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
    - shard-iclb:         NOTRUN -> [SKIP][90] ([fdo#109274]) +4 similar issues
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-iclb5/igt@kms_flip@2x-modeset-vs-vblank-race-interruptible.html

  * igt@kms_flip@2x-plain-flip-fb-recreate:
    - shard-tglb:         NOTRUN -> [SKIP][91] ([fdo#109274] / [fdo#111825]) +8 similar issues
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-tglb1/igt@kms_flip@2x-plain-flip-fb-recreate.html

  * igt@kms_flip@flip-vs-suspend@c-dp1:
    - shard-kbl:          [PASS][92] -> [DMESG-WARN][93] ([i915#180]) +5 similar issues
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11301/shard-kbl3/igt@kms_flip@flip-vs-suspend@c-dp1.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-kbl7/igt@kms_flip@flip-vs-suspend@c-dp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
    - shard-iclb:         [PASS][94] -> [SKIP][95] ([i915#3701]) +1 similar issue
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11301/shard-iclb1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling:
    - shard-tglb:         NOTRUN -> [SKIP][96] ([i915#2587])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-tglb1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-upscaling:
    - shard-iclb:         NOTRUN -> [SKIP][97] ([i915#2587]) +1 similar issue
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-iclb6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-upscaling.html

  * igt@kms_force_connector_basic@force-load-detect:
    - shard-iclb:         NOTRUN -> [SKIP][98] ([fdo#109285])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-iclb8/igt@kms_force_connector_basic@force-load-detect.html
    - shard-tglb:         NOTRUN -> [SKIP][99] ([fdo#109285])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-tglb8/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt:
    - shard-kbl:          NOTRUN -> [SKIP][100] ([fdo#109271]) +307 similar issues
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-gtt:
    - shard-glk:          [PASS][101] -> [FAIL][102] ([i915#1888] / [i915#2546])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11301/shard-glk8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-gtt.html
   [102]: h

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6720/index.html

[-- Attachment #2: Type: text/html, Size: 34295 bytes --]

[igt-dev] [PATCH i-g-t 0/3] Use supported dma-buf regions in prime_mmap*

[Zbigniew Kempczyński]

Contains library helper + changes in prime_mmap*. Additionally removes
prime_mmap_coherency libdrm dependency.

v2: addressing review comments
v3: change commit message in memory regions helper patch

Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>

Ch Sai Gowtham (1):
  tests/prime_mmap_coherency.c: Use intel_bb and intel_buf to remove
    libdrm dependency

Zbigniew Kempczyński (2):
  lib/intel_memory_regions: Add helper which creates supported dma-buf
    set
  tests/prime_mmap: Iterate over dma-buf supported memory regions

 lib/i915/intel_memory_region.c |  61 ++++++++++++++++
 lib/i915/intel_memory_region.h |   3 +
 tests/prime_mmap.c             |  34 ++-------
 tests/prime_mmap_coherency.c   | 128 ++++++++++++++++++++-------------
 4 files changed, 148 insertions(+), 78 deletions(-)

-- 
2.32.0

[igt-dev] [PATCH i-g-t 3/3] tests/prime_mmap_coherency.c: Use intel_bb and intel_buf to remove libdrm dependency

[Zbigniew Kempczyński]

From: Ch Sai Gowtham <sai.gowtham.ch@intel.com>

Using intel_bb and intel_buf to remove libdrm dependency.

v2: addressing review comments (Kamil)

Signed-off-by: Ch Sai Gowtham <sai.gowtham.ch@intel.com>
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
---
 tests/prime_mmap_coherency.c | 128 +++++++++++++++++++++--------------
 1 file changed, 78 insertions(+), 50 deletions(-)

diff --git a/tests/prime_mmap_coherency.c b/tests/prime_mmap_coherency.c
index 2a0749577..0238d9117 100644
--- a/tests/prime_mmap_coherency.c
+++ b/tests/prime_mmap_coherency.c
@@ -36,8 +36,8 @@ IGT_TEST_DESCRIPTION("Test dma-buf mmap on !llc platforms mostly and provoke"
 		" coherency bugs so we know for sure where we need the sync ioctls.");
 
 int fd;
-static drm_intel_bufmgr *bufmgr;
-struct intel_batchbuffer *batch;
+static struct buf_ops *bops;
+static struct intel_bb *batch;
 static int width = 1024, height = 1024;
 
 /*
@@ -49,29 +49,34 @@ static int width = 1024, height = 1024;
  */
 static int test_read_flush(void)
 {
-	drm_intel_bo *bo_1;
-	drm_intel_bo *bo_2;
+	struct intel_buf *buffer_1;
+	struct intel_buf *buffer_2;
 	uint32_t *ptr_cpu;
 	uint32_t *ptr_gtt;
 	int dma_buf_fd, i;
 	int stale = 0;
 
-	bo_1 = drm_intel_bo_alloc(bufmgr, "BO 1", width * height * 4, 4096);
+
+	buffer_1 = intel_buf_create(bops, width, height, 32, 4096,
+				    I915_TILING_NONE, I915_COMPRESSION_NONE);
 
 	/* STEP #1: put the BO 1 in GTT domain. We use the blitter to copy and fill
 	 * zeros to BO 1, so commands will be submitted and likely to place BO 1 in
 	 * the GTT domain. */
-	bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096);
-	intel_copy_bo(batch, bo_1, bo_2, width * height);
-	drm_intel_bo_unreference(bo_2);
 
+	buffer_2 = intel_buf_create(bops, width, height, 32, 4096,
+				    I915_TILING_NONE, I915_COMPRESSION_NONE);
+	intel_bb_copy_intel_buf(batch, buffer_2, buffer_1, width * height * 4);
+	intel_buf_destroy(buffer_2);
 	/* STEP #2: read BO 1 using the dma-buf CPU mmap. This dirties the CPU caches. */
-	dma_buf_fd = prime_handle_to_fd_for_mmap(fd, bo_1->handle);
+	dma_buf_fd = prime_handle_to_fd_for_mmap(fd, buffer_1->handle);
 
 	/* STEP #3: write 0x11 into BO 1. */
-	bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096);
-	ptr_gtt = gem_mmap__device_coherent(fd, bo_2->handle, 0, width * height, PROT_READ | PROT_WRITE);
-	gem_set_domain(fd, bo_2->handle,
+	buffer_2 = intel_buf_create(bops, width, height, 32, 4096,
+				    I915_TILING_NONE, I915_COMPRESSION_NONE);
+	ptr_gtt = gem_mmap__device_coherent(fd, buffer_2->handle, 0,
+					    width * height, PROT_READ | PROT_WRITE);
+	gem_set_domain(fd, buffer_2->handle,
 		       I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
 	memset(ptr_gtt, 0xc5, width * height);
 	munmap(ptr_gtt, width * height);
@@ -85,8 +90,8 @@ static int test_read_flush(void)
 		igt_assert_eq(ptr_cpu[i], 0);
 	prime_sync_end(dma_buf_fd, false);
 
-	intel_copy_bo(batch, bo_1, bo_2, width * height);
-	drm_intel_bo_unreference(bo_2);
+	intel_bb_copy_intel_buf(batch, buffer_2, buffer_1, width * height);
+	intel_buf_destroy(buffer_2);
 
 	/* STEP #4: read again using the CPU mmap. Doing #1 before #3 makes sure we
 	 * don't do a full CPU cache flush in step #3 again. That makes sure all the
@@ -99,7 +104,7 @@ static int test_read_flush(void)
 			stale++;
 	prime_sync_end(dma_buf_fd, false);
 
-	drm_intel_bo_unreference(bo_1);
+	intel_buf_destroy(buffer_1);
 	munmap(ptr_cpu, width * height);
 
 	close(dma_buf_fd);
@@ -116,24 +121,26 @@ static int test_read_flush(void)
  */
 static int test_write_flush(void)
 {
-	drm_intel_bo *bo_1;
-	drm_intel_bo *bo_2;
+	struct intel_buf *buffer_1;
+	struct intel_buf *buffer_2;
 	uint32_t *ptr_cpu;
 	uint32_t *ptr2_cpu;
 	int dma_buf_fd, dma_buf2_fd, i;
 	int stale = 0;
 
-	bo_1 = drm_intel_bo_alloc(bufmgr, "BO 1", width * height * 4, 4096);
+	buffer_1 = intel_buf_create(bops, width, height, 32, 4096,
+				    I915_TILING_NONE, I915_COMPRESSION_NONE);
 
 	/* STEP #1: Put the BO 1 in GTT domain. We use the blitter to copy and fill
 	 * zeros to BO 1, so commands will be submitted and likely to place BO 1 in
 	 * the GTT domain. */
-	bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096);
-	intel_copy_bo(batch, bo_1, bo_2, width * height);
-	drm_intel_bo_unreference(bo_2);
+	buffer_2 = intel_buf_create(bops, width, height, 32, 4096,
+				    I915_TILING_NONE, I915_COMPRESSION_NONE);
+	intel_bb_copy_intel_buf(batch, buffer_2, buffer_1, width * height * 4);
+	intel_buf_destroy(buffer_2);
 
 	/* STEP #2: Write '1's into BO 1 using the dma-buf CPU mmap. */
-	dma_buf_fd = prime_handle_to_fd_for_mmap(fd, bo_1->handle);
+	dma_buf_fd = prime_handle_to_fd_for_mmap(fd, buffer_1->handle);
 	igt_skip_on(errno == EINVAL);
 
 	ptr_cpu = mmap(NULL, width * height, PROT_READ | PROT_WRITE,
@@ -147,13 +154,14 @@ static int test_write_flush(void)
 	prime_sync_end(dma_buf_fd, true);
 
 	/* STEP #3: Copy BO 1 into BO 2, using blitter. */
-	bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096);
-	intel_copy_bo(batch, bo_2, bo_1, width * height);
+	buffer_2 = intel_buf_create(bops, width, height, 32, 4096,
+				    I915_TILING_NONE, I915_COMPRESSION_NONE);
+	intel_bb_copy_intel_buf(batch, buffer_1, buffer_2, width * height * 4);
 
 	/* STEP #4: compare BO 2 against written BO 1. In !llc hardware, there
 	 * should be some cache lines that didn't get flushed out and are still 0,
 	 * requiring cache flush before the write in step 2. */
-	dma_buf2_fd = prime_handle_to_fd_for_mmap(fd, bo_2->handle);
+	dma_buf2_fd = prime_handle_to_fd_for_mmap(fd, buffer_2->handle);
 	igt_skip_on(errno == EINVAL);
 
 	ptr2_cpu = mmap(NULL, width * height, PROT_READ | PROT_WRITE,
@@ -168,8 +176,8 @@ static int test_write_flush(void)
 
 	prime_sync_end(dma_buf2_fd, false);
 
-	drm_intel_bo_unreference(bo_1);
-	drm_intel_bo_unreference(bo_2);
+	intel_buf_destroy(buffer_1);
+	intel_buf_destroy(buffer_2);
 	munmap(ptr_cpu, width * height);
 
 	close(dma_buf2_fd);
@@ -180,33 +188,32 @@ static int test_write_flush(void)
 
 static void blit_and_cmp(void)
 {
-	drm_intel_bo *bo_1;
-	drm_intel_bo *bo_2;
+	struct intel_buf *buffer_1;
+	struct intel_buf *buffer_2;
 	uint32_t *ptr_cpu;
 	uint32_t *ptr2_cpu;
 	int dma_buf_fd, dma_buf2_fd, i;
 	int local_fd;
-	drm_intel_bufmgr *local_bufmgr;
-	struct intel_batchbuffer *local_batch;
-
+	struct buf_ops *local_bops;
+	struct intel_bb *local_batch;
 	/* recreate process local variables */
 	local_fd = drm_open_driver(DRIVER_INTEL);
-	local_bufmgr = drm_intel_bufmgr_gem_init(local_fd, 4096);
-	igt_assert(local_bufmgr);
+	local_bops = buf_ops_create(local_fd);
 
-	local_batch = intel_batchbuffer_alloc(local_bufmgr, intel_get_drm_devid(local_fd));
-	igt_assert(local_batch);
+	local_batch = intel_bb_create(local_fd, 4096);
 
-	bo_1 = drm_intel_bo_alloc(local_bufmgr, "BO 1", width * height * 4, 4096);
-	dma_buf_fd = prime_handle_to_fd_for_mmap(local_fd, bo_1->handle);
+	buffer_1 = intel_buf_create(local_bops, width, height, 32, 4096,
+				    I915_TILING_NONE, I915_COMPRESSION_NONE);
+	dma_buf_fd = prime_handle_to_fd_for_mmap(local_fd, buffer_1->handle);
 	igt_skip_on(errno == EINVAL);
 
 	ptr_cpu = mmap(NULL, width * height, PROT_READ | PROT_WRITE,
 		       MAP_SHARED, dma_buf_fd, 0);
 	igt_assert(ptr_cpu != MAP_FAILED);
 
-	bo_2 = drm_intel_bo_alloc(local_bufmgr, "BO 2", width * height * 4, 4096);
-	dma_buf2_fd = prime_handle_to_fd_for_mmap(local_fd, bo_2->handle);
+	buffer_2 = intel_buf_create(local_bops, width, height, 32, 4096,
+				    I915_TILING_NONE, I915_COMPRESSION_NONE);
+	dma_buf2_fd = prime_handle_to_fd_for_mmap(local_fd, buffer_2->handle);
 
 	ptr2_cpu = mmap(NULL, width * height, PROT_READ | PROT_WRITE,
 			MAP_SHARED, dma_buf2_fd, 0);
@@ -222,7 +229,7 @@ static void blit_and_cmp(void)
 	prime_sync_end(dma_buf2_fd, true);
 
 	/* Copy BO 1 into BO 2, using blitter. */
-	intel_copy_bo(local_batch, bo_2, bo_1, width * height);
+	intel_bb_copy_intel_buf(local_batch, buffer_1, buffer_2, width * height * 4);
 	usleep(0); /* let someone else claim the mutex */
 
 	/* Compare BOs. If prime_sync_* were executed properly, the caches
@@ -232,16 +239,16 @@ static void blit_and_cmp(void)
 		igt_fail_on_f(ptr2_cpu[i] != 0x11111111, "Found 0x%08x at offset 0x%08x\n", ptr2_cpu[i], i);
 	prime_sync_end(dma_buf2_fd, false);
 
-	drm_intel_bo_unreference(bo_1);
-	drm_intel_bo_unreference(bo_2);
+	intel_buf_destroy(buffer_1);
+	intel_buf_destroy(buffer_2);
 	munmap(ptr_cpu, width * height);
 	munmap(ptr2_cpu, width * height);
 
 	close(dma_buf_fd);
 	close(dma_buf2_fd);
 
-	intel_batchbuffer_free(local_batch);
-	drm_intel_bufmgr_destroy(local_bufmgr);
+	intel_bb_destroy(local_batch);
+	buf_ops_destroy(local_bops);
 	close(local_fd);
 }
 
@@ -274,49 +281,70 @@ static void test_ioctl_errors(void)
 			break;
 		}
 
-		igt_fork(child, num_children)
+		igt_fork(child, num_children) {
+			intel_allocator_init();
 			igt_while_interruptible(true) blit_and_cmp();
+		}
 		igt_waitchildren();
 	}
 }
 
 igt_main
 {
+	struct igt_collection *set, *dma_buf_set;
+	struct drm_i915_query_memory_regions *query_info;
+
 	igt_fixture {
 		fd = drm_open_driver(DRIVER_INTEL);
 		igt_require_gem(fd);
 
-		bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
-		batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
+		query_info = gem_get_query_memory_regions(fd);
+		igt_assert(query_info);
+
+		set = get_memory_region_set(query_info, I915_SYSTEM_MEMORY,
+					    I915_DEVICE_MEMORY);
+
+		dma_buf_set = get_dma_buf_mmap_supported_set(fd, set);
+		igt_require_f(dma_buf_set, "No dma-buf region supported\n");
+
+		igt_collection_destroy(set);
+		igt_collection_destroy(dma_buf_set);
+
+		bops = buf_ops_create(fd);
 	}
 
 	/* Cache coherency and the eviction are pretty much unpredictable, so
 	 * reproducing boils down to trial and error to hit different scenarios.
 	 * TODO: We may want to improve tests a bit by picking random subranges. */
 	igt_subtest("read") {
+		batch = intel_bb_create(fd, 4096);
 		igt_until_timeout(5) {
 			int stale = test_read_flush();
 			igt_fail_on_f(stale,
 				      "num of stale cache lines %d\n", stale);
 		}
+		intel_bb_destroy(batch);
 	}
 
 	igt_subtest("write") {
+		batch = intel_bb_create(fd, 4096);
 		igt_until_timeout(5) {
 			int stale = test_write_flush();
 			igt_fail_on_f(stale,
 				      "num of stale cache lines %d\n", stale);
 		}
+		intel_bb_destroy(batch);
 	}
 
 	igt_subtest("ioctl-errors") {
+		batch = intel_bb_create(fd, 4096);
 		igt_info("exercising concurrent blit to get ioctl errors\n");
 		test_ioctl_errors();
+		intel_bb_destroy(batch);
 	}
 
 	igt_fixture {
-		intel_batchbuffer_free(batch);
-		drm_intel_bufmgr_destroy(bufmgr);
+		buf_ops_destroy(bops);
 
 		close(fd);
 	}
-- 
2.32.0

Re: [igt-dev] [PATCH i-g-t 3/3] tests/prime_mmap_coherency.c: Use intel_bb and intel_buf to remove libdrm dependency

[Gwan-gyeong Mun]

Tested-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>

If the https://patchwork.freedesktop.org/series/100737/ patch (currently 
under review) is applied to the i915, you can see that the 
igt@prime_mmap_coherency test works normally in dg1.

On 3/2/22 10:06 AM, Zbigniew Kempczyński wrote:
> From: Ch Sai Gowtham <sai.gowtham.ch@intel.com>
> 
> Using intel_bb and intel_buf to remove libdrm dependency.
> 
> v2: addressing review comments (Kamil)
> 
> Signed-off-by: Ch Sai Gowtham <sai.gowtham.ch@intel.com>
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> ---
>   tests/prime_mmap_coherency.c | 128 +++++++++++++++++++++--------------
>   1 file changed, 78 insertions(+), 50 deletions(-)
> 
> diff --git a/tests/prime_mmap_coherency.c b/tests/prime_mmap_coherency.c
> index 2a0749577..0238d9117 100644
> --- a/tests/prime_mmap_coherency.c
> +++ b/tests/prime_mmap_coherency.c
> @@ -36,8 +36,8 @@ IGT_TEST_DESCRIPTION("Test dma-buf mmap on !llc platforms mostly and provoke"
>   		" coherency bugs so we know for sure where we need the sync ioctls.");
>   
>   int fd;
> -static drm_intel_bufmgr *bufmgr;
> -struct intel_batchbuffer *batch;
> +static struct buf_ops *bops;
> +static struct intel_bb *batch;
>   static int width = 1024, height = 1024;
>   
>   /*
> @@ -49,29 +49,34 @@ static int width = 1024, height = 1024;
>    */
>   static int test_read_flush(void)
>   {
> -	drm_intel_bo *bo_1;
> -	drm_intel_bo *bo_2;
> +	struct intel_buf *buffer_1;
> +	struct intel_buf *buffer_2;
>   	uint32_t *ptr_cpu;
>   	uint32_t *ptr_gtt;
>   	int dma_buf_fd, i;
>   	int stale = 0;
>   
> -	bo_1 = drm_intel_bo_alloc(bufmgr, "BO 1", width * height * 4, 4096);
> +
> +	buffer_1 = intel_buf_create(bops, width, height, 32, 4096,
> +				    I915_TILING_NONE, I915_COMPRESSION_NONE);
>   
>   	/* STEP #1: put the BO 1 in GTT domain. We use the blitter to copy and fill
>   	 * zeros to BO 1, so commands will be submitted and likely to place BO 1 in
>   	 * the GTT domain. */
> -	bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096);
> -	intel_copy_bo(batch, bo_1, bo_2, width * height);
> -	drm_intel_bo_unreference(bo_2);
>   
> +	buffer_2 = intel_buf_create(bops, width, height, 32, 4096,
> +				    I915_TILING_NONE, I915_COMPRESSION_NONE);
> +	intel_bb_copy_intel_buf(batch, buffer_2, buffer_1, width * height * 4);
32bpp used in intel_buf_create() and * 4 (byte) used for size 
calculation of intel_bb_copy_intel_buf() seem to be related to each other.
For code readability, could yoy update the code using the macro?
(for example,
   BPP (Bit Per Pixels): 32 => #define BPP 4
   PIXEL_SIZE (Byte Per Pixels): BPP / 4  => #define PIXEL_SIZE BPP/4  )
  If you have a name you think of even if it is not the name used as an 
example, please use it appropriately. )
> +	intel_buf_destroy(buffer_2);
>   	/* STEP #2: read BO 1 using the dma-buf CPU mmap. This dirties the CPU caches. */
> -	dma_buf_fd = prime_handle_to_fd_for_mmap(fd, bo_1->handle);
> +	dma_buf_fd = prime_handle_to_fd_for_mmap(fd, buffer_1->handle);
>   
>   	/* STEP #3: write 0x11 into BO 1. */
> -	bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096);
> -	ptr_gtt = gem_mmap__device_coherent(fd, bo_2->handle, 0, width * height, PROT_READ | PROT_WRITE);
> -	gem_set_domain(fd, bo_2->handle,
> +	buffer_2 = intel_buf_create(bops, width, height, 32, 4096,
> +				    I915_TILING_NONE, I915_COMPRESSION_NONE);
> +	ptr_gtt = gem_mmap__device_coherent(fd, buffer_2->handle, 0,
> +					    width * height, PROT_READ | PROT_WRITE);
> +	gem_set_domain(fd, buffer_2->handle,
>   		       I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
>   	memset(ptr_gtt, 0xc5, width * height);
>   	munmap(ptr_gtt, width * height);
> @@ -85,8 +90,8 @@ static int test_read_flush(void)
>   		igt_assert_eq(ptr_cpu[i], 0);
>   	prime_sync_end(dma_buf_fd, false);
>   
> -	intel_copy_bo(batch, bo_1, bo_2, width * height);
> -	drm_intel_bo_unreference(bo_2);
> +	intel_bb_copy_intel_buf(batch, buffer_2, buffer_1, width * height);
> +	intel_buf_destroy(buffer_2);
>   
>   	/* STEP #4: read again using the CPU mmap. Doing #1 before #3 makes sure we
>   	 * don't do a full CPU cache flush in step #3 again. That makes sure all the
> @@ -99,7 +104,7 @@ static int test_read_flush(void)
>   			stale++;
>   	prime_sync_end(dma_buf_fd, false);
>   
> -	drm_intel_bo_unreference(bo_1);
> +	intel_buf_destroy(buffer_1);
>   	munmap(ptr_cpu, width * height);
>   
>   	close(dma_buf_fd);
> @@ -116,24 +121,26 @@ static int test_read_flush(void)
>    */
>   static int test_write_flush(void)
>   {
> -	drm_intel_bo *bo_1;
> -	drm_intel_bo *bo_2;
> +	struct intel_buf *buffer_1;
> +	struct intel_buf *buffer_2;
>   	uint32_t *ptr_cpu;
>   	uint32_t *ptr2_cpu;
>   	int dma_buf_fd, dma_buf2_fd, i;
>   	int stale = 0;
>   
> -	bo_1 = drm_intel_bo_alloc(bufmgr, "BO 1", width * height * 4, 4096);
> +	buffer_1 = intel_buf_create(bops, width, height, 32, 4096,
> +				    I915_TILING_NONE, I915_COMPRESSION_NONE);
>   
>   	/* STEP #1: Put the BO 1 in GTT domain. We use the blitter to copy and fill
>   	 * zeros to BO 1, so commands will be submitted and likely to place BO 1 in
>   	 * the GTT domain. */
> -	bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096);
> -	intel_copy_bo(batch, bo_1, bo_2, width * height);
> -	drm_intel_bo_unreference(bo_2);
> +	buffer_2 = intel_buf_create(bops, width, height, 32, 4096,
> +				    I915_TILING_NONE, I915_COMPRESSION_NONE);
> +	intel_bb_copy_intel_buf(batch, buffer_2, buffer_1, width * height * 4);
> +	intel_buf_destroy(buffer_2);
>   
>   	/* STEP #2: Write '1's into BO 1 using the dma-buf CPU mmap. */
> -	dma_buf_fd = prime_handle_to_fd_for_mmap(fd, bo_1->handle);
> +	dma_buf_fd = prime_handle_to_fd_for_mmap(fd, buffer_1->handle);
>   	igt_skip_on(errno == EINVAL);
>   
>   	ptr_cpu = mmap(NULL, width * height, PROT_READ | PROT_WRITE,
> @@ -147,13 +154,14 @@ static int test_write_flush(void)
>   	prime_sync_end(dma_buf_fd, true);
>   
>   	/* STEP #3: Copy BO 1 into BO 2, using blitter. */
> -	bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096);
> -	intel_copy_bo(batch, bo_2, bo_1, width * height);
> +	buffer_2 = intel_buf_create(bops, width, height, 32, 4096,
> +				    I915_TILING_NONE, I915_COMPRESSION_NONE);
> +	intel_bb_copy_intel_buf(batch, buffer_1, buffer_2, width * height * 4);
>   
>   	/* STEP #4: compare BO 2 against written BO 1. In !llc hardware, there
>   	 * should be some cache lines that didn't get flushed out and are still 0,
>   	 * requiring cache flush before the write in step 2. */
> -	dma_buf2_fd = prime_handle_to_fd_for_mmap(fd, bo_2->handle);
> +	dma_buf2_fd = prime_handle_to_fd_for_mmap(fd, buffer_2->handle);
>   	igt_skip_on(errno == EINVAL);
>   
>   	ptr2_cpu = mmap(NULL, width * height, PROT_READ | PROT_WRITE,
> @@ -168,8 +176,8 @@ static int test_write_flush(void)
>   
>   	prime_sync_end(dma_buf2_fd, false);
>   
> -	drm_intel_bo_unreference(bo_1);
> -	drm_intel_bo_unreference(bo_2);
> +	intel_buf_destroy(buffer_1);
> +	intel_buf_destroy(buffer_2);
>   	munmap(ptr_cpu, width * height);
>   
>   	close(dma_buf2_fd);
> @@ -180,33 +188,32 @@ static int test_write_flush(void)
>   
>   static void blit_and_cmp(void)
>   {
> -	drm_intel_bo *bo_1;
> -	drm_intel_bo *bo_2;
> +	struct intel_buf *buffer_1;
> +	struct intel_buf *buffer_2;
>   	uint32_t *ptr_cpu;
>   	uint32_t *ptr2_cpu;
>   	int dma_buf_fd, dma_buf2_fd, i;
>   	int local_fd;
> -	drm_intel_bufmgr *local_bufmgr;
> -	struct intel_batchbuffer *local_batch;
> -
> +	struct buf_ops *local_bops;
> +	struct intel_bb *local_batch;
>   	/* recreate process local variables */
>   	local_fd = drm_open_driver(DRIVER_INTEL);
> -	local_bufmgr = drm_intel_bufmgr_gem_init(local_fd, 4096);
> -	igt_assert(local_bufmgr);
> +	local_bops = buf_ops_create(local_fd);
>   
> -	local_batch = intel_batchbuffer_alloc(local_bufmgr, intel_get_drm_devid(local_fd));
> -	igt_assert(local_batch);
> +	local_batch = intel_bb_create(local_fd, 4096);
>   
> -	bo_1 = drm_intel_bo_alloc(local_bufmgr, "BO 1", width * height * 4, 4096);
> -	dma_buf_fd = prime_handle_to_fd_for_mmap(local_fd, bo_1->handle);
> +	buffer_1 = intel_buf_create(local_bops, width, height, 32, 4096,
> +				    I915_TILING_NONE, I915_COMPRESSION_NONE);
> +	dma_buf_fd = prime_handle_to_fd_for_mmap(local_fd, buffer_1->handle);
>   	igt_skip_on(errno == EINVAL);
>   
>   	ptr_cpu = mmap(NULL, width * height, PROT_READ | PROT_WRITE,
>   		       MAP_SHARED, dma_buf_fd, 0);
>   	igt_assert(ptr_cpu != MAP_FAILED);
>   
> -	bo_2 = drm_intel_bo_alloc(local_bufmgr, "BO 2", width * height * 4, 4096);
> -	dma_buf2_fd = prime_handle_to_fd_for_mmap(local_fd, bo_2->handle);
> +	buffer_2 = intel_buf_create(local_bops, width, height, 32, 4096,
> +				    I915_TILING_NONE, I915_COMPRESSION_NONE);
> +	dma_buf2_fd = prime_handle_to_fd_for_mmap(local_fd, buffer_2->handle);
>   
>   	ptr2_cpu = mmap(NULL, width * height, PROT_READ | PROT_WRITE,
>   			MAP_SHARED, dma_buf2_fd, 0);
> @@ -222,7 +229,7 @@ static void blit_and_cmp(void)
>   	prime_sync_end(dma_buf2_fd, true);
>   
>   	/* Copy BO 1 into BO 2, using blitter. */
> -	intel_copy_bo(local_batch, bo_2, bo_1, width * height);
> +	intel_bb_copy_intel_buf(local_batch, buffer_1, buffer_2, width * height * 4);
>   	usleep(0); /* let someone else claim the mutex */
>   
>   	/* Compare BOs. If prime_sync_* were executed properly, the caches
> @@ -232,16 +239,16 @@ static void blit_and_cmp(void)
>   		igt_fail_on_f(ptr2_cpu[i] != 0x11111111, "Found 0x%08x at offset 0x%08x\n", ptr2_cpu[i], i);
>   	prime_sync_end(dma_buf2_fd, false);
>   
> -	drm_intel_bo_unreference(bo_1);
> -	drm_intel_bo_unreference(bo_2);
> +	intel_buf_destroy(buffer_1);
> +	intel_buf_destroy(buffer_2);
>   	munmap(ptr_cpu, width * height);
>   	munmap(ptr2_cpu, width * height);
>   
>   	close(dma_buf_fd);
>   	close(dma_buf2_fd);
>   
> -	intel_batchbuffer_free(local_batch);
> -	drm_intel_bufmgr_destroy(local_bufmgr);
> +	intel_bb_destroy(local_batch);
> +	buf_ops_destroy(local_bops);
>   	close(local_fd);
>   }
>   
> @@ -274,49 +281,70 @@ static void test_ioctl_errors(void)
>   			break;
>   		}
>   
> -		igt_fork(child, num_children)
> +		igt_fork(child, num_children) {
> +			intel_allocator_init();
>   			igt_while_interruptible(true) blit_and_cmp();
> +		}
>   		igt_waitchildren();
>   	}
>   }
>   
>   igt_main
>   {
> +	struct igt_collection *set, *dma_buf_set;
> +	struct drm_i915_query_memory_regions *query_info;
> +
>   	igt_fixture {
>   		fd = drm_open_driver(DRIVER_INTEL);
>   		igt_require_gem(fd);
>   
> -		bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
> -		batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
> +		query_info = gem_get_query_memory_regions(fd);
> +		igt_assert(query_info);
> +
> +		set = get_memory_region_set(query_info, I915_SYSTEM_MEMORY,
> +					    I915_DEVICE_MEMORY);
Since intel_buf_create() only creates memory from the I915_SYSTEM_MEMORY 
region, could you add to the commit message that this covers only 
I915_SYSTEM_MEMORY? (in order to support testing prime_mmap_coherency 
with I915_DEVICE_MEMORY, we need additional implemention.)

The rest of the parts look good to me.
> +
> +		dma_buf_set = get_dma_buf_mmap_supported_set(fd, set);
> +		igt_require_f(dma_buf_set, "No dma-buf region supported\n");
> +
> +		igt_collection_destroy(set);
> +		igt_collection_destroy(dma_buf_set);
> +
> +		bops = buf_ops_create(fd);
>   	}
>   
>   	/* Cache coherency and the eviction are pretty much unpredictable, so
>   	 * reproducing boils down to trial and error to hit different scenarios.
>   	 * TODO: We may want to improve tests a bit by picking random subranges. */
>   	igt_subtest("read") {
> +		batch = intel_bb_create(fd, 4096);
>   		igt_until_timeout(5) {
>   			int stale = test_read_flush();
>   			igt_fail_on_f(stale,
>   				      "num of stale cache lines %d\n", stale);
>   		}
> +		intel_bb_destroy(batch);
>   	}
>   
>   	igt_subtest("write") {
> +		batch = intel_bb_create(fd, 4096);
>   		igt_until_timeout(5) {
>   			int stale = test_write_flush();
>   			igt_fail_on_f(stale,
>   				      "num of stale cache lines %d\n", stale);
>   		}
> +		intel_bb_destroy(batch);
>   	}
>   
>   	igt_subtest("ioctl-errors") {
> +		batch = intel_bb_create(fd, 4096);
>   		igt_info("exercising concurrent blit to get ioctl errors\n");
>   		test_ioctl_errors();
> +		intel_bb_destroy(batch);
>   	}
>   
>   	igt_fixture {
> -		intel_batchbuffer_free(batch);
> -		drm_intel_bufmgr_destroy(bufmgr);
> +		buf_ops_destroy(bops);
>   
>   		close(fd);
>   	}
> 

[igt-dev] [PATCH i-g-t 0/3] Use supported dma-buf regions in prime_mmap*

[Zbigniew Kempczyński]

Contains library helper + changes in prime_mmap*. Additionally removes
prime_mmap_coherency libdrm dependency.

Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>

Ch Sai Gowtham (1):
  tests/prime_mmap_coherency.c: Use intel_bb and intel_buf to remove
    libdrm dependency

Zbigniew Kempczyński (2):
  lib/intel_memory_regions: Add helper which creates supported dma-buf
    set
  tests/prime_mmap: Iterate over dma-buf supported memory regions

 lib/i915/intel_memory_region.c |  61 ++++++++++++++++
 lib/i915/intel_memory_region.h |   3 +
 tests/prime_mmap.c             |  34 ++-------
 tests/prime_mmap_coherency.c   | 125 ++++++++++++++++++++-------------
 4 files changed, 145 insertions(+), 78 deletions(-)

-- 
2.32.0

[igt-dev] [PATCH i-g-t 3/3] tests/prime_mmap_coherency.c: Use intel_bb and intel_buf to remove libdrm dependency

[Zbigniew Kempczyński]

From: Ch Sai Gowtham <sai.gowtham.ch@intel.com>

Using intel_bb and intel_buf to remove libdrm dependency.

Signed-off-by: Ch Sai Gowtham <sai.gowtham.ch@intel.com>
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 tests/prime_mmap_coherency.c | 125 +++++++++++++++++++++--------------
 1 file changed, 75 insertions(+), 50 deletions(-)

diff --git a/tests/prime_mmap_coherency.c b/tests/prime_mmap_coherency.c
index 2a0749577..a619a4c9b 100644
--- a/tests/prime_mmap_coherency.c
+++ b/tests/prime_mmap_coherency.c
@@ -36,8 +36,8 @@ IGT_TEST_DESCRIPTION("Test dma-buf mmap on !llc platforms mostly and provoke"
 		" coherency bugs so we know for sure where we need the sync ioctls.");
 
 int fd;
-static drm_intel_bufmgr *bufmgr;
-struct intel_batchbuffer *batch;
+static struct buf_ops *bops;
+static struct intel_bb *batch;
 static int width = 1024, height = 1024;
 
 /*
@@ -49,29 +49,34 @@ static int width = 1024, height = 1024;
  */
 static int test_read_flush(void)
 {
-	drm_intel_bo *bo_1;
-	drm_intel_bo *bo_2;
+	struct intel_buf *buffer_1;
+	struct intel_buf *buffer_2;
 	uint32_t *ptr_cpu;
 	uint32_t *ptr_gtt;
 	int dma_buf_fd, i;
 	int stale = 0;
 
-	bo_1 = drm_intel_bo_alloc(bufmgr, "BO 1", width * height * 4, 4096);
+
+	buffer_1 = intel_buf_create(bops, width, height, 32, 4096,
+				I915_TILING_NONE, I915_COMPRESSION_NONE);
 
 	/* STEP #1: put the BO 1 in GTT domain. We use the blitter to copy and fill
 	 * zeros to BO 1, so commands will be submitted and likely to place BO 1 in
 	 * the GTT domain. */
-	bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096);
-	intel_copy_bo(batch, bo_1, bo_2, width * height);
-	drm_intel_bo_unreference(bo_2);
 
+	buffer_2 = intel_buf_create(bops, width, height, 32, 4096,
+				I915_TILING_NONE, I915_COMPRESSION_NONE);
+	intel_bb_copy_intel_buf(batch, buffer_2, buffer_1, width * height * 4);
+	intel_buf_destroy(buffer_2);
 	/* STEP #2: read BO 1 using the dma-buf CPU mmap. This dirties the CPU caches. */
-	dma_buf_fd = prime_handle_to_fd_for_mmap(fd, bo_1->handle);
+	dma_buf_fd = prime_handle_to_fd_for_mmap(fd, buffer_1->handle);
 
 	/* STEP #3: write 0x11 into BO 1. */
-	bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096);
-	ptr_gtt = gem_mmap__device_coherent(fd, bo_2->handle, 0, width * height, PROT_READ | PROT_WRITE);
-	gem_set_domain(fd, bo_2->handle,
+	buffer_2 = intel_buf_create(bops, width, height, 32, 4096,
+				I915_TILING_NONE, I915_COMPRESSION_NONE);
+	ptr_gtt = gem_mmap__device_coherent(fd, buffer_2->handle, 0,
+				width * height, PROT_READ | PROT_WRITE);
+	gem_set_domain(fd, buffer_2->handle,
 		       I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
 	memset(ptr_gtt, 0xc5, width * height);
 	munmap(ptr_gtt, width * height);
@@ -85,8 +90,8 @@ static int test_read_flush(void)
 		igt_assert_eq(ptr_cpu[i], 0);
 	prime_sync_end(dma_buf_fd, false);
 
-	intel_copy_bo(batch, bo_1, bo_2, width * height);
-	drm_intel_bo_unreference(bo_2);
+	intel_bb_copy_intel_buf(batch, buffer_2, buffer_1, width * height);
+	intel_buf_destroy(buffer_2);
 
 	/* STEP #4: read again using the CPU mmap. Doing #1 before #3 makes sure we
 	 * don't do a full CPU cache flush in step #3 again. That makes sure all the
@@ -99,7 +104,7 @@ static int test_read_flush(void)
 			stale++;
 	prime_sync_end(dma_buf_fd, false);
 
-	drm_intel_bo_unreference(bo_1);
+	intel_buf_destroy(buffer_1);
 	munmap(ptr_cpu, width * height);
 
 	close(dma_buf_fd);
@@ -116,24 +121,26 @@ static int test_read_flush(void)
  */
 static int test_write_flush(void)
 {
-	drm_intel_bo *bo_1;
-	drm_intel_bo *bo_2;
+	struct intel_buf *buffer_1;
+	struct intel_buf *buffer_2;
 	uint32_t *ptr_cpu;
 	uint32_t *ptr2_cpu;
 	int dma_buf_fd, dma_buf2_fd, i;
 	int stale = 0;
 
-	bo_1 = drm_intel_bo_alloc(bufmgr, "BO 1", width * height * 4, 4096);
+	buffer_1 = intel_buf_create(bops, width, height, 32, 4096,
+				I915_TILING_NONE, I915_COMPRESSION_NONE);
 
 	/* STEP #1: Put the BO 1 in GTT domain. We use the blitter to copy and fill
 	 * zeros to BO 1, so commands will be submitted and likely to place BO 1 in
 	 * the GTT domain. */
-	bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096);
-	intel_copy_bo(batch, bo_1, bo_2, width * height);
-	drm_intel_bo_unreference(bo_2);
+	buffer_2 = intel_buf_create(bops, width, height, 32, 4096,
+				I915_TILING_NONE, I915_COMPRESSION_NONE);
+	intel_bb_copy_intel_buf(batch, buffer_2, buffer_1, width * height * 4);
+	intel_buf_destroy(buffer_2);
 
 	/* STEP #2: Write '1's into BO 1 using the dma-buf CPU mmap. */
-	dma_buf_fd = prime_handle_to_fd_for_mmap(fd, bo_1->handle);
+	dma_buf_fd = prime_handle_to_fd_for_mmap(fd, buffer_1->handle);
 	igt_skip_on(errno == EINVAL);
 
 	ptr_cpu = mmap(NULL, width * height, PROT_READ | PROT_WRITE,
@@ -147,13 +154,14 @@ static int test_write_flush(void)
 	prime_sync_end(dma_buf_fd, true);
 
 	/* STEP #3: Copy BO 1 into BO 2, using blitter. */
-	bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096);
-	intel_copy_bo(batch, bo_2, bo_1, width * height);
+	buffer_2 = intel_buf_create(bops, width, height, 32, 4096,
+				I915_TILING_NONE, I915_COMPRESSION_NONE);
+	intel_bb_copy_intel_buf(batch, buffer_1, buffer_2, width * height * 4);
 
 	/* STEP #4: compare BO 2 against written BO 1. In !llc hardware, there
 	 * should be some cache lines that didn't get flushed out and are still 0,
 	 * requiring cache flush before the write in step 2. */
-	dma_buf2_fd = prime_handle_to_fd_for_mmap(fd, bo_2->handle);
+	dma_buf2_fd = prime_handle_to_fd_for_mmap(fd, buffer_2->handle);
 	igt_skip_on(errno == EINVAL);
 
 	ptr2_cpu = mmap(NULL, width * height, PROT_READ | PROT_WRITE,
@@ -168,8 +176,8 @@ static int test_write_flush(void)
 
 	prime_sync_end(dma_buf2_fd, false);
 
-	drm_intel_bo_unreference(bo_1);
-	drm_intel_bo_unreference(bo_2);
+	intel_buf_destroy(buffer_1);
+	intel_buf_destroy(buffer_2);
 	munmap(ptr_cpu, width * height);
 
 	close(dma_buf2_fd);
@@ -180,33 +188,32 @@ static int test_write_flush(void)
 
 static void blit_and_cmp(void)
 {
-	drm_intel_bo *bo_1;
-	drm_intel_bo *bo_2;
+	struct intel_buf *buffer_1;
+	struct intel_buf *buffer_2;
 	uint32_t *ptr_cpu;
 	uint32_t *ptr2_cpu;
 	int dma_buf_fd, dma_buf2_fd, i;
 	int local_fd;
-	drm_intel_bufmgr *local_bufmgr;
-	struct intel_batchbuffer *local_batch;
-
+	struct buf_ops *local_bops;
+	struct intel_bb *local_batch;
 	/* recreate process local variables */
 	local_fd = drm_open_driver(DRIVER_INTEL);
-	local_bufmgr = drm_intel_bufmgr_gem_init(local_fd, 4096);
-	igt_assert(local_bufmgr);
+	local_bops = buf_ops_create(local_fd);
 
-	local_batch = intel_batchbuffer_alloc(local_bufmgr, intel_get_drm_devid(local_fd));
-	igt_assert(local_batch);
+	local_batch = intel_bb_create(local_fd, 4096);
 
-	bo_1 = drm_intel_bo_alloc(local_bufmgr, "BO 1", width * height * 4, 4096);
-	dma_buf_fd = prime_handle_to_fd_for_mmap(local_fd, bo_1->handle);
+	buffer_1 = intel_buf_create(local_bops, width, height, 32, 4096,
+				I915_TILING_NONE, I915_COMPRESSION_NONE);
+	dma_buf_fd = prime_handle_to_fd_for_mmap(local_fd, buffer_1->handle);
 	igt_skip_on(errno == EINVAL);
 
 	ptr_cpu = mmap(NULL, width * height, PROT_READ | PROT_WRITE,
 		       MAP_SHARED, dma_buf_fd, 0);
 	igt_assert(ptr_cpu != MAP_FAILED);
 
-	bo_2 = drm_intel_bo_alloc(local_bufmgr, "BO 2", width * height * 4, 4096);
-	dma_buf2_fd = prime_handle_to_fd_for_mmap(local_fd, bo_2->handle);
+	buffer_2 = intel_buf_create(local_bops, width, height, 32, 4096,
+				I915_TILING_NONE, I915_COMPRESSION_NONE);
+	dma_buf2_fd = prime_handle_to_fd_for_mmap(local_fd, buffer_2->handle);
 
 	ptr2_cpu = mmap(NULL, width * height, PROT_READ | PROT_WRITE,
 			MAP_SHARED, dma_buf2_fd, 0);
@@ -222,7 +229,7 @@ static void blit_and_cmp(void)
 	prime_sync_end(dma_buf2_fd, true);
 
 	/* Copy BO 1 into BO 2, using blitter. */
-	intel_copy_bo(local_batch, bo_2, bo_1, width * height);
+	intel_bb_copy_intel_buf(local_batch, buffer_1, buffer_2, width * height * 4);
 	usleep(0); /* let someone else claim the mutex */
 
 	/* Compare BOs. If prime_sync_* were executed properly, the caches
@@ -232,16 +239,16 @@ static void blit_and_cmp(void)
 		igt_fail_on_f(ptr2_cpu[i] != 0x11111111, "Found 0x%08x at offset 0x%08x\n", ptr2_cpu[i], i);
 	prime_sync_end(dma_buf2_fd, false);
 
-	drm_intel_bo_unreference(bo_1);
-	drm_intel_bo_unreference(bo_2);
+	intel_buf_destroy(buffer_1);
+	intel_buf_destroy(buffer_2);
 	munmap(ptr_cpu, width * height);
 	munmap(ptr2_cpu, width * height);
 
 	close(dma_buf_fd);
 	close(dma_buf2_fd);
 
-	intel_batchbuffer_free(local_batch);
-	drm_intel_bufmgr_destroy(local_bufmgr);
+	intel_bb_destroy(local_batch);
+	buf_ops_destroy(local_bops);
 	close(local_fd);
 }
 
@@ -274,49 +281,67 @@ static void test_ioctl_errors(void)
 			break;
 		}
 
-		igt_fork(child, num_children)
+		igt_fork(child, num_children) {
+			intel_allocator_init();
 			igt_while_interruptible(true) blit_and_cmp();
+		}
 		igt_waitchildren();
 	}
 }
 
 igt_main
 {
+	struct igt_collection *set, *dmabufset;
+	struct drm_i915_query_memory_regions *query_info;
+
 	igt_fixture {
 		fd = drm_open_driver(DRIVER_INTEL);
 		igt_require_gem(fd);
 
-		bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
-		batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
+		query_info = gem_get_query_memory_regions(fd);
+		igt_assert(query_info);
+
+		set = get_memory_region_set(query_info, I915_SYSTEM_MEMORY,
+					    I915_DEVICE_MEMORY);
+
+		dmabufset = get_dma_buf_mmap_supported_set(fd, set);
+		igt_require_f(dmabufset, "No dma-buf region supported\n");
+
+		bops = buf_ops_create(fd);
 	}
 
 	/* Cache coherency and the eviction are pretty much unpredictable, so
 	 * reproducing boils down to trial and error to hit different scenarios.
 	 * TODO: We may want to improve tests a bit by picking random subranges. */
 	igt_subtest("read") {
+		batch = intel_bb_create(fd, 4096);
 		igt_until_timeout(5) {
 			int stale = test_read_flush();
 			igt_fail_on_f(stale,
 				      "num of stale cache lines %d\n", stale);
 		}
+		intel_bb_destroy(batch);
 	}
 
 	igt_subtest("write") {
+		batch = intel_bb_create(fd, 4096);
 		igt_until_timeout(5) {
 			int stale = test_write_flush();
 			igt_fail_on_f(stale,
 				      "num of stale cache lines %d\n", stale);
 		}
+		intel_bb_destroy(batch);
 	}
 
 	igt_subtest("ioctl-errors") {
+		batch = intel_bb_create(fd, 4096);
 		igt_info("exercising concurrent blit to get ioctl errors\n");
 		test_ioctl_errors();
+		intel_bb_destroy(batch);
 	}
 
 	igt_fixture {
-		intel_batchbuffer_free(batch);
-		drm_intel_bufmgr_destroy(bufmgr);
+		buf_ops_destroy(bops);
 
 		close(fd);
 	}
-- 
2.32.0

Re: [igt-dev] [PATCH i-g-t 3/3] tests/prime_mmap_coherency.c: Use intel_bb and intel_buf to remove libdrm dependency

[Kamil Konieczny]

Hi Zbigniew,

Dnia 2022-02-28 at 14:03:28 +0100, Zbigniew Kempczyński napisał(a):
> From: Ch Sai Gowtham <sai.gowtham.ch@intel.com>
> 
> Using intel_bb and intel_buf to remove libdrm dependency.
> 
> Signed-off-by: Ch Sai Gowtham <sai.gowtham.ch@intel.com>
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> ---
>  tests/prime_mmap_coherency.c | 125 +++++++++++++++++++++--------------
>  1 file changed, 75 insertions(+), 50 deletions(-)
> 
> diff --git a/tests/prime_mmap_coherency.c b/tests/prime_mmap_coherency.c
> index 2a0749577..a619a4c9b 100644
> --- a/tests/prime_mmap_coherency.c
> +++ b/tests/prime_mmap_coherency.c
> @@ -36,8 +36,8 @@ IGT_TEST_DESCRIPTION("Test dma-buf mmap on !llc platforms mostly and provoke"
>  		" coherency bugs so we know for sure where we need the sync ioctls.");
>  
>  int fd;
> -static drm_intel_bufmgr *bufmgr;
> -struct intel_batchbuffer *batch;
> +static struct buf_ops *bops;
> +static struct intel_bb *batch;
>  static int width = 1024, height = 1024;
>  
>  /*
> @@ -49,29 +49,34 @@ static int width = 1024, height = 1024;
>   */
>  static int test_read_flush(void)
>  {
> -	drm_intel_bo *bo_1;
> -	drm_intel_bo *bo_2;
> +	struct intel_buf *buffer_1;
> +	struct intel_buf *buffer_2;
>  	uint32_t *ptr_cpu;
>  	uint32_t *ptr_gtt;
>  	int dma_buf_fd, i;
>  	int stale = 0;
>  
> -	bo_1 = drm_intel_bo_alloc(bufmgr, "BO 1", width * height * 4, 4096);
> +
> +	buffer_1 = intel_buf_create(bops, width, height, 32, 4096,
> +				I915_TILING_NONE, I915_COMPRESSION_NONE);
----------------------------------- ^
Align to column

>  
>  	/* STEP #1: put the BO 1 in GTT domain. We use the blitter to copy and fill
>  	 * zeros to BO 1, so commands will be submitted and likely to place BO 1 in
>  	 * the GTT domain. */
> -	bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096);
> -	intel_copy_bo(batch, bo_1, bo_2, width * height);
> -	drm_intel_bo_unreference(bo_2);
>  
> +	buffer_2 = intel_buf_create(bops, width, height, 32, 4096,
> +				I915_TILING_NONE, I915_COMPRESSION_NONE);
----------------------------------- ^
align

> +	intel_bb_copy_intel_buf(batch, buffer_2, buffer_1, width * height * 4);
> +	intel_buf_destroy(buffer_2);
>  	/* STEP #2: read BO 1 using the dma-buf CPU mmap. This dirties the CPU caches. */
> -	dma_buf_fd = prime_handle_to_fd_for_mmap(fd, bo_1->handle);
> +	dma_buf_fd = prime_handle_to_fd_for_mmap(fd, buffer_1->handle);
>  
>  	/* STEP #3: write 0x11 into BO 1. */
> -	bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096);
> -	ptr_gtt = gem_mmap__device_coherent(fd, bo_2->handle, 0, width * height, PROT_READ | PROT_WRITE);
> -	gem_set_domain(fd, bo_2->handle,
> +	buffer_2 = intel_buf_create(bops, width, height, 32, 4096,
> +				I915_TILING_NONE, I915_COMPRESSION_NONE);
----------------------------------- ^
align

> +	ptr_gtt = gem_mmap__device_coherent(fd, buffer_2->handle, 0,
> +				width * height, PROT_READ | PROT_WRITE);
------------------------------------------- ^
align

> +	gem_set_domain(fd, buffer_2->handle,
>  		       I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
>  	memset(ptr_gtt, 0xc5, width * height);
>  	munmap(ptr_gtt, width * height);
> @@ -85,8 +90,8 @@ static int test_read_flush(void)
>  		igt_assert_eq(ptr_cpu[i], 0);
>  	prime_sync_end(dma_buf_fd, false);
>  
> -	intel_copy_bo(batch, bo_1, bo_2, width * height);
> -	drm_intel_bo_unreference(bo_2);
> +	intel_bb_copy_intel_buf(batch, buffer_2, buffer_1, width * height);
> +	intel_buf_destroy(buffer_2);
>  
>  	/* STEP #4: read again using the CPU mmap. Doing #1 before #3 makes sure we
>  	 * don't do a full CPU cache flush in step #3 again. That makes sure all the
> @@ -99,7 +104,7 @@ static int test_read_flush(void)
>  			stale++;
>  	prime_sync_end(dma_buf_fd, false);
>  
> -	drm_intel_bo_unreference(bo_1);
> +	intel_buf_destroy(buffer_1);
>  	munmap(ptr_cpu, width * height);
>  
>  	close(dma_buf_fd);
> @@ -116,24 +121,26 @@ static int test_read_flush(void)
>   */
>  static int test_write_flush(void)
>  {
> -	drm_intel_bo *bo_1;
> -	drm_intel_bo *bo_2;
> +	struct intel_buf *buffer_1;
> +	struct intel_buf *buffer_2;
>  	uint32_t *ptr_cpu;
>  	uint32_t *ptr2_cpu;
>  	int dma_buf_fd, dma_buf2_fd, i;
>  	int stale = 0;
>  
> -	bo_1 = drm_intel_bo_alloc(bufmgr, "BO 1", width * height * 4, 4096);
> +	buffer_1 = intel_buf_create(bops, width, height, 32, 4096,
> +				I915_TILING_NONE, I915_COMPRESSION_NONE);
----------------------------------- ^
align

>  
>  	/* STEP #1: Put the BO 1 in GTT domain. We use the blitter to copy and fill
>  	 * zeros to BO 1, so commands will be submitted and likely to place BO 1 in
>  	 * the GTT domain. */
> -	bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096);
> -	intel_copy_bo(batch, bo_1, bo_2, width * height);
> -	drm_intel_bo_unreference(bo_2);
> +	buffer_2 = intel_buf_create(bops, width, height, 32, 4096,
> +				I915_TILING_NONE, I915_COMPRESSION_NONE);
----------------------------------- ^
align

> +	intel_bb_copy_intel_buf(batch, buffer_2, buffer_1, width * height * 4);
> +	intel_buf_destroy(buffer_2);
>  
>  	/* STEP #2: Write '1's into BO 1 using the dma-buf CPU mmap. */
> -	dma_buf_fd = prime_handle_to_fd_for_mmap(fd, bo_1->handle);
> +	dma_buf_fd = prime_handle_to_fd_for_mmap(fd, buffer_1->handle);
>  	igt_skip_on(errno == EINVAL);
>  
>  	ptr_cpu = mmap(NULL, width * height, PROT_READ | PROT_WRITE,
> @@ -147,13 +154,14 @@ static int test_write_flush(void)
>  	prime_sync_end(dma_buf_fd, true);
>  
>  	/* STEP #3: Copy BO 1 into BO 2, using blitter. */
> -	bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096);
> -	intel_copy_bo(batch, bo_2, bo_1, width * height);
> +	buffer_2 = intel_buf_create(bops, width, height, 32, 4096,
> +				I915_TILING_NONE, I915_COMPRESSION_NONE);
----------------------------------- ^
align

> +	intel_bb_copy_intel_buf(batch, buffer_1, buffer_2, width * height * 4);
>  
>  	/* STEP #4: compare BO 2 against written BO 1. In !llc hardware, there
>  	 * should be some cache lines that didn't get flushed out and are still 0,
>  	 * requiring cache flush before the write in step 2. */
> -	dma_buf2_fd = prime_handle_to_fd_for_mmap(fd, bo_2->handle);
> +	dma_buf2_fd = prime_handle_to_fd_for_mmap(fd, buffer_2->handle);
>  	igt_skip_on(errno == EINVAL);
>  
>  	ptr2_cpu = mmap(NULL, width * height, PROT_READ | PROT_WRITE,
> @@ -168,8 +176,8 @@ static int test_write_flush(void)
>  
>  	prime_sync_end(dma_buf2_fd, false);
>  
> -	drm_intel_bo_unreference(bo_1);
> -	drm_intel_bo_unreference(bo_2);
> +	intel_buf_destroy(buffer_1);
> +	intel_buf_destroy(buffer_2);
>  	munmap(ptr_cpu, width * height);
>  
>  	close(dma_buf2_fd);
> @@ -180,33 +188,32 @@ static int test_write_flush(void)
>  
>  static void blit_and_cmp(void)
>  {
> -	drm_intel_bo *bo_1;
> -	drm_intel_bo *bo_2;
> +	struct intel_buf *buffer_1;
> +	struct intel_buf *buffer_2;
>  	uint32_t *ptr_cpu;
>  	uint32_t *ptr2_cpu;
>  	int dma_buf_fd, dma_buf2_fd, i;
>  	int local_fd;
> -	drm_intel_bufmgr *local_bufmgr;
> -	struct intel_batchbuffer *local_batch;
> -
> +	struct buf_ops *local_bops;
> +	struct intel_bb *local_batch;
>  	/* recreate process local variables */
>  	local_fd = drm_open_driver(DRIVER_INTEL);
> -	local_bufmgr = drm_intel_bufmgr_gem_init(local_fd, 4096);
> -	igt_assert(local_bufmgr);
> +	local_bops = buf_ops_create(local_fd);
>  
> -	local_batch = intel_batchbuffer_alloc(local_bufmgr, intel_get_drm_devid(local_fd));
> -	igt_assert(local_batch);
> +	local_batch = intel_bb_create(local_fd, 4096);
>  
> -	bo_1 = drm_intel_bo_alloc(local_bufmgr, "BO 1", width * height * 4, 4096);
> -	dma_buf_fd = prime_handle_to_fd_for_mmap(local_fd, bo_1->handle);
> +	buffer_1 = intel_buf_create(local_bops, width, height, 32, 4096,
> +				I915_TILING_NONE, I915_COMPRESSION_NONE);
----------------------------------- ^
align

> +	dma_buf_fd = prime_handle_to_fd_for_mmap(local_fd, buffer_1->handle);
>  	igt_skip_on(errno == EINVAL);
>  
>  	ptr_cpu = mmap(NULL, width * height, PROT_READ | PROT_WRITE,
>  		       MAP_SHARED, dma_buf_fd, 0);
>  	igt_assert(ptr_cpu != MAP_FAILED);
>  
> -	bo_2 = drm_intel_bo_alloc(local_bufmgr, "BO 2", width * height * 4, 4096);
> -	dma_buf2_fd = prime_handle_to_fd_for_mmap(local_fd, bo_2->handle);
> +	buffer_2 = intel_buf_create(local_bops, width, height, 32, 4096,
> +				I915_TILING_NONE, I915_COMPRESSION_NONE);
----------------------------------- ^
align

> +	dma_buf2_fd = prime_handle_to_fd_for_mmap(local_fd, buffer_2->handle);
>  
>  	ptr2_cpu = mmap(NULL, width * height, PROT_READ | PROT_WRITE,
>  			MAP_SHARED, dma_buf2_fd, 0);
> @@ -222,7 +229,7 @@ static void blit_and_cmp(void)
>  	prime_sync_end(dma_buf2_fd, true);
>  
>  	/* Copy BO 1 into BO 2, using blitter. */
> -	intel_copy_bo(local_batch, bo_2, bo_1, width * height);
> +	intel_bb_copy_intel_buf(local_batch, buffer_1, buffer_2, width * height * 4);
>  	usleep(0); /* let someone else claim the mutex */
>  
>  	/* Compare BOs. If prime_sync_* were executed properly, the caches
> @@ -232,16 +239,16 @@ static void blit_and_cmp(void)
>  		igt_fail_on_f(ptr2_cpu[i] != 0x11111111, "Found 0x%08x at offset 0x%08x\n", ptr2_cpu[i], i);
>  	prime_sync_end(dma_buf2_fd, false);
>  
> -	drm_intel_bo_unreference(bo_1);
> -	drm_intel_bo_unreference(bo_2);
> +	intel_buf_destroy(buffer_1);
> +	intel_buf_destroy(buffer_2);
>  	munmap(ptr_cpu, width * height);
>  	munmap(ptr2_cpu, width * height);
>  
>  	close(dma_buf_fd);
>  	close(dma_buf2_fd);
>  
> -	intel_batchbuffer_free(local_batch);
> -	drm_intel_bufmgr_destroy(local_bufmgr);
> +	intel_bb_destroy(local_batch);
> +	buf_ops_destroy(local_bops);
>  	close(local_fd);
>  }
>  
> @@ -274,49 +281,67 @@ static void test_ioctl_errors(void)
>  			break;
>  		}
>  
> -		igt_fork(child, num_children)
> +		igt_fork(child, num_children) {
> +			intel_allocator_init();
>  			igt_while_interruptible(true) blit_and_cmp();
> +		}
>  		igt_waitchildren();
>  	}
>  }
>  
>  igt_main
>  {
> +	struct igt_collection *set, *dmabufset;
> +	struct drm_i915_query_memory_regions *query_info;
> +
>  	igt_fixture {
>  		fd = drm_open_driver(DRIVER_INTEL);
>  		igt_require_gem(fd);
>  
> -		bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
> -		batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
> +		query_info = gem_get_query_memory_regions(fd);
> +		igt_assert(query_info);
> +
> +		set = get_memory_region_set(query_info, I915_SYSTEM_MEMORY,
> +					    I915_DEVICE_MEMORY);
> +
> +		dmabufset = get_dma_buf_mmap_supported_set(fd, set);
---------------------------------- ^
Please use _dmubuf_ instead, see 1/3

With that fixed you can add my r-b,
regards,
Kamil Konieczny

> +		igt_require_f(dmabufset, "No dma-buf region supported\n");
> +
> +		bops = buf_ops_create(fd);
>  	}
>  
>  	/* Cache coherency and the eviction are pretty much unpredictable, so
>  	 * reproducing boils down to trial and error to hit different scenarios.
>  	 * TODO: We may want to improve tests a bit by picking random subranges. */
>  	igt_subtest("read") {
> +		batch = intel_bb_create(fd, 4096);
>  		igt_until_timeout(5) {
>  			int stale = test_read_flush();
>  			igt_fail_on_f(stale,
>  				      "num of stale cache lines %d\n", stale);
>  		}
> +		intel_bb_destroy(batch);
>  	}
>  
>  	igt_subtest("write") {
> +		batch = intel_bb_create(fd, 4096);
>  		igt_until_timeout(5) {
>  			int stale = test_write_flush();
>  			igt_fail_on_f(stale,
>  				      "num of stale cache lines %d\n", stale);
>  		}
> +		intel_bb_destroy(batch);
>  	}
>  
>  	igt_subtest("ioctl-errors") {
> +		batch = intel_bb_create(fd, 4096);
>  		igt_info("exercising concurrent blit to get ioctl errors\n");
>  		test_ioctl_errors();
> +		intel_bb_destroy(batch);
>  	}
>  
>  	igt_fixture {
> -		intel_batchbuffer_free(batch);
> -		drm_intel_bufmgr_destroy(bufmgr);
> +		buf_ops_destroy(bops);
>  
>  		close(fd);
>  	}
> -- 
> 2.32.0
>