[Intel-gfx] [PATCH 00/11] drm/i915: Clean up some dpll stuff

[Intel-gfx] [PATCH 00/11] drm/i915: Clean up some dpll stuff

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Clean up a bunch of struct dpll usage, and a few other
random things around the same area.

Ville Syrjälä (11):
  drm/i915: Nuke skl_wrpll_context_init()
  drm/i915: Move a bunch of stuff into rodata from the stack
  drm/i915: Clean up some struct/array initializers
  drm/i915: Store the /5 target clock in sturct dpll on vlv/chv
  drm/i915: Remove bxt m2_frac_en
  drm/i915: Use designated initializers for bxt_dp_clk_val[]
  drm/i915: Store the m2 divider as a whole in bxt_clk_div
  drm/i915: Replace bxt_clk_div with struct dpll
  drm/i915: Replace hand rolled bxt vco calculation with
    chv_calc_dpll_params()
  drm/i915: Populate bxt/glk DPLL clock limits a bit more
  drm/i915: Remove struct dp_link_dpll

 drivers/gpu/drm/i915/display/g4x_dp.c         |  47 +++----
 drivers/gpu/drm/i915/display/intel_dpll.c     |  26 ++--
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 115 ++++++++----------
 3 files changed, 77 insertions(+), 111 deletions(-)

-- 
2.34.1

[Intel-gfx] [PATCH 01/11] drm/i915: Nuke skl_wrpll_context_init()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We can trivially replace skl_wrpll_context_init() with a single
designated initializer.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 13 +++----------
 1 file changed, 3 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 569903d47aea..1b1b70f0ff93 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -1330,13 +1330,6 @@ struct skl_wrpll_context {
 	unsigned int p;			/* chosen divider */
 };
 
-static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
-{
-	memset(ctx, 0, sizeof(*ctx));
-
-	ctx->min_deviation = U64_MAX;
-}
-
 /* DCO freq must be within +1%/-6%  of the DCO central freq */
 #define SKL_DCO_MAX_PDEVIATION	100
 #define SKL_DCO_MAX_NDEVIATION	600
@@ -1519,12 +1512,12 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
 		{ even_dividers, ARRAY_SIZE(even_dividers) },
 		{ odd_dividers, ARRAY_SIZE(odd_dividers) },
 	};
-	struct skl_wrpll_context ctx;
+	struct skl_wrpll_context ctx = {
+		.min_deviation = U64_MAX,
+	};
 	unsigned int dco, d, i;
 	unsigned int p0, p1, p2;
 
-	skl_wrpll_context_init(&ctx);
-
 	for (d = 0; d < ARRAY_SIZE(dividers); d++) {
 		for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
 			for (i = 0; i < dividers[d].n_dividers; i++) {
-- 
2.34.1

Re: [Intel-gfx] [PATCH 01/11] drm/i915: Nuke skl_wrpll_context_init()

[Jani Nikula]

On Tue, 01 Mar 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We can trivially replace skl_wrpll_context_init() with a single
> designated initializer.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 13 +++----------
>  1 file changed, 3 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 569903d47aea..1b1b70f0ff93 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -1330,13 +1330,6 @@ struct skl_wrpll_context {
>  	unsigned int p;			/* chosen divider */
>  };
>  
> -static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
> -{
> -	memset(ctx, 0, sizeof(*ctx));
> -
> -	ctx->min_deviation = U64_MAX;
> -}
> -
>  /* DCO freq must be within +1%/-6%  of the DCO central freq */
>  #define SKL_DCO_MAX_PDEVIATION	100
>  #define SKL_DCO_MAX_NDEVIATION	600
> @@ -1519,12 +1512,12 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
>  		{ even_dividers, ARRAY_SIZE(even_dividers) },
>  		{ odd_dividers, ARRAY_SIZE(odd_dividers) },
>  	};
> -	struct skl_wrpll_context ctx;
> +	struct skl_wrpll_context ctx = {
> +		.min_deviation = U64_MAX,
> +	};
>  	unsigned int dco, d, i;
>  	unsigned int p0, p1, p2;
>  
> -	skl_wrpll_context_init(&ctx);
> -
>  	for (d = 0; d < ARRAY_SIZE(dividers); d++) {
>  		for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
>  			for (i = 0; i < dividers[d].n_dividers; i++) {

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 02/11] drm/i915: Move a bunch of stuff into rodata from the stack

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Toss a bunch if constants into .rodata drom the stack. Also
shrink the types of some of the arrays to reduce the size.

bloat-o-meter -c intel_dpll_mgr.o:
add/remove: 0/0 grow/shrink: 0/2 up/down: 0/-86 (-86)
Function                                     old     new   delta
icl_get_dplls                               3393    3372     -21
skl_get_dpll                                2069    2004     -65
Total: Before=28029, After=27943, chg -0.31%
add/remove: 0/0 grow/shrink: 0/0 up/down: 0/0 (0)
Data                                         old     new   delta
Total: Before=17, After=17, chg +0.00%
add/remove: 2/0 grow/shrink: 0/2 up/down: 28/-129 (-101)
RO Data                                      old     new   delta
dco_central_freq                               -      24     +24
div1_vals                                      -       4      +4
odd_dividers                                  28       7     -21
even_dividers                                144      36    -108
Total: Before=3600, After=3499, chg -2.81%

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 24 +++++++++----------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 1b1b70f0ff93..4e06c8203aca 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -1495,18 +1495,17 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
 			int ref_clock,
 			struct skl_wrpll_params *wrpll_params)
 {
-	u64 afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
-	u64 dco_central_freq[3] = { 8400000000ULL,
-				    9000000000ULL,
-				    9600000000ULL };
-	static const int even_dividers[] = {  4,  6,  8, 10, 12, 14, 16, 18, 20,
-					     24, 28, 30, 32, 36, 40, 42, 44,
-					     48, 52, 54, 56, 60, 64, 66, 68,
-					     70, 72, 76, 78, 80, 84, 88, 90,
-					     92, 96, 98 };
-	static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
+	static const u64 dco_central_freq[3] = { 8400000000ULL,
+						 9000000000ULL,
+						 9600000000ULL };
+	static const u8 even_dividers[] = {  4,  6,  8, 10, 12, 14, 16, 18, 20,
+					    24, 28, 30, 32, 36, 40, 42, 44,
+					    48, 52, 54, 56, 60, 64, 66, 68,
+					    70, 72, 76, 78, 80, 84, 88, 90,
+					    92, 96, 98 };
+	static const u8 odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
 	static const struct {
-		const int *list;
+		const u8 *list;
 		int n_dividers;
 	} dividers[] = {
 		{ even_dividers, ARRAY_SIZE(even_dividers) },
@@ -1517,6 +1516,7 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
 	};
 	unsigned int dco, d, i;
 	unsigned int p0, p1, p2;
+	u64 afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
 
 	for (d = 0; d < ARRAY_SIZE(dividers); d++) {
 		for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
@@ -2751,8 +2751,8 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
 				     struct intel_dpll_hw_state *state,
 				     bool is_dkl)
 {
+	static const u8 div1_vals[] = { 7, 5, 3, 2 };
 	u32 dco_min_freq, dco_max_freq;
-	int div1_vals[] = {7, 5, 3, 2};
 	unsigned int i;
 	int div2;
 
-- 
2.34.1

Re: [Intel-gfx] [PATCH 02/11] drm/i915: Move a bunch of stuff into rodata from the stack

[Jani Nikula]

On Tue, 01 Mar 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Toss a bunch if constants into .rodata drom the stack. Also
> shrink the types of some of the arrays to reduce the size.
>
> bloat-o-meter -c intel_dpll_mgr.o:
> add/remove: 0/0 grow/shrink: 0/2 up/down: 0/-86 (-86)
> Function                                     old     new   delta
> icl_get_dplls                               3393    3372     -21
> skl_get_dpll                                2069    2004     -65
> Total: Before=28029, After=27943, chg -0.31%
> add/remove: 0/0 grow/shrink: 0/0 up/down: 0/0 (0)
> Data                                         old     new   delta
> Total: Before=17, After=17, chg +0.00%
> add/remove: 2/0 grow/shrink: 0/2 up/down: 28/-129 (-101)
> RO Data                                      old     new   delta
> dco_central_freq                               -      24     +24
> div1_vals                                      -       4      +4
> odd_dividers                                  28       7     -21
> even_dividers                                144      36    -108
> Total: Before=3600, After=3499, chg -2.81%
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 24 +++++++++----------
>  1 file changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 1b1b70f0ff93..4e06c8203aca 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -1495,18 +1495,17 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
>  			int ref_clock,
>  			struct skl_wrpll_params *wrpll_params)
>  {
> -	u64 afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
> -	u64 dco_central_freq[3] = { 8400000000ULL,
> -				    9000000000ULL,
> -				    9600000000ULL };
> -	static const int even_dividers[] = {  4,  6,  8, 10, 12, 14, 16, 18, 20,
> -					     24, 28, 30, 32, 36, 40, 42, 44,
> -					     48, 52, 54, 56, 60, 64, 66, 68,
> -					     70, 72, 76, 78, 80, 84, 88, 90,
> -					     92, 96, 98 };
> -	static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
> +	static const u64 dco_central_freq[3] = { 8400000000ULL,
> +						 9000000000ULL,
> +						 9600000000ULL };
> +	static const u8 even_dividers[] = {  4,  6,  8, 10, 12, 14, 16, 18, 20,
> +					    24, 28, 30, 32, 36, 40, 42, 44,
> +					    48, 52, 54, 56, 60, 64, 66, 68,
> +					    70, 72, 76, 78, 80, 84, 88, 90,
> +					    92, 96, 98 };
> +	static const u8 odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
>  	static const struct {
> -		const int *list;
> +		const u8 *list;
>  		int n_dividers;
>  	} dividers[] = {
>  		{ even_dividers, ARRAY_SIZE(even_dividers) },
> @@ -1517,6 +1516,7 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
>  	};
>  	unsigned int dco, d, i;
>  	unsigned int p0, p1, p2;
> +	u64 afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
>  
>  	for (d = 0; d < ARRAY_SIZE(dividers); d++) {
>  		for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
> @@ -2751,8 +2751,8 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
>  				     struct intel_dpll_hw_state *state,
>  				     bool is_dkl)
>  {
> +	static const u8 div1_vals[] = { 7, 5, 3, 2 };
>  	u32 dco_min_freq, dco_max_freq;
> -	int div1_vals[] = {7, 5, 3, 2};
>  	unsigned int i;
>  	int div2;

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 03/11] drm/i915: Clean up some struct/array initializers

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use the simple '= {}' form to initialize empty arrays/structs.
Also add some missing whitespace.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 4e06c8203aca..bc26ebacae12 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -832,7 +832,7 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
 {
 	u64 freq2k;
 	unsigned p, n2, r2;
-	struct hsw_wrpll_rnp best = { 0, 0, 0 };
+	struct hsw_wrpll_rnp best = {};
 	unsigned budget;
 
 	freq2k = clock / 100;
@@ -1567,8 +1567,8 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
 static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+	struct skl_wrpll_params wrpll_params = {};
 	u32 ctrl1, cfgcr1, cfgcr2;
-	struct skl_wrpll_params wrpll_params = { 0, };
 
 	/*
 	 * See comment in intel_dpll_hw_state to understand why we always use 0
@@ -2095,13 +2095,13 @@ struct bxt_clk_div {
 
 /* pre-calculated values for DP linkrates */
 static const struct bxt_clk_div bxt_dp_clk_val[] = {
-	{162000, 4, 2, 32, 1677722, 1, 1},
-	{270000, 4, 1, 27,       0, 0, 1},
-	{540000, 2, 1, 27,       0, 0, 1},
-	{216000, 3, 2, 32, 1677722, 1, 1},
-	{243000, 4, 1, 24, 1258291, 1, 1},
-	{324000, 4, 1, 32, 1677722, 1, 1},
-	{432000, 3, 1, 32, 1677722, 1, 1}
+	{ 162000, 4, 2, 32, 1677722, 1, 1 },
+	{ 270000, 4, 1, 27,       0, 0, 1 },
+	{ 540000, 2, 1, 27,       0, 0, 1 },
+	{ 216000, 3, 2, 32, 1677722, 1, 1 },
+	{ 243000, 4, 1, 24, 1258291, 1, 1 },
+	{ 324000, 4, 1, 32, 1677722, 1, 1 },
+	{ 432000, 3, 1, 32, 1677722, 1, 1 }
 };
 
 static bool
-- 
2.34.1

Re: [Intel-gfx] [PATCH 03/11] drm/i915: Clean up some struct/array initializers

[Jani Nikula]

On Tue, 01 Mar 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use the simple '= {}' form to initialize empty arrays/structs.
> Also add some missing whitespace.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 18 +++++++++---------
>  1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 4e06c8203aca..bc26ebacae12 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -832,7 +832,7 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
>  {
>  	u64 freq2k;
>  	unsigned p, n2, r2;
> -	struct hsw_wrpll_rnp best = { 0, 0, 0 };
> +	struct hsw_wrpll_rnp best = {};
>  	unsigned budget;
>  
>  	freq2k = clock / 100;
> @@ -1567,8 +1567,8 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
>  static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> +	struct skl_wrpll_params wrpll_params = {};
>  	u32 ctrl1, cfgcr1, cfgcr2;
> -	struct skl_wrpll_params wrpll_params = { 0, };
>  
>  	/*
>  	 * See comment in intel_dpll_hw_state to understand why we always use 0
> @@ -2095,13 +2095,13 @@ struct bxt_clk_div {
>  
>  /* pre-calculated values for DP linkrates */
>  static const struct bxt_clk_div bxt_dp_clk_val[] = {
> -	{162000, 4, 2, 32, 1677722, 1, 1},
> -	{270000, 4, 1, 27,       0, 0, 1},
> -	{540000, 2, 1, 27,       0, 0, 1},
> -	{216000, 3, 2, 32, 1677722, 1, 1},
> -	{243000, 4, 1, 24, 1258291, 1, 1},
> -	{324000, 4, 1, 32, 1677722, 1, 1},
> -	{432000, 3, 1, 32, 1677722, 1, 1}
> +	{ 162000, 4, 2, 32, 1677722, 1, 1 },
> +	{ 270000, 4, 1, 27,       0, 0, 1 },
> +	{ 540000, 2, 1, 27,       0, 0, 1 },
> +	{ 216000, 3, 2, 32, 1677722, 1, 1 },
> +	{ 243000, 4, 1, 24, 1258291, 1, 1 },
> +	{ 324000, 4, 1, 32, 1677722, 1, 1 },
> +	{ 432000, 3, 1, 32, 1677722, 1, 1 }
>  };
>  
>  static bool

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 04/11] drm/i915: Store the /5 target clock in sturct dpll on vlv/chv

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Unify vlv/chv with earlier platforms so that the sturct dpll::dot
represents the /5 clock frequency (ie. DP symbol rate or HDMI
TMDS rate) rather than the *5 fast clock (/2 of the bitrate).
Makes life a little less confusing to get the same number back
in .dot which we fed into the DPLL algorithm.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll.c | 23 ++++++++++-------------
 1 file changed, 10 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 14f5ffe27d05..693e07a6db80 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -253,12 +253,12 @@ static const struct intel_limit ilk_limits_dual_lvds_100m = {
 
 static const struct intel_limit intel_limits_vlv = {
 	 /*
-	  * These are the data rate limits (measured in fast clocks)
+	  * These are based on the data rate limits (measured in fast clocks)
 	  * since those are the strictest limits we have. The fast
 	  * clock and actual rate limits are more relaxed, so checking
 	  * them would make no difference.
 	  */
-	.dot = { .min = 25000 * 5, .max = 270000 * 5 },
+	.dot = { .min = 25000, .max = 270000 },
 	.vco = { .min = 4000000, .max = 6000000 },
 	.n = { .min = 1, .max = 7 },
 	.m1 = { .min = 2, .max = 3 },
@@ -269,12 +269,12 @@ static const struct intel_limit intel_limits_vlv = {
 
 static const struct intel_limit intel_limits_chv = {
 	/*
-	 * These are the data rate limits (measured in fast clocks)
+	 * These are based on the data rate limits (measured in fast clocks)
 	 * since those are the strictest limits we have.  The fast
 	 * clock and actual rate limits are more relaxed, so checking
 	 * them would make no difference.
 	 */
-	.dot = { .min = 25000 * 5, .max = 540000 * 5},
+	.dot = { .min = 25000, .max = 540000 },
 	.vco = { .min = 4800000, .max = 6480000 },
 	.n = { .min = 1, .max = 1 },
 	.m1 = { .min = 2, .max = 2 },
@@ -340,9 +340,9 @@ int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 	if (WARN_ON(clock->n == 0 || clock->p == 0))
 		return 0;
 	clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
-	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
+	clock->dot = DIV_ROUND_CLOSEST(clock->vco, 5 * clock->p);
 
-	return clock->dot / 5;
+	return clock->dot;
 }
 
 int chv_calc_dpll_params(int refclk, struct dpll *clock)
@@ -353,9 +353,9 @@ int chv_calc_dpll_params(int refclk, struct dpll *clock)
 		return 0;
 	clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),
 					   clock->n << 22);
-	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
+	clock->dot = DIV_ROUND_CLOSEST(clock->vco, 5 * clock->p);
 
-	return clock->dot / 5;
+	return clock->dot;
 }
 
 /*
@@ -658,8 +658,6 @@ vlv_find_best_dpll(const struct intel_limit *limit,
 	int max_n = min(limit->n.max, refclk / 19200);
 	bool found = false;
 
-	target *= 5; /* fast clock */
-
 	memset(best_clock, 0, sizeof(*best_clock));
 
 	/* based on hardware requirement, prefer smaller n to precision */
@@ -672,7 +670,7 @@ vlv_find_best_dpll(const struct intel_limit *limit,
 				for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 					unsigned int ppm;
 
-					clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
+					clock.m2 = DIV_ROUND_CLOSEST(target * 5 * clock.p * clock.n,
 								     refclk * clock.m1);
 
 					vlv_calc_dpll_params(refclk, &clock);
@@ -728,7 +726,6 @@ chv_find_best_dpll(const struct intel_limit *limit,
 	 */
 	clock.n = 1;
 	clock.m1 = 2;
-	target *= 5;	/* fast clock */
 
 	for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 		for (clock.p2 = limit->p2.p2_fast;
@@ -738,7 +735,7 @@ chv_find_best_dpll(const struct intel_limit *limit,
 
 			clock.p = clock.p1 * clock.p2;
 
-			m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,
+			m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, 5 * clock.p * clock.n) << 22,
 						   refclk * clock.m1);
 
 			if (m2 > INT_MAX/clock.m1)
-- 
2.34.1

[Intel-gfx] [PATCH 05/11] drm/i915: Remove bxt m2_frac_en

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Remove the pointless m2_frac_en from bxt_clk_div.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 18 ++++++++----------
 1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index bc26ebacae12..8beec5ec72f8 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2087,7 +2087,6 @@ struct bxt_clk_div {
 	u32 p2;
 	u32 m2_int;
 	u32 m2_frac;
-	bool m2_frac_en;
 	u32 n;
 
 	int vco;
@@ -2095,13 +2094,13 @@ struct bxt_clk_div {
 
 /* pre-calculated values for DP linkrates */
 static const struct bxt_clk_div bxt_dp_clk_val[] = {
-	{ 162000, 4, 2, 32, 1677722, 1, 1 },
-	{ 270000, 4, 1, 27,       0, 0, 1 },
-	{ 540000, 2, 1, 27,       0, 0, 1 },
-	{ 216000, 3, 2, 32, 1677722, 1, 1 },
-	{ 243000, 4, 1, 24, 1258291, 1, 1 },
-	{ 324000, 4, 1, 32, 1677722, 1, 1 },
-	{ 432000, 3, 1, 32, 1677722, 1, 1 }
+	{ 162000, 4, 2, 32, 1677722, 1 },
+	{ 270000, 4, 1, 27,       0, 1 },
+	{ 540000, 2, 1, 27,       0, 1 },
+	{ 216000, 3, 2, 32, 1677722, 1 },
+	{ 243000, 4, 1, 24, 1258291, 1 },
+	{ 324000, 4, 1, 32, 1677722, 1 },
+	{ 432000, 3, 1, 32, 1677722, 1 }
 };
 
 static bool
@@ -2130,7 +2129,6 @@ bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
 	clk_div->n = best_clock.n;
 	clk_div->m2_int = best_clock.m2 >> 22;
 	clk_div->m2_frac = best_clock.m2 & ((1 << 22) - 1);
-	clk_div->m2_frac_en = clk_div->m2_frac != 0;
 
 	clk_div->vco = best_clock.vco;
 
@@ -2203,7 +2201,7 @@ static bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
 	dpll_hw_state->pll1 = PORT_PLL_N(clk_div->n);
 	dpll_hw_state->pll2 = clk_div->m2_frac;
 
-	if (clk_div->m2_frac_en)
+	if (clk_div->m2_frac)
 		dpll_hw_state->pll3 = PORT_PLL_M2_FRAC_ENABLE;
 
 	dpll_hw_state->pll6 = prop_coef | PORT_PLL_INT_COEFF(int_coef);
-- 
2.34.1

Re: [Intel-gfx] [PATCH 05/11] drm/i915: Remove bxt m2_frac_en

[Jani Nikula]

On Tue, 01 Mar 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Remove the pointless m2_frac_en from bxt_clk_div.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 18 ++++++++----------
>  1 file changed, 8 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index bc26ebacae12..8beec5ec72f8 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2087,7 +2087,6 @@ struct bxt_clk_div {
>  	u32 p2;
>  	u32 m2_int;
>  	u32 m2_frac;
> -	bool m2_frac_en;
>  	u32 n;
>  
>  	int vco;
> @@ -2095,13 +2094,13 @@ struct bxt_clk_div {
>  
>  /* pre-calculated values for DP linkrates */
>  static const struct bxt_clk_div bxt_dp_clk_val[] = {
> -	{ 162000, 4, 2, 32, 1677722, 1, 1 },
> -	{ 270000, 4, 1, 27,       0, 0, 1 },
> -	{ 540000, 2, 1, 27,       0, 0, 1 },
> -	{ 216000, 3, 2, 32, 1677722, 1, 1 },
> -	{ 243000, 4, 1, 24, 1258291, 1, 1 },
> -	{ 324000, 4, 1, 32, 1677722, 1, 1 },
> -	{ 432000, 3, 1, 32, 1677722, 1, 1 }
> +	{ 162000, 4, 2, 32, 1677722, 1 },
> +	{ 270000, 4, 1, 27,       0, 1 },
> +	{ 540000, 2, 1, 27,       0, 1 },
> +	{ 216000, 3, 2, 32, 1677722, 1 },
> +	{ 243000, 4, 1, 24, 1258291, 1 },
> +	{ 324000, 4, 1, 32, 1677722, 1 },
> +	{ 432000, 3, 1, 32, 1677722, 1 }
>  };
>  
>  static bool
> @@ -2130,7 +2129,6 @@ bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
>  	clk_div->n = best_clock.n;
>  	clk_div->m2_int = best_clock.m2 >> 22;
>  	clk_div->m2_frac = best_clock.m2 & ((1 << 22) - 1);
> -	clk_div->m2_frac_en = clk_div->m2_frac != 0;
>  
>  	clk_div->vco = best_clock.vco;
>  
> @@ -2203,7 +2201,7 @@ static bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
>  	dpll_hw_state->pll1 = PORT_PLL_N(clk_div->n);
>  	dpll_hw_state->pll2 = clk_div->m2_frac;
>  
> -	if (clk_div->m2_frac_en)
> +	if (clk_div->m2_frac)
>  		dpll_hw_state->pll3 = PORT_PLL_M2_FRAC_ENABLE;
>  
>  	dpll_hw_state->pll6 = prop_coef | PORT_PLL_INT_COEFF(int_coef);

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 06/11] drm/i915: Use designated initializers for bxt_dp_clk_val[]

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use designated initializers to make it clear what is what,
and to decouple us from the specific ordering of the members.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 8beec5ec72f8..899aa42a858f 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2094,13 +2094,13 @@ struct bxt_clk_div {
 
 /* pre-calculated values for DP linkrates */
 static const struct bxt_clk_div bxt_dp_clk_val[] = {
-	{ 162000, 4, 2, 32, 1677722, 1 },
-	{ 270000, 4, 1, 27,       0, 1 },
-	{ 540000, 2, 1, 27,       0, 1 },
-	{ 216000, 3, 2, 32, 1677722, 1 },
-	{ 243000, 4, 1, 24, 1258291, 1 },
-	{ 324000, 4, 1, 32, 1677722, 1 },
-	{ 432000, 3, 1, 32, 1677722, 1 }
+	{ .clock = 162000, .p1 = 4, .p2 = 2, .m2_int = 32, .m2_frac = 1677722, .n = 1, },
+	{ .clock = 270000, .p1 = 4, .p2 = 1, .m2_int = 27, .m2_frac =       0, .n = 1, },
+	{ .clock = 540000, .p1 = 2, .p2 = 1, .m2_int = 27, .m2_frac =       0, .n = 1, },
+	{ .clock = 216000, .p1 = 3, .p2 = 2, .m2_int = 32, .m2_frac = 1677722, .n = 1, },
+	{ .clock = 243000, .p1 = 4, .p2 = 1, .m2_int = 24, .m2_frac = 1258291, .n = 1, },
+	{ .clock = 324000, .p1 = 4, .p2 = 1, .m2_int = 32, .m2_frac = 1677722, .n = 1, },
+	{ .clock = 432000, .p1 = 3, .p2 = 1, .m2_int = 32, .m2_frac = 1677722, .n = 1, },
 };
 
 static bool
-- 
2.34.1

Re: [Intel-gfx] [PATCH 06/11] drm/i915: Use designated initializers for bxt_dp_clk_val[]

[Jani Nikula]

On Tue, 01 Mar 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use designated initializers to make it clear what is what,
> and to decouple us from the specific ordering of the members.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 14 +++++++-------
>  1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 8beec5ec72f8..899aa42a858f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2094,13 +2094,13 @@ struct bxt_clk_div {
>  
>  /* pre-calculated values for DP linkrates */
>  static const struct bxt_clk_div bxt_dp_clk_val[] = {
> -	{ 162000, 4, 2, 32, 1677722, 1 },
> -	{ 270000, 4, 1, 27,       0, 1 },
> -	{ 540000, 2, 1, 27,       0, 1 },
> -	{ 216000, 3, 2, 32, 1677722, 1 },
> -	{ 243000, 4, 1, 24, 1258291, 1 },
> -	{ 324000, 4, 1, 32, 1677722, 1 },
> -	{ 432000, 3, 1, 32, 1677722, 1 }
> +	{ .clock = 162000, .p1 = 4, .p2 = 2, .m2_int = 32, .m2_frac = 1677722, .n = 1, },
> +	{ .clock = 270000, .p1 = 4, .p2 = 1, .m2_int = 27, .m2_frac =       0, .n = 1, },
> +	{ .clock = 540000, .p1 = 2, .p2 = 1, .m2_int = 27, .m2_frac =       0, .n = 1, },
> +	{ .clock = 216000, .p1 = 3, .p2 = 2, .m2_int = 32, .m2_frac = 1677722, .n = 1, },
> +	{ .clock = 243000, .p1 = 4, .p2 = 1, .m2_int = 24, .m2_frac = 1258291, .n = 1, },
> +	{ .clock = 324000, .p1 = 4, .p2 = 1, .m2_int = 32, .m2_frac = 1677722, .n = 1, },
> +	{ .clock = 432000, .p1 = 3, .p2 = 1, .m2_int = 32, .m2_frac = 1677722, .n = 1, },
>  };
>  
>  static bool

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 07/11] drm/i915: Store the m2 divider as a whole in bxt_clk_div

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Get rid of the pointless m2 int vs. frac split in bxt_clk_div
and just store the whole divider as one.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 33 +++++++++++--------
 1 file changed, 19 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 899aa42a858f..4a82e630cbec 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2085,8 +2085,7 @@ struct bxt_clk_div {
 	int clock;
 	u32 p1;
 	u32 p2;
-	u32 m2_int;
-	u32 m2_frac;
+	u32 m2;
 	u32 n;
 
 	int vco;
@@ -2094,13 +2093,20 @@ struct bxt_clk_div {
 
 /* pre-calculated values for DP linkrates */
 static const struct bxt_clk_div bxt_dp_clk_val[] = {
-	{ .clock = 162000, .p1 = 4, .p2 = 2, .m2_int = 32, .m2_frac = 1677722, .n = 1, },
-	{ .clock = 270000, .p1 = 4, .p2 = 1, .m2_int = 27, .m2_frac =       0, .n = 1, },
-	{ .clock = 540000, .p1 = 2, .p2 = 1, .m2_int = 27, .m2_frac =       0, .n = 1, },
-	{ .clock = 216000, .p1 = 3, .p2 = 2, .m2_int = 32, .m2_frac = 1677722, .n = 1, },
-	{ .clock = 243000, .p1 = 4, .p2 = 1, .m2_int = 24, .m2_frac = 1258291, .n = 1, },
-	{ .clock = 324000, .p1 = 4, .p2 = 1, .m2_int = 32, .m2_frac = 1677722, .n = 1, },
-	{ .clock = 432000, .p1 = 3, .p2 = 1, .m2_int = 32, .m2_frac = 1677722, .n = 1, },
+	{ .clock = 162000, .p1 = 4, .p2 = 2, .n = 1,
+	  .m2 = 0x819999a /* .m2_int = 32, m2_frac = 1677722 */ },
+	{ .clock = 270000, .p1 = 4, .p2 = 1, .n = 1,
+	  .m2 = 0x6c00000 /* .m2_int = 27, m2_frac =       0 */ },
+	{ .clock = 540000, .p1 = 2, .p2 = 1, .n = 1,
+	  .m2 = 0x6c00000 /* .m2_int = 27, m2_frac =       0 */ },
+	{ .clock = 216000, .p1 = 3, .p2 = 2, .n = 1,
+	  .m2 = 0x819999a /* .m2_int = 32, m2_frac = 1677722 */ },
+	{ .clock = 243000, .p1 = 4, .p2 = 1, .n = 1,
+	  .m2 = 0x6133333 /* .m2_int = 24, m2_frac = 1258291 */ },
+	{ .clock = 324000, .p1 = 4, .p2 = 1, .n = 1,
+	  .m2 = 0x819999a /* .m2_int = 32, m2_frac = 1677722 */ },
+	{ .clock = 432000, .p1 = 3, .p2 = 1, .n = 1,
+	  .m2 = 0x819999a /* .m2_int = 32, m2_frac = 1677722 */ },
 };
 
 static bool
@@ -2127,8 +2133,7 @@ bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
 	clk_div->p2 = best_clock.p2;
 	drm_WARN_ON(&i915->drm, best_clock.m1 != 2);
 	clk_div->n = best_clock.n;
-	clk_div->m2_int = best_clock.m2 >> 22;
-	clk_div->m2_frac = best_clock.m2 & ((1 << 22) - 1);
+	clk_div->m2 = best_clock.m2;
 
 	clk_div->vco = best_clock.vco;
 
@@ -2197,11 +2202,11 @@ static bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
 		lanestagger = 0x02;
 
 	dpll_hw_state->ebb0 = PORT_PLL_P1(clk_div->p1) | PORT_PLL_P2(clk_div->p2);
-	dpll_hw_state->pll0 = clk_div->m2_int;
+	dpll_hw_state->pll0 = clk_div->m2 >> 22;
 	dpll_hw_state->pll1 = PORT_PLL_N(clk_div->n);
-	dpll_hw_state->pll2 = clk_div->m2_frac;
+	dpll_hw_state->pll2 = clk_div->m2 & 0x3fffff;
 
-	if (clk_div->m2_frac)
+	if (clk_div->m2 & 0x3fffff)
 		dpll_hw_state->pll3 = PORT_PLL_M2_FRAC_ENABLE;
 
 	dpll_hw_state->pll6 = prop_coef | PORT_PLL_INT_COEFF(int_coef);
-- 
2.34.1

Re: [Intel-gfx] [PATCH 07/11] drm/i915: Store the m2 divider as a whole in bxt_clk_div

[Jani Nikula]

On Tue, 01 Mar 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Get rid of the pointless m2 int vs. frac split in bxt_clk_div
> and just store the whole divider as one.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 33 +++++++++++--------
>  1 file changed, 19 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 899aa42a858f..4a82e630cbec 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2085,8 +2085,7 @@ struct bxt_clk_div {
>  	int clock;
>  	u32 p1;
>  	u32 p2;
> -	u32 m2_int;
> -	u32 m2_frac;
> +	u32 m2;
>  	u32 n;
>  
>  	int vco;
> @@ -2094,13 +2093,20 @@ struct bxt_clk_div {
>  
>  /* pre-calculated values for DP linkrates */
>  static const struct bxt_clk_div bxt_dp_clk_val[] = {
> -	{ .clock = 162000, .p1 = 4, .p2 = 2, .m2_int = 32, .m2_frac = 1677722, .n = 1, },
> -	{ .clock = 270000, .p1 = 4, .p2 = 1, .m2_int = 27, .m2_frac =       0, .n = 1, },
> -	{ .clock = 540000, .p1 = 2, .p2 = 1, .m2_int = 27, .m2_frac =       0, .n = 1, },
> -	{ .clock = 216000, .p1 = 3, .p2 = 2, .m2_int = 32, .m2_frac = 1677722, .n = 1, },
> -	{ .clock = 243000, .p1 = 4, .p2 = 1, .m2_int = 24, .m2_frac = 1258291, .n = 1, },
> -	{ .clock = 324000, .p1 = 4, .p2 = 1, .m2_int = 32, .m2_frac = 1677722, .n = 1, },
> -	{ .clock = 432000, .p1 = 3, .p2 = 1, .m2_int = 32, .m2_frac = 1677722, .n = 1, },
> +	{ .clock = 162000, .p1 = 4, .p2 = 2, .n = 1,
> +	  .m2 = 0x819999a /* .m2_int = 32, m2_frac = 1677722 */ },
> +	{ .clock = 270000, .p1 = 4, .p2 = 1, .n = 1,
> +	  .m2 = 0x6c00000 /* .m2_int = 27, m2_frac =       0 */ },
> +	{ .clock = 540000, .p1 = 2, .p2 = 1, .n = 1,
> +	  .m2 = 0x6c00000 /* .m2_int = 27, m2_frac =       0 */ },
> +	{ .clock = 216000, .p1 = 3, .p2 = 2, .n = 1,
> +	  .m2 = 0x819999a /* .m2_int = 32, m2_frac = 1677722 */ },
> +	{ .clock = 243000, .p1 = 4, .p2 = 1, .n = 1,
> +	  .m2 = 0x6133333 /* .m2_int = 24, m2_frac = 1258291 */ },
> +	{ .clock = 324000, .p1 = 4, .p2 = 1, .n = 1,
> +	  .m2 = 0x819999a /* .m2_int = 32, m2_frac = 1677722 */ },
> +	{ .clock = 432000, .p1 = 3, .p2 = 1, .n = 1,
> +	  .m2 = 0x819999a /* .m2_int = 32, m2_frac = 1677722 */ },

Mmh, I guess here I would've added some macros to construct m2 from
m2_int and m2_frac.

#define M2_INT_SHIFT	22
#define M2_FRAC_MASK	0x3fffff

#define M2(int, frac) ((int) << M2_INT_SHIFT) | (frac))

And you get this:

	{ .clock = 432000, .p1 = 3, .p2 = 1, .m2 = M2(32, 1677722), .n = 1, },

No need to retain the int/frac in comments. Can also use
REG_FIELD_PREP/GET if you want to over-engineer...

>  };
>  
>  static bool
> @@ -2127,8 +2133,7 @@ bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
>  	clk_div->p2 = best_clock.p2;
>  	drm_WARN_ON(&i915->drm, best_clock.m1 != 2);
>  	clk_div->n = best_clock.n;
> -	clk_div->m2_int = best_clock.m2 >> 22;
> -	clk_div->m2_frac = best_clock.m2 & ((1 << 22) - 1);
> +	clk_div->m2 = best_clock.m2;
>  
>  	clk_div->vco = best_clock.vco;
>  
> @@ -2197,11 +2202,11 @@ static bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
>  		lanestagger = 0x02;
>  
>  	dpll_hw_state->ebb0 = PORT_PLL_P1(clk_div->p1) | PORT_PLL_P2(clk_div->p2);
> -	dpll_hw_state->pll0 = clk_div->m2_int;
> +	dpll_hw_state->pll0 = clk_div->m2 >> 22;
>  	dpll_hw_state->pll1 = PORT_PLL_N(clk_div->n);
> -	dpll_hw_state->pll2 = clk_div->m2_frac;
> +	dpll_hw_state->pll2 = clk_div->m2 & 0x3fffff;
>  
> -	if (clk_div->m2_frac)
> +	if (clk_div->m2 & 0x3fffff)
>  		dpll_hw_state->pll3 = PORT_PLL_M2_FRAC_ENABLE;

Also could reuse the shift and mask macros here.

Other than that, the direction seems good.

BR,
Jani.


>  
>  	dpll_hw_state->pll6 = prop_coef | PORT_PLL_INT_COEFF(int_coef);

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 07/11] drm/i915: Store the m2 divider as a whole in bxt_clk_div

[Ville Syrjälä]

On Fri, Mar 04, 2022 at 01:36:27PM +0200, Jani Nikula wrote:
> On Tue, 01 Mar 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Get rid of the pointless m2 int vs. frac split in bxt_clk_div
> > and just store the whole divider as one.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 33 +++++++++++--------
> >  1 file changed, 19 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index 899aa42a858f..4a82e630cbec 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -2085,8 +2085,7 @@ struct bxt_clk_div {
> >  	int clock;
> >  	u32 p1;
> >  	u32 p2;
> > -	u32 m2_int;
> > -	u32 m2_frac;
> > +	u32 m2;
> >  	u32 n;
> >  
> >  	int vco;
> > @@ -2094,13 +2093,20 @@ struct bxt_clk_div {
> >  
> >  /* pre-calculated values for DP linkrates */
> >  static const struct bxt_clk_div bxt_dp_clk_val[] = {
> > -	{ .clock = 162000, .p1 = 4, .p2 = 2, .m2_int = 32, .m2_frac = 1677722, .n = 1, },
> > -	{ .clock = 270000, .p1 = 4, .p2 = 1, .m2_int = 27, .m2_frac =       0, .n = 1, },
> > -	{ .clock = 540000, .p1 = 2, .p2 = 1, .m2_int = 27, .m2_frac =       0, .n = 1, },
> > -	{ .clock = 216000, .p1 = 3, .p2 = 2, .m2_int = 32, .m2_frac = 1677722, .n = 1, },
> > -	{ .clock = 243000, .p1 = 4, .p2 = 1, .m2_int = 24, .m2_frac = 1258291, .n = 1, },
> > -	{ .clock = 324000, .p1 = 4, .p2 = 1, .m2_int = 32, .m2_frac = 1677722, .n = 1, },
> > -	{ .clock = 432000, .p1 = 3, .p2 = 1, .m2_int = 32, .m2_frac = 1677722, .n = 1, },
> > +	{ .clock = 162000, .p1 = 4, .p2 = 2, .n = 1,
> > +	  .m2 = 0x819999a /* .m2_int = 32, m2_frac = 1677722 */ },
> > +	{ .clock = 270000, .p1 = 4, .p2 = 1, .n = 1,
> > +	  .m2 = 0x6c00000 /* .m2_int = 27, m2_frac =       0 */ },
> > +	{ .clock = 540000, .p1 = 2, .p2 = 1, .n = 1,
> > +	  .m2 = 0x6c00000 /* .m2_int = 27, m2_frac =       0 */ },
> > +	{ .clock = 216000, .p1 = 3, .p2 = 2, .n = 1,
> > +	  .m2 = 0x819999a /* .m2_int = 32, m2_frac = 1677722 */ },
> > +	{ .clock = 243000, .p1 = 4, .p2 = 1, .n = 1,
> > +	  .m2 = 0x6133333 /* .m2_int = 24, m2_frac = 1258291 */ },
> > +	{ .clock = 324000, .p1 = 4, .p2 = 1, .n = 1,
> > +	  .m2 = 0x819999a /* .m2_int = 32, m2_frac = 1677722 */ },
> > +	{ .clock = 432000, .p1 = 3, .p2 = 1, .n = 1,
> > +	  .m2 = 0x819999a /* .m2_int = 32, m2_frac = 1677722 */ },
> 
> Mmh, I guess here I would've added some macros to construct m2 from
> m2_int and m2_frac.
> 
> #define M2_INT_SHIFT	22
> #define M2_FRAC_MASK	0x3fffff
> 
> #define M2(int, frac) ((int) << M2_INT_SHIFT) | (frac))

I don't think this weird decimal representation of m2 is useful
for anything actually. I just copy-pasted it from the chv side
for consistency. Should just probably nuke it for both.

I guess the sensible thing would be to just write the full m2 in
decimal in the comment, eg. ".m2 = 0x819999a /* 32.4 */"

Hmm. Or we could even go a bit further and just do:
.m2 = 32.4 * (1 << 22) + .5
and hope the compiler evaluates it at compile time instead
of getting upset about the floats.

> 
> And you get this:
> 
> 	{ .clock = 432000, .p1 = 3, .p2 = 1, .m2 = M2(32, 1677722), .n = 1, },
> 
> No need to retain the int/frac in comments. Can also use
> REG_FIELD_PREP/GET if you want to over-engineer...
> 
> >  };
> >  
> >  static bool
> > @@ -2127,8 +2133,7 @@ bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
> >  	clk_div->p2 = best_clock.p2;
> >  	drm_WARN_ON(&i915->drm, best_clock.m1 != 2);
> >  	clk_div->n = best_clock.n;
> > -	clk_div->m2_int = best_clock.m2 >> 22;
> > -	clk_div->m2_frac = best_clock.m2 & ((1 << 22) - 1);
> > +	clk_div->m2 = best_clock.m2;
> >  
> >  	clk_div->vco = best_clock.vco;
> >  
> > @@ -2197,11 +2202,11 @@ static bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
> >  		lanestagger = 0x02;
> >  
> >  	dpll_hw_state->ebb0 = PORT_PLL_P1(clk_div->p1) | PORT_PLL_P2(clk_div->p2);
> > -	dpll_hw_state->pll0 = clk_div->m2_int;
> > +	dpll_hw_state->pll0 = clk_div->m2 >> 22;
> >  	dpll_hw_state->pll1 = PORT_PLL_N(clk_div->n);
> > -	dpll_hw_state->pll2 = clk_div->m2_frac;
> > +	dpll_hw_state->pll2 = clk_div->m2 & 0x3fffff;

I should probably use the REG_FIELD_PREP() macros consistently here.

> >  
> > -	if (clk_div->m2_frac)
> > +	if (clk_div->m2 & 0x3fffff)
> >  		dpll_hw_state->pll3 = PORT_PLL_M2_FRAC_ENABLE;

But here such usage would imply tht the reg value == m2
fractional part. That does happen to be the case here but 
not sure I want to write the code in a way that assumes that.

> 
> Also could reuse the shift and mask macros here.
> 
> Other than that, the direction seems good.
> 
> BR,
> Jani.
> 
> 
> >  
> >  	dpll_hw_state->pll6 = prop_coef | PORT_PLL_INT_COEFF(int_coef);
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center

-- 
Ville Syrjälä
Intel

[Intel-gfx] [PATCH 08/11] drm/i915: Replace bxt_clk_div with struct dpll

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

bxt_clk_div is basically the same as struct dpll. Just use the latter.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 50 ++++++-------------
 1 file changed, 16 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 4a82e630cbec..58e9d5960bc6 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2080,75 +2080,57 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
 	return ret;
 }
 
-/* bxt clock parameters */
-struct bxt_clk_div {
-	int clock;
-	u32 p1;
-	u32 p2;
-	u32 m2;
-	u32 n;
-
-	int vco;
-};
-
 /* pre-calculated values for DP linkrates */
-static const struct bxt_clk_div bxt_dp_clk_val[] = {
-	{ .clock = 162000, .p1 = 4, .p2 = 2, .n = 1,
+static const struct dpll bxt_dp_clk_val[] = {
+	{ .dot = 162000, .p1 = 4, .p2 = 2, .n = 1,
 	  .m2 = 0x819999a /* .m2_int = 32, m2_frac = 1677722 */ },
-	{ .clock = 270000, .p1 = 4, .p2 = 1, .n = 1,
+	{ .dot = 270000, .p1 = 4, .p2 = 1, .n = 1,
 	  .m2 = 0x6c00000 /* .m2_int = 27, m2_frac =       0 */ },
-	{ .clock = 540000, .p1 = 2, .p2 = 1, .n = 1,
+	{ .dot = 540000, .p1 = 2, .p2 = 1, .n = 1,
 	  .m2 = 0x6c00000 /* .m2_int = 27, m2_frac =       0 */ },
-	{ .clock = 216000, .p1 = 3, .p2 = 2, .n = 1,
+	{ .dot = 216000, .p1 = 3, .p2 = 2, .n = 1,
 	  .m2 = 0x819999a /* .m2_int = 32, m2_frac = 1677722 */ },
-	{ .clock = 243000, .p1 = 4, .p2 = 1, .n = 1,
+	{ .dot = 243000, .p1 = 4, .p2 = 1, .n = 1,
 	  .m2 = 0x6133333 /* .m2_int = 24, m2_frac = 1258291 */ },
-	{ .clock = 324000, .p1 = 4, .p2 = 1, .n = 1,
+	{ .dot = 324000, .p1 = 4, .p2 = 1, .n = 1,
 	  .m2 = 0x819999a /* .m2_int = 32, m2_frac = 1677722 */ },
-	{ .clock = 432000, .p1 = 3, .p2 = 1, .n = 1,
+	{ .dot = 432000, .p1 = 3, .p2 = 1, .n = 1,
 	  .m2 = 0x819999a /* .m2_int = 32, m2_frac = 1677722 */ },
 };
 
 static bool
 bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
-			  struct bxt_clk_div *clk_div)
+			  struct dpll *clk_div)
 {
 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct dpll best_clock;
 
 	/* Calculate HDMI div */
 	/*
 	 * FIXME: tie the following calculation into
 	 * i9xx_crtc_compute_clock
 	 */
-	if (!bxt_find_best_dpll(crtc_state, &best_clock)) {
+	if (!bxt_find_best_dpll(crtc_state, clk_div)) {
 		drm_dbg(&i915->drm, "no PLL dividers found for clock %d pipe %c\n",
 			crtc_state->port_clock,
 			pipe_name(crtc->pipe));
 		return false;
 	}
 
-	clk_div->p1 = best_clock.p1;
-	clk_div->p2 = best_clock.p2;
-	drm_WARN_ON(&i915->drm, best_clock.m1 != 2);
-	clk_div->n = best_clock.n;
-	clk_div->m2 = best_clock.m2;
-
-	clk_div->vco = best_clock.vco;
+	drm_WARN_ON(&i915->drm, clk_div->m1 != 2);
 
 	return true;
 }
 
 static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state,
-				    struct bxt_clk_div *clk_div)
+				    struct dpll *clk_div)
 {
 	int clock = crtc_state->port_clock;
 	int i;
 
 	*clk_div = bxt_dp_clk_val[0];
 	for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
-		if (bxt_dp_clk_val[i].clock == clock) {
+		if (bxt_dp_clk_val[i].dot == clock) {
 			*clk_div = bxt_dp_clk_val[i];
 			break;
 		}
@@ -2158,7 +2140,7 @@ static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state,
 }
 
 static bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
-				      const struct bxt_clk_div *clk_div)
+				      const struct dpll *clk_div)
 {
 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 	struct intel_dpll_hw_state *dpll_hw_state = &crtc_state->dpll_hw_state;
@@ -2230,7 +2212,7 @@ static bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
 static bool
 bxt_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
 {
-	struct bxt_clk_div clk_div = {};
+	struct dpll clk_div = {};
 
 	bxt_ddi_dp_pll_dividers(crtc_state, &clk_div);
 
@@ -2240,7 +2222,7 @@ bxt_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
 static bool
 bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
 {
-	struct bxt_clk_div clk_div = {};
+	struct dpll clk_div = {};
 
 	bxt_ddi_hdmi_pll_dividers(crtc_state, &clk_div);
 
-- 
2.34.1

Re: [Intel-gfx] [PATCH 08/11] drm/i915: Replace bxt_clk_div with struct dpll

[Jani Nikula]

On Tue, 01 Mar 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> bxt_clk_div is basically the same as struct dpll. Just use the latter.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 50 ++++++-------------
>  1 file changed, 16 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 4a82e630cbec..58e9d5960bc6 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2080,75 +2080,57 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
>  	return ret;
>  }
>  
> -/* bxt clock parameters */
> -struct bxt_clk_div {
> -	int clock;
> -	u32 p1;
> -	u32 p2;
> -	u32 m2;
> -	u32 n;
> -
> -	int vco;
> -};
> -
>  /* pre-calculated values for DP linkrates */
> -static const struct bxt_clk_div bxt_dp_clk_val[] = {
> -	{ .clock = 162000, .p1 = 4, .p2 = 2, .n = 1,
> +static const struct dpll bxt_dp_clk_val[] = {
> +	{ .dot = 162000, .p1 = 4, .p2 = 2, .n = 1,
>  	  .m2 = 0x819999a /* .m2_int = 32, m2_frac = 1677722 */ },
> -	{ .clock = 270000, .p1 = 4, .p2 = 1, .n = 1,
> +	{ .dot = 270000, .p1 = 4, .p2 = 1, .n = 1,
>  	  .m2 = 0x6c00000 /* .m2_int = 27, m2_frac =       0 */ },
> -	{ .clock = 540000, .p1 = 2, .p2 = 1, .n = 1,
> +	{ .dot = 540000, .p1 = 2, .p2 = 1, .n = 1,
>  	  .m2 = 0x6c00000 /* .m2_int = 27, m2_frac =       0 */ },
> -	{ .clock = 216000, .p1 = 3, .p2 = 2, .n = 1,
> +	{ .dot = 216000, .p1 = 3, .p2 = 2, .n = 1,
>  	  .m2 = 0x819999a /* .m2_int = 32, m2_frac = 1677722 */ },
> -	{ .clock = 243000, .p1 = 4, .p2 = 1, .n = 1,
> +	{ .dot = 243000, .p1 = 4, .p2 = 1, .n = 1,
>  	  .m2 = 0x6133333 /* .m2_int = 24, m2_frac = 1258291 */ },
> -	{ .clock = 324000, .p1 = 4, .p2 = 1, .n = 1,
> +	{ .dot = 324000, .p1 = 4, .p2 = 1, .n = 1,
>  	  .m2 = 0x819999a /* .m2_int = 32, m2_frac = 1677722 */ },
> -	{ .clock = 432000, .p1 = 3, .p2 = 1, .n = 1,
> +	{ .dot = 432000, .p1 = 3, .p2 = 1, .n = 1,
>  	  .m2 = 0x819999a /* .m2_int = 32, m2_frac = 1677722 */ },
>  };
>  
>  static bool
>  bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
> -			  struct bxt_clk_div *clk_div)
> +			  struct dpll *clk_div)
>  {
>  	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -	struct dpll best_clock;
>  
>  	/* Calculate HDMI div */
>  	/*
>  	 * FIXME: tie the following calculation into
>  	 * i9xx_crtc_compute_clock
>  	 */
> -	if (!bxt_find_best_dpll(crtc_state, &best_clock)) {
> +	if (!bxt_find_best_dpll(crtc_state, clk_div)) {
>  		drm_dbg(&i915->drm, "no PLL dividers found for clock %d pipe %c\n",
>  			crtc_state->port_clock,
>  			pipe_name(crtc->pipe));
>  		return false;
>  	}
>  
> -	clk_div->p1 = best_clock.p1;
> -	clk_div->p2 = best_clock.p2;
> -	drm_WARN_ON(&i915->drm, best_clock.m1 != 2);
> -	clk_div->n = best_clock.n;
> -	clk_div->m2 = best_clock.m2;
> -
> -	clk_div->vco = best_clock.vco;
> +	drm_WARN_ON(&i915->drm, clk_div->m1 != 2);
>  
>  	return true;
>  }
>  
>  static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state,
> -				    struct bxt_clk_div *clk_div)
> +				    struct dpll *clk_div)
>  {
>  	int clock = crtc_state->port_clock;
>  	int i;
>  
>  	*clk_div = bxt_dp_clk_val[0];
>  	for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
> -		if (bxt_dp_clk_val[i].clock == clock) {
> +		if (bxt_dp_clk_val[i].dot == clock) {
>  			*clk_div = bxt_dp_clk_val[i];
>  			break;
>  		}
> @@ -2158,7 +2140,7 @@ static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state,
>  }
>  
>  static bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
> -				      const struct bxt_clk_div *clk_div)
> +				      const struct dpll *clk_div)
>  {
>  	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
>  	struct intel_dpll_hw_state *dpll_hw_state = &crtc_state->dpll_hw_state;
> @@ -2230,7 +2212,7 @@ static bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
>  static bool
>  bxt_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
>  {
> -	struct bxt_clk_div clk_div = {};
> +	struct dpll clk_div = {};
>  
>  	bxt_ddi_dp_pll_dividers(crtc_state, &clk_div);
>  
> @@ -2240,7 +2222,7 @@ bxt_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
>  static bool
>  bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
>  {
> -	struct bxt_clk_div clk_div = {};
> +	struct dpll clk_div = {};
>  
>  	bxt_ddi_hdmi_pll_dividers(crtc_state, &clk_div);

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 09/11] drm/i915: Replace hand rolled bxt vco calculation with chv_calc_dpll_params()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use chv_calc_dpll_params() to calculate the BXT DP DPLL VCO
frequency.

We need to add the m1 divider into bxt_dp_clk_val[] for this to work.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 23 +++++++++++--------
 1 file changed, 13 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 58e9d5960bc6..5e39378ba1d0 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2082,19 +2082,19 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
 
 /* pre-calculated values for DP linkrates */
 static const struct dpll bxt_dp_clk_val[] = {
-	{ .dot = 162000, .p1 = 4, .p2 = 2, .n = 1,
+	{ .dot = 162000, .p1 = 4, .p2 = 2, .n = 1, .m1 = 2,
 	  .m2 = 0x819999a /* .m2_int = 32, m2_frac = 1677722 */ },
-	{ .dot = 270000, .p1 = 4, .p2 = 1, .n = 1,
+	{ .dot = 270000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2,
 	  .m2 = 0x6c00000 /* .m2_int = 27, m2_frac =       0 */ },
-	{ .dot = 540000, .p1 = 2, .p2 = 1, .n = 1,
+	{ .dot = 540000, .p1 = 2, .p2 = 1, .n = 1, .m1 = 2,
 	  .m2 = 0x6c00000 /* .m2_int = 27, m2_frac =       0 */ },
-	{ .dot = 216000, .p1 = 3, .p2 = 2, .n = 1,
+	{ .dot = 216000, .p1 = 3, .p2 = 2, .n = 1, .m1 = 2,
 	  .m2 = 0x819999a /* .m2_int = 32, m2_frac = 1677722 */ },
-	{ .dot = 243000, .p1 = 4, .p2 = 1, .n = 1,
+	{ .dot = 243000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2,
 	  .m2 = 0x6133333 /* .m2_int = 24, m2_frac = 1258291 */ },
-	{ .dot = 324000, .p1 = 4, .p2 = 1, .n = 1,
+	{ .dot = 324000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2,
 	  .m2 = 0x819999a /* .m2_int = 32, m2_frac = 1677722 */ },
-	{ .dot = 432000, .p1 = 3, .p2 = 1, .n = 1,
+	{ .dot = 432000, .p1 = 3, .p2 = 1, .n = 1, .m1 = 2,
 	  .m2 = 0x819999a /* .m2_int = 32, m2_frac = 1677722 */ },
 };
 
@@ -2125,18 +2125,21 @@ bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
 static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state,
 				    struct dpll *clk_div)
 {
-	int clock = crtc_state->port_clock;
+	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 	int i;
 
 	*clk_div = bxt_dp_clk_val[0];
 	for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
-		if (bxt_dp_clk_val[i].dot == clock) {
+		if (crtc_state->port_clock == bxt_dp_clk_val[i].dot) {
 			*clk_div = bxt_dp_clk_val[i];
 			break;
 		}
 	}
 
-	clk_div->vco = clock * 10 / 2 * clk_div->p1 * clk_div->p2;
+	drm_WARN_ON(&i915->drm,
+		    chv_calc_dpll_params(i915->dpll.ref_clks.nssc, clk_div));
+	drm_WARN_ON(&i915->drm,
+		    clk_div->dot != crtc_state->port_clock);
 }
 
 static bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
-- 
2.34.1

[Intel-gfx] [PATCH v2 09/11] drm/i915: Replace hand rolled bxt vco calculation with chv_calc_dpll_params()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use chv_calc_dpll_params() to calculate the BXT DP DPLL VCO
frequency.

We need to add the m1 divider into bxt_dp_clk_val[] for this to work.

v2: Make the WARN_ON() sensible

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 23 +++++++++++--------
 1 file changed, 13 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 58e9d5960bc6..a5fc63401f49 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2082,19 +2082,19 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
 
 /* pre-calculated values for DP linkrates */
 static const struct dpll bxt_dp_clk_val[] = {
-	{ .dot = 162000, .p1 = 4, .p2 = 2, .n = 1,
+	{ .dot = 162000, .p1 = 4, .p2 = 2, .n = 1, .m1 = 2,
 	  .m2 = 0x819999a /* .m2_int = 32, m2_frac = 1677722 */ },
-	{ .dot = 270000, .p1 = 4, .p2 = 1, .n = 1,
+	{ .dot = 270000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2,
 	  .m2 = 0x6c00000 /* .m2_int = 27, m2_frac =       0 */ },
-	{ .dot = 540000, .p1 = 2, .p2 = 1, .n = 1,
+	{ .dot = 540000, .p1 = 2, .p2 = 1, .n = 1, .m1 = 2,
 	  .m2 = 0x6c00000 /* .m2_int = 27, m2_frac =       0 */ },
-	{ .dot = 216000, .p1 = 3, .p2 = 2, .n = 1,
+	{ .dot = 216000, .p1 = 3, .p2 = 2, .n = 1, .m1 = 2,
 	  .m2 = 0x819999a /* .m2_int = 32, m2_frac = 1677722 */ },
-	{ .dot = 243000, .p1 = 4, .p2 = 1, .n = 1,
+	{ .dot = 243000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2,
 	  .m2 = 0x6133333 /* .m2_int = 24, m2_frac = 1258291 */ },
-	{ .dot = 324000, .p1 = 4, .p2 = 1, .n = 1,
+	{ .dot = 324000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2,
 	  .m2 = 0x819999a /* .m2_int = 32, m2_frac = 1677722 */ },
-	{ .dot = 432000, .p1 = 3, .p2 = 1, .n = 1,
+	{ .dot = 432000, .p1 = 3, .p2 = 1, .n = 1, .m1 = 2,
 	  .m2 = 0x819999a /* .m2_int = 32, m2_frac = 1677722 */ },
 };
 
@@ -2125,18 +2125,21 @@ bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
 static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state,
 				    struct dpll *clk_div)
 {
-	int clock = crtc_state->port_clock;
+	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 	int i;
 
 	*clk_div = bxt_dp_clk_val[0];
 	for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
-		if (bxt_dp_clk_val[i].dot == clock) {
+		if (crtc_state->port_clock == bxt_dp_clk_val[i].dot) {
 			*clk_div = bxt_dp_clk_val[i];
 			break;
 		}
 	}
 
-	clk_div->vco = clock * 10 / 2 * clk_div->p1 * clk_div->p2;
+	chv_calc_dpll_params(i915->dpll.ref_clks.nssc, clk_div);
+
+	drm_WARN_ON(&i915->drm, clk_div->vco == 0 ||
+		    clk_div->dot != crtc_state->port_clock);
 }
 
 static bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
-- 
2.34.1

[Intel-gfx] [PATCH 10/11] drm/i915: Populate bxt/glk DPLL clock limits a bit more

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Set the bxt/glk DPLL min dotclock to 25MHz (HDMI minimum)
and the max to 594 MHz (HDMI max). The supported DP frequencies
(162MHz-540MHz) fit within the same range.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 693e07a6db80..fee3e2e3a4b7 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -284,8 +284,7 @@ static const struct intel_limit intel_limits_chv = {
 };
 
 static const struct intel_limit intel_limits_bxt = {
-	/* FIXME: find real dot limits */
-	.dot = { .min = 0, .max = INT_MAX },
+	.dot = { .min = 25000, .max = 594000 },
 	.vco = { .min = 4800000, .max = 6700000 },
 	.n = { .min = 1, .max = 1 },
 	.m1 = { .min = 2, .max = 2 },
-- 
2.34.1

[Intel-gfx] [PATCH 11/11] drm/i915: Remove struct dp_link_dpll

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

struct dp_link_dpll is a pointless wrapper around struct dpll.
Just store the desired link rate into struct dpll::dot and
we're done.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/g4x_dp.c | 47 ++++++++++-----------------
 1 file changed, 18 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
index f67bbaaad8e0..559ce0fefaed 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -22,58 +22,47 @@
 #include "intel_pps.h"
 #include "vlv_sideband.h"
 
-struct dp_link_dpll {
-	int clock;
-	struct dpll dpll;
+static const struct dpll g4x_dpll[] = {
+	{ .dot = 162000, .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8, },
+	{ .dot = 270000, .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2, },
 };
 
-static const struct dp_link_dpll g4x_dpll[] = {
-	{ 162000,
-		{ .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
-	{ 270000,
-		{ .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
+static const struct dpll pch_dpll[] = {
+	{ .dot = 162000, .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9, },
+	{ .dot = 270000, .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8, },
 };
 
-static const struct dp_link_dpll pch_dpll[] = {
-	{ 162000,
-		{ .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
-	{ 270000,
-		{ .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
-};
-
-static const struct dp_link_dpll vlv_dpll[] = {
-	{ 162000,
-		{ .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
-	{ 270000,
-		{ .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
+static const struct dpll vlv_dpll[] = {
+	{ .dot = 162000, .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81, },
+	{ .dot = 270000, .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27, },
 };
 
 /*
  * CHV supports eDP 1.4 that have  more link rates.
  * Below only provides the fixed rate but exclude variable rate.
  */
-static const struct dp_link_dpll chv_dpll[] = {
+static const struct dpll chv_dpll[] = {
 	/*
 	 * CHV requires to program fractional division for m2.
 	 * m2 is stored in fixed point format using formula below
 	 * (m2_int << 22) | m2_fraction
 	 */
-	{ 162000,	/* m2_int = 32, m2_fraction = 1677722 */
-		{ .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
-	{ 270000,	/* m2_int = 27, m2_fraction = 0 */
-		{ .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
+	{ .dot = 162000, .p1 = 4, .p2 = 2, .n = 1, .m1 = 2,
+	  .m2 = 0x819999a /* m2_int = 32, m2_frac = 1677722 */ },
+	{ .dot = 270000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2,
+	  .m2 = 0x6c00000 /* m2_int = 27, m2_frac =       0 */ },
 };
 
 const struct dpll *vlv_get_dpll(struct drm_i915_private *i915)
 {
-	return IS_CHERRYVIEW(i915) ? &chv_dpll[0].dpll : &vlv_dpll[0].dpll;
+	return IS_CHERRYVIEW(i915) ? &chv_dpll[0] : &vlv_dpll[0];
 }
 
 void g4x_dp_set_clock(struct intel_encoder *encoder,
 		      struct intel_crtc_state *pipe_config)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	const struct dp_link_dpll *divisor = NULL;
+	const struct dpll *divisor = NULL;
 	int i, count = 0;
 
 	if (IS_G4X(dev_priv)) {
@@ -92,8 +81,8 @@ void g4x_dp_set_clock(struct intel_encoder *encoder,
 
 	if (divisor && count) {
 		for (i = 0; i < count; i++) {
-			if (pipe_config->port_clock == divisor[i].clock) {
-				pipe_config->dpll = divisor[i].dpll;
+			if (pipe_config->port_clock == divisor[i].dot) {
+				pipe_config->dpll = divisor[i];
 				pipe_config->clock_set = true;
 				break;
 			}
-- 
2.34.1

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Clean up some dpll stuff (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 6710 bytes --]

== Series Details ==

Series: drm/i915: Clean up some dpll stuff (rev2)
URL   : https://patchwork.freedesktop.org/series/100899/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11306 -> Patchwork_22450
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/index.html

Participating hosts (52 -> 43)
------------------------------

  Additional (1): fi-icl-u2 
  Missing    (10): fi-kbl-soraka shard-tglu fi-hsw-4200u fi-bsw-cyan bat-adlp-4 fi-ctg-p8600 fi-pnv-d510 shard-rkl shard-dg1 fi-bdw-samus 

Known issues
------------

  Here are the changes found in Patchwork_22450 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@semaphore:
    - fi-hsw-4770:        NOTRUN -> [SKIP][1] ([fdo#109271] / [fdo#109315]) +17 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/fi-hsw-4770/igt@amdgpu/amd_basic@semaphore.html

  * igt@amdgpu/amd_cs_nop@fork-gfx0:
    - fi-icl-u2:          NOTRUN -> [SKIP][2] ([fdo#109315]) +17 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/fi-icl-u2/igt@amdgpu/amd_cs_nop@fork-gfx0.html

  * igt@gem_huc_copy@huc-copy:
    - fi-icl-u2:          NOTRUN -> [SKIP][3] ([i915#2190])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/fi-icl-u2/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - fi-icl-u2:          NOTRUN -> [SKIP][4] ([i915#4613]) +3 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/fi-icl-u2/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_lmem_swapping@random-engines:
    - fi-ivb-3770:        NOTRUN -> [SKIP][5] ([fdo#109271]) +35 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/fi-ivb-3770/igt@gem_lmem_swapping@random-engines.html

  * igt@i915_selftest@live@execlists:
    - fi-icl-u2:          NOTRUN -> [DMESG-WARN][6] ([i915#2867])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/fi-icl-u2/igt@i915_selftest@live@execlists.html

  * igt@kms_chamelium@dp-hpd-fast:
    - fi-ivb-3770:        NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/fi-ivb-3770/igt@kms_chamelium@dp-hpd-fast.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-icl-u2:          NOTRUN -> [SKIP][8] ([fdo#111827]) +8 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - fi-icl-u2:          NOTRUN -> [SKIP][9] ([fdo#109278]) +2 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_force_connector_basic@force-load-detect:
    - fi-icl-u2:          NOTRUN -> [SKIP][10] ([fdo#109285])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/fi-icl-u2/igt@kms_force_connector_basic@force-load-detect.html

  * igt@prime_vgem@basic-userptr:
    - fi-icl-u2:          NOTRUN -> [SKIP][11] ([i915#3301])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/fi-icl-u2/igt@prime_vgem@basic-userptr.html

  
#### Possible fixes ####

  * igt@core_hotunplug@unbind-rebind:
    - fi-blb-e6850:       [FAIL][12] ([i915#3194]) -> [PASS][13]
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/fi-blb-e6850/igt@core_hotunplug@unbind-rebind.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/fi-blb-e6850/igt@core_hotunplug@unbind-rebind.html

  * igt@i915_selftest@live@gt_pm:
    - {fi-jsl-1}:         [DMESG-FAIL][14] ([i915#1886]) -> [PASS][15]
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/fi-jsl-1/igt@i915_selftest@live@gt_pm.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/fi-jsl-1/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@hangcheck:
    - fi-hsw-4770:        [INCOMPLETE][16] ([i915#3303]) -> [PASS][17]
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#3194]: https://gitlab.freedesktop.org/drm/intel/issues/3194
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613


Build changes
-------------

  * Linux: CI_DRM_11306 -> Patchwork_22450

  CI-20190529: 20190529
  CI_DRM_11306: 0eb492df610222f39eb2ad5a903626dd3ad9aea2 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6361: 2372a4beb6a33c5f0799a4a8ccbb93794f52dbca @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_22450: 7844cc75d7bdea89d71e29434bd3084d19e17f79 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

7844cc75d7bd drm/i915: Remove struct dp_link_dpll
5ee7c5e32a3e drm/i915: Populate bxt/glk DPLL clock limits a bit more
01ffc1137951 drm/i915: Replace hand rolled bxt vco calculation with chv_calc_dpll_params()
a074ff2571d9 drm/i915: Replace bxt_clk_div with struct dpll
078df1bc498e drm/i915: Store the m2 divider as a whole in bxt_clk_div
c230b94eaf63 drm/i915: Use designated initializers for bxt_dp_clk_val[]
56e1e5780605 drm/i915: Remove bxt m2_frac_en
fc2606949cb7 drm/i915: Store the /5 target clock in sturct dpll on vlv/chv
f5525e245861 drm/i915: Clean up some struct/array initializers
31bbcb2b54e4 drm/i915: Move a bunch of stuff into rodata from the stack
5fbfbfd35b7c drm/i915: Nuke skl_wrpll_context_init()

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/index.html

[-- Attachment #2: Type: text/html, Size: 7934 bytes --]

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Clean up some dpll stuff (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 30265 bytes --]

== Series Details ==

Series: drm/i915: Clean up some dpll stuff (rev2)
URL   : https://patchwork.freedesktop.org/series/100899/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11306_full -> Patchwork_22450_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 13)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_22450_full:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-5@pipe-c-edp-1-downscale-with-pixel-format}:
    - shard-iclb:         [PASS][1] -> [SKIP][2] +2 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-iclb6/igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-5@pipe-c-edp-1-downscale-with-pixel-format.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-iclb2/igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-5@pipe-c-edp-1-downscale-with-pixel-format.html

  * {igt@kms_plane_scaling@downscale-with-rotation-factor-0-5@pipe-c-hdmi-a-1-downscale-with-rotation}:
    - {shard-tglu}:       NOTRUN -> [SKIP][3] +7 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-tglu-8/igt@kms_plane_scaling@downscale-with-rotation-factor-0-5@pipe-c-hdmi-a-1-downscale-with-rotation.html

  * {igt@kms_plane_scaling@downscale-with-rotation-factor-0-5@pipe-d-hdmi-a-3-downscale-with-rotation}:
    - {shard-dg1}:        NOTRUN -> [SKIP][4] +11 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-dg1-18/igt@kms_plane_scaling@downscale-with-rotation-factor-0-5@pipe-d-hdmi-a-3-downscale-with-rotation.html

  * {igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25}:
    - {shard-rkl}:        NOTRUN -> [SKIP][5] +13 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-rkl-1/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25.html

  
New tests
---------

  New tests have been introduced between CI_DRM_11306_full and Patchwork_22450_full:

### New IGT tests (4) ###

  * igt@gem_exec_suspend@basic:
    - Statuses :
    - Exec time: [None] s

  * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
    - Statuses :
    - Exec time: [None] s

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-d-edp-1-planes-upscale-downscale:
    - Statuses : 1 pass(s)
    - Exec time: [1.28] s

  * igt@prime_mmap@test_userptr:
    - Statuses :
    - Exec time: [None] s

  

Known issues
------------

  Here are the changes found in Patchwork_22450_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_create@create-massive:
    - shard-kbl:          NOTRUN -> [DMESG-WARN][6] ([i915#4991])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-kbl4/igt@gem_create@create-massive.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - shard-iclb:         [PASS][7] -> [FAIL][8] ([i915#2842])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-iclb4/igt@gem_exec_fair@basic-none-share@rcs0.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-iclb6/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
    - shard-iclb:         NOTRUN -> [FAIL][9] ([i915#2842])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-iclb2/igt@gem_exec_fair@basic-pace@vcs1.html

  * igt@gem_exec_whisper@basic-contexts-forked-all:
    - shard-glk:          [PASS][10] -> [DMESG-WARN][11] ([i915#118])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-glk9/igt@gem_exec_whisper@basic-contexts-forked-all.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-glk4/igt@gem_exec_whisper@basic-contexts-forked-all.html

  * igt@gem_lmem_swapping@heavy-multi:
    - shard-apl:          NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4613])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-apl4/igt@gem_lmem_swapping@heavy-multi.html

  * igt@gem_lmem_swapping@heavy-verify-multi:
    - shard-skl:          NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4613]) +2 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-skl1/igt@gem_lmem_swapping@heavy-verify-multi.html

  * igt@gem_lmem_swapping@heavy-verify-random:
    - shard-iclb:         NOTRUN -> [SKIP][14] ([i915#4613])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-iclb6/igt@gem_lmem_swapping@heavy-verify-random.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-skl:          NOTRUN -> [WARN][15] ([i915#2658])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-skl6/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs:
    - shard-iclb:         NOTRUN -> [SKIP][16] ([i915#768]) +1 similar issue
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-iclb6/igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs.html

  * igt@gen3_render_tiledy_blits:
    - shard-iclb:         NOTRUN -> [SKIP][17] ([fdo#109289])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-iclb6/igt@gen3_render_tiledy_blits.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-glk:          [PASS][18] -> [DMESG-WARN][19] ([i915#1436] / [i915#716])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-glk7/igt@gen9_exec_parse@allowed-all.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-glk5/igt@gen9_exec_parse@allowed-all.html

  * igt@gen9_exec_parse@shadow-peek:
    - shard-tglb:         NOTRUN -> [SKIP][20] ([i915#2527] / [i915#2856])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-tglb2/igt@gen9_exec_parse@shadow-peek.html

  * igt@i915_module_load@reload-no-display:
    - shard-iclb:         [PASS][21] -> [DMESG-WARN][22] ([i915#2867] / [i915#4391])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-iclb2/igt@i915_module_load@reload-no-display.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-iclb7/igt@i915_module_load@reload-no-display.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-skl:          NOTRUN -> [FAIL][23] ([i915#454])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-skl6/igt@i915_pm_dc@dc6-psr.html

  * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
    - shard-kbl:          NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#1937])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-kbl4/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html

  * igt@i915_pm_sseu@full-enable:
    - shard-iclb:         NOTRUN -> [SKIP][25] ([i915#4387])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-iclb6/igt@i915_pm_sseu@full-enable.html

  * igt@i915_suspend@fence-restore-untiled:
    - shard-apl:          NOTRUN -> [DMESG-WARN][26] ([i915#180])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-apl4/igt@i915_suspend@fence-restore-untiled.html

  * igt@kms_async_flips@alternate-sync-async-flip:
    - shard-skl:          [PASS][27] -> [FAIL][28] ([i915#2521])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-skl7/igt@kms_async_flips@alternate-sync-async-flip.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-skl6/igt@kms_async_flips@alternate-sync-async-flip.html

  * igt@kms_atomic@plane-immutable-zpos:
    - shard-skl:          NOTRUN -> [DMESG-WARN][29] ([i915#1982])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-skl3/igt@kms_atomic@plane-immutable-zpos.html

  * igt@kms_big_fb@linear-32bpp-rotate-90:
    - shard-iclb:         NOTRUN -> [SKIP][30] ([fdo#110725] / [fdo#111614]) +1 similar issue
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-iclb5/igt@kms_big_fb@linear-32bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-skl:          NOTRUN -> [FAIL][31] ([i915#3743]) +3 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-skl6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-skl:          NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#3777]) +3 similar issues
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-skl1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - shard-apl:          NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#3777])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-apl4/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - shard-iclb:         NOTRUN -> [SKIP][34] ([fdo#110723])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-iclb5/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
    - shard-skl:          NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#3886]) +14 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-skl3/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
    - shard-kbl:          NOTRUN -> [SKIP][36] ([fdo#109271] / [i915#3886])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-kbl4/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
    - shard-apl:          NOTRUN -> [SKIP][37] ([fdo#109271] / [i915#3886])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-apl4/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc:
    - shard-iclb:         NOTRUN -> [SKIP][38] ([fdo#109278] / [i915#3886]) +2 similar issues
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-iclb6/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_ccs:
    - shard-apl:          NOTRUN -> [SKIP][39] ([fdo#109271]) +23 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-apl4/igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_ccs.html

  * igt@kms_chamelium@hdmi-mode-timings:
    - shard-iclb:         NOTRUN -> [SKIP][40] ([fdo#109284] / [fdo#111827]) +3 similar issues
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-iclb5/igt@kms_chamelium@hdmi-mode-timings.html

  * igt@kms_chamelium@vga-frame-dump:
    - shard-skl:          NOTRUN -> [SKIP][41] ([fdo#109271] / [fdo#111827]) +31 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-skl7/igt@kms_chamelium@vga-frame-dump.html

  * igt@kms_chamelium@vga-hpd-enable-disable-mode:
    - shard-kbl:          NOTRUN -> [SKIP][42] ([fdo#109271] / [fdo#111827]) +1 similar issue
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-kbl4/igt@kms_chamelium@vga-hpd-enable-disable-mode.html

  * igt@kms_color_chamelium@pipe-d-ctm-max:
    - shard-apl:          NOTRUN -> [SKIP][43] ([fdo#109271] / [fdo#111827])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-apl4/igt@kms_color_chamelium@pipe-d-ctm-max.html

  * igt@kms_content_protection@type1:
    - shard-iclb:         NOTRUN -> [SKIP][44] ([fdo#109300] / [fdo#111066])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-iclb6/igt@kms_content_protection@type1.html

  * igt@kms_cursor_crc@pipe-a-cursor-max-size-sliding:
    - shard-iclb:         NOTRUN -> [SKIP][45] ([fdo#109278]) +8 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-iclb6/igt@kms_cursor_crc@pipe-a-cursor-max-size-sliding.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
    - shard-iclb:         NOTRUN -> [SKIP][46] ([fdo#109274] / [fdo#109278]) +1 similar issue
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-iclb6/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html

  * igt@kms_cursor_legacy@pipe-d-single-bo:
    - shard-kbl:          NOTRUN -> [SKIP][47] ([fdo#109271] / [i915#533])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-kbl4/igt@kms_cursor_legacy@pipe-d-single-bo.html

  * igt@kms_flip@2x-plain-flip-fb-recreate:
    - shard-iclb:         NOTRUN -> [SKIP][48] ([fdo#109274])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-iclb6/igt@kms_flip@2x-plain-flip-fb-recreate.html

  * igt@kms_flip@flip-vs-suspend-interruptible@c-edp1:
    - shard-iclb:         [PASS][49] -> [DMESG-WARN][50] ([i915#2867])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-iclb2/igt@kms_flip@flip-vs-suspend-interruptible@c-edp1.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-iclb7/igt@kms_flip@flip-vs-suspend-interruptible@c-edp1.html

  * igt@kms_flip@flip-vs-suspend@c-dp1:
    - shard-kbl:          [PASS][51] -> [DMESG-WARN][52] ([i915#180]) +7 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-kbl1/igt@kms_flip@flip-vs-suspend@c-dp1.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-kbl7/igt@kms_flip@flip-vs-suspend@c-dp1.html
    - shard-apl:          [PASS][53] -> [DMESG-WARN][54] ([i915#180]) +3 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-apl6/igt@kms_flip@flip-vs-suspend@c-dp1.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-apl8/igt@kms_flip@flip-vs-suspend@c-dp1.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
    - shard-skl:          [PASS][55] -> [FAIL][56] ([i915#2122])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-skl9/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-skl8/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling:
    - shard-glk:          [PASS][57] -> [FAIL][58] ([i915#4911]) +1 similar issue
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-glk2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
    - shard-iclb:         [PASS][59] -> [SKIP][60] ([i915#3701])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-iclb8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
    - shard-skl:          NOTRUN -> [SKIP][61] ([fdo#109271]) +347 similar issues
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-skl7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-gtt:
    - shard-iclb:         NOTRUN -> [SKIP][62] ([fdo#109280]) +11 similar issues
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-skl:          NOTRUN -> [FAIL][63] ([i915#1188])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-skl8/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
    - shard-skl:          NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#533]) +1 similar issue
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-skl1/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
    - shard-skl:          NOTRUN -> [FAIL][65] ([fdo#108145] / [i915#265]) +4 similar issues
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
    - shard-kbl:          NOTRUN -> [FAIL][66] ([fdo#108145] / [i915#265])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-kbl4/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html

  * igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
    - shard-skl:          NOTRUN -> [FAIL][67] ([i915#265])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html

  * igt@kms_plane_lowres@pipe-a-tiling-x:
    - shard-iclb:         NOTRUN -> [SKIP][68] ([i915#3536])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-x.html

  * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area:
    - shard-iclb:         NOTRUN -> [SKIP][69] ([fdo#111068] / [i915#658])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-iclb5/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_sf@plane-move-sf-dmg-area:
    - shard-skl:          NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#658]) +2 similar issues
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-skl8/igt@kms_psr2_sf@plane-move-sf-dmg-area.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-iclb:         [PASS][71] -> [SKIP][72] ([fdo#109642] / [fdo#111068] / [i915#658])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-iclb2/igt@kms_psr2_su@frontbuffer-xrgb8888.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-iclb7/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr@cursor_plane_onoff:
    - shard-kbl:          NOTRUN -> [SKIP][73] ([fdo#109271]) +24 similar issues
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-kbl4/igt@kms_psr@cursor_plane_onoff.html

  * igt@kms_psr@psr2_cursor_mmap_gtt:
    - shard-iclb:         [PASS][74] -> [SKIP][75] ([fdo#109441])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_gtt.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-iclb8/igt@kms_psr@psr2_cursor_mmap_gtt.html

  * igt@kms_psr@psr2_no_drrs:
    - shard-iclb:         NOTRUN -> [SKIP][76] ([fdo#109441])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-iclb6/igt@kms_psr@psr2_no_drrs.html

  * igt@kms_sysfs_edid_timing:
    - shard-skl:          NOTRUN -> [FAIL][77] ([IGT#2])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-skl8/igt@kms_sysfs_edid_timing.html

  * igt@kms_tv_load_detect@load-detect:
    - shard-iclb:         NOTRUN -> [SKIP][78] ([fdo#109309])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-iclb6/igt@kms_tv_load_detect@load-detect.html

  * igt@kms_vrr@flip-suspend:
    - shard-iclb:         NOTRUN -> [SKIP][79] ([fdo#109502])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-iclb6/igt@kms_vrr@flip-suspend.html

  * igt@kms_writeback@writeback-invalid-parameters:
    - shard-skl:          NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#2437]) +2 similar issues
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-skl7/igt@kms_writeback@writeback-invalid-parameters.html

  * igt@nouveau_crc@pipe-d-source-rg:
    - shard-iclb:         NOTRUN -> [SKIP][81] ([fdo#109278] / [i915#2530])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-iclb5/igt@nouveau_crc@pipe-d-source-rg.html

  * igt@prime_nv_test@i915_import_gtt_mmap:
    - shard-iclb:         NOTRUN -> [SKIP][82] ([fdo#109291])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-iclb5/igt@prime_nv_test@i915_import_gtt_mmap.html

  * igt@prime_vgem@fence-flip-hang:
    - shard-iclb:         NOTRUN -> [SKIP][83] ([fdo#109295])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-iclb6/igt@prime_vgem@fence-flip-hang.html

  * igt@syncobj_timeline@invalid-transfer-non-existent-point:
    - shard-skl:          NOTRUN -> [DMESG-WARN][84] ([i915#5098])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-skl7/igt@syncobj_timeline@invalid-transfer-non-existent-point.html

  * igt@sysfs_clients@busy:
    - shard-apl:          NOTRUN -> [SKIP][85] ([fdo#109271] / [i915#2994])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-apl4/igt@sysfs_clients@busy.html

  * igt@sysfs_clients@create:
    - shard-skl:          NOTRUN -> [SKIP][86] ([fdo#109271] / [i915#2994]) +3 similar issues
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-skl6/igt@sysfs_clients@create.html

  * igt@sysfs_clients@split-10:
    - shard-iclb:         NOTRUN -> [SKIP][87] ([i915#2994]) +1 similar issue
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-iclb6/igt@sysfs_clients@split-10.html

  
#### Possible fixes ####

  * igt@feature_discovery@psr2:
    - shard-iclb:         [SKIP][88] ([i915#658]) -> [PASS][89]
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-iclb8/igt@feature_discovery@psr2.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-iclb2/igt@feature_discovery@psr2.html

  * igt@gem_eio@unwedge-stress:
    - shard-iclb:         [TIMEOUT][90] ([i915#2481] / [i915#3070]) -> [PASS][91]
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-iclb8/igt@gem_eio@unwedge-stress.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-iclb2/igt@gem_eio@unwedge-stress.html
    - {shard-rkl}:        ([PASS][92], [TIMEOUT][93]) ([i915#3063]) -> [PASS][94]
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-rkl-2/igt@gem_eio@unwedge-stress.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-rkl-4/igt@gem_eio@unwedge-stress.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-rkl-5/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-kbl:          [FAIL][95] ([i915#2842]) -> [PASS][96]
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-kbl1/igt@gem_exec_fair@basic-pace-solo@rcs0.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-kbl7/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_huc_copy@huc-copy:
    - shard-tglb:         [SKIP][97] ([i915#2190]) -> [PASS][98]
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-tglb7/igt@gem_huc_copy@huc-copy.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-tglb8/igt@gem_huc_copy@huc-copy.html

  * igt@gem_ppgtt@flink-and-close-vma-leak:
    - shard-glk:          [FAIL][99] ([i915#644]) -> [PASS][100]
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-glk8/igt@gem_ppgtt@flink-and-close-vma-leak.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-glk5/igt@gem_ppgtt@flink-and-close-vma-leak.html

  * igt@i915_pm_rpm@cursor:
    - {shard-rkl}:        ([SKIP][101], [SKIP][102]) ([i915#1849]) -> [PASS][103]
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-rkl-1/igt@i915_pm_rpm@cursor.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-rkl-4/igt@i915_pm_rpm@cursor.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-rkl-6/igt@i915_pm_rpm@cursor.html

  * igt@i915_pm_rpm@modeset-lpsp-stress:
    - {shard-rkl}:        [SKIP][104] ([i915#1397]) -> [PASS][105]
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-rkl-1/igt@i915_pm_rpm@modeset-lpsp-stress.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-rkl-6/igt@i915_pm_rpm@modeset-lpsp-stress.html

  * igt@i915_pm_rps@min-max-config-idle:
    - {shard-rkl}:        [FAIL][106] ([i915#4016]) -> [PASS][107]
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-rkl-1/igt@i915_pm_rps@min-max-config-idle.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-rkl-5/igt@i915_pm_rps@min-max-config-idle.html

  * igt@kms_atomic@plane-invalid-params:
    - {shard-rkl}:        ([SKIP][108], [SKIP][109]) ([i915#1845]) -> [PASS][110] +1 similar issue
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-rkl-4/igt@kms_atomic@plane-invalid-params.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-rkl-1/igt@kms_atomic@plane-invalid-params.html
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-rkl-6/igt@kms_atomic@plane-invalid-params.html

  * igt@kms_big_fb@y-tiled-16bpp-rotate-0:
    - shard-glk:          [DMESG-WARN][111] ([i915#118]) -> [PASS][112] +1 similar issue
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-glk4/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-glk7/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html

  * igt@kms_big_fb@y-tiled-32bpp-rotate-90:
    - {shard-rkl}:        [SKIP][113] ([i915#1845]) -> [PASS][114]
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-rkl-1/igt@kms_big_fb@y-tiled-32bpp-rotate-90.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-rkl-6/igt@kms_big_fb@y-tiled-32bpp-rotate-90.html

  * igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
    - {shard-rkl}:        ([SKIP][115], [SKIP][116]) ([i915#1845] / [i915#4098]) -> [PASS][117]
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-rkl-1/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-rkl-4/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-rkl-6/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
    - {shard-rkl}:        [SKIP][118] ([i915#1845] / [i915#4098]) -> [PASS][119] +2 similar issues
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-rkl-1/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-rkl-6/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_cursor_crc@pipe-a-cursor-256x256-random:
    - {shard-rkl}:        [SKIP][120] ([fdo#112022] / [i915#4070]) -> [PASS][121] +1 similar issue
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-rkl-1/igt@kms_cursor_crc@pipe-a-cursor-256x256-random.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-256x256-random.html

  * igt@kms_cursor_edge_walk@pipe-b-256x256-bottom-edge:
    - {shard-rkl}:        [SKIP][122] ([i915#1849] / [i915#4070]) -> [PASS][123]
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-rkl-1/igt@kms_cursor_edge_walk@pipe-b-256x256-bottom-edge.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-rkl-6/igt@kms_cursor_edge_walk@pipe-b-256x256-bottom-edge.html

  * igt@kms_cursor_legacy@cursor-vs-flip-legacy:
    - {shard-rkl}:        [SKIP][124] ([fdo#111825] / [i915#4070]) -> [PASS][125] +1 similar issue
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-rkl-1/igt@kms_cursor_legacy@cursor-vs-flip-legacy.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-rkl-6/igt@kms_cursor_legacy@cursor-vs-flip-legacy.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - {shard-rkl}:        [SKIP][126] ([i915#1849]) -> [PASS][127] +5 similar issues
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-rkl-1/igt@kms_fbcon_fbt@fbc-suspend.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-rkl-6/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
    - shard-skl:          [FAIL][128] ([i915#79]) -> [PASS][129]
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@b-dp1:
    - shard-kbl:          [INCOMPLETE][130] ([i915#3614]) -> [PASS][131]
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html

  * igt@kms_flip@flip-vs-suspend@a-dp1:
    - shard-apl:          [DMESG-WARN][132] ([i915#180]) -> [PASS][133] +2 similar issues
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-apl6/igt@kms_flip@flip-vs-suspend@a-dp1.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/shard-apl8/igt@kms_flip@flip-vs-suspend@a-dp1.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
    - shard-skl:          [FAIL][134] ([i915#2122]) -> [PASS][135]
   [134]: https://intel-gfx-ci.01.org/tr

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22450/index.html

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