* [igt-dev] [PATCH i-g-t v2 0/3] tests/i915: ccs subtests for gem_lmem_swapping
@ 2022-03-01 21:25 Ramalingam C
2022-03-01 21:25 ` [igt-dev] [PATCH i-g-t v2 1/3] i915/gem_engine_topology: Only use the main copy engines for XY_BLOCK_COPY Ramalingam C
` (5 more replies)
0 siblings, 6 replies; 8+ messages in thread
From: Ramalingam C @ 2022-03-01 21:25 UTC (permalink / raw)
To: igt-dev
Third patch adds the subtests covering the compressed obj's
eviction and restoration.
First two patches were added for the dependency purpose those will be
reviewed at their respective series.
v2: gem_sync after the init obj.
Chris Wilson (1):
i915/gem_engine_topology: Only use the main copy engines for
XY_BLOCK_COPY
Ramalingam C (1):
tests/i915/gem_lmem_swapping: ccs subtests
Zbigniew Kempczyński (1):
lib/i915_blt: Add library for blitter
lib/i915/gem_engine_topology.c | 38 ++
lib/i915/gem_engine_topology.h | 5 +
lib/i915/i915_blt.c | 992 +++++++++++++++++++++++++++++++++
lib/i915/i915_blt.h | 157 ++++++
lib/meson.build | 1 +
tests/i915/gem_lmem_swapping.c | 217 +++++++-
6 files changed, 1405 insertions(+), 5 deletions(-)
create mode 100644 lib/i915/i915_blt.c
create mode 100644 lib/i915/i915_blt.h
--
2.20.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [igt-dev] [PATCH i-g-t v2 1/3] i915/gem_engine_topology: Only use the main copy engines for XY_BLOCK_COPY
2022-03-01 21:25 [igt-dev] [PATCH i-g-t v2 0/3] tests/i915: ccs subtests for gem_lmem_swapping Ramalingam C
@ 2022-03-01 21:25 ` Ramalingam C
2022-03-01 21:25 ` [igt-dev] [PATCH i-g-t v2 2/3] lib/i915_blt: Add library for blitter Ramalingam C
` (4 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Ramalingam C @ 2022-03-01 21:25 UTC (permalink / raw)
To: igt-dev; +Cc: Melkaveri, Chris Wilson
From: Chris Wilson <chris.p.wilson@intel.com>
XY_BLOCK_COPY blt command is used to transfer the ccs data.
So, we can only run the tests on those engines which have
support for the "block_copy" capability.
Signed-off-by: Chris Wilson <chris.p.wilson@intel.com>
Signed-off-by: Apoorva Singh <apoorva1.singh@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Melkaveri, Arjun <arjun.melkaveri@intel.com>
---
lib/i915/gem_engine_topology.c | 38 ++++++++++++++++++++++++++++++++++
lib/i915/gem_engine_topology.h | 5 +++++
2 files changed, 43 insertions(+)
diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
index bd12d0bc986d..18fc00ab00e9 100644
--- a/lib/i915/gem_engine_topology.c
+++ b/lib/i915/gem_engine_topology.c
@@ -534,6 +534,44 @@ void gem_engine_properties_restore(int fd, const struct gem_engine_properties *s
}
}
+static bool
+__gem_engine_has_capability(int i915, const char *engine,
+ const char *attr, const char *cap)
+{
+ char buf[4096] = {};
+ FILE *file;
+
+ file = __open_attr(igt_sysfs_open(i915), "r",
+ "engine", engine, attr, NULL);
+ if (file) {
+ fread(buf, 1, sizeof(buf) - 1, file);
+ fclose(file);
+ }
+
+ return strstr(buf, cap);
+}
+
+bool gem_engine_has_capability(int i915, const char *engine, const char *cap)
+{
+ return __gem_engine_has_capability(i915, engine, "capabilities", cap);
+}
+
+bool gem_engine_has_known_capability(int i915, const char *engine, const char *cap)
+{
+ return __gem_engine_has_capability(i915, engine, "known_capabilities", cap);
+}
+
+bool gem_engine_can_block_copy(int i915, const struct intel_execution_engine2 *engine)
+{
+ if (engine->class != I915_ENGINE_CLASS_COPY)
+ return false;
+
+ if (!gem_engine_has_known_capability(i915, engine->name, "block_copy"))
+ return intel_gen(intel_get_drm_devid(i915)) >= 12;
+
+ return gem_engine_has_capability(i915, engine->name, "block_copy");
+}
+
uint32_t gem_engine_mmio_base(int i915, const char *engine)
{
unsigned int mmio = 0;
diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
index b413aa8aba30..987f2bf9449d 100644
--- a/lib/i915/gem_engine_topology.h
+++ b/lib/i915/gem_engine_topology.h
@@ -133,6 +133,11 @@ int gem_engine_property_printf(int i915, const char *engine, const char *attr,
uint32_t gem_engine_mmio_base(int i915, const char *engine);
+bool gem_engine_has_capability(int i915, const char *engine, const char *cap);
+bool gem_engine_has_known_capability(int i915, const char *engine, const char *cap);
+
+bool gem_engine_can_block_copy(int i915, const struct intel_execution_engine2 *engine);
+
void dyn_sysfs_engines(int i915, int engines, const char *file,
void (*test)(int i915, int engine));
--
2.20.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [igt-dev] [PATCH i-g-t v2 2/3] lib/i915_blt: Add library for blitter
2022-03-01 21:25 [igt-dev] [PATCH i-g-t v2 0/3] tests/i915: ccs subtests for gem_lmem_swapping Ramalingam C
2022-03-01 21:25 ` [igt-dev] [PATCH i-g-t v2 1/3] i915/gem_engine_topology: Only use the main copy engines for XY_BLOCK_COPY Ramalingam C
@ 2022-03-01 21:25 ` Ramalingam C
2022-03-01 21:25 ` [igt-dev] [PATCH i-g-t v2 3/3] tests/i915/gem_lmem_swapping: ccs subtests Ramalingam C
` (3 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Ramalingam C @ 2022-03-01 21:25 UTC (permalink / raw)
To: igt-dev
From: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Blitter commands became complicated thus manual bitshifting is error
prone and hard debugable - XY_BLOCK_COPY_BLT is the best example -
in extended version (for DG2+) it takes 20 dwords of command data.
To avoid mistakes and dozens of arguments for command library provides
input data in more structured form.
Currently supported commands:
- XY_BLOCK_COPY_BLT:
a) TGL/DG1 uses shorter version of command which doesn't support
compression
b) DG2+ command is extended and supports compression
- XY_CTRL_SURF_COPY_BLT
- XY_FAST_COPY_BLT
Source, destination and batchbuffer are provided to blitter functions
as objects (structs). This increases readability and allows use same
object in many functions. Only drawback of such attitude is some fields
used in one function may be ignored in another. As an example is
blt_copy_object which contains a lot of information about gem object.
In block-copy all of data are used but in fast-copy only some of them
(fast-copy doesn't support compression).
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
lib/i915/i915_blt.c | 992 ++++++++++++++++++++++++++++++++++++++++++++
lib/i915/i915_blt.h | 157 +++++++
lib/meson.build | 1 +
3 files changed, 1150 insertions(+)
create mode 100644 lib/i915/i915_blt.c
create mode 100644 lib/i915/i915_blt.h
diff --git a/lib/i915/i915_blt.c b/lib/i915/i915_blt.c
new file mode 100644
index 000000000000..7079802b68c4
--- /dev/null
+++ b/lib/i915/i915_blt.c
@@ -0,0 +1,992 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include <errno.h>
+#include <sys/ioctl.h>
+#include <sys/time.h>
+#include <malloc.h>
+#include <cairo.h>
+#include "drm.h"
+#include "igt.h"
+#include "gem_create.h"
+#include "i915_blt.h"
+
+#define BITRANGE(start, end) (end - start + 1)
+
+enum blt_special_mode {
+ SM_NONE,
+ SM_FULL_RESOLVE,
+ SM_PARTIAL_RESOLVE,
+ SM_RESERVED,
+};
+
+enum blt_aux_mode {
+ AM_AUX_NONE,
+ AM_AUX_CCS_E = 5,
+};
+
+enum blt_target_mem {
+ TM_LOCAL_MEM,
+ TM_SYSTEM_MEM,
+};
+
+struct gen12_block_copy_data {
+ struct {
+ uint32_t length: BITRANGE(0, 7);
+ uint32_t rsvd1: BITRANGE(8, 8);
+ uint32_t multisamples: BITRANGE(9, 11);
+ uint32_t special_mode: BITRANGE(12, 13);
+ uint32_t rsvd0: BITRANGE(14, 18);
+ uint32_t color_depth: BITRANGE(19, 21);
+ uint32_t opcode: BITRANGE(22, 28);
+ uint32_t client: BITRANGE(29, 31);
+ } dw00;
+
+ struct {
+ uint32_t dst_pitch: BITRANGE(0, 17);
+ uint32_t dst_aux_mode: BITRANGE(18, 20);
+ uint32_t dst_mocs: BITRANGE(21, 27);
+ uint32_t dst_ctrl_surface_type: BITRANGE(28, 28);
+ uint32_t dst_compression: BITRANGE(29, 29);
+ uint32_t dst_tiling: BITRANGE(30, 31);
+ } dw01;
+
+ struct {
+ int32_t dst_x1: BITRANGE(0, 15);
+ int32_t dst_y1: BITRANGE(16, 31);
+ } dw02;
+
+ struct {
+ int32_t dst_x2: BITRANGE(0, 15);
+ int32_t dst_y2: BITRANGE(16, 31);
+ } dw03;
+
+ struct {
+ uint32_t dst_address_lo;
+ } dw04;
+
+ struct {
+ uint32_t dst_address_hi;
+ } dw05;
+
+ struct {
+ uint32_t dst_x_offset: BITRANGE(0, 13);
+ uint32_t rsvd1: BITRANGE(14, 15);
+ uint32_t dst_y_offset: BITRANGE(16, 29);
+ uint32_t rsvd0: BITRANGE(30, 30);
+ uint32_t dst_target_memory: BITRANGE(31, 31);
+ } dw06;
+
+ struct {
+ int32_t src_x1: BITRANGE(0, 15);
+ int32_t src_y1: BITRANGE(16, 31);
+ } dw07;
+
+ struct {
+ uint32_t src_pitch: BITRANGE(0, 17);
+ uint32_t src_aux_mode: BITRANGE(18, 20);
+ uint32_t src_mocs: BITRANGE(21, 27);
+ uint32_t src_ctrl_surface_type: BITRANGE(28, 28);
+ uint32_t src_compression: BITRANGE(29, 29);
+ uint32_t src_tiling: BITRANGE(30, 31);
+ } dw08;
+
+ struct {
+ uint32_t src_address_lo;
+ } dw09;
+
+ struct {
+ uint32_t src_address_hi;
+ } dw10;
+
+ struct {
+ uint32_t src_x_offset: BITRANGE(0, 13);
+ uint32_t rsvd1: BITRANGE(14, 15);
+ uint32_t src_y_offset: BITRANGE(16, 29);
+ uint32_t rsvd0: BITRANGE(30, 30);
+ uint32_t src_target_memory: BITRANGE(31, 31);
+ } dw11;
+};
+
+struct gen12_block_copy_data_ext {
+ struct {
+ uint32_t src_compression_format: BITRANGE(0, 4);
+ uint32_t src_clear_value_enable: BITRANGE(5, 5);
+ uint32_t src_clear_address_low: BITRANGE(6, 31);
+ } dw12;
+
+ union {
+ /* DG2, XEHP */
+ uint32_t src_clear_address_hi0;
+ /* Others */
+ uint32_t src_clear_address_hi1;
+ } dw13;
+
+ struct {
+ uint32_t dst_compression_format: BITRANGE(0, 4);
+ uint32_t dst_clear_value_enable: BITRANGE(5, 5);
+ uint32_t dst_clear_address_low: BITRANGE(6, 31);
+ } dw14;
+
+ union {
+ /* DG2, XEHP */
+ uint32_t dst_clear_address_hi0;
+ /* Others */
+ uint32_t dst_clear_address_hi1;
+ } dw15;
+
+ struct {
+ uint32_t dst_surface_height: BITRANGE(0, 13);
+ uint32_t dst_surface_width: BITRANGE(14, 27);
+ uint32_t rsvd0: BITRANGE(28, 28);
+ uint32_t dst_surface_type: BITRANGE(29, 31);
+ } dw16;
+
+ struct {
+ uint32_t dst_lod: BITRANGE(0, 3);
+ uint32_t dst_surface_qpitch: BITRANGE(4, 18);
+ uint32_t rsvd0: BITRANGE(19, 20);
+ uint32_t dst_surface_depth: BITRANGE(21, 31);
+ } dw17;
+
+ struct {
+ uint32_t dst_horizontal_align: BITRANGE(0, 1);
+ uint32_t rsvd0: BITRANGE(2, 2);
+ uint32_t dst_vertical_align: BITRANGE(3, 4);
+ uint32_t rsvd1: BITRANGE(5, 7);
+ uint32_t dst_mip_tail_start_lod: BITRANGE(8, 11);
+ uint32_t rsvd2: BITRANGE(12, 17);
+ uint32_t dst_depth_stencil_resource: BITRANGE(18, 18);
+ uint32_t rsvd3: BITRANGE(19, 20);
+ uint32_t dst_array_index: BITRANGE(21, 31);
+ } dw18;
+
+ struct {
+ uint32_t src_surface_height: BITRANGE(0, 13);
+ uint32_t src_surface_width: BITRANGE(14, 27);
+ uint32_t rsvd0: BITRANGE(28, 28);
+ uint32_t src_surface_type: BITRANGE(29, 31);
+ } dw19;
+
+ struct {
+ uint32_t src_lod: BITRANGE(0, 3);
+ uint32_t src_surface_qpitch: BITRANGE(4, 18);
+ uint32_t rsvd0: BITRANGE(19, 20);
+ uint32_t src_surface_depth: BITRANGE(21, 31);
+ } dw20;
+
+ struct {
+ uint32_t src_horizontal_align: BITRANGE(0, 1);
+ uint32_t rsvd0: BITRANGE(2, 2);
+ uint32_t src_vertical_align: BITRANGE(3, 4);
+ uint32_t rsvd1: BITRANGE(5, 7);
+ uint32_t src_mip_tail_start_lod: BITRANGE(8, 11);
+ uint32_t rsvd2: BITRANGE(12, 17);
+ uint32_t src_depth_stencil_resource: BITRANGE(18, 18);
+ uint32_t rsvd3: BITRANGE(19, 20);
+ uint32_t src_array_index: BITRANGE(21, 31);
+ } dw21;
+};
+
+bool blt_supports_compression(int i915)
+{
+ uint32_t devid = intel_get_drm_devid(i915);
+
+ if (IS_TIGERLAKE(devid) || IS_DG1(devid))
+ return false;
+
+ return true;
+}
+
+bool blt_supports_tiling(int i915, enum blt_tiling tiling)
+{
+ uint32_t devid = intel_get_drm_devid(i915);
+
+ if (tiling == T_XMAJOR) {
+ if (IS_TIGERLAKE(devid) || IS_DG1(devid))
+ return false;
+ else
+ return true;
+ }
+
+ if (tiling == T_YMAJOR) {
+ if (IS_TIGERLAKE(devid) || IS_DG1(devid))
+ return true;
+ else
+ return false;
+ }
+
+ return true;
+}
+
+const char *blt_tiling_name(enum blt_tiling tiling)
+{
+ switch (tiling) {
+ case T_LINEAR: return "linear";
+ case T_XMAJOR: return "xmajor";
+ case T_YMAJOR: return "ymajor";
+ case T_TILE4: return "tile4";
+ case T_TILE64: return "tile64";
+ }
+
+ igt_warn("invalid tiling passed: %d\n", tiling);
+ return NULL;
+}
+
+static int __block_tiling(enum blt_tiling tiling)
+{
+ switch (tiling) {
+ case T_LINEAR: return 0;
+ case T_XMAJOR: return 1;
+ case T_YMAJOR: return 1;
+ case T_TILE4: return 2;
+ case T_TILE64: return 3;
+ }
+
+ igt_warn("invalid tiling passed: %d\n", tiling);
+ return 0;
+}
+
+static int __special_mode(const struct blt_copy_data *blt)
+{
+ if (blt->src.handle == blt->dst.handle &&
+ blt->src.compression && !blt->dst.compression)
+ return SM_FULL_RESOLVE;
+
+
+ return SM_NONE;
+}
+
+static int __memory_type(uint32_t region)
+{
+ igt_assert_f(IS_DEVICE_MEMORY_REGION(region) ||
+ IS_SYSTEM_MEMORY_REGION(region),
+ "Invalid region: %x\n", region);
+
+ if (IS_DEVICE_MEMORY_REGION(region))
+ return TM_LOCAL_MEM;
+ return TM_SYSTEM_MEM;
+}
+
+static enum blt_aux_mode __aux_mode(const struct blt_copy_object *obj)
+{
+ if (obj->compression == COMPRESSION_ENABLED) {
+ igt_assert_f(IS_DEVICE_MEMORY_REGION(obj->region),
+ "XY_BLOCK_COPY_BLT supports compression "
+ "on device memory only\n");
+ return AM_AUX_CCS_E;
+ }
+
+ return AM_AUX_NONE;
+}
+
+static void fill_data(struct gen12_block_copy_data *data,
+ const struct blt_copy_data *blt,
+ uint64_t src_offset, uint64_t dst_offset,
+ bool extended_command)
+{
+ data->dw00.client = 0x2;
+ data->dw00.opcode = 0x41;
+ data->dw00.color_depth = blt->color_depth;
+ data->dw00.special_mode = __special_mode(blt);
+ data->dw00.length = extended_command ? 20 : 10;
+
+ data->dw01.dst_pitch = blt->dst.pitch - 1;
+ data->dw01.dst_aux_mode = __aux_mode(&blt->dst);
+ data->dw01.dst_mocs = blt->dst.mocs;
+ data->dw01.dst_compression = blt->dst.compression;
+ data->dw01.dst_tiling = __block_tiling(blt->dst.tiling);
+
+ if (blt->dst.compression)
+ data->dw01.dst_ctrl_surface_type = blt->dst.compression_type;
+
+ data->dw02.dst_x1 = blt->dst.x1;
+ data->dw02.dst_y1 = blt->dst.y1;
+
+ data->dw03.dst_x2 = blt->dst.x2;
+ data->dw03.dst_y2 = blt->dst.y2;
+
+ data->dw04.dst_address_lo = dst_offset;
+ data->dw05.dst_address_hi = dst_offset >> 32;
+
+ data->dw06.dst_x_offset = blt->dst.x_offset;
+ data->dw06.dst_y_offset = blt->dst.y_offset;
+ data->dw06.dst_target_memory = __memory_type(blt->dst.region);
+
+ data->dw07.src_x1 = blt->src.x1;
+ data->dw07.src_y1 = blt->src.y1;
+
+ data->dw08.src_pitch = blt->src.pitch - 1;
+ data->dw08.src_aux_mode = __aux_mode(&blt->src);
+ data->dw08.src_mocs = blt->src.mocs;
+ data->dw08.src_compression = blt->src.compression;
+ data->dw08.src_tiling = __block_tiling(blt->src.tiling);
+
+ if (blt->src.compression)
+ data->dw08.src_ctrl_surface_type = blt->src.compression_type;
+
+ data->dw09.src_address_lo = src_offset;
+ data->dw10.src_address_hi = src_offset >> 32;
+
+ data->dw11.src_x_offset = blt->src.x_offset;
+ data->dw11.src_y_offset = blt->src.y_offset;
+ data->dw11.src_target_memory = __memory_type(blt->src.region);
+}
+
+static void fill_data_ext(int i915,
+ struct gen12_block_copy_data_ext *dext,
+ const struct blt_block_copy_data_ext *ext)
+{
+ dext->dw12.src_compression_format = ext->src.compression_format;
+ dext->dw12.src_clear_value_enable = ext->src.clear_value_enable;
+ dext->dw12.src_clear_address_low = ext->src.clear_address;
+
+ dext->dw13.src_clear_address_hi0 = ext->src.clear_address >> 32;
+
+ dext->dw14.dst_compression_format = ext->dst.compression_format;
+ dext->dw14.dst_clear_value_enable = ext->dst.clear_value_enable;
+ dext->dw14.dst_clear_address_low = ext->dst.clear_address;
+
+ dext->dw15.dst_clear_address_hi0 = ext->dst.clear_address >> 32;
+
+ dext->dw16.dst_surface_width = ext->dst.surface_width - 1;
+ dext->dw16.dst_surface_height = ext->dst.surface_height - 1;
+ dext->dw16.dst_surface_type = ext->dst.surface_type;
+
+ dext->dw17.dst_lod = ext->dst.lod;
+ dext->dw17.dst_surface_depth = ext->dst.surface_depth;
+ dext->dw17.dst_surface_qpitch = ext->dst.surface_qpitch;
+
+ dext->dw18.dst_horizontal_align = ext->dst.horizontal_align;
+ dext->dw18.dst_vertical_align = ext->dst.vertical_align;
+ dext->dw18.dst_mip_tail_start_lod = ext->dst.mip_tail_start_lod;
+ dext->dw18.dst_depth_stencil_resource = ext->dst.depth_stencil_resource;
+ dext->dw18.dst_array_index = ext->dst.array_index;
+
+ dext->dw19.src_surface_width = ext->src.surface_width - 1;
+ dext->dw19.src_surface_height = ext->src.surface_height - 1;
+
+ dext->dw19.src_surface_type = ext->src.surface_type;
+
+ dext->dw20.src_lod = ext->src.lod;
+ dext->dw20.src_surface_depth = ext->src.surface_depth;
+ dext->dw20.src_surface_qpitch = ext->src.surface_qpitch;
+
+ dext->dw21.src_horizontal_align = ext->src.horizontal_align;
+ dext->dw21.src_vertical_align = ext->src.vertical_align;
+ dext->dw21.src_mip_tail_start_lod = ext->src.mip_tail_start_lod;
+ dext->dw21.src_depth_stencil_resource = ext->src.depth_stencil_resource;
+ dext->dw21.src_array_index = ext->src.array_index;
+}
+
+static void dump_bb_cmd(struct gen12_block_copy_data *data)
+{
+ uint32_t *cmd = (uint32_t *) data;
+
+ igt_info("details:\n");
+ igt_info(" dw00: [%08x] <client: 0x%x, opcode: 0x%x, color depth: %d, "
+ "special mode: %d, length: %d>\n",
+ cmd[0],
+ data->dw00.client, data->dw00.opcode, data->dw00.color_depth,
+ data->dw00.special_mode, data->dw00.length);
+ igt_info(" dw01: [%08x] dst <pitch: %d, aux: %d, mocs: %d, compr: %d, "
+ "tiling: %d, ctrl surf type: %d>\n",
+ cmd[1], data->dw01.dst_pitch, data->dw01.dst_aux_mode,
+ data->dw01.dst_mocs, data->dw01.dst_compression,
+ data->dw01.dst_tiling, data->dw01.dst_ctrl_surface_type);
+ igt_info(" dw02: [%08x] dst geom <x1: %d, y1: %d>\n",
+ cmd[2], data->dw02.dst_x1, data->dw02.dst_y1);
+ igt_info(" dw03: [%08x] <x2: %d, y2: %d>\n",
+ cmd[3], data->dw03.dst_x2, data->dw03.dst_y2);
+ igt_info(" dw04: [%08x] dst offset lo (0x%x)\n",
+ cmd[4], data->dw04.dst_address_lo);
+ igt_info(" dw05: [%08x] dst offset hi (0x%x)\n",
+ cmd[5], data->dw05.dst_address_hi);
+ igt_info(" dw06: [%08x] dst <x offset: 0x%x, y offset: 0x%0x, target mem: %d>\n",
+ cmd[6], data->dw06.dst_x_offset, data->dw06.dst_y_offset,
+ data->dw06.dst_target_memory);
+ igt_info(" dw07: [%08x] src geom <x1: %d, y1: %d>\n",
+ cmd[7], data->dw07.src_x1, data->dw07.src_y1);
+ igt_info(" dw08: [%08x] src <pitch: %d, aux: %d, mocs: %d, compr: %d, "
+ "tiling: %d, ctrl surf type: %d>\n",
+ cmd[8], data->dw08.src_pitch, data->dw08.src_aux_mode,
+ data->dw08.src_mocs, data->dw08.src_compression,
+ data->dw08.src_tiling, data->dw08.src_ctrl_surface_type);
+ igt_info(" dw09: [%08x] src offset lo (0x%x)\n",
+ cmd[9], data->dw09.src_address_lo);
+ igt_info(" dw10: [%08x] src offset hi (0x%x)\n",
+ cmd[10], data->dw10.src_address_hi);
+ igt_info(" dw11: [%08x] src <x offset: 0x%x, y offset: 0x%0x, target mem: %d>\n",
+ cmd[11], data->dw11.src_x_offset, data->dw11.src_y_offset,
+ data->dw11.src_target_memory);
+}
+
+static void dump_bb_ext(struct gen12_block_copy_data_ext *data)
+{
+ uint32_t *cmd = (uint32_t *) data;
+
+ igt_info("ext details:\n");
+ igt_info(" dw12: [%08x] src <compression fmt: %d, clear value enable: %d, "
+ "clear address low: 0x%x>\n",
+ cmd[0],
+ data->dw12.src_compression_format,
+ data->dw12.src_clear_value_enable,
+ data->dw12.src_clear_address_low);
+ igt_info(" dw13: [%08x] src clear address hi: 0x%x\n",
+ cmd[1], data->dw13.src_clear_address_hi0);
+ igt_info(" dw14: [%08x] dst <compression fmt: %d, clear value enable: %d, "
+ "clear address low: 0x%x>\n",
+ cmd[2],
+ data->dw14.dst_compression_format,
+ data->dw14.dst_clear_value_enable,
+ data->dw14.dst_clear_address_low);
+ igt_info(" dw15: [%08x] dst clear address hi: 0x%x\n",
+ cmd[3], data->dw15.dst_clear_address_hi0);
+ igt_info(" dw16: [%08x] dst surface <width: %d, height: %d, type: %d>\n",
+ cmd[4], data->dw16.dst_surface_width,
+ data->dw16.dst_surface_height, data->dw16.dst_surface_type);
+ igt_info(" dw17: [%08x] dst surface <lod: %d, depth: %d, qpitch: %d>\n",
+ cmd[5], data->dw17.dst_lod,
+ data->dw17.dst_surface_depth, data->dw17.dst_surface_qpitch);
+ igt_info(" dw18: [%08x] dst <halign: %d, valign: %d, mip tail: %d, "
+ "depth stencil: %d, array index: %d>\n",
+ cmd[6],
+ data->dw18.dst_horizontal_align,
+ data->dw18.dst_vertical_align,
+ data->dw18.dst_mip_tail_start_lod,
+ data->dw18.dst_depth_stencil_resource,
+ data->dw18.dst_array_index);
+
+ igt_info(" dw19: [%08x] src surface <width: %d, height: %d, type: %d>\n",
+ cmd[7], data->dw19.src_surface_width,
+ data->dw19.src_surface_height, data->dw19.src_surface_type);
+ igt_info(" dw20: [%08x] src surface <lod: %d, depth: %d, qpitch: %d>\n",
+ cmd[8], data->dw20.src_lod,
+ data->dw20.src_surface_depth, data->dw20.src_surface_qpitch);
+ igt_info(" dw21: [%08x] src <halign: %d, valign: %d, mip tail: %d, "
+ "depth stencil: %d, array index: %d>\n",
+ cmd[9],
+ data->dw21.src_horizontal_align,
+ data->dw21.src_vertical_align,
+ data->dw21.src_mip_tail_start_lod,
+ data->dw21.src_depth_stencil_resource,
+ data->dw21.src_array_index);
+}
+
+int blt_block_copy(int i915,
+ const intel_ctx_t *ctx,
+ const struct intel_execution_engine2 *e,
+ uint64_t ahnd,
+ const struct blt_copy_data *blt,
+ const struct blt_block_copy_data_ext *ext)
+{
+ struct drm_i915_gem_execbuffer2 execbuf = {};
+ struct drm_i915_gem_exec_object2 obj[3] = {};
+ struct gen12_block_copy_data data = {};
+ struct gen12_block_copy_data_ext dext = {};
+ uint64_t dst_offset, src_offset, bb_offset, alignment;
+ uint32_t *bb;
+ int i, ret;
+
+ alignment = gem_detect_safe_alignment(i915);
+ src_offset = get_offset(ahnd, blt->src.handle, blt->src.size, alignment);
+ if (__special_mode(blt) == SM_FULL_RESOLVE)
+ dst_offset = src_offset;
+ else
+ dst_offset = get_offset(ahnd, blt->dst.handle, blt->dst.size, alignment);
+ bb_offset = get_offset(ahnd, blt->bb.handle, blt->bb.size, alignment);
+
+ fill_data(&data, blt, src_offset, dst_offset, ext);
+
+ i = sizeof(data) / sizeof(uint32_t);
+ bb = gem_mmap__device_coherent(i915, blt->bb.handle, 0, blt->bb.size,
+ PROT_READ | PROT_WRITE);
+ memcpy(bb, &data, sizeof(data));
+
+ if (ext) {
+ fill_data_ext(i915, &dext, ext);
+ memcpy(bb + i, &dext, sizeof(dext));
+ i += sizeof(dext) / sizeof(uint32_t);
+ }
+ bb[i++] = MI_BATCH_BUFFER_END;
+
+ if (blt->print_bb) {
+ igt_info("[BLOCK COPY]\n");
+ igt_info("src offset: %llx, dst offset: %llx, bb offset: %llx\n",
+ (long long) src_offset, (long long) dst_offset,
+ (long long) bb_offset);
+
+ dump_bb_cmd(&data);
+ if (ext)
+ dump_bb_ext(&dext);
+ }
+
+ munmap(bb, blt->bb.size);
+
+ obj[0].offset = CANONICAL(dst_offset);
+ obj[1].offset = CANONICAL(src_offset);
+ obj[2].offset = CANONICAL(bb_offset);
+ obj[0].handle = blt->dst.handle;
+ obj[1].handle = blt->src.handle;
+ obj[2].handle = blt->bb.handle;
+ obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
+ EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ execbuf.buffer_count = 3;
+ execbuf.buffers_ptr = to_user_pointer(obj);
+ execbuf.rsvd1 = ctx ? ctx->id : 0;
+ execbuf.flags = e ? e->flags : I915_EXEC_BLT;
+ ret = __gem_execbuf(i915, &execbuf);
+ if (data.dw00.special_mode != SM_FULL_RESOLVE)
+ put_offset(ahnd, blt->dst.handle);
+ put_offset(ahnd, blt->src.handle);
+ put_offset(ahnd, blt->bb.handle);
+
+ return ret;
+}
+
+static uint16_t __ccs_size(const struct blt_ctrl_surf_copy_data *surf)
+{
+ uint32_t src_size, dst_size;
+
+ src_size = surf->src.access_type == DIRECT_ACCESS ?
+ surf->src.size : surf->src.size / CCS_RATIO;
+
+ dst_size = surf->dst.access_type == DIRECT_ACCESS ?
+ surf->dst.size : surf->dst.size / CCS_RATIO;
+
+ igt_assert_f(src_size <= dst_size, "dst size must be >= src size for CCS copy\n");
+
+ return src_size;
+}
+
+struct gen12_ctrl_surf_copy_data {
+ struct {
+ uint32_t length: BITRANGE(0, 7);
+ uint32_t size_of_ctrl_copy: BITRANGE(8, 17);
+ uint32_t rsvd0: BITRANGE(18, 19);
+ uint32_t dst_access_type: BITRANGE(20, 20);
+ uint32_t src_access_type: BITRANGE(21, 21);
+ uint32_t opcode: BITRANGE(22, 28);
+ uint32_t client: BITRANGE(29, 31);
+ } dw00;
+
+ struct {
+ uint32_t src_address_lo;
+ } dw01;
+
+ struct {
+ uint32_t src_address_hi: BITRANGE(0, 24);
+ uint32_t src_mocs: BITRANGE(25, 31);
+ } dw02;
+
+ struct {
+ uint32_t dst_address_lo;
+ } dw03;
+
+ struct {
+ uint32_t dst_address_hi: BITRANGE(0, 24);
+ uint32_t dst_mocs: BITRANGE(25, 31);
+ } dw04;
+};
+
+static void dump_bb_surf_ctrl_cmd(const struct gen12_ctrl_surf_copy_data *data)
+{
+ uint32_t *cmd = (uint32_t *) data;
+
+ igt_info("details:\n");
+ igt_info(" dw00: [%08x] <client: 0x%x, opcode: 0x%x, "
+ "src/dst access type: <%d, %d>, size of ctrl copy: %u, length: %d>\n",
+ cmd[0],
+ data->dw00.client, data->dw00.opcode,
+ data->dw00.src_access_type, data->dw00.dst_access_type,
+ data->dw00.size_of_ctrl_copy, data->dw00.length);
+ igt_info(" dw01: [%08x] src offset lo (0x%x)\n",
+ cmd[1], data->dw01.src_address_lo);
+ igt_info(" dw02: [%08x] src offset hi (0x%x), src mocs: %u\n",
+ cmd[2], data->dw02.src_address_hi, data->dw02.src_mocs);
+ igt_info(" dw03: [%08x] dst offset lo (0x%x)\n",
+ cmd[3], data->dw03.dst_address_lo);
+ igt_info(" dw04: [%08x] dst offset hi (0x%x), src mocs: %u\n",
+ cmd[4], data->dw04.dst_address_hi, data->dw04.dst_mocs);
+}
+
+int blt_ctrl_surf_copy(int i915,
+ const intel_ctx_t *ctx,
+ const struct intel_execution_engine2 *e,
+ uint64_t ahnd,
+ const struct blt_ctrl_surf_copy_data *surf)
+{
+ struct drm_i915_gem_execbuffer2 execbuf = {};
+ struct drm_i915_gem_exec_object2 obj[3] = {};
+ struct gen12_ctrl_surf_copy_data data = {};
+ uint64_t dst_offset, src_offset, bb_offset, alignment;
+ uint32_t *bb;
+ int i;
+
+ alignment = gem_detect_safe_alignment(i915);
+
+ data.dw00.client = 0x2;
+ data.dw00.opcode = 0x48;
+ data.dw00.src_access_type = surf->src.access_type;
+ data.dw00.dst_access_type = surf->dst.access_type;
+
+ /* Ensure dst has size capable to keep src ccs aux */
+ data.dw00.size_of_ctrl_copy = __ccs_size(surf) / CCS_RATIO - 1;
+ data.dw00.length = 0x3;
+
+ src_offset = get_offset(ahnd, surf->src.handle, surf->src.size,
+ alignment);
+ dst_offset = get_offset(ahnd, surf->dst.handle, surf->dst.size,
+ alignment);
+ bb_offset = get_offset(ahnd, surf->bb.handle, surf->bb.size,
+ alignment);
+
+ data.dw01.src_address_lo = src_offset;
+ data.dw02.src_address_hi = src_offset >> 32;
+ data.dw02.src_mocs = surf->src.mocs;
+
+ data.dw03.dst_address_lo = dst_offset;
+ data.dw04.dst_address_hi = dst_offset >> 32;
+ data.dw04.dst_mocs = surf->dst.mocs;
+
+ i = sizeof(data) / sizeof(uint32_t);
+ bb = gem_mmap__device_coherent(i915, surf->bb.handle, 0, surf->bb.size,
+ PROT_READ | PROT_WRITE);
+ memcpy(bb, &data, sizeof(data));
+ bb[i++] = MI_BATCH_BUFFER_END;
+
+ if (surf->print_bb) {
+ igt_info("BB [CTRL SURF]:\n");
+ igt_info("src offset: %llx, dst offset: %llx, bb offset: %llx\n",
+ (long long) src_offset, (long long) dst_offset,
+ (long long) bb_offset);
+
+ dump_bb_surf_ctrl_cmd(&data);
+ }
+ munmap(bb, surf->bb.size);
+
+ obj[0].offset = CANONICAL(dst_offset);
+ obj[1].offset = CANONICAL(src_offset);
+ obj[2].offset = CANONICAL(bb_offset);
+ obj[0].handle = surf->dst.handle;
+ obj[1].handle = surf->src.handle;
+ obj[2].handle = surf->bb.handle;
+ obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
+ EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ execbuf.buffer_count = 3;
+ execbuf.buffers_ptr = to_user_pointer(obj);
+ execbuf.flags = e ? e->flags : I915_EXEC_BLT;
+ execbuf.rsvd1 = ctx ? ctx->id : 0;
+ gem_execbuf(i915, &execbuf);
+ put_offset(ahnd, surf->dst.handle);
+ put_offset(ahnd, surf->src.handle);
+ put_offset(ahnd, surf->bb.handle);
+
+ return 0;
+}
+
+struct gen12_fast_copy_data {
+ struct {
+ uint32_t length: BITRANGE(0, 7);
+ uint32_t rsvd1: BITRANGE(8, 12);
+ uint32_t dst_tiling: BITRANGE(13, 14);
+ uint32_t rsvd0: BITRANGE(15, 19);
+ uint32_t src_tiling: BITRANGE(20, 21);
+ uint32_t opcode: BITRANGE(22, 28);
+ uint32_t client: BITRANGE(29, 31);
+ } dw00;
+
+ struct {
+ uint32_t dst_pitch: BITRANGE(0, 15);
+ uint32_t rsvd1: BITRANGE(16, 23);
+ uint32_t color_depth: BITRANGE(24, 26);
+ uint32_t rsvd0: BITRANGE(27, 27);
+ uint32_t dst_memory: BITRANGE(28, 28);
+ uint32_t src_memory: BITRANGE(29, 29);
+ uint32_t dst_type_y: BITRANGE(30, 30);
+ uint32_t src_type_y: BITRANGE(31, 31);
+ } dw01;
+
+ struct {
+ int32_t dst_x1: BITRANGE(0, 15);
+ int32_t dst_y1: BITRANGE(16, 31);
+ } dw02;
+
+ struct {
+ int32_t dst_x2: BITRANGE(0, 15);
+ int32_t dst_y2: BITRANGE(16, 31);
+ } dw03;
+
+ struct {
+ uint32_t dst_address_lo;
+ } dw04;
+
+ struct {
+ uint32_t dst_address_hi;
+ } dw05;
+
+ struct {
+ int32_t src_x1: BITRANGE(0, 15);
+ int32_t src_y1: BITRANGE(16, 31);
+ } dw06;
+
+ struct {
+ uint32_t src_pitch: BITRANGE(0, 15);
+ uint32_t rsvd0: BITRANGE(16, 31);
+ } dw07;
+
+ struct {
+ uint32_t src_address_lo;
+ } dw08;
+
+ struct {
+ uint32_t src_address_hi;
+ } dw09;
+};
+
+static int __fast_tiling(enum blt_tiling tiling)
+{
+ switch (tiling) {
+ case T_LINEAR: return 0;
+ case T_XMAJOR: return 1;
+ case T_YMAJOR: return 2;
+ case T_TILE4: return 2;
+ case T_TILE64: return 3;
+ }
+ return 0;
+}
+
+static int __fast_color_depth(enum blt_color_depth depth)
+{
+ switch (depth) {
+ case CD_8bit: return 0;
+ case CD_16bit: return 1;
+ case CD_32bit: return 3;
+ case CD_64bit: return 4;
+ case CD_96bit:
+ igt_assert_f(0, "Unsupported depth\n");
+ break;
+ case CD_128bit: return 5;
+ };
+ return 0;
+}
+
+static void dump_bb_fast_cmd(struct gen12_fast_copy_data *data)
+{
+ uint32_t *cmd = (uint32_t *) data;
+
+ igt_info("BB details:\n");
+ igt_info(" dw00: [%08x] <client: 0x%x, opcode: 0x%x, src tiling: %d, "
+ "dst tiling: %d, length: %d>\n",
+ cmd[0], data->dw00.client, data->dw00.opcode,
+ data->dw00.src_tiling, data->dw00.dst_tiling, data->dw00.length);
+ igt_info(" dw01: [%08x] dst <pitch: %d, color depth: %d, dst memory: %d, "
+ "src memory: %d, \n"
+ "\t\t\tdst type tile: %d (0-legacy, 1-tile4),\n"
+ "\t\t\tsrc type tile: %d (0-legacy, 1-tile4)>\n",
+ cmd[1], data->dw01.dst_pitch, data->dw01.color_depth,
+ data->dw01.dst_memory, data->dw01.src_memory,
+ data->dw01.dst_type_y, data->dw01.src_type_y);
+ igt_info(" dw02: [%08x] dst geom <x1: %d, y1: %d>\n",
+ cmd[2], data->dw02.dst_x1, data->dw02.dst_y1);
+ igt_info(" dw03: [%08x] <x2: %d, y2: %d>\n",
+ cmd[3], data->dw03.dst_x2, data->dw03.dst_y2);
+ igt_info(" dw04: [%08x] dst offset lo (0x%x)\n",
+ cmd[4], data->dw04.dst_address_lo);
+ igt_info(" dw05: [%08x] dst offset hi (0x%x)\n",
+ cmd[5], data->dw05.dst_address_hi);
+ igt_info(" dw06: [%08x] src geom <x1: %d, y1: %d>\n",
+ cmd[6], data->dw06.src_x1, data->dw06.src_y1);
+ igt_info(" dw07: [%08x] src <pitch: %d>\n",
+ cmd[7], data->dw07.src_pitch);
+ igt_info(" dw08: [%08x] src offset lo (0x%x)\n",
+ cmd[8], data->dw08.src_address_lo);
+ igt_info(" dw09: [%08x] src offset hi (0x%x)\n",
+ cmd[9], data->dw09.src_address_hi);
+}
+
+#define BCS_SWCTRL 0x22200
+#define BCS_SRC_Y (1 << 0)
+#define BCS_DST_Y (1 << 1)
+int blt_fast_copy(int i915,
+ const intel_ctx_t *ctx,
+ const struct intel_execution_engine2 *e,
+ uint64_t ahnd,
+ const struct blt_copy_data *blt)
+{
+ struct drm_i915_gem_execbuffer2 execbuf = {};
+ struct drm_i915_gem_exec_object2 obj[3] = {};
+ struct gen12_fast_copy_data data = {};
+ uint64_t dst_offset, src_offset, bb_offset, alignment;
+ uint32_t *bb;
+ int i, ret;
+
+ alignment = gem_detect_safe_alignment(i915);
+
+ data.dw00.client = 0x2;
+ data.dw00.opcode = 0x42;
+ data.dw00.dst_tiling = __fast_tiling(blt->dst.tiling);
+ data.dw00.src_tiling = __fast_tiling(blt->src.tiling);
+ data.dw00.length = 8;
+
+ data.dw01.dst_pitch = blt->dst.pitch;
+ data.dw01.color_depth = __fast_color_depth(blt->color_depth);
+ data.dw01.dst_memory = __memory_type(blt->dst.region);
+ data.dw01.src_memory = __memory_type(blt->src.region);
+ data.dw01.dst_type_y = blt->dst.tiling == T_TILE4 ? 1 : 0;
+ data.dw01.src_type_y = blt->src.tiling == T_TILE4 ? 1 : 0;
+
+ data.dw02.dst_x1 = blt->dst.x1;
+ data.dw02.dst_y1 = blt->dst.y1;
+
+ data.dw03.dst_x2 = blt->dst.x2;
+ data.dw03.dst_y2 = blt->dst.y2;
+
+ src_offset = get_offset(ahnd, blt->src.handle, blt->src.size, alignment);
+ dst_offset = get_offset(ahnd, blt->dst.handle, blt->dst.size, alignment);
+ bb_offset = get_offset(ahnd, blt->bb.handle, blt->bb.size, alignment);
+
+ data.dw04.dst_address_lo = dst_offset;
+ data.dw05.dst_address_hi = dst_offset >> 32;
+
+ data.dw06.src_x1 = blt->src.x1;
+ data.dw06.src_y1 = blt->src.y1;
+
+ data.dw07.src_pitch = blt->src.pitch;
+
+ data.dw08.src_address_lo = src_offset;
+ data.dw09.src_address_hi = src_offset >> 32;
+
+ i = sizeof(data) / sizeof(uint32_t);
+ bb = gem_mmap__device_coherent(i915, blt->bb.handle, 0, blt->bb.size,
+ PROT_READ | PROT_WRITE);
+
+ memcpy(bb, &data, sizeof(data));
+ bb[i++] = MI_BATCH_BUFFER_END;
+
+ if (blt->print_bb) {
+ igt_info("BB [FAST COPY]\n");
+ igt_info("blit [src offset: %llx, dst offset: %llx\n",
+ (long long) src_offset, (long long) dst_offset);
+ dump_bb_fast_cmd(&data);
+ }
+
+ munmap(bb, blt->bb.size);
+
+ obj[0].offset = CANONICAL(dst_offset);
+ obj[1].offset = CANONICAL(src_offset);
+ obj[2].offset = CANONICAL(bb_offset);
+ obj[0].handle = blt->dst.handle;
+ obj[1].handle = blt->src.handle;
+ obj[2].handle = blt->bb.handle;
+ obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
+ EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ execbuf.buffer_count = 3;
+ execbuf.buffers_ptr = to_user_pointer(obj);
+ execbuf.rsvd1 = ctx ? ctx->id : 0;
+ execbuf.flags = e ? e->flags : I915_EXEC_BLT;
+ ret = __gem_execbuf(i915, &execbuf);
+ put_offset(ahnd, blt->dst.handle);
+ put_offset(ahnd, blt->src.handle);
+ put_offset(ahnd, blt->bb.handle);
+
+ return ret;
+}
+
+void blt_surface_fill_rect(int i915, const struct blt_copy_object *obj,
+ uint32_t width, uint32_t height)
+{
+ cairo_surface_t *surface;
+ cairo_pattern_t *pat;
+ cairo_t *cr;
+ void *map = obj->ptr;
+
+ if (!map)
+ map = gem_mmap__device_coherent(i915, obj->handle, 0,
+ obj->size, PROT_READ | PROT_WRITE);
+
+ surface = cairo_image_surface_create_for_data(map,
+ CAIRO_FORMAT_RGB24,
+ width, height,
+ obj->pitch);
+
+ cr = cairo_create(surface);
+
+ cairo_rectangle(cr, 0, 0, width, height);
+ cairo_clip(cr);
+
+ pat = cairo_pattern_create_mesh();
+ cairo_mesh_pattern_begin_patch(pat);
+ cairo_mesh_pattern_move_to(pat, 0, 0);
+ cairo_mesh_pattern_line_to(pat, width, 0);
+ cairo_mesh_pattern_line_to(pat, width, height);
+ cairo_mesh_pattern_line_to(pat, 0, height);
+ cairo_mesh_pattern_set_corner_color_rgb(pat, 0, 1.0, 0.0, 0.0);
+ cairo_mesh_pattern_set_corner_color_rgb(pat, 1, 0.0, 1.0, 0.0);
+ cairo_mesh_pattern_set_corner_color_rgb(pat, 2, 0.0, 0.0, 1.0);
+ cairo_mesh_pattern_set_corner_color_rgb(pat, 3, 1.0, 1.0, 1.0);
+ cairo_mesh_pattern_end_patch(pat);
+
+ cairo_rectangle(cr, 0, 0, width, height);
+ cairo_set_source(cr, pat);
+ cairo_fill(cr);
+ cairo_pattern_destroy(pat);
+
+ cairo_destroy(cr);
+
+ cairo_surface_destroy(surface);
+ if (!obj->ptr)
+ munmap(map, obj->size);
+}
+
+void blt_surface_info(const char *info, const struct blt_copy_object *obj)
+{
+ igt_info("[%s]\n", info);
+ igt_info("surface <handle: %u, size: %llx, region: %x, mocs: %x>\n",
+ obj->handle, (long long) obj->size, obj->region, obj->mocs);
+ igt_info(" <tiling: %s, compression: %u, compression type: %d>\n",
+ blt_tiling_name(obj->tiling), obj->compression, obj->compression_type);
+ igt_info(" <pitch: %u, offset [x: %u, y: %u] geom [<%d,%d> <%d,%d>]>\n",
+ obj->pitch, obj->x_offset, obj->y_offset,
+ obj->x1, obj->y1, obj->x2, obj->y2);
+}
+
+void blt_surface_to_png(int i915, uint32_t run_id, const char *fileid,
+ const struct blt_copy_object *obj,
+ uint32_t width, uint32_t height)
+{
+ cairo_surface_t *surface;
+ cairo_status_t ret;
+ uint8_t *map = (uint8_t *) obj->ptr;
+ int format;
+ int stride = obj->tiling ? obj->pitch * 4 : obj->pitch;
+ char filename[FILENAME_MAX];
+
+ snprintf(filename, FILENAME_MAX-1, "%d-%s-%s-%ux%u-%s.png",
+ run_id, fileid, blt_tiling_name(obj->tiling), width, height,
+ obj->compression ? "compressed" : "uncompressed");
+
+ if (!map)
+ map = gem_mmap__device_coherent(i915, obj->handle, 0,
+ obj->size, PROT_READ);
+ format = CAIRO_FORMAT_RGB24;
+ surface = cairo_image_surface_create_for_data(map,
+ format, width, height,
+ stride);
+ ret = cairo_surface_write_to_png(surface, filename);
+ if (ret)
+ igt_info("Cairo ret: %d (%s)\n", ret, cairo_status_to_string(ret));
+ igt_assert(ret == CAIRO_STATUS_SUCCESS);
+ cairo_surface_destroy(surface);
+
+ if (!obj->ptr)
+ munmap(map, obj->size);
+}
diff --git a/lib/i915/i915_blt.h b/lib/i915/i915_blt.h
new file mode 100644
index 000000000000..2f4198e8acde
--- /dev/null
+++ b/lib/i915/i915_blt.h
@@ -0,0 +1,157 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include <errno.h>
+#include <sys/ioctl.h>
+#include <sys/time.h>
+#include <malloc.h>
+#include "drm.h"
+#include "igt.h"
+
+#define CCS_RATIO 256
+
+enum blt_color_depth {
+ CD_8bit,
+ CD_16bit,
+ CD_32bit,
+ CD_64bit,
+ CD_96bit,
+ CD_128bit,
+};
+
+enum blt_tiling {
+ T_LINEAR,
+ T_XMAJOR,
+ T_YMAJOR,
+ T_TILE4,
+ T_TILE64,
+};
+
+enum blt_compression {
+ COMPRESSION_DISABLED,
+ COMPRESSION_ENABLED,
+};
+
+enum blt_compression_type {
+ COMPRESSION_TYPE_3D,
+ COMPRESSION_TYPE_MEDIA,
+};
+
+struct blt_copy_object {
+ uint32_t handle;
+ uint32_t region;
+ uint64_t size;
+ uint8_t mocs;
+ enum blt_tiling tiling;
+ enum blt_compression compression;
+ enum blt_compression_type compression_type;
+ uint32_t pitch;
+ uint16_t x_offset, y_offset;
+ int16_t x1, y1, x2, y2;
+
+ /* mapping or null */
+ uint32_t *ptr;
+};
+
+struct blt_copy_batch {
+ uint32_t handle;
+ uint32_t region;
+ uint64_t size;
+};
+
+/* Common for block-copy and fast-copy */
+struct blt_copy_data {
+ int i915;
+ struct blt_copy_object src;
+ struct blt_copy_object dst;
+ struct blt_copy_batch bb;
+ enum blt_color_depth color_depth;
+
+ /* debug stuff */
+ bool print_bb;
+};
+
+enum blt_surface_type {
+ SURFACE_TYPE_1D,
+ SURFACE_TYPE_2D,
+ SURFACE_TYPE_3D,
+ SURFACE_TYPE_CUBE,
+};
+
+struct blt_block_copy_object_ext {
+ uint8_t compression_format;
+ bool clear_value_enable;
+ uint64_t clear_address;
+ uint16_t surface_width;
+ uint16_t surface_height;
+ enum blt_surface_type surface_type;
+ uint16_t surface_qpitch;
+ uint16_t surface_depth;
+ uint8_t lod;
+ uint8_t horizontal_align;
+ uint8_t vertical_align;
+ uint8_t mip_tail_start_lod;
+ bool depth_stencil_resource;
+ uint16_t array_index;
+};
+
+struct blt_block_copy_data_ext {
+ struct blt_block_copy_object_ext src;
+ struct blt_block_copy_object_ext dst;
+};
+
+enum blt_access_type {
+ INDIRECT_ACCESS,
+ DIRECT_ACCESS,
+};
+
+struct blt_ctrl_surf_copy_object {
+ uint32_t handle;
+ uint32_t region;
+ uint64_t size;
+ uint8_t mocs;
+ enum blt_access_type access_type;
+};
+
+struct blt_ctrl_surf_copy_data {
+ int i915;
+ struct blt_ctrl_surf_copy_object src;
+ struct blt_ctrl_surf_copy_object dst;
+ struct blt_copy_batch bb;
+
+ /* debug stuff */
+ bool print_bb;
+};
+
+bool blt_supports_compression(int i915);
+bool blt_supports_tiling(int i915, enum blt_tiling tiling);
+const char *blt_tiling_name(enum blt_tiling tiling);
+
+int blt_block_copy(int i915,
+ const intel_ctx_t *ctx,
+ const struct intel_execution_engine2 *e,
+ uint64_t ahnd,
+ const struct blt_copy_data *blt,
+ const struct blt_block_copy_data_ext *ext);
+
+int blt_ctrl_surf_copy(int i915,
+ const intel_ctx_t *ctx,
+ const struct intel_execution_engine2 *e,
+ uint64_t ahnd,
+ const struct blt_ctrl_surf_copy_data *surf);
+
+int blt_fast_copy(int i915,
+ const intel_ctx_t *ctx,
+ const struct intel_execution_engine2 *e,
+ uint64_t ahnd,
+ const struct blt_copy_data *blt);
+
+void blt_surface_info(const char *info,
+ const struct blt_copy_object *obj);
+void blt_surface_fill_rect(int i915, const struct blt_copy_object *obj,
+ uint32_t width, uint32_t height);
+void blt_surface_to_png(int i915, uint32_t run_id, const char *fileid,
+ const struct blt_copy_object *obj,
+ uint32_t width, uint32_t height);
diff --git a/lib/meson.build b/lib/meson.build
index 3e43316d1e36..fe035672e2c5 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -11,6 +11,7 @@ lib_sources = [
'i915/gem_mman.c',
'i915/gem_vm.c',
'i915/intel_memory_region.c',
+ 'i915/i915_blt.c',
'igt_collection.c',
'igt_color_encoding.c',
'igt_debugfs.c',
--
2.20.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [igt-dev] [PATCH i-g-t v2 3/3] tests/i915/gem_lmem_swapping: ccs subtests
2022-03-01 21:25 [igt-dev] [PATCH i-g-t v2 0/3] tests/i915: ccs subtests for gem_lmem_swapping Ramalingam C
2022-03-01 21:25 ` [igt-dev] [PATCH i-g-t v2 1/3] i915/gem_engine_topology: Only use the main copy engines for XY_BLOCK_COPY Ramalingam C
2022-03-01 21:25 ` [igt-dev] [PATCH i-g-t v2 2/3] lib/i915_blt: Add library for blitter Ramalingam C
@ 2022-03-01 21:25 ` Ramalingam C
2022-03-02 4:49 ` Zbigniew Kempczyński
2022-03-01 22:02 ` [igt-dev] ✗ GitLab.Pipeline: warning for tests/i915: ccs subtests for gem_lmem_swapping (rev3) Patchwork
` (2 subsequent siblings)
5 siblings, 1 reply; 8+ messages in thread
From: Ramalingam C @ 2022-03-01 21:25 UTC (permalink / raw)
To: igt-dev
Subtests for covering the compressed object's eviction are added.
v2:
gem_sync after the block_copy blit for init
Signed-off-by: Chris Wilson <chris.p.wilson@intel.com>
Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
tests/i915/gem_lmem_swapping.c | 217 ++++++++++++++++++++++++++++++++-
1 file changed, 212 insertions(+), 5 deletions(-)
diff --git a/tests/i915/gem_lmem_swapping.c b/tests/i915/gem_lmem_swapping.c
index 39f9e1f536dd..574fe5030cd5 100644
--- a/tests/i915/gem_lmem_swapping.c
+++ b/tests/i915/gem_lmem_swapping.c
@@ -22,6 +22,7 @@
#include <sys/time.h>
#include <sys/wait.h>
#include "drm.h"
+#include "i915/i915_blt.h"
IGT_TEST_DESCRIPTION("Exercise local memory swapping.");
@@ -30,6 +31,7 @@ IGT_TEST_DESCRIPTION("Exercise local memory swapping.");
#define PAGE_SIZE (1ULL << 12)
#define SZ_64K (16 * PAGE_SIZE)
+#define DG2_MOCS (2 << 1)
static const char *readable_unit(uint64_t size)
{
@@ -60,6 +62,7 @@ struct params {
#define TEST_RANDOM (1 << 3)
#define TEST_ENGINES (1 << 4)
#define TEST_MULTI (1 << 5)
+#define TEST_CCS (1 << 6)
unsigned int flags;
unsigned int seed;
bool oom_test;
@@ -69,8 +72,56 @@ struct object {
uint64_t size;
uint32_t seed;
uint32_t handle;
+ struct blt_copy_object *blt_obj;
};
+static void set_object(struct blt_copy_object *obj,
+ uint32_t handle, uint64_t size, uint32_t region,
+ uint8_t mocs, enum blt_tiling tiling,
+ enum blt_compression compression,
+ enum blt_compression_type compression_type)
+{
+ obj->handle = handle;
+ obj->size = size;
+ obj->region = region;
+ obj->mocs = mocs;
+ obj->tiling = tiling;
+ obj->compression = compression;
+ obj->compression_type = compression_type;
+}
+
+static void set_geom(struct blt_copy_object *obj, uint32_t pitch,
+ int16_t x1, int16_t y1, int16_t x2, int16_t y2,
+ uint16_t x_offset, uint16_t y_offset)
+{
+ obj->pitch = pitch;
+ obj->x1 = x1;
+ obj->y1 = y1;
+ obj->x2 = x2;
+ obj->y2 = y2;
+ obj->x_offset = x_offset;
+ obj->y_offset = y_offset;
+}
+
+static void set_batch(struct blt_copy_batch *batch,
+ uint32_t handle, uint64_t size, uint32_t region)
+{
+ batch->handle = handle;
+ batch->size = size;
+ batch->region = region;
+}
+
+static void set_object_ext(struct blt_block_copy_object_ext *obj,
+ uint8_t compression_format,
+ uint16_t surface_width, uint16_t surface_height,
+ enum blt_surface_type surface_type)
+{
+ obj->compression_format = compression_format;
+ obj->surface_width = surface_width;
+ obj->surface_height = surface_height;
+ obj->surface_type = surface_type;
+}
+
static uint32_t create_bo(int i915,
uint64_t size,
struct drm_i915_gem_memory_class_instance *region,
@@ -105,6 +156,51 @@ init_object(int i915, struct object *obj, unsigned long seed, unsigned int flags
munmap(buf, obj->size);
}
+#define BATCH_SIZE 4096
+static void
+init_object_ccs(int i915, struct object *obj, struct blt_copy_object *tmp,
+ struct blt_copy_object *cmd, unsigned long seed,
+ unsigned int flags, const intel_ctx_t *ctx, uint32_t region)
+{
+ uint64_t ahnd = intel_allocator_open_full(i915, ctx->id, 0, 0,
+ INTEL_ALLOCATOR_SIMPLE,
+ ALLOC_STRATEGY_LOW_TO_HIGH, 0);
+ struct blt_block_copy_data_ext ext = {}, *pext = &ext;
+ const struct intel_execution_engine2 *e;
+ struct blt_copy_data blt = {};
+ unsigned long *buf, j;
+
+ obj->seed = seed;
+
+ for_each_ctx_engine(i915, ctx, e) {
+ igt_assert_f(gem_engine_can_block_copy(i915, e),
+ "Ctx dont have Blt engine");
+ break;
+ }
+
+ buf = gem_mmap__device_coherent(i915, tmp->handle, 0, obj->size, PROT_WRITE);
+ gem_set_domain(i915, tmp->handle, I915_GEM_DOMAIN_WC, I915_GEM_DOMAIN_WC);
+
+ for (j = 0; j < obj->size / sizeof(*buf); j++)
+ buf[j] = seed++;
+ munmap(buf, obj->size);
+
+ memset(&blt, 0, sizeof(blt));
+ blt.color_depth = CD_32bit;
+
+ memcpy(&blt.src, tmp, sizeof(blt.src));
+ memcpy(&blt.dst, obj->blt_obj, sizeof(blt.dst));
+
+ set_object_ext(&ext.src, 0, tmp->x2, tmp->y2, SURFACE_TYPE_2D);
+ set_object_ext(&ext.dst, 0, obj->blt_obj->x2, obj->blt_obj->y2,
+ SURFACE_TYPE_2D);
+
+ set_batch(&blt.bb, cmd->handle, BATCH_SIZE, region);
+ blt_block_copy(i915, ctx, e, ahnd, &blt, pext);
+ gem_sync(i915, obj->blt_obj->handle);
+ put_ahnd(ahnd);
+}
+
static void
verify_object(int i915, const struct object *obj, unsigned int flags)
{
@@ -125,6 +221,56 @@ verify_object(int i915, const struct object *obj, unsigned int flags)
munmap(buf, obj->size);
}
+static void
+verify_object_ccs(int i915, const struct object *obj,
+ struct blt_copy_object *tmp,
+ struct blt_copy_object *cmd, unsigned int flags,
+ const intel_ctx_t *ctx, uint32_t region)
+{
+ uint64_t ahnd = intel_allocator_open_full(i915, ctx->id, 0, 0,
+ INTEL_ALLOCATOR_SIMPLE,
+ ALLOC_STRATEGY_LOW_TO_HIGH, 0);
+ struct blt_block_copy_data_ext ext = {}, *pext = &ext;
+ const struct intel_execution_engine2 *e;
+ struct blt_copy_data blt = {};
+ unsigned long j, val, *buf;
+
+ for_each_ctx_engine(i915, ctx, e) {
+ igt_assert_f(gem_engine_can_block_copy(i915, e),
+ "ctx dont have Blt engine");
+ break;
+ }
+
+ memset(&blt, 0, sizeof(blt));
+ blt.color_depth = CD_32bit;
+
+ memcpy(&blt.src, obj->blt_obj, sizeof(blt.src));
+ memcpy(&blt.dst, tmp, sizeof(blt.dst));
+
+ set_object_ext(&ext.src, 0, obj->blt_obj->x2, obj->blt_obj->y2,
+ SURFACE_TYPE_2D);
+ set_object_ext(&ext.dst, 0, tmp->x2, tmp->y2, SURFACE_TYPE_2D);
+ set_batch(&blt.bb, cmd->handle, BATCH_SIZE, region);
+
+ blt_block_copy(i915, ctx, e, ahnd, &blt, pext);
+ put_ahnd(ahnd);
+
+ buf = gem_mmap__device_coherent(i915, tmp->handle, 0,
+ obj->size, PROT_READ);
+ gem_set_domain(i915, tmp->handle, I915_GEM_DOMAIN_WC, 0);
+
+ for (j = 0; j < obj->size / PAGE_SIZE; j++) {
+ unsigned long x = (j * PAGE_SIZE + rand() % PAGE_SIZE) / sizeof(*buf);
+
+ val = obj->seed + x;
+ igt_assert_f(buf[x] == val,
+ "Object mismatch at offset %lu - found %lx, expected %lx, difference:%lx!\n",
+ x * sizeof(*buf), buf[x], val, buf[x] ^ val);
+ }
+
+ munmap(buf, obj->size);
+}
+
static void move_to_lmem(int i915,
struct object *list,
unsigned int num,
@@ -160,22 +306,36 @@ static void __do_evict(int i915,
struct params *params,
unsigned int seed)
{
+ uint32_t region_id = INTEL_MEMORY_REGION_ID(region->memory_class,
+ region->memory_instance);
const unsigned int max_swap_in = params->count / 100 + 1;
const uint32_t bbe = MI_BATCH_BUFFER_END;
struct object *objects, *obj, *list;
- uint32_t batch;
+ const uint32_t bpp = 32;
+ uint32_t batch, width, height, stride;
+ const intel_ctx_t *blt_ctx;
+ struct blt_copy_object *tmp, *cmd;
unsigned int engine = 0;
unsigned int i, l;
uint64_t size;
struct timespec t = {};
unsigned int num;
+ width = PAGE_SIZE / (bpp / 8);
+ height = params->size.max / (bpp / 8) / width;
+ stride = width * 4;
+
+ tmp = calloc(1, sizeof(*tmp));
+ cmd = calloc(1, sizeof(*cmd));
+
__gem_context_set_persistence(i915, 0, false);
size = 4096;
batch = create_bo(i915, size, region, params->oom_test);
-
gem_write(i915, batch, 0, &bbe, sizeof(bbe));
+ if (params->flags & TEST_CCS)
+ blt_ctx = intel_ctx_create_for_engine(i915, I915_ENGINE_CLASS_COPY, 0);
+
objects = calloc(params->count, sizeof(*objects));
igt_assert(objects);
@@ -185,6 +345,18 @@ static void __do_evict(int i915,
srand(seed);
/* Create the initial working set of objects. */
+ if (params->flags & TEST_CCS) {
+ tmp->handle = gem_create_in_memory_regions(i915, params->size.max,
+ INTEL_MEMORY_REGION_ID(I915_SYSTEM_MEMORY, 0));
+ set_object(tmp, tmp->handle, params->size.max,
+ INTEL_MEMORY_REGION_ID(I915_SYSTEM_MEMORY, 0), DG2_MOCS,
+ T_LINEAR, COMPRESSION_DISABLED, COMPRESSION_TYPE_3D);
+ set_geom(tmp, stride, 0, 0, width, height, 0, 0);
+ cmd->handle = gem_create_in_memory_regions(i915, BATCH_SIZE, region_id);
+ set_object(cmd, cmd->handle, BATCH_SIZE, region_id, DG2_MOCS,
+ T_LINEAR, COMPRESSION_DISABLED, COMPRESSION_TYPE_3D);
+ }
+
size = 0;
for (i = 0, obj = objects; i < params->count; i++, obj++) {
if (params->flags & TEST_RANDOM)
@@ -201,11 +373,24 @@ static void __do_evict(int i915,
}
obj->handle = create_bo(i915, obj->size, region, params->oom_test);
- if (params->flags & TEST_VERIFY)
+ if (params->flags & TEST_CCS) {
+ width = PAGE_SIZE / (bpp / 8);
+ height = obj->size / (bpp / 8) / width;
+ stride = width * 4;
+
+ obj->blt_obj = calloc(1, sizeof(*obj->blt_obj));
+ set_object(obj->blt_obj, obj->handle, obj->size, region_id,
+ DG2_MOCS, T_LINEAR, COMPRESSION_ENABLED,
+ COMPRESSION_TYPE_3D);
+ set_geom(obj->blt_obj, stride, 0, 0, width, height, 0, 0);
+ init_object_ccs(i915, obj, tmp, cmd, rand(),
+ params->flags, blt_ctx, region_id);
+ } else if (params->flags & TEST_VERIFY) {
init_object(i915, obj, rand(), params->flags);
- else
+ } else {
move_to_lmem(i915, objects + i, 1, batch, engine,
params->oom_test);
+ }
}
igt_debug("obj size min/max=%lu %s/%lu %s, count=%u, seed: %u\n",
@@ -232,7 +417,16 @@ static void __do_evict(int i915,
if (params->flags & TEST_ENGINES)
engine = (engine + 1) % __num_engines__;
- if (params->flags & TEST_VERIFY) {
+ if (params->flags & TEST_CCS) {
+ for (i = 0; i < num; i++)
+ verify_object_ccs(i915, &list[i], tmp,
+ cmd, params->flags, blt_ctx,
+ region_id);
+ /* Update random object - may swap it back in. */
+ i = rand() % params->count;
+ init_object_ccs(i915, &objects[i], tmp, cmd, rand(),
+ params->flags, blt_ctx, region_id);
+ } else if (params->flags & TEST_VERIFY) {
for (i = 0; i < num; i++)
verify_object(i915, &list[i], params->flags);
@@ -247,6 +441,11 @@ static void __do_evict(int i915,
free(list);
free(objects);
+ if (params->flags & TEST_CCS) {
+ gem_close(i915, cmd->handle);
+ gem_close(i915, tmp->handle);
+ gem_context_destroy(i915, blt_ctx->id);
+ }
gem_close(i915, batch);
}
@@ -349,6 +548,9 @@ static void test_evict(int i915,
const unsigned int nproc = sysconf(_SC_NPROCESSORS_ONLN) + 1;
struct params params;
+ if (flags & TEST_CCS)
+ igt_require(IS_DG2(intel_get_drm_devid(i915)));
+
fill_params(i915, ¶ms, region, flags, nproc, false);
if (flags & TEST_PARALLEL) {
@@ -512,6 +714,11 @@ igt_main_args("", long_options, help_str, opt_handler, NULL)
{ "parallel-random-engines", TEST_PARALLEL | TEST_RANDOM | TEST_ENGINES },
{ "parallel-random-verify", TEST_PARALLEL | TEST_RANDOM | TEST_VERIFY },
{ "parallel-multi", TEST_PARALLEL | TEST_RANDOM | TEST_VERIFY | TEST_ENGINES | TEST_MULTI },
+ { "verify-ccs", TEST_CCS },
+ { "verify-random-ccs", TEST_CCS | TEST_RANDOM },
+ { "heavy-verify-random-ccs", TEST_CCS | TEST_RANDOM | TEST_HEAVY },
+ { "heavy-verify-multi-ccs", TEST_CCS | TEST_RANDOM | TEST_HEAVY | TEST_ENGINES | TEST_MULTI },
+ { "parallel-random-verify-ccs", TEST_PARALLEL | TEST_RANDOM | TEST_CCS },
{ }
};
int i915 = -1;
--
2.20.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [igt-dev] ✗ GitLab.Pipeline: warning for tests/i915: ccs subtests for gem_lmem_swapping (rev3)
2022-03-01 21:25 [igt-dev] [PATCH i-g-t v2 0/3] tests/i915: ccs subtests for gem_lmem_swapping Ramalingam C
` (2 preceding siblings ...)
2022-03-01 21:25 ` [igt-dev] [PATCH i-g-t v2 3/3] tests/i915/gem_lmem_swapping: ccs subtests Ramalingam C
@ 2022-03-01 22:02 ` Patchwork
2022-03-01 22:30 ` [igt-dev] ✓ Fi.CI.BAT: success " Patchwork
2022-03-02 2:48 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
5 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2022-03-01 22:02 UTC (permalink / raw)
To: Ramalingam C; +Cc: igt-dev
== Series Details ==
Series: tests/i915: ccs subtests for gem_lmem_swapping (rev3)
URL : https://patchwork.freedesktop.org/series/100816/
State : warning
== Summary ==
Pipeline status: FAILED.
see https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/pipelines/521477 for the overview.
build:tests-debian-meson-mips has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/19336488):
Preparing environment
Running on runner-zbmz6-qr-project-3185-concurrent-1 via fdo-packet-m1xl-1...
section_end:1646171975:prepare_script
section_start:1646171975:get_sources
Getting source from Git repository
$ eval "$CI_PRE_CLONE_SCRIPT"
Fetching changes...
Reinitialized existing Git repository in /builds/gfx-ci/igt-ci-tags/.git/
Checking out 63d43637 as intel/IGTPW_6726...
Skipping Git submodules setup
section_end:1646171979:get_sources
section_start:1646171979:step_script
Executing "step_script" stage of the job script
Using docker image sha256:cc55efdc667be826910d414a562c76ce1130a9c15255a0dd115431bc42f83448 for registry.freedesktop.org/gfx-ci/igt-ci-tags/build-debian-mips:commit-63d43637a2d264a98f6d30eabbff50fa40a925a3 with digest registry.freedesktop.org/gfx-ci/igt-ci-tags/build-debian-mips@sha256:c829c44880da4782b7a72626c259ac6904b4bd5f08601e66b3be889ca1c0cf79 ...
section_end:1646171981:step_script
section_start:1646171981:cleanup_file_variables
Cleaning up project directory and file based variables
section_end:1646171984:cleanup_file_variables
ERROR: Job failed (system failure): Error response from daemon: layer does not exist (docker.go:651:1s)
== Logs ==
For more details see: https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/pipelines/521477
^ permalink raw reply [flat|nested] 8+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for tests/i915: ccs subtests for gem_lmem_swapping (rev3)
2022-03-01 21:25 [igt-dev] [PATCH i-g-t v2 0/3] tests/i915: ccs subtests for gem_lmem_swapping Ramalingam C
` (3 preceding siblings ...)
2022-03-01 22:02 ` [igt-dev] ✗ GitLab.Pipeline: warning for tests/i915: ccs subtests for gem_lmem_swapping (rev3) Patchwork
@ 2022-03-01 22:30 ` Patchwork
2022-03-02 2:48 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
5 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2022-03-01 22:30 UTC (permalink / raw)
To: Ramalingam C; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 6854 bytes --]
== Series Details ==
Series: tests/i915: ccs subtests for gem_lmem_swapping (rev3)
URL : https://patchwork.freedesktop.org/series/100816/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11306 -> IGTPW_6726
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/index.html
Participating hosts (52 -> 41)
------------------------------
Missing (11): fi-kbl-soraka fi-cml-u2 shard-tglu fi-hsw-4200u fi-bsw-cyan bat-adlp-4 fi-ctg-p8600 shard-rkl shard-dg1 bat-jsl-2 fi-bdw-samus
Known issues
------------
Here are the changes found in IGTPW_6726 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@semaphore:
- fi-hsw-4770: NOTRUN -> [SKIP][1] ([fdo#109271] / [fdo#109315]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/fi-hsw-4770/igt@amdgpu/amd_basic@semaphore.html
* igt@amdgpu/amd_cs_nop@nop-compute0:
- fi-pnv-d510: NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/fi-pnv-d510/igt@amdgpu/amd_cs_nop@nop-compute0.html
* igt@gem_flink_basic@bad-flink:
- fi-skl-6600u: [PASS][3] -> [FAIL][4] ([i915#4547])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html
* igt@gem_lmem_swapping@random-engines:
- fi-ivb-3770: NOTRUN -> [SKIP][5] ([fdo#109271]) +35 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/fi-ivb-3770/igt@gem_lmem_swapping@random-engines.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: [PASS][6] -> [DMESG-FAIL][7] ([i915#4494] / [i915#4957])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [PASS][8] -> [DMESG-FAIL][9] ([i915#5026])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/fi-blb-e6850/igt@i915_selftest@live@requests.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/fi-blb-e6850/igt@i915_selftest@live@requests.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-ivb-3770: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/fi-ivb-3770/igt@kms_chamelium@dp-hpd-fast.html
* igt@runner@aborted:
- fi-blb-e6850: NOTRUN -> [FAIL][11] ([fdo#109271] / [i915#2403] / [i915#2426] / [i915#4312])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/fi-blb-e6850/igt@runner@aborted.html
- fi-bdw-5557u: NOTRUN -> [FAIL][12] ([i915#2426] / [i915#4312])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/fi-bdw-5557u/igt@runner@aborted.html
#### Possible fixes ####
* igt@core_hotunplug@unbind-rebind:
- fi-blb-e6850: [FAIL][13] ([i915#3194]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/fi-blb-e6850/igt@core_hotunplug@unbind-rebind.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/fi-blb-e6850/igt@core_hotunplug@unbind-rebind.html
* igt@i915_selftest@live@gt_pm:
- {fi-jsl-1}: [DMESG-FAIL][15] ([i915#1886]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/fi-jsl-1/igt@i915_selftest@live@gt_pm.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/fi-jsl-1/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770: [INCOMPLETE][17] ([i915#3303]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-pnv-d510: [DMESG-FAIL][19] ([i915#2927] / [i915#4528]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/fi-pnv-d510/igt@i915_selftest@live@requests.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/fi-pnv-d510/igt@i915_selftest@live@requests.html
#### Warnings ####
* igt@runner@aborted:
- fi-skl-6600u: [FAIL][21] ([i915#1436] / [i915#4312]) -> [FAIL][22] ([i915#4312])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/fi-skl-6600u/igt@runner@aborted.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/fi-skl-6600u/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
[i915#3194]: https://gitlab.freedesktop.org/drm/intel/issues/3194
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#5026]: https://gitlab.freedesktop.org/drm/intel/issues/5026
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_6361 -> IGTPW_6726
CI-20190529: 20190529
CI_DRM_11306: 0eb492df610222f39eb2ad5a903626dd3ad9aea2 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_6726: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/index.html
IGT_6361: 2372a4beb6a33c5f0799a4a8ccbb93794f52dbca @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
== Testlist changes ==
+igt@gem_lmem_swapping@heavy-verify-multi-ccs
+igt@gem_lmem_swapping@heavy-verify-random-ccs
+igt@gem_lmem_swapping@parallel-random-verify-ccs
+igt@gem_lmem_swapping@verify-ccs
+igt@gem_lmem_swapping@verify-random-ccs
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/index.html
[-- Attachment #2: Type: text/html, Size: 8274 bytes --]
^ permalink raw reply [flat|nested] 8+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for tests/i915: ccs subtests for gem_lmem_swapping (rev3)
2022-03-01 21:25 [igt-dev] [PATCH i-g-t v2 0/3] tests/i915: ccs subtests for gem_lmem_swapping Ramalingam C
` (4 preceding siblings ...)
2022-03-01 22:30 ` [igt-dev] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-03-02 2:48 ` Patchwork
5 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2022-03-02 2:48 UTC (permalink / raw)
To: Ramalingam C; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 30272 bytes --]
== Series Details ==
Series: tests/i915: ccs subtests for gem_lmem_swapping (rev3)
URL : https://patchwork.freedesktop.org/series/100816/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11306_full -> IGTPW_6726_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_6726_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_6726_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/index.html
Participating hosts (13 -> 8)
------------------------------
Missing (5): pig-kbl-iris pig-glk-j5005 pig-skl-6260u shard-rkl shard-dg1
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_6726_full:
### IGT changes ###
#### Possible regressions ####
* {igt@gem_lmem_swapping@heavy-verify-multi-ccs} (NEW):
- shard-iclb: NOTRUN -> [SKIP][1] +4 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-iclb3/igt@gem_lmem_swapping@heavy-verify-multi-ccs.html
* {igt@gem_lmem_swapping@parallel-random-verify-ccs} (NEW):
- shard-tglb: NOTRUN -> [SKIP][2] +4 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-tglb1/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
* {igt@kms_plane_scaling@downscale-with-rotation-factor-0-25@pipe-d-hdmi-a-1-downscale-with-rotation} (NEW):
- {shard-tglu}: NOTRUN -> [SKIP][3] +5 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-tglu-5/igt@kms_plane_scaling@downscale-with-rotation-factor-0-25@pipe-d-hdmi-a-1-downscale-with-rotation.html
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-a-edp-1-scaler-with-clipping-clamping:
- shard-iclb: [PASS][4] -> [SKIP][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-iclb2/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-a-edp-1-scaler-with-clipping-clamping.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-iclb3/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-a-edp-1-scaler-with-clipping-clamping.html
#### Warnings ####
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-b-edp-1-scaler-with-clipping-clamping:
- shard-iclb: [INCOMPLETE][6] -> [SKIP][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-iclb2/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-b-edp-1-scaler-with-clipping-clamping.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-iclb3/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-b-edp-1-scaler-with-clipping-clamping.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-1-planes-upscale-downscale}:
- {shard-tglu}: NOTRUN -> [SKIP][8] +13 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-tglu-1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-1-planes-upscale-downscale.html
New tests
---------
New tests have been introduced between CI_DRM_11306_full and IGTPW_6726_full:
### New IGT tests (38) ###
* igt@gem_ctx_persistence@legacy-engines-queued@bsd1:
- Statuses : 2 pass(s)
- Exec time: [0.02, 0.03] s
* igt@gem_ctx_persistence@legacy-engines-queued@bsd2:
- Statuses : 2 pass(s)
- Exec time: [0.03] s
* igt@gem_exec_suspend@basic:
- Statuses :
- Exec time: [None] s
* igt@gem_lmem_swapping@heavy-verify-multi-ccs:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@gem_lmem_swapping@heavy-verify-random-ccs:
- Statuses : 6 skip(s)
- Exec time: [0.0] s
* igt@gem_lmem_swapping@parallel-random-verify-ccs:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@gem_lmem_swapping@verify-ccs:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@gem_lmem_swapping@verify-random-ccs:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@gem_render_copy@mixed-tiled-to-yf-tiled-ccs:
- Statuses :
- Exec time: [None] s
* igt@gem_render_copy@y-tiled-ccs-to-x-tiled:
- Statuses :
- Exec time: [None] s
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- Statuses :
- Exec time: [None] s
* igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-75@pipe-b-hdmi-a-1-downscale-with-pixel-format:
- Statuses : 1 pass(s)
- Exec time: [22.74] s
* igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-75@pipe-d-hdmi-a-1-downscale-with-pixel-format:
- Statuses : 1 pass(s)
- Exec time: [0.28] s
* igt@kms_plane_scaling@downscale-with-rotation-factor-0-25@pipe-b-hdmi-a-1-downscale-with-rotation:
- Statuses : 1 skip(s)
- Exec time: [0.02] s
* igt@kms_plane_scaling@downscale-with-rotation-factor-0-25@pipe-d-hdmi-a-1-downscale-with-rotation:
- Statuses : 1 skip(s)
- Exec time: [0.02] s
* igt@kms_plane_scaling@invalid-num-scalers@pipe-d-edp-1-invalid-num-scalers:
- Statuses : 1 pass(s)
- Exec time: [0.02] s
* igt@kms_plane_scaling@planes-downscale-factor-0-75@pipe-d-edp-1-planes-downscale:
- Statuses : 1 pass(s)
- Exec time: [1.28] s
* igt@kms_plane_scaling@planes-scaling-unity-scaling@pipe-d-edp-1-planes-unity-scaling:
- Statuses : 1 pass(s)
- Exec time: [1.22] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-b-hdmi-a-1-planes-upscale-downscale:
- Statuses : 1 pass(s)
- Exec time: [0.14] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-d-edp-1-planes-upscale-downscale:
- Statuses : 1 pass(s)
- Exec time: [1.28] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-d-hdmi-a-1-planes-upscale-downscale:
- Statuses : 1 pass(s)
- Exec time: [0.13] s
* igt@kms_plane_scaling@planes-upscale-20x20@pipe-b-hdmi-a-1-planes-upscale:
- Statuses : 1 pass(s)
- Exec time: [0.10] s
* igt@kms_plane_scaling@planes-upscale-20x20@pipe-d-edp-1-planes-upscale:
- Statuses : 1 pass(s)
- Exec time: [1.22] s
* igt@kms_plane_scaling@planes-upscale-20x20@pipe-d-hdmi-a-1-planes-upscale:
- Statuses : 1 pass(s)
- Exec time: [0.10] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-a-edp-1-planes-upscale-downscale:
- Statuses : 2 pass(s)
- Exec time: [0.13, 0.19] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-a-hdmi-a-1-planes-upscale-downscale:
- Statuses : 2 pass(s)
- Exec time: [0.10, 0.36] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-a-vga-1-planes-upscale-downscale:
- Statuses : 1 skip(s)
- Exec time: [0.05] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-b-edp-1-planes-upscale-downscale:
- Statuses : 2 pass(s)
- Exec time: [1.23, 1.27] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-b-hdmi-a-1-planes-upscale-downscale:
- Statuses : 1 pass(s)
- Exec time: [0.13] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-b-hdmi-a-2-planes-upscale-downscale:
- Statuses : 1 pass(s)
- Exec time: [0.33] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-b-vga-1-planes-upscale-downscale:
- Statuses : 1 skip(s)
- Exec time: [0.03] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-c-edp-1-planes-upscale-downscale:
- Statuses : 2 pass(s)
- Exec time: [1.22, 1.28] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-c-hdmi-a-1-planes-upscale-downscale:
- Statuses : 1 pass(s) 1 skip(s)
- Exec time: [0.11, 0.12] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-d-edp-1-planes-upscale-downscale:
- Statuses : 1 pass(s)
- Exec time: [1.22] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-d-hdmi-a-1-planes-upscale-downscale:
- Statuses : 1 pass(s)
- Exec time: [0.11] s
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-b-hdmi-a-1-scaler-with-clipping-clamping:
- Statuses : 1 pass(s)
- Exec time: [22.84] s
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-d-hdmi-a-1-scaler-with-clipping-clamping:
- Statuses : 1 pass(s)
- Exec time: [0.31] s
* igt@prime_mmap@test_userptr:
- Statuses :
- Exec time: [None] s
Known issues
------------
Here are the changes found in IGTPW_6726_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@display-2x:
- shard-tglb: NOTRUN -> [SKIP][9] ([i915#1839])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-tglb6/igt@feature_discovery@display-2x.html
- shard-iclb: NOTRUN -> [SKIP][10] ([i915#1839])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-iclb4/igt@feature_discovery@display-2x.html
* igt@gem_create@create-massive:
- shard-kbl: NOTRUN -> [DMESG-WARN][11] ([i915#4991])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-kbl6/igt@gem_create@create-massive.html
* igt@gem_ctx_persistence@legacy-engines-queued:
- shard-snb: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#1099]) +2 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-snb4/igt@gem_ctx_persistence@legacy-engines-queued.html
* igt@gem_ctx_sseu@mmap-args:
- shard-tglb: NOTRUN -> [SKIP][13] ([i915#280])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-tglb8/igt@gem_ctx_sseu@mmap-args.html
* igt@gem_eio@in-flight-suspend:
- shard-kbl: [PASS][14] -> [DMESG-WARN][15] ([i915#180]) +3 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-kbl6/igt@gem_eio@in-flight-suspend.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-kbl7/igt@gem_eio@in-flight-suspend.html
* igt@gem_exec_balancer@parallel-out-fence:
- shard-kbl: NOTRUN -> [DMESG-WARN][16] ([i915#5076])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-kbl1/igt@gem_exec_balancer@parallel-out-fence.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: NOTRUN -> [FAIL][17] ([i915#2842]) +6 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-tglb6/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl: NOTRUN -> [FAIL][18] ([i915#2842]) +1 similar issue
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-kbl3/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][19] ([i915#2842])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-iclb1/igt@gem_exec_fair@basic-none@vcs1.html
* igt@gem_exec_params@secure-non-root:
- shard-tglb: NOTRUN -> [SKIP][20] ([fdo#112283])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-tglb8/igt@gem_exec_params@secure-non-root.html
* igt@gem_exec_suspend@basic-s3@smem:
- shard-apl: [PASS][21] -> [DMESG-WARN][22] ([i915#180]) +3 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-apl1/igt@gem_exec_suspend@basic-s3@smem.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-apl3/igt@gem_exec_suspend@basic-s3@smem.html
* igt@gem_lmem_swapping@heavy-multi:
- shard-apl: NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#4613])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-apl2/igt@gem_lmem_swapping@heavy-multi.html
* igt@gem_lmem_swapping@heavy-random:
- shard-iclb: NOTRUN -> [SKIP][24] ([i915#4613]) +1 similar issue
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-iclb2/igt@gem_lmem_swapping@heavy-random.html
- shard-glk: NOTRUN -> [SKIP][25] ([fdo#109271] / [i915#4613])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-glk3/igt@gem_lmem_swapping@heavy-random.html
* igt@gem_lmem_swapping@heavy-verify-random:
- shard-kbl: NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#4613])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-kbl7/igt@gem_lmem_swapping@heavy-verify-random.html
- shard-tglb: NOTRUN -> [SKIP][27] ([i915#4613]) +2 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-tglb1/igt@gem_lmem_swapping@heavy-verify-random.html
* igt@gem_pxp@create-protected-buffer:
- shard-iclb: NOTRUN -> [SKIP][28] ([i915#4270]) +1 similar issue
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-iclb8/igt@gem_pxp@create-protected-buffer.html
* igt@gem_pxp@reject-modify-context-protection-off-2:
- shard-tglb: NOTRUN -> [SKIP][29] ([i915#4270]) +2 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-tglb6/igt@gem_pxp@reject-modify-context-protection-off-2.html
* igt@gem_render_copy@x-tiled-to-vebox-yf-tiled:
- shard-kbl: NOTRUN -> [SKIP][30] ([fdo#109271]) +223 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-kbl1/igt@gem_render_copy@x-tiled-to-vebox-yf-tiled.html
* igt@gem_render_copy@yf-tiled-to-vebox-x-tiled:
- shard-iclb: NOTRUN -> [SKIP][31] ([i915#768]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-iclb4/igt@gem_render_copy@yf-tiled-to-vebox-x-tiled.html
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-tglb: NOTRUN -> [SKIP][32] ([i915#3297])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-tglb7/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@gen3_render_tiledy_blits:
- shard-tglb: NOTRUN -> [SKIP][33] ([fdo#109289]) +4 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-tglb6/igt@gen3_render_tiledy_blits.html
* igt@gen7_exec_parse@chained-batch:
- shard-iclb: NOTRUN -> [SKIP][34] ([fdo#109289]) +2 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-iclb4/igt@gen7_exec_parse@chained-batch.html
* igt@gen9_exec_parse@shadow-peek:
- shard-tglb: NOTRUN -> [SKIP][35] ([i915#2527] / [i915#2856]) +4 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-tglb8/igt@gen9_exec_parse@shadow-peek.html
* igt@gen9_exec_parse@unaligned-access:
- shard-iclb: NOTRUN -> [SKIP][36] ([i915#2856]) +1 similar issue
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-iclb4/igt@gen9_exec_parse@unaligned-access.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][37] -> [FAIL][38] ([i915#454])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-iclb2/igt@i915_pm_dc@dc6-psr.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-iclb6/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rc6_residency@media-rc6-accuracy:
- shard-tglb: NOTRUN -> [SKIP][39] ([fdo#109289] / [fdo#111719])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-tglb5/igt@i915_pm_rc6_residency@media-rc6-accuracy.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-tglb: NOTRUN -> [WARN][40] ([i915#2681] / [i915#2684])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-tglb5/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@i915_pm_sseu@full-enable:
- shard-tglb: NOTRUN -> [SKIP][41] ([i915#4387])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-tglb3/igt@i915_pm_sseu@full-enable.html
- shard-iclb: NOTRUN -> [SKIP][42] ([i915#4387])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-iclb4/igt@i915_pm_sseu@full-enable.html
* igt@kms_atomic_transition@plane-all-modeset-transition:
- shard-iclb: NOTRUN -> [SKIP][43] ([i915#1769])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-iclb2/igt@kms_atomic_transition@plane-all-modeset-transition.html
- shard-tglb: NOTRUN -> [SKIP][44] ([i915#1769])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-tglb8/igt@kms_atomic_transition@plane-all-modeset-transition.html
* igt@kms_big_fb@linear-32bpp-rotate-90:
- shard-iclb: NOTRUN -> [SKIP][45] ([fdo#110725] / [fdo#111614]) +2 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-iclb4/igt@kms_big_fb@linear-32bpp-rotate-90.html
* igt@kms_big_fb@linear-8bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][46] ([fdo#111614]) +3 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-tglb5/igt@kms_big_fb@linear-8bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
- shard-apl: NOTRUN -> [SKIP][47] ([fdo#109271] / [i915#3777]) +1 similar issue
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-apl2/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-kbl: NOTRUN -> [SKIP][48] ([fdo#109271] / [i915#3777]) +3 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-kbl4/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][49] ([fdo#111615]) +9 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-tglb8/igt@kms_big_fb@yf-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
- shard-apl: NOTRUN -> [SKIP][50] ([fdo#109271]) +147 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-apl6/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html
- shard-iclb: NOTRUN -> [SKIP][51] ([fdo#110723]) +2 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-iclb5/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_big_joiner@basic:
- shard-tglb: NOTRUN -> [SKIP][52] ([i915#2705])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-tglb8/igt@kms_big_joiner@basic.html
- shard-iclb: NOTRUN -> [SKIP][53] ([i915#2705])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-iclb6/igt@kms_big_joiner@basic.html
* igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
- shard-glk: NOTRUN -> [SKIP][54] ([fdo#109271] / [i915#3886]) +5 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-glk5/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
- shard-iclb: NOTRUN -> [SKIP][55] ([fdo#109278] / [i915#3886]) +8 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-iclb5/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
- shard-kbl: NOTRUN -> [SKIP][56] ([fdo#109271] / [i915#3886]) +9 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-kbl4/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html
- shard-tglb: NOTRUN -> [SKIP][57] ([i915#3689] / [i915#3886]) +5 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-tglb6/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][58] ([i915#3689]) +7 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-tglb5/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_ccs.html
* igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_ccs:
- shard-snb: NOTRUN -> [SKIP][59] ([fdo#109271]) +169 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-snb5/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_ccs.html
* igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#3886]) +7 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-apl6/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-d-missing-ccs-buffer-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][61] ([fdo#111615] / [i915#3689]) +9 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-tglb7/igt@kms_ccs@pipe-d-missing-ccs-buffer-yf_tiled_ccs.html
* igt@kms_cdclk@plane-scaling:
- shard-tglb: NOTRUN -> [SKIP][62] ([i915#3742])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-tglb7/igt@kms_cdclk@plane-scaling.html
* igt@kms_chamelium@hdmi-hpd:
- shard-glk: NOTRUN -> [SKIP][63] ([fdo#109271] / [fdo#111827]) +10 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-glk2/igt@kms_chamelium@hdmi-hpd.html
* igt@kms_chamelium@hdmi-hpd-for-each-pipe:
- shard-kbl: NOTRUN -> [SKIP][64] ([fdo#109271] / [fdo#111827]) +15 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-kbl4/igt@kms_chamelium@hdmi-hpd-for-each-pipe.html
* igt@kms_chamelium@hdmi-mode-timings:
- shard-iclb: NOTRUN -> [SKIP][65] ([fdo#109284] / [fdo#111827]) +12 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-iclb1/igt@kms_chamelium@hdmi-mode-timings.html
* igt@kms_chamelium@vga-hpd-for-each-pipe:
- shard-apl: NOTRUN -> [SKIP][66] ([fdo#109271] / [fdo#111827]) +13 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-apl7/igt@kms_chamelium@vga-hpd-for-each-pipe.html
* igt@kms_color_chamelium@pipe-b-ctm-limited-range:
- shard-tglb: NOTRUN -> [SKIP][67] ([fdo#109284] / [fdo#111827]) +16 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-tglb1/igt@kms_color_chamelium@pipe-b-ctm-limited-range.html
* igt@kms_color_chamelium@pipe-c-ctm-green-to-red:
- shard-snb: NOTRUN -> [SKIP][68] ([fdo#109271] / [fdo#111827]) +8 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-snb6/igt@kms_color_chamelium@pipe-c-ctm-green-to-red.html
* igt@kms_color_chamelium@pipe-d-ctm-limited-range:
- shard-iclb: NOTRUN -> [SKIP][69] ([fdo#109278] / [fdo#109284] / [fdo#111827])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-iclb4/igt@kms_color_chamelium@pipe-d-ctm-limited-range.html
* igt@kms_content_protection@atomic-dpms:
- shard-tglb: NOTRUN -> [SKIP][70] ([i915#1063]) +2 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-tglb1/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@lic:
- shard-kbl: NOTRUN -> [TIMEOUT][71] ([i915#1319])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-kbl6/igt@kms_content_protection@lic.html
* igt@kms_content_protection@type1:
- shard-iclb: NOTRUN -> [SKIP][72] ([fdo#109300] / [fdo#111066])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-iclb2/igt@kms_content_protection@type1.html
* igt@kms_content_protection@uevent:
- shard-kbl: NOTRUN -> [FAIL][73] ([i915#2105])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-kbl4/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@pipe-b-cursor-32x10-rapid-movement:
- shard-iclb: NOTRUN -> [SKIP][74] ([fdo#109278]) +32 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-iclb7/igt@kms_cursor_crc@pipe-b-cursor-32x10-rapid-movement.html
* igt@kms_cursor_crc@pipe-b-cursor-32x32-sliding:
- shard-tglb: NOTRUN -> [SKIP][75] ([i915#3319]) +3 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-tglb7/igt@kms_cursor_crc@pipe-b-cursor-32x32-sliding.html
* igt@kms_cursor_crc@pipe-b-cursor-512x512-rapid-movement:
- shard-iclb: NOTRUN -> [SKIP][76] ([fdo#109278] / [fdo#109279]) +1 similar issue
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-iclb3/igt@kms_cursor_crc@pipe-b-cursor-512x512-rapid-movement.html
* igt@kms_cursor_crc@pipe-c-cursor-512x512-random:
- shard-tglb: NOTRUN -> [SKIP][77] ([fdo#109279] / [i915#3359]) +6 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-tglb2/igt@kms_cursor_crc@pipe-c-cursor-512x512-random.html
* igt@kms_cursor_crc@pipe-c-cursor-max-size-rapid-movement:
- shard-tglb: NOTRUN -> [SKIP][78] ([i915#3359]) +6 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-tglb3/igt@kms_cursor_crc@pipe-c-cursor-max-size-rapid-movement.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- shard-tglb: NOTRUN -> [SKIP][79] ([i915#4103]) +2 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-tglb3/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
- shard-iclb: NOTRUN -> [SKIP][80] ([fdo#109274] / [fdo#109278]) +2 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-iclb7/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
* igt@kms_cursor_legacy@pipe-d-torture-bo:
- shard-kbl: NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#533]) +2 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-kbl4/igt@kms_cursor_legacy@pipe-d-torture-bo.html
- shard-apl: NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#533]) +1 similar issue
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-apl4/igt@kms_cursor_legacy@pipe-d-torture-bo.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [PASS][83] -> [INCOMPLETE][84] ([i915#180] / [i915#1982])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-apl1/igt@kms_fbcon_fbt@fbc-suspend.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-apl6/igt@kms_fbcon_fbt@fbc-suspend.html
- shard-kbl: [PASS][85] -> [INCOMPLETE][86] ([i915#636])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-kbl4/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-absolute-wf_vblank:
- shard-tglb: NOTRUN -> [SKIP][87] ([fdo#109274] / [fdo#111825] / [i915#3966])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-tglb2/igt@kms_flip@2x-absolute-wf_vblank.html
* igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][88] -> [FAIL][89] ([i915#79])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-glk5/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
- shard-iclb: NOTRUN -> [SKIP][90] ([fdo#109274]) +3 similar issues
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-iclb4/igt@kms_flip@2x-modeset-vs-vblank-race-interruptible.html
* igt@kms_flip@2x-plain-flip-fb-recreate:
- shard-tglb: NOTRUN -> [SKIP][91] ([fdo#109274] / [fdo#111825]) +8 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-tglb6/igt@kms_flip@2x-plain-flip-fb-recreate.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling:
- shard-tglb: NOTRUN -> [SKIP][92] ([i915#2587])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-tglb1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling:
- shard-iclb: NOTRUN -> [SKIP][93] ([i915#2587])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-iclb8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
- shard-iclb: [PASS][94] -> [SKIP][95] ([i915#3701])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11306/shard-iclb7/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html
* igt@kms_force_connector_basic@force-load-detect:
- shard-iclb: NOTRUN -> [SKIP][96] ([fdo#109285])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-iclb1/igt@kms_force_connector_basic@force-load-detect.html
- shard-tglb: NOTRUN -> [SKIP][97] ([fdo#109285])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-tglb7/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-wc:
- shard-glk: NOTRUN -> [SKIP][98] ([fdo#109271]) +83 similar issues
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/shard-glk1/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt:
- shard-tglb: NOTRUN -> [S
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6726/index.html
[-- Attachment #2: Type: text/html, Size: 34520 bytes --]
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v2 3/3] tests/i915/gem_lmem_swapping: ccs subtests
2022-03-01 21:25 ` [igt-dev] [PATCH i-g-t v2 3/3] tests/i915/gem_lmem_swapping: ccs subtests Ramalingam C
@ 2022-03-02 4:49 ` Zbigniew Kempczyński
0 siblings, 0 replies; 8+ messages in thread
From: Zbigniew Kempczyński @ 2022-03-02 4:49 UTC (permalink / raw)
To: Ramalingam C; +Cc: igt-dev
On Wed, Mar 02, 2022 at 02:55:13AM +0530, Ramalingam C wrote:
> Subtests for covering the compressed object's eviction are added.
>
> v2:
> gem_sync after the block_copy blit for init
>
> Signed-off-by: Chris Wilson <chris.p.wilson@intel.com>
> Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> ---
> tests/i915/gem_lmem_swapping.c | 217 ++++++++++++++++++++++++++++++++-
> 1 file changed, 212 insertions(+), 5 deletions(-)
>
> diff --git a/tests/i915/gem_lmem_swapping.c b/tests/i915/gem_lmem_swapping.c
> index 39f9e1f536dd..574fe5030cd5 100644
> --- a/tests/i915/gem_lmem_swapping.c
> +++ b/tests/i915/gem_lmem_swapping.c
> @@ -22,6 +22,7 @@
> #include <sys/time.h>
> #include <sys/wait.h>
> #include "drm.h"
> +#include "i915/i915_blt.h"
>
> IGT_TEST_DESCRIPTION("Exercise local memory swapping.");
>
> @@ -30,6 +31,7 @@ IGT_TEST_DESCRIPTION("Exercise local memory swapping.");
>
> #define PAGE_SIZE (1ULL << 12)
> #define SZ_64K (16 * PAGE_SIZE)
> +#define DG2_MOCS (2 << 1)
>
> static const char *readable_unit(uint64_t size)
> {
> @@ -60,6 +62,7 @@ struct params {
> #define TEST_RANDOM (1 << 3)
> #define TEST_ENGINES (1 << 4)
> #define TEST_MULTI (1 << 5)
> +#define TEST_CCS (1 << 6)
> unsigned int flags;
> unsigned int seed;
> bool oom_test;
> @@ -69,8 +72,56 @@ struct object {
> uint64_t size;
> uint32_t seed;
> uint32_t handle;
> + struct blt_copy_object *blt_obj;
> };
>
> +static void set_object(struct blt_copy_object *obj,
> + uint32_t handle, uint64_t size, uint32_t region,
> + uint8_t mocs, enum blt_tiling tiling,
> + enum blt_compression compression,
> + enum blt_compression_type compression_type)
> +{
> + obj->handle = handle;
> + obj->size = size;
> + obj->region = region;
> + obj->mocs = mocs;
> + obj->tiling = tiling;
> + obj->compression = compression;
> + obj->compression_type = compression_type;
> +}
> +
> +static void set_geom(struct blt_copy_object *obj, uint32_t pitch,
> + int16_t x1, int16_t y1, int16_t x2, int16_t y2,
> + uint16_t x_offset, uint16_t y_offset)
> +{
> + obj->pitch = pitch;
> + obj->x1 = x1;
> + obj->y1 = y1;
> + obj->x2 = x2;
> + obj->y2 = y2;
> + obj->x_offset = x_offset;
> + obj->y_offset = y_offset;
> +}
> +
> +static void set_batch(struct blt_copy_batch *batch,
> + uint32_t handle, uint64_t size, uint32_t region)
> +{
> + batch->handle = handle;
> + batch->size = size;
> + batch->region = region;
> +}
> +
> +static void set_object_ext(struct blt_block_copy_object_ext *obj,
> + uint8_t compression_format,
> + uint16_t surface_width, uint16_t surface_height,
> + enum blt_surface_type surface_type)
> +{
> + obj->compression_format = compression_format;
> + obj->surface_width = surface_width;
> + obj->surface_height = surface_height;
> + obj->surface_type = surface_type;
> +}
> +
> static uint32_t create_bo(int i915,
> uint64_t size,
> struct drm_i915_gem_memory_class_instance *region,
> @@ -105,6 +156,51 @@ init_object(int i915, struct object *obj, unsigned long seed, unsigned int flags
> munmap(buf, obj->size);
> }
>
> +#define BATCH_SIZE 4096
> +static void
> +init_object_ccs(int i915, struct object *obj, struct blt_copy_object *tmp,
> + struct blt_copy_object *cmd, unsigned long seed,
> + unsigned int flags, const intel_ctx_t *ctx, uint32_t region)
> +{
> + uint64_t ahnd = intel_allocator_open_full(i915, ctx->id, 0, 0,
> + INTEL_ALLOCATOR_SIMPLE,
> + ALLOC_STRATEGY_LOW_TO_HIGH, 0);
cmd should be blt_copy_batch, not blt_copy_object.
You should provide ahnd as an argument instead of creating/destroying it
for each call.
> + struct blt_block_copy_data_ext ext = {}, *pext = &ext;
> + const struct intel_execution_engine2 *e;
> + struct blt_copy_data blt = {};
> + unsigned long *buf, j;
> +
> + obj->seed = seed;
> +
> + for_each_ctx_engine(i915, ctx, e) {
> + igt_assert_f(gem_engine_can_block_copy(i915, e),
> + "Ctx dont have Blt engine");
> + break;
> + }
> +
> + buf = gem_mmap__device_coherent(i915, tmp->handle, 0, obj->size, PROT_WRITE);
> + gem_set_domain(i915, tmp->handle, I915_GEM_DOMAIN_WC, I915_GEM_DOMAIN_WC);
> +
> + for (j = 0; j < obj->size / sizeof(*buf); j++)
> + buf[j] = seed++;
> + munmap(buf, obj->size);
> +
> + memset(&blt, 0, sizeof(blt));
> + blt.color_depth = CD_32bit;
> +
> + memcpy(&blt.src, tmp, sizeof(blt.src));
> + memcpy(&blt.dst, obj->blt_obj, sizeof(blt.dst));
> +
> + set_object_ext(&ext.src, 0, tmp->x2, tmp->y2, SURFACE_TYPE_2D);
> + set_object_ext(&ext.dst, 0, obj->blt_obj->x2, obj->blt_obj->y2,
> + SURFACE_TYPE_2D);
> +
> + set_batch(&blt.bb, cmd->handle, BATCH_SIZE, region);
> + blt_block_copy(i915, ctx, e, ahnd, &blt, pext);
> + gem_sync(i915, obj->blt_obj->handle);
Reason you got hang before was write to inflight bb.
I started to think to provide similar caching solution libdrm has - I mean
creating buffers from the pool. At least for bb.
BTW above case realized me i915_blt.c is getting/putting offsets so when
we reuse same object rebind occurs.
> + put_ahnd(ahnd);
And this can be removed.
> +}
> +
> static void
> verify_object(int i915, const struct object *obj, unsigned int flags)
> {
> @@ -125,6 +221,56 @@ verify_object(int i915, const struct object *obj, unsigned int flags)
> munmap(buf, obj->size);
> }
>
> +static void
> +verify_object_ccs(int i915, const struct object *obj,
> + struct blt_copy_object *tmp,
> + struct blt_copy_object *cmd, unsigned int flags,
> + const intel_ctx_t *ctx, uint32_t region)
> +{
> + uint64_t ahnd = intel_allocator_open_full(i915, ctx->id, 0, 0,
> + INTEL_ALLOCATOR_SIMPLE,
> + ALLOC_STRATEGY_LOW_TO_HIGH, 0);
Same as above, ahnd should be an arg here.
> + struct blt_block_copy_data_ext ext = {}, *pext = &ext;
> + const struct intel_execution_engine2 *e;
> + struct blt_copy_data blt = {};
> + unsigned long j, val, *buf;
> +
> + for_each_ctx_engine(i915, ctx, e) {
> + igt_assert_f(gem_engine_can_block_copy(i915, e),
> + "ctx dont have Blt engine");
> + break;
> + }
> +
> + memset(&blt, 0, sizeof(blt));
> + blt.color_depth = CD_32bit;
> +
> + memcpy(&blt.src, obj->blt_obj, sizeof(blt.src));
> + memcpy(&blt.dst, tmp, sizeof(blt.dst));
> +
> + set_object_ext(&ext.src, 0, obj->blt_obj->x2, obj->blt_obj->y2,
> + SURFACE_TYPE_2D);
> + set_object_ext(&ext.dst, 0, tmp->x2, tmp->y2, SURFACE_TYPE_2D);
> + set_batch(&blt.bb, cmd->handle, BATCH_SIZE, region);
> +
> + blt_block_copy(i915, ctx, e, ahnd, &blt, pext);
> + put_ahnd(ahnd);
This also can be removed.
> +
> + buf = gem_mmap__device_coherent(i915, tmp->handle, 0,
> + obj->size, PROT_READ);
> + gem_set_domain(i915, tmp->handle, I915_GEM_DOMAIN_WC, 0);
Uhm, sync.
> +
> + for (j = 0; j < obj->size / PAGE_SIZE; j++) {
> + unsigned long x = (j * PAGE_SIZE + rand() % PAGE_SIZE) / sizeof(*buf);
> +
> + val = obj->seed + x;
> + igt_assert_f(buf[x] == val,
> + "Object mismatch at offset %lu - found %lx, expected %lx, difference:%lx!\n",
> + x * sizeof(*buf), buf[x], val, buf[x] ^ val);
> + }
> +
> + munmap(buf, obj->size);
> +}
> +
> static void move_to_lmem(int i915,
> struct object *list,
> unsigned int num,
> @@ -160,22 +306,36 @@ static void __do_evict(int i915,
> struct params *params,
> unsigned int seed)
> {
> + uint32_t region_id = INTEL_MEMORY_REGION_ID(region->memory_class,
> + region->memory_instance);
> const unsigned int max_swap_in = params->count / 100 + 1;
> const uint32_t bbe = MI_BATCH_BUFFER_END;
> struct object *objects, *obj, *list;
> - uint32_t batch;
> + const uint32_t bpp = 32;
> + uint32_t batch, width, height, stride;
> + const intel_ctx_t *blt_ctx;
> + struct blt_copy_object *tmp, *cmd;
cmd -> struct blt_copy_batch.
> unsigned int engine = 0;
> unsigned int i, l;
> uint64_t size;
> struct timespec t = {};
> unsigned int num;
>
> + width = PAGE_SIZE / (bpp / 8);
> + height = params->size.max / (bpp / 8) / width;
> + stride = width * 4;
> +
> + tmp = calloc(1, sizeof(*tmp));
> + cmd = calloc(1, sizeof(*cmd));
> +
> __gem_context_set_persistence(i915, 0, false);
> size = 4096;
> batch = create_bo(i915, size, region, params->oom_test);
> -
> gem_write(i915, batch, 0, &bbe, sizeof(bbe));
>
> + if (params->flags & TEST_CCS)
> + blt_ctx = intel_ctx_create_for_engine(i915, I915_ENGINE_CLASS_COPY, 0);
> +
> objects = calloc(params->count, sizeof(*objects));
> igt_assert(objects);
>
> @@ -185,6 +345,18 @@ static void __do_evict(int i915,
> srand(seed);
>
> /* Create the initial working set of objects. */
> + if (params->flags & TEST_CCS) {
> + tmp->handle = gem_create_in_memory_regions(i915, params->size.max,
> + INTEL_MEMORY_REGION_ID(I915_SYSTEM_MEMORY, 0));
> + set_object(tmp, tmp->handle, params->size.max,
> + INTEL_MEMORY_REGION_ID(I915_SYSTEM_MEMORY, 0), DG2_MOCS,
> + T_LINEAR, COMPRESSION_DISABLED, COMPRESSION_TYPE_3D);
> + set_geom(tmp, stride, 0, 0, width, height, 0, 0);
> + cmd->handle = gem_create_in_memory_regions(i915, BATCH_SIZE, region_id);
> + set_object(cmd, cmd->handle, BATCH_SIZE, region_id, DG2_MOCS,
> + T_LINEAR, COMPRESSION_DISABLED, COMPRESSION_TYPE_3D);
Cmd is not blitting object but bb. Above is confusing.
Anyway - I'm going to prepare some changes in i915_blt.c to allow
your code be pipelined.
--
Zbigniew
> + }
> +
> size = 0;
> for (i = 0, obj = objects; i < params->count; i++, obj++) {
> if (params->flags & TEST_RANDOM)
> @@ -201,11 +373,24 @@ static void __do_evict(int i915,
> }
> obj->handle = create_bo(i915, obj->size, region, params->oom_test);
>
> - if (params->flags & TEST_VERIFY)
> + if (params->flags & TEST_CCS) {
> + width = PAGE_SIZE / (bpp / 8);
> + height = obj->size / (bpp / 8) / width;
> + stride = width * 4;
> +
> + obj->blt_obj = calloc(1, sizeof(*obj->blt_obj));
> + set_object(obj->blt_obj, obj->handle, obj->size, region_id,
> + DG2_MOCS, T_LINEAR, COMPRESSION_ENABLED,
> + COMPRESSION_TYPE_3D);
> + set_geom(obj->blt_obj, stride, 0, 0, width, height, 0, 0);
> + init_object_ccs(i915, obj, tmp, cmd, rand(),
> + params->flags, blt_ctx, region_id);
> + } else if (params->flags & TEST_VERIFY) {
> init_object(i915, obj, rand(), params->flags);
> - else
> + } else {
> move_to_lmem(i915, objects + i, 1, batch, engine,
> params->oom_test);
> + }
> }
>
> igt_debug("obj size min/max=%lu %s/%lu %s, count=%u, seed: %u\n",
> @@ -232,7 +417,16 @@ static void __do_evict(int i915,
> if (params->flags & TEST_ENGINES)
> engine = (engine + 1) % __num_engines__;
>
> - if (params->flags & TEST_VERIFY) {
> + if (params->flags & TEST_CCS) {
> + for (i = 0; i < num; i++)
> + verify_object_ccs(i915, &list[i], tmp,
> + cmd, params->flags, blt_ctx,
> + region_id);
> + /* Update random object - may swap it back in. */
> + i = rand() % params->count;
> + init_object_ccs(i915, &objects[i], tmp, cmd, rand(),
> + params->flags, blt_ctx, region_id);
> + } else if (params->flags & TEST_VERIFY) {
> for (i = 0; i < num; i++)
> verify_object(i915, &list[i], params->flags);
>
> @@ -247,6 +441,11 @@ static void __do_evict(int i915,
>
> free(list);
> free(objects);
> + if (params->flags & TEST_CCS) {
> + gem_close(i915, cmd->handle);
> + gem_close(i915, tmp->handle);
> + gem_context_destroy(i915, blt_ctx->id);
> + }
>
> gem_close(i915, batch);
> }
> @@ -349,6 +548,9 @@ static void test_evict(int i915,
> const unsigned int nproc = sysconf(_SC_NPROCESSORS_ONLN) + 1;
> struct params params;
>
> + if (flags & TEST_CCS)
> + igt_require(IS_DG2(intel_get_drm_devid(i915)));
> +
> fill_params(i915, ¶ms, region, flags, nproc, false);
>
> if (flags & TEST_PARALLEL) {
> @@ -512,6 +714,11 @@ igt_main_args("", long_options, help_str, opt_handler, NULL)
> { "parallel-random-engines", TEST_PARALLEL | TEST_RANDOM | TEST_ENGINES },
> { "parallel-random-verify", TEST_PARALLEL | TEST_RANDOM | TEST_VERIFY },
> { "parallel-multi", TEST_PARALLEL | TEST_RANDOM | TEST_VERIFY | TEST_ENGINES | TEST_MULTI },
> + { "verify-ccs", TEST_CCS },
> + { "verify-random-ccs", TEST_CCS | TEST_RANDOM },
> + { "heavy-verify-random-ccs", TEST_CCS | TEST_RANDOM | TEST_HEAVY },
> + { "heavy-verify-multi-ccs", TEST_CCS | TEST_RANDOM | TEST_HEAVY | TEST_ENGINES | TEST_MULTI },
> + { "parallel-random-verify-ccs", TEST_PARALLEL | TEST_RANDOM | TEST_CCS },
> { }
> };
> int i915 = -1;
> --
> 2.20.1
>
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2022-03-02 4:49 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-03-01 21:25 [igt-dev] [PATCH i-g-t v2 0/3] tests/i915: ccs subtests for gem_lmem_swapping Ramalingam C
2022-03-01 21:25 ` [igt-dev] [PATCH i-g-t v2 1/3] i915/gem_engine_topology: Only use the main copy engines for XY_BLOCK_COPY Ramalingam C
2022-03-01 21:25 ` [igt-dev] [PATCH i-g-t v2 2/3] lib/i915_blt: Add library for blitter Ramalingam C
2022-03-01 21:25 ` [igt-dev] [PATCH i-g-t v2 3/3] tests/i915/gem_lmem_swapping: ccs subtests Ramalingam C
2022-03-02 4:49 ` Zbigniew Kempczyński
2022-03-01 22:02 ` [igt-dev] ✗ GitLab.Pipeline: warning for tests/i915: ccs subtests for gem_lmem_swapping (rev3) Patchwork
2022-03-01 22:30 ` [igt-dev] ✓ Fi.CI.BAT: success " Patchwork
2022-03-02 2:48 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
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