* [PATCH v3 0/8] Prep work for next GuC release
@ 2022-03-02 0:33 ` John.C.Harrison
0 siblings, 0 replies; 22+ messages in thread
From: John.C.Harrison @ 2022-03-02 0:33 UTC (permalink / raw)
To: Intel-GFX; +Cc: John Harrison, DRI-Devel
From: John Harrison <John.C.Harrison@Intel.com>
The next GuC firmware release includes some significant backwards
breaking API changes. One such is that there is no longer an LRC
descriptor pool. A bunch of prep work for that change can be done in
advance - the descriptor pool was being used for things it shouldn't
really have been used for anyway.
v2: Extend commit message on 'better name' patch. Improve 'split
apart' patch to include some necessary re-arrangement that was in a
later patch and which introduced an unnecessary conditional in said
patch too. (review feedback from Daniele)
v3: Rebase to newer tree.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
John Harrison (8):
drm/i915/guc: Do not conflate lrc_desc with GuC id for registration
drm/i915/guc: Add an explicit 'submission_initialized' flag
drm/i915/guc: Better name for context id limit
drm/i915/guc: Split guc_lrc_desc_pin apart
drm/i915/guc: Move lrc desc setup to where it is needed
drm/i915/guc: Rename desc_idx to ctx_id
drm/i915/guc: Drop obsolete H2G definitions
drm/i915/guc: Fix potential invalid pointer dereferences when decoding
G2Hs
drivers/gpu/drm/i915/gt/intel_context.c | 2 +-
.../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 2 -
drivers/gpu/drm/i915/gt/uc/intel_guc.h | 2 +
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 4 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 181 ++++++++++--------
drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 2 +-
6 files changed, 109 insertions(+), 84 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH v3 0/8] Prep work for next GuC release
@ 2022-03-02 0:33 ` John.C.Harrison
0 siblings, 0 replies; 22+ messages in thread
From: John.C.Harrison @ 2022-03-02 0:33 UTC (permalink / raw)
To: Intel-GFX; +Cc: DRI-Devel
From: John Harrison <John.C.Harrison@Intel.com>
The next GuC firmware release includes some significant backwards
breaking API changes. One such is that there is no longer an LRC
descriptor pool. A bunch of prep work for that change can be done in
advance - the descriptor pool was being used for things it shouldn't
really have been used for anyway.
v2: Extend commit message on 'better name' patch. Improve 'split
apart' patch to include some necessary re-arrangement that was in a
later patch and which introduced an unnecessary conditional in said
patch too. (review feedback from Daniele)
v3: Rebase to newer tree.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
John Harrison (8):
drm/i915/guc: Do not conflate lrc_desc with GuC id for registration
drm/i915/guc: Add an explicit 'submission_initialized' flag
drm/i915/guc: Better name for context id limit
drm/i915/guc: Split guc_lrc_desc_pin apart
drm/i915/guc: Move lrc desc setup to where it is needed
drm/i915/guc: Rename desc_idx to ctx_id
drm/i915/guc: Drop obsolete H2G definitions
drm/i915/guc: Fix potential invalid pointer dereferences when decoding
G2Hs
drivers/gpu/drm/i915/gt/intel_context.c | 2 +-
.../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 2 -
drivers/gpu/drm/i915/gt/uc/intel_guc.h | 2 +
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 4 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 181 ++++++++++--------
drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 2 +-
6 files changed, 109 insertions(+), 84 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 1/8] drm/i915/guc: Do not conflate lrc_desc with GuC id for registration
2022-03-02 0:33 ` [Intel-gfx] " John.C.Harrison
@ 2022-03-02 0:33 ` John.C.Harrison
-1 siblings, 0 replies; 22+ messages in thread
From: John.C.Harrison @ 2022-03-02 0:33 UTC (permalink / raw)
To: Intel-GFX; +Cc: Daniele Ceraolo Spurio, John Harrison, DRI-Devel
From: John Harrison <John.C.Harrison@Intel.com>
The LRC descriptor pool is going away. So, stop using it as a check for
context registration, use the GuC id instead (being the thing that
actually gets registered with the GuC).
Also, rename the set/clear/query helper functions for context id
mappings to better reflect their purpose and to differentiate from
other registration related helper functions.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 69 ++++++++++---------
1 file changed, 38 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 810910e8042e..2f5f2099a9fc 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -511,31 +511,20 @@ static inline bool guc_submission_initialized(struct intel_guc *guc)
return !!guc->lrc_desc_pool_vaddr;
}
-static inline void reset_lrc_desc(struct intel_guc *guc, u32 id)
+static inline void _reset_lrc_desc(struct intel_guc *guc, u32 id)
{
- if (likely(guc_submission_initialized(guc))) {
- struct guc_lrc_desc *desc = __get_lrc_desc(guc, id);
- unsigned long flags;
-
- memset(desc, 0, sizeof(*desc));
+ struct guc_lrc_desc *desc = __get_lrc_desc(guc, id);
- /*
- * xarray API doesn't have xa_erase_irqsave wrapper, so calling
- * the lower level functions directly.
- */
- xa_lock_irqsave(&guc->context_lookup, flags);
- __xa_erase(&guc->context_lookup, id);
- xa_unlock_irqrestore(&guc->context_lookup, flags);
- }
+ memset(desc, 0, sizeof(*desc));
}
-static inline bool lrc_desc_registered(struct intel_guc *guc, u32 id)
+static inline bool ctx_id_mapped(struct intel_guc *guc, u32 id)
{
return __get_context(guc, id);
}
-static inline void set_lrc_desc_registered(struct intel_guc *guc, u32 id,
- struct intel_context *ce)
+static inline void set_ctx_id_mapping(struct intel_guc *guc, u32 id,
+ struct intel_context *ce)
{
unsigned long flags;
@@ -548,6 +537,24 @@ static inline void set_lrc_desc_registered(struct intel_guc *guc, u32 id,
xa_unlock_irqrestore(&guc->context_lookup, flags);
}
+static inline void clr_ctx_id_mapping(struct intel_guc *guc, u32 id)
+{
+ unsigned long flags;
+
+ if (unlikely(!guc_submission_initialized(guc)))
+ return;
+
+ _reset_lrc_desc(guc, id);
+
+ /*
+ * xarray API doesn't have xa_erase_irqsave wrapper, so calling
+ * the lower level functions directly.
+ */
+ xa_lock_irqsave(&guc->context_lookup, flags);
+ __xa_erase(&guc->context_lookup, id);
+ xa_unlock_irqrestore(&guc->context_lookup, flags);
+}
+
static void decr_outstanding_submission_g2h(struct intel_guc *guc)
{
if (atomic_dec_and_test(&guc->outstanding_submission_g2h))
@@ -792,7 +799,7 @@ static int __guc_wq_item_append(struct i915_request *rq)
GEM_BUG_ON(!atomic_read(&ce->guc_id.ref));
GEM_BUG_ON(context_guc_id_invalid(ce));
GEM_BUG_ON(context_wait_for_deregister_to_register(ce));
- GEM_BUG_ON(!lrc_desc_registered(ce_to_guc(ce), ce->guc_id.id));
+ GEM_BUG_ON(!ctx_id_mapped(ce_to_guc(ce), ce->guc_id.id));
/* Insert NOOP if this work queue item will wrap the tail pointer. */
if (wqi_size > wq_space_until_wrap(ce)) {
@@ -920,7 +927,7 @@ static int guc_dequeue_one_context(struct intel_guc *guc)
if (submit) {
struct intel_context *ce = request_to_scheduling_context(last);
- if (unlikely(!lrc_desc_registered(guc, ce->guc_id.id) &&
+ if (unlikely(!ctx_id_mapped(guc, ce->guc_id.id) &&
!intel_context_is_banned(ce))) {
ret = guc_lrc_desc_pin(ce, false);
if (unlikely(ret == -EPIPE)) {
@@ -1884,7 +1891,7 @@ static bool need_tasklet(struct intel_guc *guc, struct i915_request *rq)
return submission_disabled(guc) || guc->stalled_request ||
!i915_sched_engine_is_empty(sched_engine) ||
- !lrc_desc_registered(guc, ce->guc_id.id);
+ !ctx_id_mapped(guc, ce->guc_id.id);
}
static void guc_submit_request(struct i915_request *rq)
@@ -1941,7 +1948,7 @@ static void __release_guc_id(struct intel_guc *guc, struct intel_context *ce)
else
ida_simple_remove(&guc->submission_state.guc_ids,
ce->guc_id.id);
- reset_lrc_desc(guc, ce->guc_id.id);
+ clr_ctx_id_mapping(guc, ce->guc_id.id);
set_context_guc_id_invalid(ce);
}
if (!list_empty(&ce->guc_id.link))
@@ -2237,10 +2244,10 @@ static int guc_lrc_desc_pin(struct intel_context *ce, bool loop)
GEM_BUG_ON(i915_gem_object_is_lmem(guc->ct.vma->obj) !=
i915_gem_object_is_lmem(ce->ring->vma->obj));
- context_registered = lrc_desc_registered(guc, desc_idx);
+ context_registered = ctx_id_mapped(guc, desc_idx);
- reset_lrc_desc(guc, desc_idx);
- set_lrc_desc_registered(guc, desc_idx, ce);
+ clr_ctx_id_mapping(guc, desc_idx);
+ set_ctx_id_mapping(guc, desc_idx, ce);
desc = __get_lrc_desc(guc, desc_idx);
desc->engine_class = engine_class_to_guc_class(engine->class);
@@ -2311,7 +2318,7 @@ static int guc_lrc_desc_pin(struct intel_context *ce, bool loop)
}
spin_unlock_irqrestore(&ce->guc_state.lock, flags);
if (unlikely(disabled)) {
- reset_lrc_desc(guc, desc_idx);
+ clr_ctx_id_mapping(guc, desc_idx);
return 0; /* Will get registered later */
}
@@ -2327,9 +2334,9 @@ static int guc_lrc_desc_pin(struct intel_context *ce, bool loop)
with_intel_runtime_pm(runtime_pm, wakeref)
ret = register_context(ce, loop);
if (unlikely(ret == -EBUSY)) {
- reset_lrc_desc(guc, desc_idx);
+ clr_ctx_id_mapping(guc, desc_idx);
} else if (unlikely(ret == -ENODEV)) {
- reset_lrc_desc(guc, desc_idx);
+ clr_ctx_id_mapping(guc, desc_idx);
ret = 0; /* Will get registered later */
}
}
@@ -2516,7 +2523,7 @@ static bool context_cant_unblock(struct intel_context *ce)
return (ce->guc_state.sched_state & SCHED_STATE_NO_UNBLOCK) ||
context_guc_id_invalid(ce) ||
- !lrc_desc_registered(ce_to_guc(ce), ce->guc_id.id) ||
+ !ctx_id_mapped(ce_to_guc(ce), ce->guc_id.id) ||
!intel_context_is_pinned(ce);
}
@@ -2686,7 +2693,7 @@ static inline void guc_lrc_desc_unpin(struct intel_context *ce)
bool disabled;
GEM_BUG_ON(!intel_gt_pm_is_awake(gt));
- GEM_BUG_ON(!lrc_desc_registered(guc, ce->guc_id.id));
+ GEM_BUG_ON(!ctx_id_mapped(guc, ce->guc_id.id));
GEM_BUG_ON(ce != __get_context(guc, ce->guc_id.id));
GEM_BUG_ON(context_enabled(ce));
@@ -2803,7 +2810,7 @@ static void guc_context_destroy(struct kref *kref)
*/
spin_lock_irqsave(&guc->submission_state.lock, flags);
destroy = submission_disabled(guc) || context_guc_id_invalid(ce) ||
- !lrc_desc_registered(guc, ce->guc_id.id);
+ !ctx_id_mapped(guc, ce->guc_id.id);
if (likely(!destroy)) {
if (!list_empty(&ce->guc_id.link))
list_del_init(&ce->guc_id.link);
@@ -3046,7 +3053,7 @@ static void guc_signal_context_fence(struct intel_context *ce)
static bool context_needs_register(struct intel_context *ce, bool new_guc_id)
{
return (new_guc_id || test_bit(CONTEXT_LRCA_DIRTY, &ce->flags) ||
- !lrc_desc_registered(ce_to_guc(ce), ce->guc_id.id)) &&
+ !ctx_id_mapped(ce_to_guc(ce), ce->guc_id.id)) &&
!submission_disabled(ce_to_guc(ce));
}
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH v3 1/8] drm/i915/guc: Do not conflate lrc_desc with GuC id for registration
@ 2022-03-02 0:33 ` John.C.Harrison
0 siblings, 0 replies; 22+ messages in thread
From: John.C.Harrison @ 2022-03-02 0:33 UTC (permalink / raw)
To: Intel-GFX; +Cc: DRI-Devel
From: John Harrison <John.C.Harrison@Intel.com>
The LRC descriptor pool is going away. So, stop using it as a check for
context registration, use the GuC id instead (being the thing that
actually gets registered with the GuC).
Also, rename the set/clear/query helper functions for context id
mappings to better reflect their purpose and to differentiate from
other registration related helper functions.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 69 ++++++++++---------
1 file changed, 38 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 810910e8042e..2f5f2099a9fc 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -511,31 +511,20 @@ static inline bool guc_submission_initialized(struct intel_guc *guc)
return !!guc->lrc_desc_pool_vaddr;
}
-static inline void reset_lrc_desc(struct intel_guc *guc, u32 id)
+static inline void _reset_lrc_desc(struct intel_guc *guc, u32 id)
{
- if (likely(guc_submission_initialized(guc))) {
- struct guc_lrc_desc *desc = __get_lrc_desc(guc, id);
- unsigned long flags;
-
- memset(desc, 0, sizeof(*desc));
+ struct guc_lrc_desc *desc = __get_lrc_desc(guc, id);
- /*
- * xarray API doesn't have xa_erase_irqsave wrapper, so calling
- * the lower level functions directly.
- */
- xa_lock_irqsave(&guc->context_lookup, flags);
- __xa_erase(&guc->context_lookup, id);
- xa_unlock_irqrestore(&guc->context_lookup, flags);
- }
+ memset(desc, 0, sizeof(*desc));
}
-static inline bool lrc_desc_registered(struct intel_guc *guc, u32 id)
+static inline bool ctx_id_mapped(struct intel_guc *guc, u32 id)
{
return __get_context(guc, id);
}
-static inline void set_lrc_desc_registered(struct intel_guc *guc, u32 id,
- struct intel_context *ce)
+static inline void set_ctx_id_mapping(struct intel_guc *guc, u32 id,
+ struct intel_context *ce)
{
unsigned long flags;
@@ -548,6 +537,24 @@ static inline void set_lrc_desc_registered(struct intel_guc *guc, u32 id,
xa_unlock_irqrestore(&guc->context_lookup, flags);
}
+static inline void clr_ctx_id_mapping(struct intel_guc *guc, u32 id)
+{
+ unsigned long flags;
+
+ if (unlikely(!guc_submission_initialized(guc)))
+ return;
+
+ _reset_lrc_desc(guc, id);
+
+ /*
+ * xarray API doesn't have xa_erase_irqsave wrapper, so calling
+ * the lower level functions directly.
+ */
+ xa_lock_irqsave(&guc->context_lookup, flags);
+ __xa_erase(&guc->context_lookup, id);
+ xa_unlock_irqrestore(&guc->context_lookup, flags);
+}
+
static void decr_outstanding_submission_g2h(struct intel_guc *guc)
{
if (atomic_dec_and_test(&guc->outstanding_submission_g2h))
@@ -792,7 +799,7 @@ static int __guc_wq_item_append(struct i915_request *rq)
GEM_BUG_ON(!atomic_read(&ce->guc_id.ref));
GEM_BUG_ON(context_guc_id_invalid(ce));
GEM_BUG_ON(context_wait_for_deregister_to_register(ce));
- GEM_BUG_ON(!lrc_desc_registered(ce_to_guc(ce), ce->guc_id.id));
+ GEM_BUG_ON(!ctx_id_mapped(ce_to_guc(ce), ce->guc_id.id));
/* Insert NOOP if this work queue item will wrap the tail pointer. */
if (wqi_size > wq_space_until_wrap(ce)) {
@@ -920,7 +927,7 @@ static int guc_dequeue_one_context(struct intel_guc *guc)
if (submit) {
struct intel_context *ce = request_to_scheduling_context(last);
- if (unlikely(!lrc_desc_registered(guc, ce->guc_id.id) &&
+ if (unlikely(!ctx_id_mapped(guc, ce->guc_id.id) &&
!intel_context_is_banned(ce))) {
ret = guc_lrc_desc_pin(ce, false);
if (unlikely(ret == -EPIPE)) {
@@ -1884,7 +1891,7 @@ static bool need_tasklet(struct intel_guc *guc, struct i915_request *rq)
return submission_disabled(guc) || guc->stalled_request ||
!i915_sched_engine_is_empty(sched_engine) ||
- !lrc_desc_registered(guc, ce->guc_id.id);
+ !ctx_id_mapped(guc, ce->guc_id.id);
}
static void guc_submit_request(struct i915_request *rq)
@@ -1941,7 +1948,7 @@ static void __release_guc_id(struct intel_guc *guc, struct intel_context *ce)
else
ida_simple_remove(&guc->submission_state.guc_ids,
ce->guc_id.id);
- reset_lrc_desc(guc, ce->guc_id.id);
+ clr_ctx_id_mapping(guc, ce->guc_id.id);
set_context_guc_id_invalid(ce);
}
if (!list_empty(&ce->guc_id.link))
@@ -2237,10 +2244,10 @@ static int guc_lrc_desc_pin(struct intel_context *ce, bool loop)
GEM_BUG_ON(i915_gem_object_is_lmem(guc->ct.vma->obj) !=
i915_gem_object_is_lmem(ce->ring->vma->obj));
- context_registered = lrc_desc_registered(guc, desc_idx);
+ context_registered = ctx_id_mapped(guc, desc_idx);
- reset_lrc_desc(guc, desc_idx);
- set_lrc_desc_registered(guc, desc_idx, ce);
+ clr_ctx_id_mapping(guc, desc_idx);
+ set_ctx_id_mapping(guc, desc_idx, ce);
desc = __get_lrc_desc(guc, desc_idx);
desc->engine_class = engine_class_to_guc_class(engine->class);
@@ -2311,7 +2318,7 @@ static int guc_lrc_desc_pin(struct intel_context *ce, bool loop)
}
spin_unlock_irqrestore(&ce->guc_state.lock, flags);
if (unlikely(disabled)) {
- reset_lrc_desc(guc, desc_idx);
+ clr_ctx_id_mapping(guc, desc_idx);
return 0; /* Will get registered later */
}
@@ -2327,9 +2334,9 @@ static int guc_lrc_desc_pin(struct intel_context *ce, bool loop)
with_intel_runtime_pm(runtime_pm, wakeref)
ret = register_context(ce, loop);
if (unlikely(ret == -EBUSY)) {
- reset_lrc_desc(guc, desc_idx);
+ clr_ctx_id_mapping(guc, desc_idx);
} else if (unlikely(ret == -ENODEV)) {
- reset_lrc_desc(guc, desc_idx);
+ clr_ctx_id_mapping(guc, desc_idx);
ret = 0; /* Will get registered later */
}
}
@@ -2516,7 +2523,7 @@ static bool context_cant_unblock(struct intel_context *ce)
return (ce->guc_state.sched_state & SCHED_STATE_NO_UNBLOCK) ||
context_guc_id_invalid(ce) ||
- !lrc_desc_registered(ce_to_guc(ce), ce->guc_id.id) ||
+ !ctx_id_mapped(ce_to_guc(ce), ce->guc_id.id) ||
!intel_context_is_pinned(ce);
}
@@ -2686,7 +2693,7 @@ static inline void guc_lrc_desc_unpin(struct intel_context *ce)
bool disabled;
GEM_BUG_ON(!intel_gt_pm_is_awake(gt));
- GEM_BUG_ON(!lrc_desc_registered(guc, ce->guc_id.id));
+ GEM_BUG_ON(!ctx_id_mapped(guc, ce->guc_id.id));
GEM_BUG_ON(ce != __get_context(guc, ce->guc_id.id));
GEM_BUG_ON(context_enabled(ce));
@@ -2803,7 +2810,7 @@ static void guc_context_destroy(struct kref *kref)
*/
spin_lock_irqsave(&guc->submission_state.lock, flags);
destroy = submission_disabled(guc) || context_guc_id_invalid(ce) ||
- !lrc_desc_registered(guc, ce->guc_id.id);
+ !ctx_id_mapped(guc, ce->guc_id.id);
if (likely(!destroy)) {
if (!list_empty(&ce->guc_id.link))
list_del_init(&ce->guc_id.link);
@@ -3046,7 +3053,7 @@ static void guc_signal_context_fence(struct intel_context *ce)
static bool context_needs_register(struct intel_context *ce, bool new_guc_id)
{
return (new_guc_id || test_bit(CONTEXT_LRCA_DIRTY, &ce->flags) ||
- !lrc_desc_registered(ce_to_guc(ce), ce->guc_id.id)) &&
+ !ctx_id_mapped(ce_to_guc(ce), ce->guc_id.id)) &&
!submission_disabled(ce_to_guc(ce));
}
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v3 2/8] drm/i915/guc: Add an explicit 'submission_initialized' flag
2022-03-02 0:33 ` [Intel-gfx] " John.C.Harrison
@ 2022-03-02 0:33 ` John.C.Harrison
-1 siblings, 0 replies; 22+ messages in thread
From: John.C.Harrison @ 2022-03-02 0:33 UTC (permalink / raw)
To: Intel-GFX; +Cc: Daniele Ceraolo Spurio, John Harrison, DRI-Devel
From: John Harrison <John.C.Harrison@Intel.com>
The LRC descriptor pool is going away. So, stop using it as a check
for whether submission has been initialised or not.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h | 2 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 8 +++++---
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index bf7079480d47..e439e6c1ac8b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -138,6 +138,8 @@ struct intel_guc {
bool submission_supported;
/** @submission_selected: tracks whether the user enabled GuC submission */
bool submission_selected;
+ /** @submission_initialized: tracks whether GuC submission has been initialised */
+ bool submission_initialized;
/**
* @rc_supported: tracks whether we support GuC rc on the current platform
*/
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 2f5f2099a9fc..f2251ce8776e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -508,7 +508,7 @@ static void guc_lrc_desc_pool_destroy(struct intel_guc *guc)
static inline bool guc_submission_initialized(struct intel_guc *guc)
{
- return !!guc->lrc_desc_pool_vaddr;
+ return guc->submission_initialized;
}
static inline void _reset_lrc_desc(struct intel_guc *guc, u32 id)
@@ -1813,7 +1813,7 @@ int intel_guc_submission_init(struct intel_guc *guc)
struct intel_gt *gt = guc_to_gt(guc);
int ret;
- if (guc->lrc_desc_pool)
+ if (guc->submission_initialized)
return 0;
ret = guc_lrc_desc_pool_create(guc);
@@ -1832,19 +1832,21 @@ int intel_guc_submission_init(struct intel_guc *guc)
guc->timestamp.ping_delay = (POLL_TIME_CLKS / gt->clock_frequency + 1) * HZ;
guc->timestamp.shift = gpm_timestamp_shift(gt);
+ guc->submission_initialized = true;
return 0;
}
void intel_guc_submission_fini(struct intel_guc *guc)
{
- if (!guc->lrc_desc_pool)
+ if (!guc->submission_initialized)
return;
guc_flush_destroyed_contexts(guc);
guc_lrc_desc_pool_destroy(guc);
i915_sched_engine_put(guc->sched_engine);
bitmap_free(guc->submission_state.guc_ids_bitmap);
+ guc->submission_initialized = false;
}
static inline void queue_request(struct i915_sched_engine *sched_engine,
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH v3 2/8] drm/i915/guc: Add an explicit 'submission_initialized' flag
@ 2022-03-02 0:33 ` John.C.Harrison
0 siblings, 0 replies; 22+ messages in thread
From: John.C.Harrison @ 2022-03-02 0:33 UTC (permalink / raw)
To: Intel-GFX; +Cc: DRI-Devel
From: John Harrison <John.C.Harrison@Intel.com>
The LRC descriptor pool is going away. So, stop using it as a check
for whether submission has been initialised or not.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h | 2 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 8 +++++---
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index bf7079480d47..e439e6c1ac8b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -138,6 +138,8 @@ struct intel_guc {
bool submission_supported;
/** @submission_selected: tracks whether the user enabled GuC submission */
bool submission_selected;
+ /** @submission_initialized: tracks whether GuC submission has been initialised */
+ bool submission_initialized;
/**
* @rc_supported: tracks whether we support GuC rc on the current platform
*/
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 2f5f2099a9fc..f2251ce8776e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -508,7 +508,7 @@ static void guc_lrc_desc_pool_destroy(struct intel_guc *guc)
static inline bool guc_submission_initialized(struct intel_guc *guc)
{
- return !!guc->lrc_desc_pool_vaddr;
+ return guc->submission_initialized;
}
static inline void _reset_lrc_desc(struct intel_guc *guc, u32 id)
@@ -1813,7 +1813,7 @@ int intel_guc_submission_init(struct intel_guc *guc)
struct intel_gt *gt = guc_to_gt(guc);
int ret;
- if (guc->lrc_desc_pool)
+ if (guc->submission_initialized)
return 0;
ret = guc_lrc_desc_pool_create(guc);
@@ -1832,19 +1832,21 @@ int intel_guc_submission_init(struct intel_guc *guc)
guc->timestamp.ping_delay = (POLL_TIME_CLKS / gt->clock_frequency + 1) * HZ;
guc->timestamp.shift = gpm_timestamp_shift(gt);
+ guc->submission_initialized = true;
return 0;
}
void intel_guc_submission_fini(struct intel_guc *guc)
{
- if (!guc->lrc_desc_pool)
+ if (!guc->submission_initialized)
return;
guc_flush_destroyed_contexts(guc);
guc_lrc_desc_pool_destroy(guc);
i915_sched_engine_put(guc->sched_engine);
bitmap_free(guc->submission_state.guc_ids_bitmap);
+ guc->submission_initialized = false;
}
static inline void queue_request(struct i915_sched_engine *sched_engine,
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v3 3/8] drm/i915/guc: Better name for context id limit
2022-03-02 0:33 ` [Intel-gfx] " John.C.Harrison
@ 2022-03-02 0:33 ` John.C.Harrison
-1 siblings, 0 replies; 22+ messages in thread
From: John.C.Harrison @ 2022-03-02 0:33 UTC (permalink / raw)
To: Intel-GFX; +Cc: Daniele Ceraolo Spurio, John Harrison, DRI-Devel
From: John Harrison <John.C.Harrison@Intel.com>
The LRC descriptor pool is going away. So, stop using it as the limit
for how many context ids are available. Instead, size the pool
according to the number of contexts allowed. Note that this is just a
naming change, the actual limit is identical in value.
While at it, also update a kzalloc(sizeof()*count) to be a
kcalloc(count,size).
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/gt/intel_context.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 4 ++--
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 16 ++++++++--------
drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 2 +-
4 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c
index 5d0ec7c49b6a..d87145b8fca0 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -400,7 +400,7 @@ intel_context_init(struct intel_context *ce, struct intel_engine_cs *engine)
INIT_LIST_HEAD(&ce->guc_state.fences);
INIT_LIST_HEAD(&ce->guc_state.requests);
- ce->guc_id.id = GUC_INVALID_LRC_ID;
+ ce->guc_id.id = GUC_INVALID_CONTEXT_ID;
INIT_LIST_HEAD(&ce->guc_id.link);
INIT_LIST_HEAD(&ce->destroyed_link);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index 6a4612a852e2..11099f0320ce 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -32,8 +32,8 @@
#define GUC_CLIENT_PRIORITY_NORMAL 3
#define GUC_CLIENT_PRIORITY_NUM 4
-#define GUC_MAX_LRC_DESCRIPTORS 65535
-#define GUC_INVALID_LRC_ID GUC_MAX_LRC_DESCRIPTORS
+#define GUC_MAX_CONTEXT_ID 65535
+#define GUC_INVALID_CONTEXT_ID GUC_MAX_CONTEXT_ID
#define GUC_RENDER_ENGINE 0
#define GUC_VIDEO_ENGINE 1
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index f2251ce8776e..833e57e67f2f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -351,12 +351,12 @@ request_to_scheduling_context(struct i915_request *rq)
static inline bool context_guc_id_invalid(struct intel_context *ce)
{
- return ce->guc_id.id == GUC_INVALID_LRC_ID;
+ return ce->guc_id.id == GUC_INVALID_CONTEXT_ID;
}
static inline void set_context_guc_id_invalid(struct intel_context *ce)
{
- ce->guc_id.id = GUC_INVALID_LRC_ID;
+ ce->guc_id.id = GUC_INVALID_CONTEXT_ID;
}
static inline struct intel_guc *ce_to_guc(struct intel_context *ce)
@@ -471,7 +471,7 @@ static struct guc_lrc_desc *__get_lrc_desc(struct intel_guc *guc, u32 index)
{
struct guc_lrc_desc *base = guc->lrc_desc_pool_vaddr;
- GEM_BUG_ON(index >= GUC_MAX_LRC_DESCRIPTORS);
+ GEM_BUG_ON(index >= GUC_MAX_CONTEXT_ID);
return &base[index];
}
@@ -480,7 +480,7 @@ static inline struct intel_context *__get_context(struct intel_guc *guc, u32 id)
{
struct intel_context *ce = xa_load(&guc->context_lookup, id);
- GEM_BUG_ON(id >= GUC_MAX_LRC_DESCRIPTORS);
+ GEM_BUG_ON(id >= GUC_MAX_CONTEXT_ID);
return ce;
}
@@ -491,7 +491,7 @@ static int guc_lrc_desc_pool_create(struct intel_guc *guc)
int ret;
size = PAGE_ALIGN(sizeof(struct guc_lrc_desc) *
- GUC_MAX_LRC_DESCRIPTORS);
+ GUC_MAX_CONTEXT_ID);
ret = intel_guc_allocate_and_map_vma(guc, size, &guc->lrc_desc_pool,
(void **)&guc->lrc_desc_pool_vaddr);
if (ret)
@@ -2428,7 +2428,7 @@ static void __guc_context_sched_disable(struct intel_guc *guc,
GUC_CONTEXT_DISABLE
};
- GEM_BUG_ON(guc_id == GUC_INVALID_LRC_ID);
+ GEM_BUG_ON(guc_id == GUC_INVALID_CONTEXT_ID);
GEM_BUG_ON(intel_context_is_child(ce));
trace_intel_context_sched_disable(ce);
@@ -3841,7 +3841,7 @@ void intel_guc_submission_init_early(struct intel_guc *guc)
spin_lock_init(&guc->timestamp.lock);
INIT_DELAYED_WORK(&guc->timestamp.work, guc_timestamp_ping);
- guc->submission_state.num_guc_ids = GUC_MAX_LRC_DESCRIPTORS;
+ guc->submission_state.num_guc_ids = GUC_MAX_CONTEXT_ID;
guc->submission_supported = __guc_submission_supported(guc);
guc->submission_selected = __guc_submission_selected(guc);
}
@@ -3851,7 +3851,7 @@ g2h_context_lookup(struct intel_guc *guc, u32 desc_idx)
{
struct intel_context *ce;
- if (unlikely(desc_idx >= GUC_MAX_LRC_DESCRIPTORS)) {
+ if (unlikely(desc_idx >= GUC_MAX_CONTEXT_ID)) {
drm_err(&guc_to_gt(guc)->i915->drm,
"Invalid desc_idx %u", desc_idx);
return NULL;
diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
index a115894d5896..1df71d0796ae 100644
--- a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
@@ -148,7 +148,7 @@ static int intel_guc_steal_guc_ids(void *arg)
struct i915_request *spin_rq = NULL, *rq, *last = NULL;
int number_guc_id_stolen = guc->number_guc_id_stolen;
- ce = kzalloc(sizeof(*ce) * GUC_MAX_LRC_DESCRIPTORS, GFP_KERNEL);
+ ce = kcalloc(GUC_MAX_CONTEXT_ID, sizeof(*ce), GFP_KERNEL);
if (!ce) {
pr_err("Context array allocation failed\n");
return -ENOMEM;
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH v3 3/8] drm/i915/guc: Better name for context id limit
@ 2022-03-02 0:33 ` John.C.Harrison
0 siblings, 0 replies; 22+ messages in thread
From: John.C.Harrison @ 2022-03-02 0:33 UTC (permalink / raw)
To: Intel-GFX; +Cc: DRI-Devel
From: John Harrison <John.C.Harrison@Intel.com>
The LRC descriptor pool is going away. So, stop using it as the limit
for how many context ids are available. Instead, size the pool
according to the number of contexts allowed. Note that this is just a
naming change, the actual limit is identical in value.
While at it, also update a kzalloc(sizeof()*count) to be a
kcalloc(count,size).
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/gt/intel_context.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 4 ++--
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 16 ++++++++--------
drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 2 +-
4 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c
index 5d0ec7c49b6a..d87145b8fca0 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -400,7 +400,7 @@ intel_context_init(struct intel_context *ce, struct intel_engine_cs *engine)
INIT_LIST_HEAD(&ce->guc_state.fences);
INIT_LIST_HEAD(&ce->guc_state.requests);
- ce->guc_id.id = GUC_INVALID_LRC_ID;
+ ce->guc_id.id = GUC_INVALID_CONTEXT_ID;
INIT_LIST_HEAD(&ce->guc_id.link);
INIT_LIST_HEAD(&ce->destroyed_link);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index 6a4612a852e2..11099f0320ce 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -32,8 +32,8 @@
#define GUC_CLIENT_PRIORITY_NORMAL 3
#define GUC_CLIENT_PRIORITY_NUM 4
-#define GUC_MAX_LRC_DESCRIPTORS 65535
-#define GUC_INVALID_LRC_ID GUC_MAX_LRC_DESCRIPTORS
+#define GUC_MAX_CONTEXT_ID 65535
+#define GUC_INVALID_CONTEXT_ID GUC_MAX_CONTEXT_ID
#define GUC_RENDER_ENGINE 0
#define GUC_VIDEO_ENGINE 1
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index f2251ce8776e..833e57e67f2f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -351,12 +351,12 @@ request_to_scheduling_context(struct i915_request *rq)
static inline bool context_guc_id_invalid(struct intel_context *ce)
{
- return ce->guc_id.id == GUC_INVALID_LRC_ID;
+ return ce->guc_id.id == GUC_INVALID_CONTEXT_ID;
}
static inline void set_context_guc_id_invalid(struct intel_context *ce)
{
- ce->guc_id.id = GUC_INVALID_LRC_ID;
+ ce->guc_id.id = GUC_INVALID_CONTEXT_ID;
}
static inline struct intel_guc *ce_to_guc(struct intel_context *ce)
@@ -471,7 +471,7 @@ static struct guc_lrc_desc *__get_lrc_desc(struct intel_guc *guc, u32 index)
{
struct guc_lrc_desc *base = guc->lrc_desc_pool_vaddr;
- GEM_BUG_ON(index >= GUC_MAX_LRC_DESCRIPTORS);
+ GEM_BUG_ON(index >= GUC_MAX_CONTEXT_ID);
return &base[index];
}
@@ -480,7 +480,7 @@ static inline struct intel_context *__get_context(struct intel_guc *guc, u32 id)
{
struct intel_context *ce = xa_load(&guc->context_lookup, id);
- GEM_BUG_ON(id >= GUC_MAX_LRC_DESCRIPTORS);
+ GEM_BUG_ON(id >= GUC_MAX_CONTEXT_ID);
return ce;
}
@@ -491,7 +491,7 @@ static int guc_lrc_desc_pool_create(struct intel_guc *guc)
int ret;
size = PAGE_ALIGN(sizeof(struct guc_lrc_desc) *
- GUC_MAX_LRC_DESCRIPTORS);
+ GUC_MAX_CONTEXT_ID);
ret = intel_guc_allocate_and_map_vma(guc, size, &guc->lrc_desc_pool,
(void **)&guc->lrc_desc_pool_vaddr);
if (ret)
@@ -2428,7 +2428,7 @@ static void __guc_context_sched_disable(struct intel_guc *guc,
GUC_CONTEXT_DISABLE
};
- GEM_BUG_ON(guc_id == GUC_INVALID_LRC_ID);
+ GEM_BUG_ON(guc_id == GUC_INVALID_CONTEXT_ID);
GEM_BUG_ON(intel_context_is_child(ce));
trace_intel_context_sched_disable(ce);
@@ -3841,7 +3841,7 @@ void intel_guc_submission_init_early(struct intel_guc *guc)
spin_lock_init(&guc->timestamp.lock);
INIT_DELAYED_WORK(&guc->timestamp.work, guc_timestamp_ping);
- guc->submission_state.num_guc_ids = GUC_MAX_LRC_DESCRIPTORS;
+ guc->submission_state.num_guc_ids = GUC_MAX_CONTEXT_ID;
guc->submission_supported = __guc_submission_supported(guc);
guc->submission_selected = __guc_submission_selected(guc);
}
@@ -3851,7 +3851,7 @@ g2h_context_lookup(struct intel_guc *guc, u32 desc_idx)
{
struct intel_context *ce;
- if (unlikely(desc_idx >= GUC_MAX_LRC_DESCRIPTORS)) {
+ if (unlikely(desc_idx >= GUC_MAX_CONTEXT_ID)) {
drm_err(&guc_to_gt(guc)->i915->drm,
"Invalid desc_idx %u", desc_idx);
return NULL;
diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
index a115894d5896..1df71d0796ae 100644
--- a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
@@ -148,7 +148,7 @@ static int intel_guc_steal_guc_ids(void *arg)
struct i915_request *spin_rq = NULL, *rq, *last = NULL;
int number_guc_id_stolen = guc->number_guc_id_stolen;
- ce = kzalloc(sizeof(*ce) * GUC_MAX_LRC_DESCRIPTORS, GFP_KERNEL);
+ ce = kcalloc(GUC_MAX_CONTEXT_ID, sizeof(*ce), GFP_KERNEL);
if (!ce) {
pr_err("Context array allocation failed\n");
return -ENOMEM;
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v3 4/8] drm/i915/guc: Split guc_lrc_desc_pin apart
2022-03-02 0:33 ` [Intel-gfx] " John.C.Harrison
@ 2022-03-02 0:33 ` John.C.Harrison
-1 siblings, 0 replies; 22+ messages in thread
From: John.C.Harrison @ 2022-03-02 0:33 UTC (permalink / raw)
To: Intel-GFX; +Cc: Daniele Ceraolo Spurio, John Harrison, DRI-Devel
From: John Harrison <John.C.Harrison@Intel.com>
The LRC descriptor pool is going away. Further, the function that was
populating it was also doing a bunch of logic about the context
registration sequence. So, split that code apart into separate state
setup and try to register functions. Note that some of those 'try to
register' code paths actually undo the state setup and leave it to be
redone again later (with potentially different values). This is
inefficient. The next patch will correct this.
Also, move a comment about ignoring return values to the place where
the return values are actually ignored.
v2: Move some more splitting from a later patch (and do it correctly).
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 54 +++++++++++--------
1 file changed, 33 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 833e57e67f2f..04b6af6fc416 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -631,7 +631,7 @@ int intel_guc_wait_for_idle(struct intel_guc *guc, long timeout)
true, timeout);
}
-static int guc_lrc_desc_pin(struct intel_context *ce, bool loop);
+static int try_context_registration(struct intel_context *ce, bool loop);
static int __guc_add_request(struct intel_guc *guc, struct i915_request *rq)
{
@@ -929,7 +929,7 @@ static int guc_dequeue_one_context(struct intel_guc *guc)
if (unlikely(!ctx_id_mapped(guc, ce->guc_id.id) &&
!intel_context_is_banned(ce))) {
- ret = guc_lrc_desc_pin(ce, false);
+ ret = try_context_registration(ce, false);
if (unlikely(ret == -EPIPE)) {
goto deadlk;
} else if (ret == -EBUSY) {
@@ -2224,20 +2224,15 @@ static void guc_context_policy_init(struct intel_engine_cs *engine,
desc->preemption_timeout = engine->props.preempt_timeout_ms * 1000;
}
-static int guc_lrc_desc_pin(struct intel_context *ce, bool loop)
+static void prepare_context_registration_info(struct intel_context *ce)
{
struct intel_engine_cs *engine = ce->engine;
- struct intel_runtime_pm *runtime_pm = engine->uncore->rpm;
struct intel_guc *guc = &engine->gt->uc.guc;
u32 desc_idx = ce->guc_id.id;
struct guc_lrc_desc *desc;
- bool context_registered;
- intel_wakeref_t wakeref;
struct intel_context *child;
- int ret = 0;
GEM_BUG_ON(!engine->mask);
- GEM_BUG_ON(!sched_state_is_init(ce));
/*
* Ensure LRC + CT vmas are is same region as write barrier is done
@@ -2246,11 +2241,6 @@ static int guc_lrc_desc_pin(struct intel_context *ce, bool loop)
GEM_BUG_ON(i915_gem_object_is_lmem(guc->ct.vma->obj) !=
i915_gem_object_is_lmem(ce->ring->vma->obj));
- context_registered = ctx_id_mapped(guc, desc_idx);
-
- clr_ctx_id_mapping(guc, desc_idx);
- set_ctx_id_mapping(guc, desc_idx, ce);
-
desc = __get_lrc_desc(guc, desc_idx);
desc->engine_class = engine_class_to_guc_class(engine->class);
desc->engine_submit_mask = engine->logical_mask;
@@ -2295,6 +2285,26 @@ static int guc_lrc_desc_pin(struct intel_context *ce, bool loop)
clear_children_join_go_memory(ce);
}
+}
+
+static int try_context_registration(struct intel_context *ce, bool loop)
+{
+ struct intel_engine_cs *engine = ce->engine;
+ struct intel_runtime_pm *runtime_pm = engine->uncore->rpm;
+ struct intel_guc *guc = &engine->gt->uc.guc;
+ intel_wakeref_t wakeref;
+ u32 desc_idx = ce->guc_id.id;
+ bool context_registered;
+ int ret = 0;
+
+ GEM_BUG_ON(!sched_state_is_init(ce));
+
+ context_registered = ctx_id_mapped(guc, desc_idx);
+
+ clr_ctx_id_mapping(guc, desc_idx);
+ set_ctx_id_mapping(guc, desc_idx, ce);
+
+ prepare_context_registration_info(ce);
/*
* The context_lookup xarray is used to determine if the hardware
@@ -3132,7 +3142,7 @@ static int guc_request_alloc(struct i915_request *rq)
if (unlikely(ret < 0))
return ret;
if (context_needs_register(ce, !!ret)) {
- ret = guc_lrc_desc_pin(ce, true);
+ ret = try_context_registration(ce, true);
if (unlikely(ret)) { /* unwind */
if (ret == -EPIPE) {
disable_submission(guc);
@@ -3620,9 +3630,17 @@ static void guc_set_default_submission(struct intel_engine_cs *engine)
static inline void guc_kernel_context_pin(struct intel_guc *guc,
struct intel_context *ce)
{
+ /*
+ * Note: we purposefully do not check the returns below because
+ * the registration can only fail if a reset is just starting.
+ * This is called at the end of reset so presumably another reset
+ * isn't happening and even it did this code would be run again.
+ */
+
if (context_guc_id_invalid(ce))
pin_guc_id(guc, ce);
- guc_lrc_desc_pin(ce, true);
+
+ try_context_registration(ce, true);
}
static inline void guc_init_lrc_mapping(struct intel_guc *guc)
@@ -3640,13 +3658,7 @@ static inline void guc_init_lrc_mapping(struct intel_guc *guc)
* Also, after a reset the of the GuC we want to make sure that the
* information shared with GuC is properly reset. The kernel LRCs are
* not attached to the gem_context, so they need to be added separately.
- *
- * Note: we purposefully do not check the return of guc_lrc_desc_pin,
- * because that function can only fail if a reset is just starting. This
- * is at the end of reset so presumably another reset isn't happening
- * and even it did this code would be run again.
*/
-
for_each_engine(engine, gt, id) {
struct intel_context *ce;
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH v3 4/8] drm/i915/guc: Split guc_lrc_desc_pin apart
@ 2022-03-02 0:33 ` John.C.Harrison
0 siblings, 0 replies; 22+ messages in thread
From: John.C.Harrison @ 2022-03-02 0:33 UTC (permalink / raw)
To: Intel-GFX; +Cc: DRI-Devel
From: John Harrison <John.C.Harrison@Intel.com>
The LRC descriptor pool is going away. Further, the function that was
populating it was also doing a bunch of logic about the context
registration sequence. So, split that code apart into separate state
setup and try to register functions. Note that some of those 'try to
register' code paths actually undo the state setup and leave it to be
redone again later (with potentially different values). This is
inefficient. The next patch will correct this.
Also, move a comment about ignoring return values to the place where
the return values are actually ignored.
v2: Move some more splitting from a later patch (and do it correctly).
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 54 +++++++++++--------
1 file changed, 33 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 833e57e67f2f..04b6af6fc416 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -631,7 +631,7 @@ int intel_guc_wait_for_idle(struct intel_guc *guc, long timeout)
true, timeout);
}
-static int guc_lrc_desc_pin(struct intel_context *ce, bool loop);
+static int try_context_registration(struct intel_context *ce, bool loop);
static int __guc_add_request(struct intel_guc *guc, struct i915_request *rq)
{
@@ -929,7 +929,7 @@ static int guc_dequeue_one_context(struct intel_guc *guc)
if (unlikely(!ctx_id_mapped(guc, ce->guc_id.id) &&
!intel_context_is_banned(ce))) {
- ret = guc_lrc_desc_pin(ce, false);
+ ret = try_context_registration(ce, false);
if (unlikely(ret == -EPIPE)) {
goto deadlk;
} else if (ret == -EBUSY) {
@@ -2224,20 +2224,15 @@ static void guc_context_policy_init(struct intel_engine_cs *engine,
desc->preemption_timeout = engine->props.preempt_timeout_ms * 1000;
}
-static int guc_lrc_desc_pin(struct intel_context *ce, bool loop)
+static void prepare_context_registration_info(struct intel_context *ce)
{
struct intel_engine_cs *engine = ce->engine;
- struct intel_runtime_pm *runtime_pm = engine->uncore->rpm;
struct intel_guc *guc = &engine->gt->uc.guc;
u32 desc_idx = ce->guc_id.id;
struct guc_lrc_desc *desc;
- bool context_registered;
- intel_wakeref_t wakeref;
struct intel_context *child;
- int ret = 0;
GEM_BUG_ON(!engine->mask);
- GEM_BUG_ON(!sched_state_is_init(ce));
/*
* Ensure LRC + CT vmas are is same region as write barrier is done
@@ -2246,11 +2241,6 @@ static int guc_lrc_desc_pin(struct intel_context *ce, bool loop)
GEM_BUG_ON(i915_gem_object_is_lmem(guc->ct.vma->obj) !=
i915_gem_object_is_lmem(ce->ring->vma->obj));
- context_registered = ctx_id_mapped(guc, desc_idx);
-
- clr_ctx_id_mapping(guc, desc_idx);
- set_ctx_id_mapping(guc, desc_idx, ce);
-
desc = __get_lrc_desc(guc, desc_idx);
desc->engine_class = engine_class_to_guc_class(engine->class);
desc->engine_submit_mask = engine->logical_mask;
@@ -2295,6 +2285,26 @@ static int guc_lrc_desc_pin(struct intel_context *ce, bool loop)
clear_children_join_go_memory(ce);
}
+}
+
+static int try_context_registration(struct intel_context *ce, bool loop)
+{
+ struct intel_engine_cs *engine = ce->engine;
+ struct intel_runtime_pm *runtime_pm = engine->uncore->rpm;
+ struct intel_guc *guc = &engine->gt->uc.guc;
+ intel_wakeref_t wakeref;
+ u32 desc_idx = ce->guc_id.id;
+ bool context_registered;
+ int ret = 0;
+
+ GEM_BUG_ON(!sched_state_is_init(ce));
+
+ context_registered = ctx_id_mapped(guc, desc_idx);
+
+ clr_ctx_id_mapping(guc, desc_idx);
+ set_ctx_id_mapping(guc, desc_idx, ce);
+
+ prepare_context_registration_info(ce);
/*
* The context_lookup xarray is used to determine if the hardware
@@ -3132,7 +3142,7 @@ static int guc_request_alloc(struct i915_request *rq)
if (unlikely(ret < 0))
return ret;
if (context_needs_register(ce, !!ret)) {
- ret = guc_lrc_desc_pin(ce, true);
+ ret = try_context_registration(ce, true);
if (unlikely(ret)) { /* unwind */
if (ret == -EPIPE) {
disable_submission(guc);
@@ -3620,9 +3630,17 @@ static void guc_set_default_submission(struct intel_engine_cs *engine)
static inline void guc_kernel_context_pin(struct intel_guc *guc,
struct intel_context *ce)
{
+ /*
+ * Note: we purposefully do not check the returns below because
+ * the registration can only fail if a reset is just starting.
+ * This is called at the end of reset so presumably another reset
+ * isn't happening and even it did this code would be run again.
+ */
+
if (context_guc_id_invalid(ce))
pin_guc_id(guc, ce);
- guc_lrc_desc_pin(ce, true);
+
+ try_context_registration(ce, true);
}
static inline void guc_init_lrc_mapping(struct intel_guc *guc)
@@ -3640,13 +3658,7 @@ static inline void guc_init_lrc_mapping(struct intel_guc *guc)
* Also, after a reset the of the GuC we want to make sure that the
* information shared with GuC is properly reset. The kernel LRCs are
* not attached to the gem_context, so they need to be added separately.
- *
- * Note: we purposefully do not check the return of guc_lrc_desc_pin,
- * because that function can only fail if a reset is just starting. This
- * is at the end of reset so presumably another reset isn't happening
- * and even it did this code would be run again.
*/
-
for_each_engine(engine, gt, id) {
struct intel_context *ce;
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v3 5/8] drm/i915/guc: Move lrc desc setup to where it is needed
2022-03-02 0:33 ` [Intel-gfx] " John.C.Harrison
@ 2022-03-02 0:33 ` John.C.Harrison
-1 siblings, 0 replies; 22+ messages in thread
From: John.C.Harrison @ 2022-03-02 0:33 UTC (permalink / raw)
To: Intel-GFX; +Cc: Daniele Ceraolo Spurio, John Harrison, DRI-Devel
From: John Harrison <John.C.Harrison@Intel.com>
The LRC descriptor was being initialised early on in the context
registration sequence. It could then be determined that the actual
registration needs to be delayed and the descriptor would be wiped
out. This is inefficient, so move the setup to later in the process
after the point of no return.
v2: Move some split changes into the split patch (and do them
correctly).
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 04b6af6fc416..f493bb57f64e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2140,6 +2140,8 @@ static int __guc_action_register_context(struct intel_guc *guc,
0, loop);
}
+static void prepare_context_registration_info(struct intel_context *ce);
+
static int register_context(struct intel_context *ce, bool loop)
{
struct intel_guc *guc = ce_to_guc(ce);
@@ -2150,6 +2152,8 @@ static int register_context(struct intel_context *ce, bool loop)
GEM_BUG_ON(intel_context_is_child(ce));
trace_intel_context_register(ce);
+ prepare_context_registration_info(ce);
+
if (intel_context_is_parent(ce))
ret = __guc_action_register_multi_lrc(guc, ce, ce->guc_id.id,
offset, loop);
@@ -2304,8 +2308,6 @@ static int try_context_registration(struct intel_context *ce, bool loop)
clr_ctx_id_mapping(guc, desc_idx);
set_ctx_id_mapping(guc, desc_idx, ce);
- prepare_context_registration_info(ce);
-
/*
* The context_lookup xarray is used to determine if the hardware
* context is currently registered. There are two cases in which it
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH v3 5/8] drm/i915/guc: Move lrc desc setup to where it is needed
@ 2022-03-02 0:33 ` John.C.Harrison
0 siblings, 0 replies; 22+ messages in thread
From: John.C.Harrison @ 2022-03-02 0:33 UTC (permalink / raw)
To: Intel-GFX; +Cc: DRI-Devel
From: John Harrison <John.C.Harrison@Intel.com>
The LRC descriptor was being initialised early on in the context
registration sequence. It could then be determined that the actual
registration needs to be delayed and the descriptor would be wiped
out. This is inefficient, so move the setup to later in the process
after the point of no return.
v2: Move some split changes into the split patch (and do them
correctly).
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 04b6af6fc416..f493bb57f64e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2140,6 +2140,8 @@ static int __guc_action_register_context(struct intel_guc *guc,
0, loop);
}
+static void prepare_context_registration_info(struct intel_context *ce);
+
static int register_context(struct intel_context *ce, bool loop)
{
struct intel_guc *guc = ce_to_guc(ce);
@@ -2150,6 +2152,8 @@ static int register_context(struct intel_context *ce, bool loop)
GEM_BUG_ON(intel_context_is_child(ce));
trace_intel_context_register(ce);
+ prepare_context_registration_info(ce);
+
if (intel_context_is_parent(ce))
ret = __guc_action_register_multi_lrc(guc, ce, ce->guc_id.id,
offset, loop);
@@ -2304,8 +2308,6 @@ static int try_context_registration(struct intel_context *ce, bool loop)
clr_ctx_id_mapping(guc, desc_idx);
set_ctx_id_mapping(guc, desc_idx, ce);
- prepare_context_registration_info(ce);
-
/*
* The context_lookup xarray is used to determine if the hardware
* context is currently registered. There are two cases in which it
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v3 6/8] drm/i915/guc: Rename desc_idx to ctx_id
2022-03-02 0:33 ` [Intel-gfx] " John.C.Harrison
@ 2022-03-02 0:33 ` John.C.Harrison
-1 siblings, 0 replies; 22+ messages in thread
From: John.C.Harrison @ 2022-03-02 0:33 UTC (permalink / raw)
To: Intel-GFX; +Cc: Daniele Ceraolo Spurio, John Harrison, DRI-Devel
From: John Harrison <John.C.Harrison@Intel.com>
The LRC descriptor pool is going away. So, stop naming context ids as
descriptor pool indecies.
While at it, add a bunch of missing line feeds to some error messages.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 52 +++++++++----------
1 file changed, 26 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index f493bb57f64e..5dbebf15fae1 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2232,7 +2232,7 @@ static void prepare_context_registration_info(struct intel_context *ce)
{
struct intel_engine_cs *engine = ce->engine;
struct intel_guc *guc = &engine->gt->uc.guc;
- u32 desc_idx = ce->guc_id.id;
+ u32 ctx_id = ce->guc_id.id;
struct guc_lrc_desc *desc;
struct intel_context *child;
@@ -2245,7 +2245,7 @@ static void prepare_context_registration_info(struct intel_context *ce)
GEM_BUG_ON(i915_gem_object_is_lmem(guc->ct.vma->obj) !=
i915_gem_object_is_lmem(ce->ring->vma->obj));
- desc = __get_lrc_desc(guc, desc_idx);
+ desc = __get_lrc_desc(guc, ctx_id);
desc->engine_class = engine_class_to_guc_class(engine->class);
desc->engine_submit_mask = engine->logical_mask;
desc->hw_context_desc = ce->lrc.lrca;
@@ -2297,16 +2297,16 @@ static int try_context_registration(struct intel_context *ce, bool loop)
struct intel_runtime_pm *runtime_pm = engine->uncore->rpm;
struct intel_guc *guc = &engine->gt->uc.guc;
intel_wakeref_t wakeref;
- u32 desc_idx = ce->guc_id.id;
+ u32 ctx_id = ce->guc_id.id;
bool context_registered;
int ret = 0;
GEM_BUG_ON(!sched_state_is_init(ce));
- context_registered = ctx_id_mapped(guc, desc_idx);
+ context_registered = ctx_id_mapped(guc, ctx_id);
- clr_ctx_id_mapping(guc, desc_idx);
- set_ctx_id_mapping(guc, desc_idx, ce);
+ clr_ctx_id_mapping(guc, ctx_id);
+ set_ctx_id_mapping(guc, ctx_id, ce);
/*
* The context_lookup xarray is used to determine if the hardware
@@ -2332,7 +2332,7 @@ static int try_context_registration(struct intel_context *ce, bool loop)
}
spin_unlock_irqrestore(&ce->guc_state.lock, flags);
if (unlikely(disabled)) {
- clr_ctx_id_mapping(guc, desc_idx);
+ clr_ctx_id_mapping(guc, ctx_id);
return 0; /* Will get registered later */
}
@@ -2348,9 +2348,9 @@ static int try_context_registration(struct intel_context *ce, bool loop)
with_intel_runtime_pm(runtime_pm, wakeref)
ret = register_context(ce, loop);
if (unlikely(ret == -EBUSY)) {
- clr_ctx_id_mapping(guc, desc_idx);
+ clr_ctx_id_mapping(guc, ctx_id);
} else if (unlikely(ret == -ENODEV)) {
- clr_ctx_id_mapping(guc, desc_idx);
+ clr_ctx_id_mapping(guc, ctx_id);
ret = 0; /* Will get registered later */
}
}
@@ -3861,26 +3861,26 @@ void intel_guc_submission_init_early(struct intel_guc *guc)
}
static inline struct intel_context *
-g2h_context_lookup(struct intel_guc *guc, u32 desc_idx)
+g2h_context_lookup(struct intel_guc *guc, u32 ctx_id)
{
struct intel_context *ce;
- if (unlikely(desc_idx >= GUC_MAX_CONTEXT_ID)) {
+ if (unlikely(ctx_id >= GUC_MAX_CONTEXT_ID)) {
drm_err(&guc_to_gt(guc)->i915->drm,
- "Invalid desc_idx %u", desc_idx);
+ "Invalid ctx_id %u\n", ctx_id);
return NULL;
}
- ce = __get_context(guc, desc_idx);
+ ce = __get_context(guc, ctx_id);
if (unlikely(!ce)) {
drm_err(&guc_to_gt(guc)->i915->drm,
- "Context is NULL, desc_idx %u", desc_idx);
+ "Context is NULL, ctx_id %u\n", ctx_id);
return NULL;
}
if (unlikely(intel_context_is_child(ce))) {
drm_err(&guc_to_gt(guc)->i915->drm,
- "Context is child, desc_idx %u", desc_idx);
+ "Context is child, ctx_id %u\n", ctx_id);
return NULL;
}
@@ -3892,14 +3892,14 @@ int intel_guc_deregister_done_process_msg(struct intel_guc *guc,
u32 len)
{
struct intel_context *ce;
- u32 desc_idx = msg[0];
+ u32 ctx_id = msg[0];
if (unlikely(len < 1)) {
- drm_err(&guc_to_gt(guc)->i915->drm, "Invalid length %u", len);
+ drm_err(&guc_to_gt(guc)->i915->drm, "Invalid length %u\n", len);
return -EPROTO;
}
- ce = g2h_context_lookup(guc, desc_idx);
+ ce = g2h_context_lookup(guc, ctx_id);
if (unlikely(!ce))
return -EPROTO;
@@ -3943,14 +3943,14 @@ int intel_guc_sched_done_process_msg(struct intel_guc *guc,
{
struct intel_context *ce;
unsigned long flags;
- u32 desc_idx = msg[0];
+ u32 ctx_id = msg[0];
if (unlikely(len < 2)) {
- drm_err(&guc_to_gt(guc)->i915->drm, "Invalid length %u", len);
+ drm_err(&guc_to_gt(guc)->i915->drm, "Invalid length %u\n", len);
return -EPROTO;
}
- ce = g2h_context_lookup(guc, desc_idx);
+ ce = g2h_context_lookup(guc, ctx_id);
if (unlikely(!ce))
return -EPROTO;
@@ -3958,8 +3958,8 @@ int intel_guc_sched_done_process_msg(struct intel_guc *guc,
(!context_pending_enable(ce) &&
!context_pending_disable(ce)))) {
drm_err(&guc_to_gt(guc)->i915->drm,
- "Bad context sched_state 0x%x, desc_idx %u",
- ce->guc_state.sched_state, desc_idx);
+ "Bad context sched_state 0x%x, ctx_id %u\n",
+ ce->guc_state.sched_state, ctx_id);
return -EPROTO;
}
@@ -4057,14 +4057,14 @@ int intel_guc_context_reset_process_msg(struct intel_guc *guc,
{
struct intel_context *ce;
unsigned long flags;
- int desc_idx;
+ int ctx_id;
if (unlikely(len != 1)) {
drm_err(&guc_to_gt(guc)->i915->drm, "Invalid length %u", len);
return -EPROTO;
}
- desc_idx = msg[0];
+ ctx_id = msg[0];
/*
* The context lookup uses the xarray but lookups only require an RCU lock
@@ -4073,7 +4073,7 @@ int intel_guc_context_reset_process_msg(struct intel_guc *guc,
* asynchronously until the reset is done.
*/
xa_lock_irqsave(&guc->context_lookup, flags);
- ce = g2h_context_lookup(guc, desc_idx);
+ ce = g2h_context_lookup(guc, ctx_id);
if (ce)
intel_context_get(ce);
xa_unlock_irqrestore(&guc->context_lookup, flags);
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH v3 6/8] drm/i915/guc: Rename desc_idx to ctx_id
@ 2022-03-02 0:33 ` John.C.Harrison
0 siblings, 0 replies; 22+ messages in thread
From: John.C.Harrison @ 2022-03-02 0:33 UTC (permalink / raw)
To: Intel-GFX; +Cc: DRI-Devel
From: John Harrison <John.C.Harrison@Intel.com>
The LRC descriptor pool is going away. So, stop naming context ids as
descriptor pool indecies.
While at it, add a bunch of missing line feeds to some error messages.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 52 +++++++++----------
1 file changed, 26 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index f493bb57f64e..5dbebf15fae1 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2232,7 +2232,7 @@ static void prepare_context_registration_info(struct intel_context *ce)
{
struct intel_engine_cs *engine = ce->engine;
struct intel_guc *guc = &engine->gt->uc.guc;
- u32 desc_idx = ce->guc_id.id;
+ u32 ctx_id = ce->guc_id.id;
struct guc_lrc_desc *desc;
struct intel_context *child;
@@ -2245,7 +2245,7 @@ static void prepare_context_registration_info(struct intel_context *ce)
GEM_BUG_ON(i915_gem_object_is_lmem(guc->ct.vma->obj) !=
i915_gem_object_is_lmem(ce->ring->vma->obj));
- desc = __get_lrc_desc(guc, desc_idx);
+ desc = __get_lrc_desc(guc, ctx_id);
desc->engine_class = engine_class_to_guc_class(engine->class);
desc->engine_submit_mask = engine->logical_mask;
desc->hw_context_desc = ce->lrc.lrca;
@@ -2297,16 +2297,16 @@ static int try_context_registration(struct intel_context *ce, bool loop)
struct intel_runtime_pm *runtime_pm = engine->uncore->rpm;
struct intel_guc *guc = &engine->gt->uc.guc;
intel_wakeref_t wakeref;
- u32 desc_idx = ce->guc_id.id;
+ u32 ctx_id = ce->guc_id.id;
bool context_registered;
int ret = 0;
GEM_BUG_ON(!sched_state_is_init(ce));
- context_registered = ctx_id_mapped(guc, desc_idx);
+ context_registered = ctx_id_mapped(guc, ctx_id);
- clr_ctx_id_mapping(guc, desc_idx);
- set_ctx_id_mapping(guc, desc_idx, ce);
+ clr_ctx_id_mapping(guc, ctx_id);
+ set_ctx_id_mapping(guc, ctx_id, ce);
/*
* The context_lookup xarray is used to determine if the hardware
@@ -2332,7 +2332,7 @@ static int try_context_registration(struct intel_context *ce, bool loop)
}
spin_unlock_irqrestore(&ce->guc_state.lock, flags);
if (unlikely(disabled)) {
- clr_ctx_id_mapping(guc, desc_idx);
+ clr_ctx_id_mapping(guc, ctx_id);
return 0; /* Will get registered later */
}
@@ -2348,9 +2348,9 @@ static int try_context_registration(struct intel_context *ce, bool loop)
with_intel_runtime_pm(runtime_pm, wakeref)
ret = register_context(ce, loop);
if (unlikely(ret == -EBUSY)) {
- clr_ctx_id_mapping(guc, desc_idx);
+ clr_ctx_id_mapping(guc, ctx_id);
} else if (unlikely(ret == -ENODEV)) {
- clr_ctx_id_mapping(guc, desc_idx);
+ clr_ctx_id_mapping(guc, ctx_id);
ret = 0; /* Will get registered later */
}
}
@@ -3861,26 +3861,26 @@ void intel_guc_submission_init_early(struct intel_guc *guc)
}
static inline struct intel_context *
-g2h_context_lookup(struct intel_guc *guc, u32 desc_idx)
+g2h_context_lookup(struct intel_guc *guc, u32 ctx_id)
{
struct intel_context *ce;
- if (unlikely(desc_idx >= GUC_MAX_CONTEXT_ID)) {
+ if (unlikely(ctx_id >= GUC_MAX_CONTEXT_ID)) {
drm_err(&guc_to_gt(guc)->i915->drm,
- "Invalid desc_idx %u", desc_idx);
+ "Invalid ctx_id %u\n", ctx_id);
return NULL;
}
- ce = __get_context(guc, desc_idx);
+ ce = __get_context(guc, ctx_id);
if (unlikely(!ce)) {
drm_err(&guc_to_gt(guc)->i915->drm,
- "Context is NULL, desc_idx %u", desc_idx);
+ "Context is NULL, ctx_id %u\n", ctx_id);
return NULL;
}
if (unlikely(intel_context_is_child(ce))) {
drm_err(&guc_to_gt(guc)->i915->drm,
- "Context is child, desc_idx %u", desc_idx);
+ "Context is child, ctx_id %u\n", ctx_id);
return NULL;
}
@@ -3892,14 +3892,14 @@ int intel_guc_deregister_done_process_msg(struct intel_guc *guc,
u32 len)
{
struct intel_context *ce;
- u32 desc_idx = msg[0];
+ u32 ctx_id = msg[0];
if (unlikely(len < 1)) {
- drm_err(&guc_to_gt(guc)->i915->drm, "Invalid length %u", len);
+ drm_err(&guc_to_gt(guc)->i915->drm, "Invalid length %u\n", len);
return -EPROTO;
}
- ce = g2h_context_lookup(guc, desc_idx);
+ ce = g2h_context_lookup(guc, ctx_id);
if (unlikely(!ce))
return -EPROTO;
@@ -3943,14 +3943,14 @@ int intel_guc_sched_done_process_msg(struct intel_guc *guc,
{
struct intel_context *ce;
unsigned long flags;
- u32 desc_idx = msg[0];
+ u32 ctx_id = msg[0];
if (unlikely(len < 2)) {
- drm_err(&guc_to_gt(guc)->i915->drm, "Invalid length %u", len);
+ drm_err(&guc_to_gt(guc)->i915->drm, "Invalid length %u\n", len);
return -EPROTO;
}
- ce = g2h_context_lookup(guc, desc_idx);
+ ce = g2h_context_lookup(guc, ctx_id);
if (unlikely(!ce))
return -EPROTO;
@@ -3958,8 +3958,8 @@ int intel_guc_sched_done_process_msg(struct intel_guc *guc,
(!context_pending_enable(ce) &&
!context_pending_disable(ce)))) {
drm_err(&guc_to_gt(guc)->i915->drm,
- "Bad context sched_state 0x%x, desc_idx %u",
- ce->guc_state.sched_state, desc_idx);
+ "Bad context sched_state 0x%x, ctx_id %u\n",
+ ce->guc_state.sched_state, ctx_id);
return -EPROTO;
}
@@ -4057,14 +4057,14 @@ int intel_guc_context_reset_process_msg(struct intel_guc *guc,
{
struct intel_context *ce;
unsigned long flags;
- int desc_idx;
+ int ctx_id;
if (unlikely(len != 1)) {
drm_err(&guc_to_gt(guc)->i915->drm, "Invalid length %u", len);
return -EPROTO;
}
- desc_idx = msg[0];
+ ctx_id = msg[0];
/*
* The context lookup uses the xarray but lookups only require an RCU lock
@@ -4073,7 +4073,7 @@ int intel_guc_context_reset_process_msg(struct intel_guc *guc,
* asynchronously until the reset is done.
*/
xa_lock_irqsave(&guc->context_lookup, flags);
- ce = g2h_context_lookup(guc, desc_idx);
+ ce = g2h_context_lookup(guc, ctx_id);
if (ce)
intel_context_get(ce);
xa_unlock_irqrestore(&guc->context_lookup, flags);
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v3 7/8] drm/i915/guc: Drop obsolete H2G definitions
2022-03-02 0:33 ` [Intel-gfx] " John.C.Harrison
@ 2022-03-02 0:33 ` John.C.Harrison
-1 siblings, 0 replies; 22+ messages in thread
From: John.C.Harrison @ 2022-03-02 0:33 UTC (permalink / raw)
To: Intel-GFX; +Cc: Daniele Ceraolo Spurio, John Harrison, DRI-Devel
From: John Harrison <John.C.Harrison@Intel.com>
The CTB registration process changed significantly a while back using
a single KLV based H2G. So drop the original and now obsolete H2G
definitions.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
index 7afdadc7656f..e77f955435ce 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
@@ -131,8 +131,6 @@ enum intel_guc_action {
INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
INTEL_GUC_ACTION_REGISTER_CONTEXT = 0x4502,
INTEL_GUC_ACTION_DEREGISTER_CONTEXT = 0x4503,
- INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505,
- INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506,
INTEL_GUC_ACTION_DEREGISTER_CONTEXT_DONE = 0x4600,
INTEL_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC = 0x4601,
INTEL_GUC_ACTION_CLIENT_SOFT_RESET = 0x5507,
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH v3 7/8] drm/i915/guc: Drop obsolete H2G definitions
@ 2022-03-02 0:33 ` John.C.Harrison
0 siblings, 0 replies; 22+ messages in thread
From: John.C.Harrison @ 2022-03-02 0:33 UTC (permalink / raw)
To: Intel-GFX; +Cc: DRI-Devel
From: John Harrison <John.C.Harrison@Intel.com>
The CTB registration process changed significantly a while back using
a single KLV based H2G. So drop the original and now obsolete H2G
definitions.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
index 7afdadc7656f..e77f955435ce 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
@@ -131,8 +131,6 @@ enum intel_guc_action {
INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
INTEL_GUC_ACTION_REGISTER_CONTEXT = 0x4502,
INTEL_GUC_ACTION_DEREGISTER_CONTEXT = 0x4503,
- INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505,
- INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506,
INTEL_GUC_ACTION_DEREGISTER_CONTEXT_DONE = 0x4600,
INTEL_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC = 0x4601,
INTEL_GUC_ACTION_CLIENT_SOFT_RESET = 0x5507,
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v3 8/8] drm/i915/guc: Fix potential invalid pointer dereferences when decoding G2Hs
2022-03-02 0:33 ` [Intel-gfx] " John.C.Harrison
@ 2022-03-02 0:33 ` John.C.Harrison
-1 siblings, 0 replies; 22+ messages in thread
From: John.C.Harrison @ 2022-03-02 0:33 UTC (permalink / raw)
To: Intel-GFX; +Cc: Daniele Ceraolo Spurio, John Harrison, DRI-Devel
From: John Harrison <John.C.Harrison@Intel.com>
Some G2H handlers were reading the context id field from the payload
before checking the payload met the minimum length required.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 5dbebf15fae1..a85e10af0d24 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -3892,12 +3892,13 @@ int intel_guc_deregister_done_process_msg(struct intel_guc *guc,
u32 len)
{
struct intel_context *ce;
- u32 ctx_id = msg[0];
+ u32 ctx_id;
if (unlikely(len < 1)) {
drm_err(&guc_to_gt(guc)->i915->drm, "Invalid length %u\n", len);
return -EPROTO;
}
+ ctx_id = msg[0];
ce = g2h_context_lookup(guc, ctx_id);
if (unlikely(!ce))
@@ -3943,12 +3944,13 @@ int intel_guc_sched_done_process_msg(struct intel_guc *guc,
{
struct intel_context *ce;
unsigned long flags;
- u32 ctx_id = msg[0];
+ u32 ctx_id;
if (unlikely(len < 2)) {
drm_err(&guc_to_gt(guc)->i915->drm, "Invalid length %u\n", len);
return -EPROTO;
}
+ ctx_id = msg[0];
ce = g2h_context_lookup(guc, ctx_id);
if (unlikely(!ce))
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH v3 8/8] drm/i915/guc: Fix potential invalid pointer dereferences when decoding G2Hs
@ 2022-03-02 0:33 ` John.C.Harrison
0 siblings, 0 replies; 22+ messages in thread
From: John.C.Harrison @ 2022-03-02 0:33 UTC (permalink / raw)
To: Intel-GFX; +Cc: DRI-Devel
From: John Harrison <John.C.Harrison@Intel.com>
Some G2H handlers were reading the context id field from the payload
before checking the payload met the minimum length required.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 5dbebf15fae1..a85e10af0d24 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -3892,12 +3892,13 @@ int intel_guc_deregister_done_process_msg(struct intel_guc *guc,
u32 len)
{
struct intel_context *ce;
- u32 ctx_id = msg[0];
+ u32 ctx_id;
if (unlikely(len < 1)) {
drm_err(&guc_to_gt(guc)->i915->drm, "Invalid length %u\n", len);
return -EPROTO;
}
+ ctx_id = msg[0];
ce = g2h_context_lookup(guc, ctx_id);
if (unlikely(!ce))
@@ -3943,12 +3944,13 @@ int intel_guc_sched_done_process_msg(struct intel_guc *guc,
{
struct intel_context *ce;
unsigned long flags;
- u32 ctx_id = msg[0];
+ u32 ctx_id;
if (unlikely(len < 2)) {
drm_err(&guc_to_gt(guc)->i915->drm, "Invalid length %u\n", len);
return -EPROTO;
}
+ ctx_id = msg[0];
ce = g2h_context_lookup(guc, ctx_id);
if (unlikely(!ce))
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Prep work for next GuC release (rev4)
2022-03-02 0:33 ` [Intel-gfx] " John.C.Harrison
` (8 preceding siblings ...)
(?)
@ 2022-03-02 2:57 ` Patchwork
-1 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2022-03-02 2:57 UTC (permalink / raw)
To: john.c.harrison; +Cc: intel-gfx
== Series Details ==
Series: Prep work for next GuC release (rev4)
URL : https://patchwork.freedesktop.org/series/99805/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 22+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Prep work for next GuC release (rev4)
2022-03-02 0:33 ` [Intel-gfx] " John.C.Harrison
` (9 preceding siblings ...)
(?)
@ 2022-03-02 3:27 ` Patchwork
-1 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2022-03-02 3:27 UTC (permalink / raw)
To: john.c.harrison; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5318 bytes --]
== Series Details ==
Series: Prep work for next GuC release (rev4)
URL : https://patchwork.freedesktop.org/series/99805/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11308 -> Patchwork_22457
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/index.html
Participating hosts (49 -> 43)
------------------------------
Additional (1): fi-pnv-d510
Missing (7): fi-kbl-soraka shard-tglu fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 bat-jsl-2 fi-bdw-samus
Known issues
------------
Here are the changes found in Patchwork_22457 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s3@smem:
- fi-skl-6600u: [PASS][1] -> [INCOMPLETE][2] ([i915#4547])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/fi-skl-6600u/igt@gem_exec_suspend@basic-s3@smem.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/fi-skl-6600u/igt@gem_exec_suspend@basic-s3@smem.html
* igt@gem_huc_copy@huc-copy:
- fi-pnv-d510: NOTRUN -> [SKIP][3] ([fdo#109271]) +57 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/fi-pnv-d510/igt@gem_huc_copy@huc-copy.html
* igt@i915_selftest@live@hangcheck:
- fi-bdw-5557u: NOTRUN -> [INCOMPLETE][4] ([i915#3921])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/fi-bdw-5557u/igt@i915_selftest@live@hangcheck.html
* igt@kms_chamelium@vga-edid-read:
- fi-bdw-5557u: NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/fi-bdw-5557u/igt@kms_chamelium@vga-edid-read.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cfl-8109u: [PASS][6] -> [DMESG-FAIL][7] ([i915#295])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_pipe_crc_basic@read-crc-pipe-b:
- fi-cfl-8109u: [PASS][8] -> [DMESG-WARN][9] ([i915#295]) +10 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/fi-cfl-8109u/igt@kms_pipe_crc_basic@read-crc-pipe-b.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/fi-cfl-8109u/igt@kms_pipe_crc_basic@read-crc-pipe-b.html
* igt@kms_psr@cursor_plane_move:
- fi-bdw-5557u: NOTRUN -> [SKIP][10] ([fdo#109271]) +13 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/fi-bdw-5557u/igt@kms_psr@cursor_plane_move.html
#### Possible fixes ####
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [DMESG-FAIL][11] ([i915#4494] / [i915#4957]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
* igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- {bat-adlp-6}: [DMESG-WARN][13] ([i915#3576]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/bat-adlp-6/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/bat-adlp-6/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#5127]: https://gitlab.freedesktop.org/drm/intel/issues/5127
Build changes
-------------
* Linux: CI_DRM_11308 -> Patchwork_22457
CI-20190529: 20190529
CI_DRM_11308: e1345b708d76052ef668aaba362ef8ad81ed0b9b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6361: 2372a4beb6a33c5f0799a4a8ccbb93794f52dbca @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22457: da44f4dc3562c87a74941ed7fdeb939d5253a5a1 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
da44f4dc3562 drm/i915/guc: Fix potential invalid pointer dereferences when decoding G2Hs
bc4439187e03 drm/i915/guc: Drop obsolete H2G definitions
22af86b65853 drm/i915/guc: Rename desc_idx to ctx_id
fbffe6d6aac9 drm/i915/guc: Move lrc desc setup to where it is needed
ca92cf9c01b7 drm/i915/guc: Split guc_lrc_desc_pin apart
42f04658236c drm/i915/guc: Better name for context id limit
4b948ca2ff07 drm/i915/guc: Add an explicit 'submission_initialized' flag
88ec280a1eee drm/i915/guc: Do not conflate lrc_desc with GuC id for registration
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/index.html
[-- Attachment #2: Type: text/html, Size: 6328 bytes --]
^ permalink raw reply [flat|nested] 22+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for Prep work for next GuC release (rev4)
2022-03-02 0:33 ` [Intel-gfx] " John.C.Harrison
` (10 preceding siblings ...)
(?)
@ 2022-03-02 9:27 ` Patchwork
2022-03-03 23:00 ` John Harrison
-1 siblings, 1 reply; 22+ messages in thread
From: Patchwork @ 2022-03-02 9:27 UTC (permalink / raw)
To: john.c.harrison; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30260 bytes --]
== Series Details ==
Series: Prep work for next GuC release (rev4)
URL : https://patchwork.freedesktop.org/series/99805/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11308_full -> Patchwork_22457_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_22457_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22457_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (13 -> 13)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22457_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-b-edp-1-scaler-with-clipping-clamping:
- shard-iclb: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-iclb1/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-b-edp-1-scaler-with-clipping-clamping.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb2/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-b-edp-1-scaler-with-clipping-clamping.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-25@pipe-a-edp-1-downscale-with-pixel-format}:
- shard-iclb: NOTRUN -> [SKIP][3] +2 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb3/igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-25@pipe-a-edp-1-downscale-with-pixel-format.html
* {igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25}:
- {shard-rkl}: NOTRUN -> [SKIP][4] +6 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-rkl-5/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25.html
* {igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale}:
- shard-iclb: [PASS][5] -> [SKIP][6] +5 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-iclb6/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb2/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale.html
New tests
---------
New tests have been introduced between CI_DRM_11308_full and Patchwork_22457_full:
### New IGT tests (1) ###
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-d-edp-1-planes-upscale-downscale:
- Statuses : 1 pass(s)
- Exec time: [1.28] s
Known issues
------------
Here are the changes found in Patchwork_22457_full that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- shard-glk: ([PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31]) -> ([PASS][32], [FAIL][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53], [PASS][54], [PASS][55], [PASS][56]) ([i915#4392])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk9/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk9/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk9/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk8/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk8/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk8/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk7/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk7/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk7/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk6/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk6/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk5/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk5/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk5/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk4/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk4/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk4/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk3/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk3/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk2/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk2/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk2/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk1/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk1/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk1/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk9/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk9/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk9/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk8/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk8/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk7/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk7/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk7/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk6/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk6/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk6/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk5/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk5/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk4/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk4/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk4/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk3/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk3/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk3/boot.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk2/boot.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk2/boot.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk2/boot.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk1/boot.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk1/boot.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk1/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-apl: [PASS][57] -> [DMESG-WARN][58] ([i915#180])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-apl3/igt@gem_ctx_isolation@preservation-s3@bcs0.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-apl6/igt@gem_ctx_isolation@preservation-s3@bcs0.html
* igt@gem_ctx_param@set-priority-not-supported:
- shard-iclb: NOTRUN -> [SKIP][59] ([fdo#109314])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb3/igt@gem_ctx_param@set-priority-not-supported.html
* igt@gem_exec_balancer@parallel-bb-first:
- shard-tglb: NOTRUN -> [DMESG-WARN][60] ([i915#5076])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-tglb8/igt@gem_exec_balancer@parallel-bb-first.html
* igt@gem_exec_balancer@parallel-out-fence:
- shard-kbl: NOTRUN -> [DMESG-WARN][61] ([i915#5076])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-kbl1/igt@gem_exec_balancer@parallel-out-fence.html
* igt@gem_exec_fair@basic-deadline:
- shard-skl: NOTRUN -> [FAIL][62] ([i915#2846])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-skl4/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][63] -> [FAIL][64] ([i915#2842])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-iclb4/igt@gem_exec_fair@basic-none-share@rcs0.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb1/igt@gem_exec_fair@basic-none-share@rcs0.html
- shard-glk: [PASS][65] -> [FAIL][66] ([i915#2842])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk5/igt@gem_exec_fair@basic-none-share@rcs0.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk2/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-kbl: [PASS][67] -> [FAIL][68] ([i915#2842])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-kbl6/igt@gem_exec_fair@basic-none-vip@rcs0.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-kbl1/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-iclb: NOTRUN -> [FAIL][69] ([i915#2842]) +3 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb3/igt@gem_exec_fair@basic-none@vecs0.html
- shard-apl: [PASS][70] -> [FAIL][71] ([i915#2842])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-apl7/igt@gem_exec_fair@basic-none@vecs0.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-apl2/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-apl: NOTRUN -> [FAIL][72] ([i915#2842])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-apl7/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl: NOTRUN -> [FAIL][73] ([i915#2842]) +1 similar issue
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_lmem_swapping@basic:
- shard-iclb: NOTRUN -> [SKIP][74] ([i915#4613]) +1 similar issue
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb3/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@parallel-random-verify:
- shard-glk: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#4613])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk9/igt@gem_lmem_swapping@parallel-random-verify.html
* igt@gem_lmem_swapping@random:
- shard-skl: NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#4613]) +1 similar issue
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-skl4/igt@gem_lmem_swapping@random.html
* igt@gem_pxp@create-regular-context-2:
- shard-tglb: NOTRUN -> [SKIP][77] ([i915#4270])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-tglb8/igt@gem_pxp@create-regular-context-2.html
* igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs:
- shard-iclb: NOTRUN -> [SKIP][78] ([i915#768])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb7/igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-skl: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#3323])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-skl4/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-iclb: NOTRUN -> [SKIP][80] ([i915#3297])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb3/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-kbl: [PASS][81] -> [DMESG-WARN][82] ([i915#180]) +2 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-kbl4/igt@gem_workarounds@suspend-resume-fd.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-kbl6/igt@gem_workarounds@suspend-resume-fd.html
* igt@gen3_render_tiledy_blits:
- shard-iclb: NOTRUN -> [SKIP][83] ([fdo#109289])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb7/igt@gen3_render_tiledy_blits.html
* igt@gen9_exec_parse@shadow-peek:
- shard-tglb: NOTRUN -> [SKIP][84] ([i915#2527] / [i915#2856]) +1 similar issue
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-tglb5/igt@gen9_exec_parse@shadow-peek.html
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [PASS][85] -> [FAIL][86] ([i915#454])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-iclb4/igt@i915_pm_dc@dc6-dpms.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_dc@dc6-psr:
- shard-skl: NOTRUN -> [FAIL][87] ([i915#454])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-skl9/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
- shard-apl: NOTRUN -> [SKIP][88] ([fdo#109271] / [i915#1937])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-apl7/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html
* igt@i915_pm_rpm@gem-execbuf-stress-pc8:
- shard-iclb: NOTRUN -> [SKIP][89] ([fdo#109293] / [fdo#109506])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb3/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html
* igt@i915_pm_sseu@full-enable:
- shard-iclb: NOTRUN -> [SKIP][90] ([i915#4387])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb7/igt@i915_pm_sseu@full-enable.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [PASS][91] -> [INCOMPLETE][92] ([i915#3921])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-snb7/igt@i915_selftest@live@hangcheck.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-snb6/igt@i915_selftest@live@hangcheck.html
* igt@kms_async_flips@crc:
- shard-skl: NOTRUN -> [FAIL][93] ([i915#4272])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-skl4/igt@kms_async_flips@crc.html
* igt@kms_atomic@plane-primary-overlay-mutable-zpos:
- shard-tglb: NOTRUN -> [SKIP][94] ([i915#404])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-tglb8/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
- shard-apl: NOTRUN -> [SKIP][95] ([fdo#109271] / [i915#3777]) +3 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-apl6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_fb@y-tiled-16bpp-rotate-0:
- shard-glk: [PASS][96] -> [DMESG-WARN][97] ([i915#118])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk6/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk5/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-kbl: NOTRUN -> [SKIP][98] ([fdo#109271] / [i915#3777])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-kbl7/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-0:
- shard-tglb: NOTRUN -> [SKIP][99] ([fdo#111615])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-tglb8/igt@kms_big_fb@yf-tiled-64bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180:
- shard-iclb: NOTRUN -> [SKIP][100] ([fdo#110723]) +1 similar issue
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb3/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180.html
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][101] ([fdo#109271] / [i915#3886])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-kbl1/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][102] ([i915#3689])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-tglb8/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_ccs.html
* igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][103] ([fdo#109271] / [i915#3886])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-skl4/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-crc-primary-rotation-180-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][104] ([fdo#111615] / [i915#3689]) +1 similar issue
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-tglb8/igt@kms_ccs@pipe-b-crc-primary-rotation-180-yf_tiled_ccs.html
* igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc:
- shard-iclb: NOTRUN -> [SKIP][105] ([fdo#109278] / [i915#3886]) +1 similar issue
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb7/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][106] ([fdo#109271] / [i915#3886]) +7 similar issues
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-apl7/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@dp-crc-multiple:
- shard-apl: NOTRUN -> [SKIP][107] ([fdo#109271] / [fdo#111827]) +8 similar issues
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-apl7/igt@kms_chamelium@dp-crc-multiple.html
* igt@kms_chamelium@dp-hpd-for-each-pipe:
- shard-kbl: NOTRUN -> [SKIP][108] ([fdo#109271] / [fdo#111827]) +4 similar issues
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-kbl7/igt@kms_chamelium@dp-hpd-for-each-pipe.html
* igt@kms_chamelium@vga-hpd-with-enabled-mode:
- shard-skl: NOTRUN -> [SKIP][109] ([fdo#109271] / [fdo#111827]) +6 similar issues
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-skl4/igt@kms_chamelium@vga-hpd-with-enabled-mode.html
* igt@kms_color_chamelium@pipe-b-ctm-red-to-blue:
- shard-glk: NOTRUN -> [SKIP][110] ([fdo#109271] / [fdo#111827])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk9/igt@kms_color_chamelium@pipe-b-ctm-red-to-blue.html
* igt@kms_color_chamelium@pipe-b-gamma:
- shard-iclb: NOTRUN -> [SKIP][111] ([fdo#109284] / [fdo#111827]) +4 similar issues
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb3/igt@kms_color_chamelium@pipe-b-gamma.html
* igt@kms_content_protection@lic:
- shard-apl: NOTRUN -> [TIMEOUT][112] ([i915#1319]) +1 similar issue
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-apl3/igt@kms_content_protection@lic.html
* igt@kms_content_protection@type1:
- shard-iclb: NOTRUN -> [SKIP][113] ([fdo#109300] / [fdo#111066])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb7/igt@kms_content_protection@type1.html
* igt@kms_cursor_crc@pipe-a-cursor-512x170-offscreen:
- shard-tglb: NOTRUN -> [SKIP][114] ([fdo#109279] / [i915#3359]) +1 similar issue
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-tglb8/igt@kms_cursor_crc@pipe-a-cursor-512x170-offscreen.html
* igt@kms_cursor_crc@pipe-a-cursor-max-size-onscreen:
- shard-kbl: NOTRUN -> [SKIP][115] ([fdo#109271]) +33 similar issues
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-max-size-onscreen.html
* igt@kms_cursor_crc@pipe-a-cursor-max-size-sliding:
- shard-iclb: NOTRUN -> [SKIP][116] ([fdo#109278]) +19 similar issues
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb7/igt@kms_cursor_crc@pipe-a-cursor-max-size-sliding.html
* igt@kms_cursor_legacy@cursora-vs-flipb-atomic:
- shard-tglb: NOTRUN -> [SKIP][117] ([fdo#109274] / [fdo#111825]) +2 similar issues
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-tglb8/igt@kms_cursor_legacy@cursora-vs-flipb-atomic.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
- shard-iclb: NOTRUN -> [SKIP][118] ([fdo#109274] / [fdo#109278]) +2 similar issues
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb3/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: [PASS][119] -> [FAIL][120] ([i915#2346] / [i915#533])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@pipe-d-torture-move:
- shard-skl: NOTRUN -> [SKIP][121] ([fdo#109271]) +67 similar issues
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-skl4/igt@kms_cursor_legacy@pipe-d-torture-move.html
* igt@kms_flip@2x-flip-vs-panning-vs-hang:
- shard-iclb: NOTRUN -> [SKIP][122] ([fdo#109274]) +3 similar issues
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb3/igt@kms_flip@2x-flip-vs-panning-vs-hang.html
* igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1:
- shard-glk: [PASS][123] -> [FAIL][124] ([i915#79])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk7/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk3/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1.html
* igt@kms_flip@flip-vs-expired-vblank@b-edp1:
- shard-skl: [PASS][125] -> [FAIL][126] ([i915#79])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-skl4/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-skl3/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@b-dp1:
- shard-kbl: [PASS][127] -> [INCOMPLETE][128] ([i915#3614])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
- shard-skl: NOTRUN -> [INCOMPLETE][129] ([i915#3701])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-skl4/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-blt:
- shard-tglb: NOTRUN -> [SKIP][130] ([fdo#109280] / [fdo#111825]) +3 similar issues
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt:
- shard-iclb: NOTRUN -> [SKIP][131] ([fdo#109280]) +14 similar issues
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [PASS][132] -> [FAIL][133] ([i915#1188]) +1 similar issue
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-skl9/igt@kms_hdr@bpc-switch-dpms.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-skl9/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- shard-apl: NOTRUN -> [SKIP][134] ([fdo#109271] / [i915#533]) +1 similar issue
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-apl4/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-apl: NOTRUN -> [FAIL][135] ([fdo#108145] / [i915#265])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-apl3/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
- shard-kbl: NOTRUN -> [FAIL][136] ([fdo#108145] / [i915#265]) +1 similar issue
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-kbl1/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-skl: NOTRUN -> [FAIL][137] ([fdo#108145] / [i915#265]) +1 similar issue
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][138] ([i915#265])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-apl6/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][139] -> [FAIL][140] ([fdo#108145] / [i915#265])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: NOTRUN -> [SKIP][141] ([i915#3536])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb7/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_plane_lowres@pipe-b-tiling-yf:
- shard-tglb: NOTRUN -> [SKIP][142] ([fdo#111615] / [fdo#112054])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-tglb8/igt@kms_plane_lowres@pipe-b-tiling-yf.html
* igt@kms_plane_lowres@pipe-c-tiling-none:
- shard-tglb: NOTRUN -> [SKIP][143] ([i915#3536]) +1 similar issue
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-tglb8/igt@kms_plane_lowres@pipe-c-tiling-none.html
* igt@kms_psr2_sf@cursor-plane-update-sf:
- shard-skl: NOTRUN -> [SKIP][144] ([fdo#109271] / [i915#658])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-skl4/igt@kms_psr2_sf@cursor-plane-update-sf.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-apl: NOTRUN -> [SKIP][145] ([fdo#109271] / [i915#658])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-apl4/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
* igt@kms_psr@psr2_cursor_mmap_gtt:
- shard-iclb: [PASS][146] -> [SKIP][147] ([fdo#109441])
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_gtt.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb6/igt@kms_psr@psr2_cursor_mmap_gtt.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: NOTRUN -> [SKIP][148] ([fdo#109441]) +2 similar issues
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb7/igt@kms_psr@psr2_no_drrs.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-tglb: NOTRUN -> [FAIL][149] ([i915#132] / [i915#3467])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-tglb8/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_tv_load_detect@load-detect:
- shard-iclb: NOTRUN -> [SKIP][150] ([fdo#109309])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb7/igt@kms_tv_load_detect@load-detect.html
* igt@kms_vblank@pipe-d-ts-continuation-idle:
- shard-apl: NOTRUN -> [SKIP][151] ([fdo#109271]) +104 similar issues
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-apl7/igt@kms_vblank@pipe-d-ts-continuation-idle.html
* igt@kms_vrr@flip-suspend:
- shard-iclb: NOTRUN -> [SKIP][152] ([fdo#109502])
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb7/igt@kms_vrr@flip-suspend.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-apl: NOTRUN -> [SKIP][153] ([fdo#1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/index.html
[-- Attachment #2: Type: text/html, Size: 33735 bytes --]
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Prep work for next GuC release (rev4)
2022-03-02 9:27 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2022-03-03 23:00 ` John Harrison
0 siblings, 0 replies; 22+ messages in thread
From: John Harrison @ 2022-03-03 23:00 UTC (permalink / raw)
To: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 31800 bytes --]
On 3/2/2022 01:27, Patchwork wrote:
> Project List - Patchwork *Patch Details*
> *Series:* Prep work for next GuC release (rev4)
> *URL:* https://patchwork.freedesktop.org/series/99805/
> *State:* failure
> *Details:*
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/index.html
>
>
> CI Bug Log - changes from CI_DRM_11308_full -> Patchwork_22457_full
>
>
> Summary
>
> *FAILURE*
>
> Serious unknown changes coming with Patchwork_22457_full absolutely
> need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_22457_full, please notify your bug team to
> allow them
> to document this new failure mode, which will reduce false positives
> in CI.
>
>
> Participating hosts (13 -> 13)
>
> No changes in participating hosts
>
>
> Possible new issues
>
> Here are the unknown changes that may have been introduced in
> Patchwork_22457_full:
>
>
> IGT changes
>
>
> Possible regressions
>
> * igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-b-edp-1-scaler-with-clipping-clamping:
>
> o shard-iclb: PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-iclb1/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-b-edp-1-scaler-with-clipping-clamping.html>
> -> INCOMPLETE
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb2/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-b-edp-1-scaler-with-clipping-clamping.html>
>
Unrelated display test on an execlist only platform.
John.
> *
>
>
> Suppressed
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> *
>
> {igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-25@pipe-a-edp-1-downscale-with-pixel-format}:
>
> o shard-iclb: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb3/igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-25@pipe-a-edp-1-downscale-with-pixel-format.html>
> +2 similar issues
> *
>
> {igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25}:
>
> o {shard-rkl}: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-rkl-5/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25.html>
> +6 similar issues
> *
>
> {igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale}:
>
> o shard-iclb: PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-iclb6/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale.html>
> -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb2/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale.html>
> +5 similar issues
>
>
> New tests
>
> New tests have been introduced between CI_DRM_11308_full and
> Patchwork_22457_full:
>
>
> New IGT tests (1)
>
> * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-d-edp-1-planes-upscale-downscale:
>
> o Statuses : 1 pass(s)
> o Exec time: [1.28] s
>
>
> Known issues
>
> Here are the changes found in Patchwork_22457_full that come from
> known issues:
>
>
> CI changes
>
>
> Issues hit
>
> * boot:
> o shard-glk: (PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk9/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk9/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk9/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk8/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk8/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk8/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk7/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk7/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk7/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk6/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk6/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk5/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk5/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk5/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk4/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk4/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk4/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk3/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk3/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk2/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk2/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk2/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk1/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk1/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk1/boot.html>)
> -> (PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk9/boot.html>,
> FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk9/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk9/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk8/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk8/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk7/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk7/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk7/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk6/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk6/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk6/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk5/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk5/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk4/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk4/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk4/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk3/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk3/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk3/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk2/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk2/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk2/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk1/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk1/boot.html>,
> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk1/boot.html>)
> ([i915#4392])
>
>
> IGT changes
>
>
> Issues hit
>
> *
>
> igt@gem_ctx_isolation@preservation-s3@bcs0:
>
> o shard-apl: PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-apl3/igt@gem_ctx_isolation@preservation-s3@bcs0.html>
> -> DMESG-WARN
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-apl6/igt@gem_ctx_isolation@preservation-s3@bcs0.html>
> ([i915#180])
> *
>
> igt@gem_ctx_param@set-priority-not-supported:
>
> o shard-iclb: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb3/igt@gem_ctx_param@set-priority-not-supported.html>
> ([fdo#109314])
> *
>
> igt@gem_exec_balancer@parallel-bb-first:
>
> o shard-tglb: NOTRUN -> DMESG-WARN
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-tglb8/igt@gem_exec_balancer@parallel-bb-first.html>
> ([i915#5076])
> *
>
> igt@gem_exec_balancer@parallel-out-fence:
>
> o shard-kbl: NOTRUN -> DMESG-WARN
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-kbl1/igt@gem_exec_balancer@parallel-out-fence.html>
> ([i915#5076])
> *
>
> igt@gem_exec_fair@basic-deadline:
>
> o shard-skl: NOTRUN -> FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-skl4/igt@gem_exec_fair@basic-deadline.html>
> ([i915#2846])
> *
>
> igt@gem_exec_fair@basic-none-share@rcs0:
>
> o
>
> shard-iclb: PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-iclb4/igt@gem_exec_fair@basic-none-share@rcs0.html>
> -> FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb1/igt@gem_exec_fair@basic-none-share@rcs0.html>
> ([i915#2842])
>
> o
>
> shard-glk: PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk5/igt@gem_exec_fair@basic-none-share@rcs0.html>
> -> FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk2/igt@gem_exec_fair@basic-none-share@rcs0.html>
> ([i915#2842])
>
> *
>
> igt@gem_exec_fair@basic-none-vip@rcs0:
>
> o shard-kbl: PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-kbl6/igt@gem_exec_fair@basic-none-vip@rcs0.html>
> -> FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-kbl1/igt@gem_exec_fair@basic-none-vip@rcs0.html>
> ([i915#2842])
> *
>
> igt@gem_exec_fair@basic-none@vecs0:
>
> o
>
> shard-iclb: NOTRUN -> FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb3/igt@gem_exec_fair@basic-none@vecs0.html>
> ([i915#2842]) +3 similar issues
>
> o
>
> shard-apl: PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-apl7/igt@gem_exec_fair@basic-none@vecs0.html>
> -> FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-apl2/igt@gem_exec_fair@basic-none@vecs0.html>
> ([i915#2842])
>
> *
>
> igt@gem_exec_fair@basic-pace-share@rcs0:
>
> o shard-apl: NOTRUN -> FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-apl7/igt@gem_exec_fair@basic-pace-share@rcs0.html>
> ([i915#2842])
> *
>
> igt@gem_exec_fair@basic-pace@vcs1:
>
> o shard-kbl: NOTRUN -> FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs1.html>
> ([i915#2842]) +1 similar issue
> *
>
> igt@gem_lmem_swapping@basic:
>
> o shard-iclb: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb3/igt@gem_lmem_swapping@basic.html>
> ([i915#4613]) +1 similar issue
> *
>
> igt@gem_lmem_swapping@parallel-random-verify:
>
> o shard-glk: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk9/igt@gem_lmem_swapping@parallel-random-verify.html>
> ([fdo#109271] / [i915#4613])
> *
>
> igt@gem_lmem_swapping@random:
>
> o shard-skl: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-skl4/igt@gem_lmem_swapping@random.html>
> ([fdo#109271] / [i915#4613]) +1 similar issue
> *
>
> igt@gem_pxp@create-regular-context-2:
>
> o shard-tglb: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-tglb8/igt@gem_pxp@create-regular-context-2.html>
> ([i915#4270])
> *
>
> igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs:
>
> o shard-iclb: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb7/igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs.html>
> ([i915#768])
> *
>
> igt@gem_userptr_blits@dmabuf-sync:
>
> o shard-skl: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-skl4/igt@gem_userptr_blits@dmabuf-sync.html>
> ([fdo#109271] / [i915#3323])
> *
>
> igt@gem_userptr_blits@unsync-unmap-cycles:
>
> o shard-iclb: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb3/igt@gem_userptr_blits@unsync-unmap-cycles.html>
> ([i915#3297])
> *
>
> igt@gem_workarounds@suspend-resume-fd:
>
> o shard-kbl: PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-kbl4/igt@gem_workarounds@suspend-resume-fd.html>
> -> DMESG-WARN
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-kbl6/igt@gem_workarounds@suspend-resume-fd.html>
> ([i915#180]) +2 similar issues
> *
>
> igt@gen3_render_tiledy_blits:
>
> o shard-iclb: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb7/igt@gen3_render_tiledy_blits.html>
> ([fdo#109289])
> *
>
> igt@gen9_exec_parse@shadow-peek:
>
> o shard-tglb: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-tglb5/igt@gen9_exec_parse@shadow-peek.html>
> ([i915#2527] / [i915#2856]) +1 similar issue
> *
>
> igt@i915_pm_dc@dc6-dpms:
>
> o shard-iclb: PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-iclb4/igt@i915_pm_dc@dc6-dpms.html>
> -> FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html>
> ([i915#454])
> *
>
> igt@i915_pm_dc@dc6-psr:
>
> o shard-skl: NOTRUN -> FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-skl9/igt@i915_pm_dc@dc6-psr.html>
> ([i915#454])
> *
>
> igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
>
> o shard-apl: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-apl7/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html>
> ([fdo#109271] / [i915#1937])
> *
>
> igt@i915_pm_rpm@gem-execbuf-stress-pc8:
>
> o shard-iclb: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb3/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html>
> ([fdo#109293] / [fdo#109506])
> *
>
> igt@i915_pm_sseu@full-enable:
>
> o shard-iclb: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb7/igt@i915_pm_sseu@full-enable.html>
> ([i915#4387])
> *
>
> igt@i915_selftest@live@hangcheck:
>
> o shard-snb: PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-snb7/igt@i915_selftest@live@hangcheck.html>
> -> INCOMPLETE
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-snb6/igt@i915_selftest@live@hangcheck.html>
> ([i915#3921])
> *
>
> igt@kms_async_flips@crc:
>
> o shard-skl: NOTRUN -> FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-skl4/igt@kms_async_flips@crc.html>
> ([i915#4272])
> *
>
> igt@kms_atomic@plane-primary-overlay-mutable-zpos:
>
> o shard-tglb: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-tglb8/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html>
> ([i915#404])
> *
>
> igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
>
> o shard-apl: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-apl6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html>
> ([fdo#109271] / [i915#3777]) +3 similar issues
> *
>
> igt@kms_big_fb@y-tiled-16bpp-rotate-0:
>
> o shard-glk: PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk6/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html>
> -> DMESG-WARN
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk5/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html>
> ([i915#118])
> *
>
> igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
>
> o shard-kbl: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-kbl7/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html>
> ([fdo#109271] / [i915#3777])
> *
>
> igt@kms_big_fb@yf-tiled-64bpp-rotate-0:
>
> o shard-tglb: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-tglb8/igt@kms_big_fb@yf-tiled-64bpp-rotate-0.html>
> ([fdo#111615])
> *
>
> igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180:
>
> o shard-iclb: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb3/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180.html>
> ([fdo#110723]) +1 similar issue
> *
>
> igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
>
> o shard-kbl: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-kbl1/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html>
> ([fdo#109271] / [i915#3886])
> *
>
> igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_ccs:
>
> o shard-tglb: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-tglb8/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_ccs.html>
> ([i915#3689])
> *
>
> igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
>
> o shard-skl: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-skl4/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html>
> ([fdo#109271] / [i915#3886])
> *
>
> igt@kms_ccs@pipe-b-crc-primary-rotation-180-yf_tiled_ccs:
>
> o shard-tglb: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-tglb8/igt@kms_ccs@pipe-b-crc-primary-rotation-180-yf_tiled_ccs.html>
> ([fdo#111615] / [i915#3689]) +1 similar issue
> *
>
> igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc:
>
> o shard-iclb: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb7/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc.html>
> ([fdo#109278] / [i915#3886]) +1 similar issue
> *
>
> igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
>
> o shard-apl: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-apl7/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html>
> ([fdo#109271] / [i915#3886]) +7 similar issues
> *
>
> igt@kms_chamelium@dp-crc-multiple:
>
> o shard-apl: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-apl7/igt@kms_chamelium@dp-crc-multiple.html>
> ([fdo#109271] / [fdo#111827]) +8 similar issues
> *
>
> igt@kms_chamelium@dp-hpd-for-each-pipe:
>
> o shard-kbl: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-kbl7/igt@kms_chamelium@dp-hpd-for-each-pipe.html>
> ([fdo#109271] / [fdo#111827]) +4 similar issues
> *
>
> igt@kms_chamelium@vga-hpd-with-enabled-mode:
>
> o shard-skl: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-skl4/igt@kms_chamelium@vga-hpd-with-enabled-mode.html>
> ([fdo#109271] / [fdo#111827]) +6 similar issues
> *
>
> igt@kms_color_chamelium@pipe-b-ctm-red-to-blue:
>
> o shard-glk: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk9/igt@kms_color_chamelium@pipe-b-ctm-red-to-blue.html>
> ([fdo#109271] / [fdo#111827])
> *
>
> igt@kms_color_chamelium@pipe-b-gamma:
>
> o shard-iclb: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb3/igt@kms_color_chamelium@pipe-b-gamma.html>
> ([fdo#109284] / [fdo#111827]) +4 similar issues
> *
>
> igt@kms_content_protection@lic:
>
> o shard-apl: NOTRUN -> TIMEOUT
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-apl3/igt@kms_content_protection@lic.html>
> ([i915#1319]) +1 similar issue
> *
>
> igt@kms_content_protection@type1:
>
> o shard-iclb: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb7/igt@kms_content_protection@type1.html>
> ([fdo#109300] / [fdo#111066])
> *
>
> igt@kms_cursor_crc@pipe-a-cursor-512x170-offscreen:
>
> o shard-tglb: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-tglb8/igt@kms_cursor_crc@pipe-a-cursor-512x170-offscreen.html>
> ([fdo#109279] / [i915#3359]) +1 similar issue
> *
>
> igt@kms_cursor_crc@pipe-a-cursor-max-size-onscreen:
>
> o shard-kbl: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-max-size-onscreen.html>
> ([fdo#109271]) +33 similar issues
> *
>
> igt@kms_cursor_crc@pipe-a-cursor-max-size-sliding:
>
> o shard-iclb: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb7/igt@kms_cursor_crc@pipe-a-cursor-max-size-sliding.html>
> ([fdo#109278]) +19 similar issues
> *
>
> igt@kms_cursor_legacy@cursora-vs-flipb-atomic:
>
> o shard-tglb: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-tglb8/igt@kms_cursor_legacy@cursora-vs-flipb-atomic.html>
> ([fdo#109274] / [fdo#111825]) +2 similar issues
> *
>
> igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
>
> o shard-iclb: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb3/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html>
> ([fdo#109274] / [fdo#109278]) +2 similar issues
> *
>
> igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
>
> o shard-skl: PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html>
> -> FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html>
> ([i915#2346] / [i915#533])
> *
>
> igt@kms_cursor_legacy@pipe-d-torture-move:
>
> o shard-skl: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-skl4/igt@kms_cursor_legacy@pipe-d-torture-move.html>
> ([fdo#109271]) +67 similar issues
> *
>
> igt@kms_flip@2x-flip-vs-panning-vs-hang:
>
> o shard-iclb: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb3/igt@kms_flip@2x-flip-vs-panning-vs-hang.html>
> ([fdo#109274]) +3 similar issues
> *
>
> igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1:
>
> o shard-glk: PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-glk7/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1.html>
> -> FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-glk3/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1.html>
> ([i915#79])
> *
>
> igt@kms_flip@flip-vs-expired-vblank@b-edp1:
>
> o shard-skl: PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-skl4/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html>
> -> FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-skl3/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html>
> ([i915#79])
> *
>
> igt@kms_flip@flip-vs-suspend-interruptible@b-dp1:
>
> o shard-kbl: PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html>
> -> INCOMPLETE
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html>
> ([i915#3614])
> *
>
> igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
>
> o shard-skl: NOTRUN -> INCOMPLETE
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-skl4/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html>
> ([i915#3701])
> *
>
> igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-blt:
>
> o shard-tglb: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-blt.html>
> ([fdo#109280] / [fdo#111825]) +3 similar issues
> *
>
> igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt:
>
> o shard-iclb: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt.html>
> ([fdo#109280]) +14 similar issues
> *
>
> igt@kms_hdr@bpc-switch-dpms:
>
> o shard-skl: PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-skl9/igt@kms_hdr@bpc-switch-dpms.html>
> -> FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-skl9/igt@kms_hdr@bpc-switch-dpms.html>
> ([i915#1188]) +1 similar issue
> *
>
> igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
>
> o shard-apl: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-apl4/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html>
> ([fdo#109271] / [i915#533]) +1 similar issue
> *
>
> igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
>
> o
>
> shard-apl: NOTRUN -> FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-apl3/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html>
> ([fdo#108145] / [i915#265])
>
> o
>
> shard-kbl: NOTRUN -> FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-kbl1/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html>
> ([fdo#108145] / [i915#265]) +1 similar issue
>
> *
>
> igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
>
> o shard-skl: NOTRUN -> FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html>
> ([fdo#108145] / [i915#265]) +1 similar issue
> *
>
> igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
>
> o shard-apl: NOTRUN -> FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-apl6/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html>
> ([i915#265])
> *
>
> igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
>
> o shard-skl: PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html>
> -> FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html>
> ([fdo#108145] / [i915#265])
> *
>
> igt@kms_plane_lowres@pipe-a-tiling-x:
>
> o shard-iclb: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb7/igt@kms_plane_lowres@pipe-a-tiling-x.html>
> ([i915#3536])
> *
>
> igt@kms_plane_lowres@pipe-b-tiling-yf:
>
> o shard-tglb: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-tglb8/igt@kms_plane_lowres@pipe-b-tiling-yf.html>
> ([fdo#111615] / [fdo#112054])
> *
>
> igt@kms_plane_lowres@pipe-c-tiling-none:
>
> o shard-tglb: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-tglb8/igt@kms_plane_lowres@pipe-c-tiling-none.html>
> ([i915#3536]) +1 similar issue
> *
>
> igt@kms_psr2_sf@cursor-plane-update-sf:
>
> o shard-skl: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-skl4/igt@kms_psr2_sf@cursor-plane-update-sf.html>
> ([fdo#109271] / [i915#658])
> *
>
> igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
>
> o shard-apl: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-apl4/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html>
> ([fdo#109271] / [i915#658])
> *
>
> igt@kms_psr@psr2_cursor_mmap_gtt:
>
> o shard-iclb: PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11308/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_gtt.html>
> -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb6/igt@kms_psr@psr2_cursor_mmap_gtt.html>
> ([fdo#109441])
> *
>
> igt@kms_psr@psr2_no_drrs:
>
> o shard-iclb: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb7/igt@kms_psr@psr2_no_drrs.html>
> ([fdo#109441]) +2 similar issues
> *
>
> igt@kms_psr@psr2_sprite_mmap_gtt:
>
> o shard-tglb: NOTRUN -> FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-tglb8/igt@kms_psr@psr2_sprite_mmap_gtt.html>
> ([i915#132] / [i915#3467])
> *
>
> igt@kms_tv_load_detect@load-detect:
>
> o shard-iclb: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb7/igt@kms_tv_load_detect@load-detect.html>
> ([fdo#109309])
> *
>
> igt@kms_vblank@pipe-d-ts-continuation-idle:
>
> o shard-apl: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-apl7/igt@kms_vblank@pipe-d-ts-continuation-idle.html>
> ([fdo#109271]) +104 similar issues
> *
>
> igt@kms_vrr@flip-suspend:
>
> o shard-iclb: NOTRUN -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/shard-iclb7/igt@kms_vrr@flip-suspend.html>
> ([fdo#109502])
> *
>
> igt@kms_writeback@writeback-invalid-parameters:
>
> o shard-apl: NOTRUN -> [SKIP][153] ([fdo#1
>
[-- Attachment #2: Type: text/html, Size: 43348 bytes --]
^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2022-03-03 23:00 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-03-02 0:33 [PATCH v3 0/8] Prep work for next GuC release John.C.Harrison
2022-03-02 0:33 ` [Intel-gfx] " John.C.Harrison
2022-03-02 0:33 ` [PATCH v3 1/8] drm/i915/guc: Do not conflate lrc_desc with GuC id for registration John.C.Harrison
2022-03-02 0:33 ` [Intel-gfx] " John.C.Harrison
2022-03-02 0:33 ` [PATCH v3 2/8] drm/i915/guc: Add an explicit 'submission_initialized' flag John.C.Harrison
2022-03-02 0:33 ` [Intel-gfx] " John.C.Harrison
2022-03-02 0:33 ` [PATCH v3 3/8] drm/i915/guc: Better name for context id limit John.C.Harrison
2022-03-02 0:33 ` [Intel-gfx] " John.C.Harrison
2022-03-02 0:33 ` [PATCH v3 4/8] drm/i915/guc: Split guc_lrc_desc_pin apart John.C.Harrison
2022-03-02 0:33 ` [Intel-gfx] " John.C.Harrison
2022-03-02 0:33 ` [PATCH v3 5/8] drm/i915/guc: Move lrc desc setup to where it is needed John.C.Harrison
2022-03-02 0:33 ` [Intel-gfx] " John.C.Harrison
2022-03-02 0:33 ` [PATCH v3 6/8] drm/i915/guc: Rename desc_idx to ctx_id John.C.Harrison
2022-03-02 0:33 ` [Intel-gfx] " John.C.Harrison
2022-03-02 0:33 ` [PATCH v3 7/8] drm/i915/guc: Drop obsolete H2G definitions John.C.Harrison
2022-03-02 0:33 ` [Intel-gfx] " John.C.Harrison
2022-03-02 0:33 ` [PATCH v3 8/8] drm/i915/guc: Fix potential invalid pointer dereferences when decoding G2Hs John.C.Harrison
2022-03-02 0:33 ` [Intel-gfx] " John.C.Harrison
2022-03-02 2:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Prep work for next GuC release (rev4) Patchwork
2022-03-02 3:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-03-02 9:27 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-03-03 23:00 ` John Harrison
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