* Re: [PATCH v2] arm64: dts: rockchip: Add sata nodes to rk356x
@ 2022-03-01 21:44 kernel test robot
0 siblings, 0 replies; 7+ messages in thread
From: kernel test robot @ 2022-03-01 21:44 UTC (permalink / raw)
To: kbuild
[-- Attachment #1: Type: text/plain, Size: 2173 bytes --]
CC: kbuild-all(a)lists.01.org
BCC: lkp(a)intel.com
In-Reply-To: <20220227082131.131883-1-linux@fw-web.de>
References: <20220227082131.131883-1-linux@fw-web.de>
TO: Frank Wunderlich <linux@fw-web.de>
Hi Frank,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on rockchip/for-next]
[also build test ERROR on v5.17-rc6 next-20220301]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Frank-Wunderlich/arm64-dts-rockchip-Add-sata-nodes-to-rk356x/20220227-162306
base: https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git for-next
:::::: branch date: 3 days ago
:::::: commit date: 3 days ago
config: arm64-randconfig-s031-20220301 (https://download.01.org/0day-ci/archive/20220302/202203020519.laJnMRjD-lkp(a)intel.com/config)
compiler: aarch64-linux-gcc (GCC) 11.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# apt-get install sparse
# sparse version: v0.6.4-dirty
# https://github.com/0day-ci/linux/commit/2e7fa3bd39c4a4103d0b14d6b4a5a737c79ba78a
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Frank-Wunderlich/arm64-dts-rockchip-Add-sata-nodes-to-rk356x/20220227-162306
git checkout 2e7fa3bd39c4a4103d0b14d6b4a5a737c79ba78a
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=build_dir ARCH=arm64 SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> ERROR: Input tree has errors, aborting (use -f to force output)
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2] arm64: dts: rockchip: Add sata nodes to rk356x
2022-02-27 8:21 ` Frank Wunderlich
(?)
@ 2022-02-27 9:32 ` Johan Jonker
-1 siblings, 0 replies; 7+ messages in thread
From: Johan Jonker @ 2022-02-27 9:32 UTC (permalink / raw)
To: Frank Wunderlich, linux-rockchip
Cc: Frank Wunderlich, Rob Herring, Krzysztof Kozlowski,
Heiko Stuebner, Peter Geis, Michael Riesch, devicetree,
linux-arm-kernel, linux-kernel
Hi Frank,
Combine your patch in a serie with the ahci-platform.yaml conversion and
include all current CC people and Rockchip list.
Your conversion and DT patch contains lots of errors.
Check your serie before you submit and fix.
ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- make dt_binding_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/ata/ahci-platform.yaml
ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- make dtbs_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/ata/ahci-platform.yaml
Add power-domains as a new property after the conversion patch.
Johan
===
make a serie:
conversion ahci-platform.yaml
power-domains patch
rockchip rk356x sata nodes patch
On 2/27/22 09:21, Frank Wunderlich wrote:
> From: Frank Wunderlich <frank-w@public-files.de>
>
> RK356x supports up to 3 sata controllers which were compatible with the
> existing snps,dwc-ahci binding.
>
> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
> ---
> changes in v2:
> - added sata0 + 1, but have only tested sata2
> ---
> arch/arm64/boot/dts/rockchip/rk356x.dtsi | 45 ++++++++++++++++++++++++
> 1 file changed, 45 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> index 7cdef800cb3c..2e2e73be7417 100644
> --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> @@ -230,6 +230,51 @@ scmi_shmem: sram@0 {
> };
> };
>
> + sata0: sata@fc000000 {
rk3566 has no combphy0
Move to rk3568.dtsi
> + compatible = "snps,dwc-ahci";
> + reg = <0 0xfc000000 0 0x1000>;
> + clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
> + <&cru CLK_SATA0_RXOOB>;
> + clock-names = "sata", "pmalive", "rxoob";
remove
> + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hostc";
remove
> + phys = <&combphy0 PHY_TYPE_SATA>;
> + phy-names = "sata-phy";
> + ports-implemented = <0x1>;
> + power-domains = <&power RK3568_PD_PIPE>;
> + status = "disabled";
> + };
> +
> + sata1: sata@fc400000 {
> + compatible = "snps,dwc-ahci";
> + reg = <0 0xfc400000 0 0x1000>;
> + clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
> + <&cru CLK_SATA1_RXOOB>;
> + clock-names = "sata", "pmalive", "rxoob";
remove
> + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hostc";
remove
> + phys = <&combphy1 PHY_TYPE_SATA>;
> + phy-names = "sata-phy";
> + ports-implemented = <0x1>;
> + power-domains = <&power RK3568_PD_PIPE>;
> + status = "disabled";
> + };
> +
> + sata2: sata@fc800000 {
> + compatible = "snps,dwc-ahci";
> + reg = <0 0xfc800000 0 0x1000>;
> + clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
> + <&cru CLK_SATA2_RXOOB>;
> + clock-names = "sata", "pmalive", "rxoob";
remove
> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hostc";
remove
> + phys = <&combphy2 PHY_TYPE_SATA>;
> + phy-names = "sata-phy";
> + ports-implemented = <0x1>;
> + power-domains = <&power RK3568_PD_PIPE>;
> + status = "disabled";
> + };
> +
> gic: interrupt-controller@fd400000 {
> compatible = "arm,gic-v3";
> reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2] arm64: dts: rockchip: Add sata nodes to rk356x
@ 2022-02-27 9:32 ` Johan Jonker
0 siblings, 0 replies; 7+ messages in thread
From: Johan Jonker @ 2022-02-27 9:32 UTC (permalink / raw)
To: Frank Wunderlich, linux-rockchip
Cc: Frank Wunderlich, Rob Herring, Krzysztof Kozlowski,
Heiko Stuebner, Peter Geis, Michael Riesch, devicetree,
linux-arm-kernel, linux-kernel
Hi Frank,
Combine your patch in a serie with the ahci-platform.yaml conversion and
include all current CC people and Rockchip list.
Your conversion and DT patch contains lots of errors.
Check your serie before you submit and fix.
ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- make dt_binding_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/ata/ahci-platform.yaml
ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- make dtbs_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/ata/ahci-platform.yaml
Add power-domains as a new property after the conversion patch.
Johan
===
make a serie:
conversion ahci-platform.yaml
power-domains patch
rockchip rk356x sata nodes patch
On 2/27/22 09:21, Frank Wunderlich wrote:
> From: Frank Wunderlich <frank-w@public-files.de>
>
> RK356x supports up to 3 sata controllers which were compatible with the
> existing snps,dwc-ahci binding.
>
> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
> ---
> changes in v2:
> - added sata0 + 1, but have only tested sata2
> ---
> arch/arm64/boot/dts/rockchip/rk356x.dtsi | 45 ++++++++++++++++++++++++
> 1 file changed, 45 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> index 7cdef800cb3c..2e2e73be7417 100644
> --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> @@ -230,6 +230,51 @@ scmi_shmem: sram@0 {
> };
> };
>
> + sata0: sata@fc000000 {
rk3566 has no combphy0
Move to rk3568.dtsi
> + compatible = "snps,dwc-ahci";
> + reg = <0 0xfc000000 0 0x1000>;
> + clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
> + <&cru CLK_SATA0_RXOOB>;
> + clock-names = "sata", "pmalive", "rxoob";
remove
> + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hostc";
remove
> + phys = <&combphy0 PHY_TYPE_SATA>;
> + phy-names = "sata-phy";
> + ports-implemented = <0x1>;
> + power-domains = <&power RK3568_PD_PIPE>;
> + status = "disabled";
> + };
> +
> + sata1: sata@fc400000 {
> + compatible = "snps,dwc-ahci";
> + reg = <0 0xfc400000 0 0x1000>;
> + clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
> + <&cru CLK_SATA1_RXOOB>;
> + clock-names = "sata", "pmalive", "rxoob";
remove
> + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hostc";
remove
> + phys = <&combphy1 PHY_TYPE_SATA>;
> + phy-names = "sata-phy";
> + ports-implemented = <0x1>;
> + power-domains = <&power RK3568_PD_PIPE>;
> + status = "disabled";
> + };
> +
> + sata2: sata@fc800000 {
> + compatible = "snps,dwc-ahci";
> + reg = <0 0xfc800000 0 0x1000>;
> + clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
> + <&cru CLK_SATA2_RXOOB>;
> + clock-names = "sata", "pmalive", "rxoob";
remove
> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hostc";
remove
> + phys = <&combphy2 PHY_TYPE_SATA>;
> + phy-names = "sata-phy";
> + ports-implemented = <0x1>;
> + power-domains = <&power RK3568_PD_PIPE>;
> + status = "disabled";
> + };
> +
> gic: interrupt-controller@fd400000 {
> compatible = "arm,gic-v3";
> reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2] arm64: dts: rockchip: Add sata nodes to rk356x
@ 2022-02-27 9:32 ` Johan Jonker
0 siblings, 0 replies; 7+ messages in thread
From: Johan Jonker @ 2022-02-27 9:32 UTC (permalink / raw)
To: Frank Wunderlich, linux-rockchip
Cc: Frank Wunderlich, Rob Herring, Krzysztof Kozlowski,
Heiko Stuebner, Peter Geis, Michael Riesch, devicetree,
linux-arm-kernel, linux-kernel
Hi Frank,
Combine your patch in a serie with the ahci-platform.yaml conversion and
include all current CC people and Rockchip list.
Your conversion and DT patch contains lots of errors.
Check your serie before you submit and fix.
ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- make dt_binding_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/ata/ahci-platform.yaml
ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- make dtbs_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/ata/ahci-platform.yaml
Add power-domains as a new property after the conversion patch.
Johan
===
make a serie:
conversion ahci-platform.yaml
power-domains patch
rockchip rk356x sata nodes patch
On 2/27/22 09:21, Frank Wunderlich wrote:
> From: Frank Wunderlich <frank-w@public-files.de>
>
> RK356x supports up to 3 sata controllers which were compatible with the
> existing snps,dwc-ahci binding.
>
> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
> ---
> changes in v2:
> - added sata0 + 1, but have only tested sata2
> ---
> arch/arm64/boot/dts/rockchip/rk356x.dtsi | 45 ++++++++++++++++++++++++
> 1 file changed, 45 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> index 7cdef800cb3c..2e2e73be7417 100644
> --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> @@ -230,6 +230,51 @@ scmi_shmem: sram@0 {
> };
> };
>
> + sata0: sata@fc000000 {
rk3566 has no combphy0
Move to rk3568.dtsi
> + compatible = "snps,dwc-ahci";
> + reg = <0 0xfc000000 0 0x1000>;
> + clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
> + <&cru CLK_SATA0_RXOOB>;
> + clock-names = "sata", "pmalive", "rxoob";
remove
> + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hostc";
remove
> + phys = <&combphy0 PHY_TYPE_SATA>;
> + phy-names = "sata-phy";
> + ports-implemented = <0x1>;
> + power-domains = <&power RK3568_PD_PIPE>;
> + status = "disabled";
> + };
> +
> + sata1: sata@fc400000 {
> + compatible = "snps,dwc-ahci";
> + reg = <0 0xfc400000 0 0x1000>;
> + clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
> + <&cru CLK_SATA1_RXOOB>;
> + clock-names = "sata", "pmalive", "rxoob";
remove
> + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hostc";
remove
> + phys = <&combphy1 PHY_TYPE_SATA>;
> + phy-names = "sata-phy";
> + ports-implemented = <0x1>;
> + power-domains = <&power RK3568_PD_PIPE>;
> + status = "disabled";
> + };
> +
> + sata2: sata@fc800000 {
> + compatible = "snps,dwc-ahci";
> + reg = <0 0xfc800000 0 0x1000>;
> + clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
> + <&cru CLK_SATA2_RXOOB>;
> + clock-names = "sata", "pmalive", "rxoob";
remove
> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hostc";
remove
> + phys = <&combphy2 PHY_TYPE_SATA>;
> + phy-names = "sata-phy";
> + ports-implemented = <0x1>;
> + power-domains = <&power RK3568_PD_PIPE>;
> + status = "disabled";
> + };
> +
> gic: interrupt-controller@fd400000 {
> compatible = "arm,gic-v3";
> reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2] arm64: dts: rockchip: Add sata nodes to rk356x
@ 2022-02-27 8:21 ` Frank Wunderlich
0 siblings, 0 replies; 7+ messages in thread
From: Frank Wunderlich @ 2022-02-27 8:21 UTC (permalink / raw)
To: linux-rockchip
Cc: Frank Wunderlich, Rob Herring, Krzysztof Kozlowski,
Heiko Stuebner, Peter Geis, Michael Riesch, devicetree,
linux-arm-kernel, linux-kernel
From: Frank Wunderlich <frank-w@public-files.de>
RK356x supports up to 3 sata controllers which were compatible with the
existing snps,dwc-ahci binding.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
changes in v2:
- added sata0 + 1, but have only tested sata2
---
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 45 ++++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 7cdef800cb3c..2e2e73be7417 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -230,6 +230,51 @@ scmi_shmem: sram@0 {
};
};
+ sata0: sata@fc000000 {
+ compatible = "snps,dwc-ahci";
+ reg = <0 0xfc000000 0 0x1000>;
+ clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
+ <&cru CLK_SATA0_RXOOB>;
+ clock-names = "sata", "pmalive", "rxoob";
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hostc";
+ phys = <&combphy0 PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ ports-implemented = <0x1>;
+ power-domains = <&power RK3568_PD_PIPE>;
+ status = "disabled";
+ };
+
+ sata1: sata@fc400000 {
+ compatible = "snps,dwc-ahci";
+ reg = <0 0xfc400000 0 0x1000>;
+ clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
+ <&cru CLK_SATA1_RXOOB>;
+ clock-names = "sata", "pmalive", "rxoob";
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hostc";
+ phys = <&combphy1 PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ ports-implemented = <0x1>;
+ power-domains = <&power RK3568_PD_PIPE>;
+ status = "disabled";
+ };
+
+ sata2: sata@fc800000 {
+ compatible = "snps,dwc-ahci";
+ reg = <0 0xfc800000 0 0x1000>;
+ clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
+ <&cru CLK_SATA2_RXOOB>;
+ clock-names = "sata", "pmalive", "rxoob";
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hostc";
+ phys = <&combphy2 PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ ports-implemented = <0x1>;
+ power-domains = <&power RK3568_PD_PIPE>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@fd400000 {
compatible = "arm,gic-v3";
reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v2] arm64: dts: rockchip: Add sata nodes to rk356x
@ 2022-02-27 8:21 ` Frank Wunderlich
0 siblings, 0 replies; 7+ messages in thread
From: Frank Wunderlich @ 2022-02-27 8:21 UTC (permalink / raw)
To: linux-rockchip
Cc: Frank Wunderlich, Rob Herring, Krzysztof Kozlowski,
Heiko Stuebner, Peter Geis, Michael Riesch, devicetree,
linux-arm-kernel, linux-kernel
From: Frank Wunderlich <frank-w@public-files.de>
RK356x supports up to 3 sata controllers which were compatible with the
existing snps,dwc-ahci binding.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
changes in v2:
- added sata0 + 1, but have only tested sata2
---
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 45 ++++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 7cdef800cb3c..2e2e73be7417 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -230,6 +230,51 @@ scmi_shmem: sram@0 {
};
};
+ sata0: sata@fc000000 {
+ compatible = "snps,dwc-ahci";
+ reg = <0 0xfc000000 0 0x1000>;
+ clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
+ <&cru CLK_SATA0_RXOOB>;
+ clock-names = "sata", "pmalive", "rxoob";
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hostc";
+ phys = <&combphy0 PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ ports-implemented = <0x1>;
+ power-domains = <&power RK3568_PD_PIPE>;
+ status = "disabled";
+ };
+
+ sata1: sata@fc400000 {
+ compatible = "snps,dwc-ahci";
+ reg = <0 0xfc400000 0 0x1000>;
+ clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
+ <&cru CLK_SATA1_RXOOB>;
+ clock-names = "sata", "pmalive", "rxoob";
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hostc";
+ phys = <&combphy1 PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ ports-implemented = <0x1>;
+ power-domains = <&power RK3568_PD_PIPE>;
+ status = "disabled";
+ };
+
+ sata2: sata@fc800000 {
+ compatible = "snps,dwc-ahci";
+ reg = <0 0xfc800000 0 0x1000>;
+ clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
+ <&cru CLK_SATA2_RXOOB>;
+ clock-names = "sata", "pmalive", "rxoob";
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hostc";
+ phys = <&combphy2 PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ ports-implemented = <0x1>;
+ power-domains = <&power RK3568_PD_PIPE>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@fd400000 {
compatible = "arm,gic-v3";
reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
--
2.25.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v2] arm64: dts: rockchip: Add sata nodes to rk356x
@ 2022-02-27 8:21 ` Frank Wunderlich
0 siblings, 0 replies; 7+ messages in thread
From: Frank Wunderlich @ 2022-02-27 8:21 UTC (permalink / raw)
To: linux-rockchip
Cc: Frank Wunderlich, Rob Herring, Krzysztof Kozlowski,
Heiko Stuebner, Peter Geis, Michael Riesch, devicetree,
linux-arm-kernel, linux-kernel
From: Frank Wunderlich <frank-w@public-files.de>
RK356x supports up to 3 sata controllers which were compatible with the
existing snps,dwc-ahci binding.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
changes in v2:
- added sata0 + 1, but have only tested sata2
---
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 45 ++++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 7cdef800cb3c..2e2e73be7417 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -230,6 +230,51 @@ scmi_shmem: sram@0 {
};
};
+ sata0: sata@fc000000 {
+ compatible = "snps,dwc-ahci";
+ reg = <0 0xfc000000 0 0x1000>;
+ clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
+ <&cru CLK_SATA0_RXOOB>;
+ clock-names = "sata", "pmalive", "rxoob";
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hostc";
+ phys = <&combphy0 PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ ports-implemented = <0x1>;
+ power-domains = <&power RK3568_PD_PIPE>;
+ status = "disabled";
+ };
+
+ sata1: sata@fc400000 {
+ compatible = "snps,dwc-ahci";
+ reg = <0 0xfc400000 0 0x1000>;
+ clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
+ <&cru CLK_SATA1_RXOOB>;
+ clock-names = "sata", "pmalive", "rxoob";
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hostc";
+ phys = <&combphy1 PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ ports-implemented = <0x1>;
+ power-domains = <&power RK3568_PD_PIPE>;
+ status = "disabled";
+ };
+
+ sata2: sata@fc800000 {
+ compatible = "snps,dwc-ahci";
+ reg = <0 0xfc800000 0 0x1000>;
+ clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
+ <&cru CLK_SATA2_RXOOB>;
+ clock-names = "sata", "pmalive", "rxoob";
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hostc";
+ phys = <&combphy2 PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ ports-implemented = <0x1>;
+ power-domains = <&power RK3568_PD_PIPE>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@fd400000 {
compatible = "arm,gic-v3";
reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
--
2.25.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread
end of thread, other threads:[~2022-03-01 21:44 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
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2022-03-01 21:44 [PATCH v2] arm64: dts: rockchip: Add sata nodes to rk356x kernel test robot
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2022-02-27 8:21 Frank Wunderlich
2022-02-27 8:21 ` Frank Wunderlich
2022-02-27 8:21 ` Frank Wunderlich
2022-02-27 9:32 ` Johan Jonker
2022-02-27 9:32 ` Johan Jonker
2022-02-27 9:32 ` Johan Jonker
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