[PATCH] arm: Add AM335x based CBC board

* [PATCH] arm: Add AM335x based CBC board
@ 2022-02-22  8:57 Lukasz Majewski
  2022-03-03  9:27 ` Lukasz Majewski
  0 siblings, 1 reply; 7+ messages in thread
From: Lukasz Majewski @ 2022-02-22  8:57 UTC (permalink / raw)
  To: Tom Rini, u-boot
  Cc: Lukasz Majewski, Andre Przywara, Bharat Gooty, Christian Hewitt,
	Dario Binacchi, Fabio Estevam, Gireesh Hiremath, Heiko Schocher,
	Jaehoon Chung, Jagan Teki, Kever Yang, Kory Maincent,
	Lokesh Vutla, Marcin Niestroj, Peter Robinson,
	Rayagonda Kokatanur, Simon Glass, Tim Harvey,
	Ying-Chun Liu (PaulLiu)

This commit adds CBC board to U-Boot.

U-Boot 2022.04-rc1-00271-g930634a4c9 (Feb 21 2022 - 15:08:13 +0100)

CPU  : AM335X-GP rev 2.1
Model: AM335x Bosch CBC
DRAM:  512 MiB
Core:  198 devices, 14 uclasses, devicetree: separate
MMC:   OMAP SD/MMC: 2, OMAP SD/MMC: 0, OMAP SD/MMC: 1
Loading Environment from MMC... OK
Boot Device is eMMC
CBC Variant found: BCT531
Net:   eth2: ethernet@4a100000
Hit any key to stop autoboot:  0

Signed-off-by: Lukasz Majewski <lukma@denx.de>

---

 arch/arm/Kconfig                    |   1 +
 arch/arm/dts/Makefile               |   1 +
 arch/arm/dts/am335x-cbc-u-boot.dtsi |  18 ++
 arch/arm/dts/am335x-cbc.dts         | 309 ++++++++++++++++++++
 arch/arm/dts/am335x-cbc.dtsi        | 136 +++++++++
 arch/arm/mach-omap2/am33xx/Kconfig  |   8 +
 board/bosch/cbc/Kconfig             |  15 +
 board/bosch/cbc/MAINTAINERS         |   6 +
 board/bosch/cbc/Makefile            |   9 +
 board/bosch/cbc/README              |  17 ++
 board/bosch/cbc/board.c             | 437 ++++++++++++++++++++++++++++
 board/bosch/cbc/board.h             |  71 +++++
 board/bosch/cbc/mux.c               | 171 +++++++++++
 configs/am335x_cbc_defconfig        |  81 ++++++
 include/configs/am335x_cbc.h        |  84 ++++++
 15 files changed, 1364 insertions(+)
 create mode 100644 arch/arm/dts/am335x-cbc-u-boot.dtsi
 create mode 100644 arch/arm/dts/am335x-cbc.dts
 create mode 100644 arch/arm/dts/am335x-cbc.dtsi
 create mode 100644 board/bosch/cbc/Kconfig
 create mode 100644 board/bosch/cbc/MAINTAINERS
 create mode 100644 board/bosch/cbc/Makefile
 create mode 100644 board/bosch/cbc/README
 create mode 100644 board/bosch/cbc/board.c
 create mode 100644 board/bosch/cbc/board.h
 create mode 100644 board/bosch/cbc/mux.c
 create mode 100644 configs/am335x_cbc_defconfig
 create mode 100644 include/configs/am335x_cbc.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9a62b55786..4c6ab18e7c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -2194,6 +2194,7 @@ source "arch/arm/mach-nexell/Kconfig"
 
 source "board/armltd/total_compute/Kconfig"
 
+source "board/bosch/cbc/Kconfig"
 source "board/bosch/shc/Kconfig"
 source "board/bosch/guardian/Kconfig"
 source "board/Marvell/octeontx/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 5a5706918a..a5f31f0b45 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -378,6 +378,7 @@ dtb-$(CONFIG_AM33XX) += \
 	am335x-brppt1-spi.dtb \
 	am335x-brxre1.dtb \
 	am335x-brsmarc1.dtb \
+	am335x-cbc.dtb \
 	am335x-draco.dtb \
 	am335x-evm.dtb \
 	am335x-evmsk.dtb \
diff --git a/arch/arm/dts/am335x-cbc-u-boot.dtsi b/arch/arm/dts/am335x-cbc-u-boot.dtsi
new file mode 100644
index 0000000000..1d33b45acd
--- /dev/null
+++ b/arch/arm/dts/am335x-cbc-u-boot.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+ or X11
+/*
+ * Copyright 2022
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+
+#include "am33xx-u-boot.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &uart0;
+		tick-timer = &timer2;
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/am335x-cbc.dts b/arch/arm/dts/am335x-cbc.dts
new file mode 100644
index 0000000000..15ce0475ee
--- /dev/null
+++ b/arch/arm/dts/am335x-cbc.dts
@@ -0,0 +1,309 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+
+/dts-v1/;
+#include "am335x-cbc.dtsi"
+
+/ {
+	model = "AM335x Bosch CBC";
+	compatible = "bosch,am335x-cbc", "ti,am33xx";
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&keys_gpio_pins>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		key@1 {
+			label = "Hand";
+			linux,code = <0x100>;
+			gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
+			debounce-interval = <20>;
+		};
+		key@2 {
+			label = "Reset";
+			linux,code = <0x101>;
+			gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
+			debounce-interval = <20>;
+		};
+		key@3 {
+			label = "Service";
+			linux,code = <0x102>;
+			gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
+			debounce-interval = <20>;
+		};
+		key@4 {
+			label = "B1";
+			gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
+			debounce-interval = <20>;
+		};
+		key@5 {
+			label = "B2";
+			gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
+			debounce-interval = <20>;
+		};
+		key@6 {
+			label = "B3";
+			gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
+			debounce-interval = <20>;
+		};
+		key@7 {
+			label = "B4";
+			gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+			debounce-interval = <20>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&led_gpio_pins>;
+
+		led0 {
+			label = "red";
+			gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+		};
+
+		led1 {
+			label = "green";
+			gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
+		};
+
+		led2 {
+			label = "blue";
+			gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&am33xx_pinmux {
+	uart0_pins: pinmux_uart0_pins {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)	/* uart0_rxd.uart0_rxd */
+			AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart0_txd.uart0_txd */
+		>;
+	};
+
+	cpsw_default: cpsw_default {
+		pinctrl-single,pins = <
+			/* Slave 1 RMII mode */
+			AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_crs.rmii1_crs */
+			AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE1)	/* mii1_rxerr.rmii1_rxerr */
+			AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* mii1_txen.rmii1_txen */
+			AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* mii1_txd1.rmii1_txd1 */
+			AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* mii1_txd0.rmii1_txd0 */
+			AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE1)	/* mii1_rxd1.rmii1_rxd1 */
+			AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE1)	/* mii1_rxd0.rmii1_rxd0 */
+			AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* rmii1_ref_clk.rmii_ref_clk */
+			/* Slave 2 RMII mode */
+			AM33XX_IOPAD(0x870, (PIN_INPUT_PULLUP | MUX_MODE3))	/* gpmc_wait0.rmii2_crs_dv */
+			AM33XX_IOPAD(0x908, (PIN_INPUT_PULLUP | MUX_MODE1))	/* mii1_col.rmii2_refclk */
+			AM33XX_IOPAD(0x86c, (PIN_INPUT_PULLUP | MUX_MODE3))	/* gpmc_a11.rmii2_rxd0 */
+			AM33XX_IOPAD(0x868, (PIN_INPUT_PULLUP | MUX_MODE3))	/* gpmc_a10.rmii2_rxd1 */
+			AM33XX_IOPAD(0x874, (PIN_INPUT_PULLUP | MUX_MODE3))	/* gpmc_wpn.rmii2_rxerr */
+			AM33XX_IOPAD(0x854, (PIN_OUTPUT_PULLDOWN | MUX_MODE3))	/* gpmc_a5.rmii2_txd0 */
+			AM33XX_IOPAD(0x850, (PIN_OUTPUT_PULLDOWN | MUX_MODE3))	/* gpmc_a4.rmii2_txd1 */
+			AM33XX_IOPAD(0x840, (PIN_OUTPUT_PULLDOWN | MUX_MODE3))	/* gpmc_a0.rmii2_txen */
+		>;
+	};
+
+	cpsw_sleep: cpsw_sleep {
+		pinctrl-single,pins = <
+			/* Slave 1 reset value */
+			AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
+
+			/* Slave 2 reset value */
+			AM33XX_IOPAD(0x870, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_IOPAD(0x908, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_IOPAD(0x86c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_IOPAD(0x868, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_IOPAD(0x874, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_IOPAD(0x854, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_IOPAD(0x850, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_IOPAD(0x840, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+		>;
+	};
+
+	davinci_mdio_default: davinci_mdio_default {
+		pinctrl-single,pins = <
+			/* mdio_data.mdio_data */
+			AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)
+			/* mdio_clk.mdio_clk */
+			AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)
+		>;
+	};
+
+	davinci_mdio_sleep: davinci_mdio_sleep {
+		pinctrl-single,pins = <
+			/* MDIO reset value */
+			AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
+
+	emmc_pins: pinmux_emmc_pins {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x880, PIN_INPUT | MUX_MODE2)
+			AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2)
+			AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1)
+			AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1)
+			AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1)
+			AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1)
+			AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1)
+			AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1)
+			AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1)
+			AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1)
+		>;
+	};
+
+	keys_gpio_pins: pinmux_keys_gpio_pins {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x858, PIN_INPUT | MUX_MODE7) /* gpmc_a6.gpio1_22 */
+			AM33XX_IOPAD(0x85c, PIN_INPUT | MUX_MODE7) /* gpmc_a7.gpio1_23 */
+			AM33XX_IOPAD(0x860, PIN_INPUT | MUX_MODE7) /* gpmc_a8.gpio1_24 */
+			AM33XX_IOPAD(0x95c, PIN_INPUT | MUX_MODE7) /* spi0_cs0.gpio0_5 */
+			AM33XX_IOPAD(0x958, PIN_INPUT | MUX_MODE7) /* spi0_d1.gpio0_4 */
+			AM33XX_IOPAD(0x954, PIN_INPUT | MUX_MODE7) /* spi0_d0.gpio0_3 */
+			AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE7) /* spi0_sclk.gpio0_2 */
+		>;
+	};
+
+	sd_pins: pinmux_sd_pins {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x878, PIN_INPUT | MUX_MODE3)
+			AM33XX_IOPAD(0x84c, PIN_INPUT | MUX_MODE3)
+			AM33XX_IOPAD(0x848, PIN_INPUT | MUX_MODE3)
+			AM33XX_IOPAD(0x844, PIN_INPUT | MUX_MODE3)
+			AM33XX_IOPAD(0x88c, PIN_INPUT | MUX_MODE3)
+			AM33XX_IOPAD(0x888, PIN_INPUT | MUX_MODE3)
+			AM33XX_IOPAD(0x998, PIN_INPUT | MUX_MODE7)
+			AM33XX_IOPAD(0x994, PIN_INPUT | MUX_MODE7)
+		>;
+	};
+
+	usd_pins: pinmux_usd_card {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x8f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
+			AM33XX_IOPAD(0x8f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
+			AM33XX_IOPAD(0x8f8, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
+			AM33XX_IOPAD(0x8fc, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
+			AM33XX_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
+			AM33XX_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
+			AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+		>;
+	};
+
+	led_gpio_pins: pinmux_led_gpio_pins {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE7) /* gpmc_wen.gpio2_4 */
+			AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */
+			AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE7) /* gpmc_be0n_cle.gpio2_5 */
+		>;
+	};
+};
+
+&cppi41dma  {
+	status = "okay";
+};
+
+&cpsw_emac0 {
+	phy-handle = <&ethphy0>;
+	phy-mode = "rmii";
+};
+
+&cpsw_emac1 {
+	phy-handle = <&ethphy1>;
+	phy-mode = "rmii";
+};
+
+&davinci_mdio {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&davinci_mdio_default>;
+	pinctrl-1 = <&davinci_mdio_sleep>;
+	status = "okay";
+
+	ethphy0: ethernet-phy@0 {
+		reg = <0>;
+	};
+
+	ethphy1: ethernet-phy@1 {
+		reg = <1>;
+	};
+};
+
+&ldo4_reg {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+};
+
+/* Ethernet */
+&mac {
+	active_slave = <1>;
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&cpsw_default>;
+	pinctrl-1 = <&cpsw_sleep>;
+	status = "okay";
+};
+
+/* microSD */
+&mmc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&usd_pins>;
+	vmmc-supply = <&ldo4_reg>;
+	bus-width = <0x4>;
+	status = "okay";
+};
+
+/* eMMC */
+&mmc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_pins>;
+	vmmc-supply = <&ldo4_reg>;
+	bus-width = <0x8>;
+	non-removable;
+	status = "okay";
+};
+
+/* SD card */
+&mmc3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&sd_pins>;
+	bus-width = <0x4>;
+	wp-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&phy_sel {
+	rmii-clock-ext;
+};
+
+&tps {
+	interrupt-parent = <&intc>;
+	interrupts = <7>; /* NNMI */
+
+	charger {
+		status = "okay";
+	};
+
+	pwrbutton {
+		status = "okay";
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins>;
+
+	status = "okay";
+};
diff --git a/arch/arm/dts/am335x-cbc.dtsi b/arch/arm/dts/am335x-cbc.dtsi
new file mode 100644
index 0000000000..ad24e08190
--- /dev/null
+++ b/arch/arm/dts/am335x-cbc.dtsi
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+
+/dts-v1/;
+
+#include "am33xx.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	model = "Bosch AM335x CBC";
+	compatible = "bosch,am335x-cbc", "ti,am33xx";
+
+	cpus {
+		cpu@0 {
+			cpu0-supply = <&dcdc2_reg>;
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x80000000 0x20000000>; /* 512 MB */
+	};
+};
+
+&am33xx_pinmux {
+	pinctrl-names = "default";
+
+	i2c0_pins: pinmux_i2c0_pins {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
+			AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
+		>;
+	};
+
+	i2c1_pins: pinmux_i2c1_pins {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x968, PIN_INPUT_PULLUP | MUX_MODE3)	/* uart0_ctsn.i2c1_sda */
+			AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE3)	/* uart0_rtsn.i2c1_scl */
+		>;
+	};
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins>;
+
+	status = "okay";
+	clock-frequency = <400000>;
+
+	tps: tps@24 {
+		reg = <0x24>;
+	};
+};
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
+
+	status = "okay";
+	clock-frequency = <100000>;
+
+	i2c_eeprom: eeprom@50 {
+		compatible = "atmel,24c32";
+		pagesize = <32>;
+		reg = <0x50>;
+		status = "okay";
+	};
+};
+
+&rtc {
+	system-power-controller;
+
+	pinctrl-0 = <&ext_wakeup>;
+	pinctrl-names = "default";
+
+	ext_wakeup: ext-wakeup {
+		pins = "ext_wakeup0";
+		input-enable;
+	};
+};
+
+/include/ "tps65217.dtsi"
+
+&tps {
+	regulators {
+		dcdc1_reg: regulator@0 {
+			regulator-name = "vdds_dpr";
+			regulator-always-on;
+		};
+
+		dcdc2_reg: regulator@1 {
+			/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
+			regulator-name = "vdd_mpu";
+			regulator-min-microvolt = <925000>;
+			regulator-max-microvolt = <1325000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		dcdc3_reg: regulator@2 {
+			/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+			regulator-name = "vdd_core";
+			regulator-min-microvolt = <925000>;
+			regulator-max-microvolt = <1150000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		ldo1_reg: regulator@3 {
+			regulator-name = "vio,vrtc,vdds";
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		ldo2_reg: regulator@4 {
+			regulator-name = "vdd_3v3aux";
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		ldo3_reg: regulator@5 {
+			regulator-name = "vdd_1v8";
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		ldo4_reg: regulator@6 {
+			regulator-name = "vdd_3v3d";
+			regulator-boot-on;
+			regulator-always-on;
+		};
+	};
+};
diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig
index 1402376915..45cb8ff6d2 100644
--- a/arch/arm/mach-omap2/am33xx/Kconfig
+++ b/arch/arm/mach-omap2/am33xx/Kconfig
@@ -71,6 +71,14 @@ config TARGET_AM335X_BALTOS
 	select DM_SERIAL
 	imply CMD_DM
 
+config TARGET_AM335X_CBC
+	bool "Support am335x based cbc board from bosch"
+	select BOARD_LATE_INIT
+	select DM
+	select DM_GPIO
+	select DM_SERIAL
+	imply CMD_DM
+
 config TARGET_AM335X_IGEP003X
 	bool "Support am335x_igep003x"
 	select BOARD_LATE_INIT
diff --git a/board/bosch/cbc/Kconfig b/board/bosch/cbc/Kconfig
new file mode 100644
index 0000000000..03fae6d48c
--- /dev/null
+++ b/board/bosch/cbc/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_AM335X_CBC
+
+config SYS_BOARD
+	default "cbc"
+
+config SYS_VENDOR
+	default "bosch"
+
+config SYS_CONFIG_NAME
+	default "am335x_cbc"
+
+config SYS_SOC
+	default "am33xx"
+
+endif
diff --git a/board/bosch/cbc/MAINTAINERS b/board/bosch/cbc/MAINTAINERS
new file mode 100644
index 0000000000..c5216383b7
--- /dev/null
+++ b/board/bosch/cbc/MAINTAINERS
@@ -0,0 +1,6 @@
+CBC BOARD
+M:	Lukasz Majewski <lukma@denx.de>
+S:	Maintained
+F:	board/bosch/cbc/
+F:	include/configs/am335x_cbc.h
+F:	configs/am335x_cbc_defconfig
diff --git a/board/bosch/cbc/Makefile b/board/bosch/cbc/Makefile
new file mode 100644
index 0000000000..93f3ead28e
--- /dev/null
+++ b/board/bosch/cbc/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2022
+# Lukasz Majewski, DENX Software Engineering, lukma@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= mux.o
+obj-y	+= board.o
diff --git a/board/bosch/cbc/README b/board/bosch/cbc/README
new file mode 100644
index 0000000000..b1265ba2bf
--- /dev/null
+++ b/board/bosch/cbc/README
@@ -0,0 +1,17 @@
+How to use U-Boot on Bosh's CBC
+===============================
+
+- Build U-Boot for cbc:
+
+$ make mrproper
+$ make am335x_cbc_defconfig
+$ make
+
+This will generate the SPL image called MLO and the u-boot.img.
+
+Prepare uSD card:
+-----------------
+
+- Create primary boot partition with FAT16 type (16 MiB size)
+- Format it to use vfat (mkfs.vfat -F16)
+- Copy the MLO and u-boot.img to this partition
diff --git a/board/bosch/cbc/board.c b/board/bosch/cbc/board.c
new file mode 100644
index 0000000000..9187c6d2f4
--- /dev/null
+++ b/board/bosch/cbc/board.c
@@ -0,0 +1,437 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * Copyright (C) 2017, Grinn - http://grinn-global.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ */
+
+#include <common.h>
+#include <init.h>
+#include <net.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/emif.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <cpsw.h>
+#include <env.h>
+#include <errno.h>
+#include <miiphy.h>
+#include <spl.h>
+#include <watchdog.h>
+#include <i2c.h>
+#include <power/tps65217.h>
+#include <linux/delay.h>
+#include <dm/uclass.h>
+#include <i2c_eeprom.h>
+#include <led.h>
+#include <button.h>
+
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static __maybe_unused struct ctrl_dev *cdev =
+	(struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+static struct cbc_baseboard_id header;
+static int cbc_eeprom_valid;
+
+/*
+ * Read header information from EEPROM into global structure.
+ */
+static int read_eeprom(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = uclass_get_device_by_name(UCLASS_I2C_EEPROM, "eeprom@50", &dev);
+	if (ret) {
+		debug("%s: could not get EEPROM [%d]\n", __func__, ret);
+		return ret;
+	}
+
+	ret = i2c_eeprom_read(dev, 0, (uint8_t *)&header, sizeof(header));
+	if (ret < 0) {
+		debug("%s: EEPROM read failed! [%d]\n", __func__, ret);
+		return -EIO;
+	}
+
+	if (header.magic != HDR_MAGIC) {
+		printf("Incorrect magic number (0x%x) in EEPROM\n",
+		       header.magic);
+		return -EIO;
+	}
+
+	cbc_eeprom_valid = 1;
+	return 0;
+}
+
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
+void set_uart_mux_conf(void)
+{
+	enable_uart0_pin_mux();
+	enable_uart1_pin_mux();
+	enable_uart2_pin_mux();
+	enable_uart3_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+	enable_board_pin_mux();
+}
+
+/* DDR3 configuration data */
+static const struct ddr_data ddr3_cbc_data = {
+	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
+	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_cbc_cmd_ctrl_data = {
+	.cmd0csratio = MT41K256M16HA125E_RATIO,
+	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41K256M16HA125E_RATIO,
+	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41K256M16HA125E_RATIO,
+	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_cbc_emif_reg_data = {
+	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+	.ocp_config = 0x00141414,
+	.zq_config = MT41K256M16HA125E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+#define OSC	(V_OSCK / 1000000)
+const struct dpll_params dpll_ddr_cbc = {
+		400, OSC - 1, 1, -1, -1, -1, -1};
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	return &dpll_ddr_cbc;
+}
+
+const struct ctrl_ioregs ioregs_cbc = {
+	.cm0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm2ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+void sdram_init(void)
+{
+	config_ddr(400, &ioregs_cbc,
+		   &ddr3_cbc_data,
+		   &ddr3_cbc_cmd_ctrl_data,
+		   &ddr3_cbc_emif_reg_data, 0);
+}
+
+void am33xx_spl_board_init(void)
+{
+	int mpu_vdd;
+	int usb_cur_lim;
+
+	enable_i2c0_pin_mux();
+
+	/* Get the frequency */
+	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+
+	if (power_tps65217_init(0))
+		return;
+
+	/*
+	 * Increase USB current limit to 1300mA or 1800mA and set
+	 * the MPU voltage controller as needed.
+	 */
+	if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
+		usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
+	} else {
+		usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
+	}
+
+	if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+			       TPS65217_POWER_PATH,
+			       usb_cur_lim,
+			       TPS65217_USB_INPUT_CUR_LIMIT_MASK))
+		puts("tps65217_reg_write failure\n");
+
+	/* Set DCDC3 (CORE) voltage to 1.125V */
+	if (tps65217_voltage_update(TPS65217_DEFDCDC3,
+				    TPS65217_DCDC_VOLT_SEL_1125MV)) {
+		puts("tps65217_voltage_update failure\n");
+		return;
+	}
+
+	/* Set CORE Frequencies to OPP100 */
+	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+	/* Set DCDC2 (MPU) voltage */
+	if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
+		puts("tps65217_voltage_update failure\n");
+		return;
+	}
+
+	/* Set LDO3 to 1.8V and LDO4 to 3.3V */
+	if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+			       TPS65217_DEFLS1,
+			       TPS65217_LDO_VOLTAGE_OUT_1_8,
+			       TPS65217_LDO_MASK))
+		puts("tps65217_reg_write failure\n");
+
+	if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+			       TPS65217_DEFLS2,
+			       TPS65217_LDO_VOLTAGE_OUT_3_3,
+			       TPS65217_LDO_MASK))
+		puts("tps65217_reg_write failure\n");
+
+	/* Set MPU Frequency to what we detected now that voltages are set */
+	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+}
+#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
+
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+	int ret;
+
+	ret = read_eeprom();
+	if (ret < 0)
+		printf("EEPROM Content Invalid [%d].\n", ret);
+
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gpmc_init();
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+static int cbc_encode_address_switch(int *id)
+{
+	struct udevice b1, b2, b3, b4;
+	const char *b1_name = "B1";
+	const char *b2_name = "B2";
+	const char *b3_name = "B3";
+	const char *b4_name = "B4";
+
+	int bit1, bit2, bit3, bit4;
+	struct udevice *dev;
+	int cbc_id = 0;
+	int ret;
+
+	/* CBC-ID Switch */
+	dev = &b1;
+	ret = button_get_by_label(b1_name, &dev);
+	if (ret) {
+		printf("Button '%s' not found (err=%d)\n", b1_name, ret);
+		return ret;
+	}
+	bit1 = button_get_state(dev);
+
+	dev = &b2;
+	ret = button_get_by_label(b2_name, &dev);
+	if (ret) {
+		printf("Button '%s' not found (err=%d)\n", b2_name, ret);
+		return ret;
+	}
+	bit2 = button_get_state(dev);
+
+	dev = &b3;
+	ret = button_get_by_label(b3_name, &dev);
+	if (ret) {
+		printf("Button '%s' not found (err=%d)\n", b3_name, ret);
+		return ret;
+	}
+	bit3 = button_get_state(dev);
+
+	dev = &b4;
+	ret = button_get_by_label(b4_name, &dev);
+	if (ret) {
+		printf("Button '%s' not found (err=%d)\n", b4_name, ret);
+		return ret;
+	}
+	bit4 = button_get_state(dev);
+
+	debug("%s: b1: %d b2: %d b3: %d b4: %d\n", __func__, bit1, bit2,
+	      bit3, bit4);
+
+	/* create integer value from 4 bit-value */
+	(bit1 == 1) ? (cbc_id = cbc_id + 8) : (cbc_id = cbc_id + 0);
+	(bit2 == 1) ? (cbc_id = cbc_id + 4) : (cbc_id = cbc_id + 0);
+	(bit3 == 1) ? (cbc_id = cbc_id + 2) : (cbc_id = cbc_id + 0);
+	(bit4 == 1) ? (cbc_id = cbc_id + 1) : (cbc_id = cbc_id + 0);
+
+	*id = cbc_id;
+	debug("%s: CBC ID: 0x%x\n", __func__, *id);
+
+	return 0;
+}
+
+static int cbc_select_mmcboot_dev(void)
+{
+	const char *bl_name = "Hand";
+	const char *bc_name = "Service";
+	const char *br_name = "Reset";
+	struct udevice bl, bc, br;
+	struct udevice *dev;
+
+	/* Front buttons states */
+	int button_l = 1;
+	int button_c = 1;
+	int button_r = 1;
+	int ret;
+
+	dev = &bl;
+	ret = button_get_by_label(bl_name, &dev);
+	if (ret) {
+		printf("Button '%s' not found (err=%d)\n", bl_name, ret);
+		return ret;
+	}
+	button_l = !button_get_state(dev);
+
+	dev = &bc;
+	ret = button_get_by_label(bc_name, &dev);
+	if (ret) {
+		printf("Button '%s' not found (err=%d)\n", bc_name, ret);
+		return ret;
+	}
+	button_c = !button_get_state(dev);
+
+	dev = &br;
+	ret = button_get_by_label(br_name, &dev);
+	if (ret) {
+		printf("Button '%s' not found (err=%d)\n", br_name, ret);
+		return ret;
+	}
+	button_r = !button_get_state(dev);
+
+	debug("bl: %d bc: %d br: %d\n", button_l, button_c, button_r);
+
+	if (button_l == 0 && button_c == 1 && button_r == 1) {
+		/* only left button pressed: eMMC booot */
+		printf("Boot Device is eMMC\n");
+		env_set("boot_targets", "mmc1");
+	} else if (button_l == 1 && button_c == 0 && button_r == 1) {
+		/* only center button pressed: SD Card 2 */
+		printf("Boot Device is SD Card 2\n");
+		env_set("boot_targets", "mmc2 mmc1");
+	} else if (button_l == 1 && button_c == 1 && button_r == 0) {
+		/* only right button pressed: microSD booot */
+		printf("Boot Device is micro SDCard\n");
+		env_set("boot_targets", "mmc0 mmc1");
+	} else {
+		/* default: boot rfs+kernel from eMMC2 boot */
+		printf("Boot Device is eMMC\n");
+		env_set("boot_targets", "mmc1");
+	}
+
+	return ret;
+}
+
+int board_late_init(void)
+{
+	uchar safe_string_hwrev[HDR_HWREV_ALEN];
+	u8 mac_addr1[HDR_ETH_ALEN];
+	u8 mac_addr[HDR_ETH_ALEN];
+	char *cbc_variant = NULL;
+	u32 mac_hi, mac_lo;
+	int cbc_id = 0;
+	uchar id[4];
+	int ret;
+
+	if (IS_ENABLED(CONFIG_LED))
+		led_default_state();
+
+	if (cbc_eeprom_valid) {
+		memcpy(mac_addr, header.mac_addr, HDR_ETH_ALEN);
+		memcpy(mac_addr1, header.mac1_addr, HDR_ETH_ALEN);
+		if (is_valid_ethaddr(mac_addr))
+			eth_env_set_enetaddr("ethaddr", mac_addr);
+
+		if (is_valid_ethaddr(mac_addr1))
+			eth_env_set_enetaddr("eth1addr", mac_addr1);
+	} else {
+		/* try reading mac address from efuse */
+		mac_lo = readl(&cdev->macid0l);
+		mac_hi = readl(&cdev->macid0h);
+		mac_addr[0] = mac_hi & 0xFF;
+		mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+		mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+		mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+		mac_addr[4] = mac_lo & 0xFF;
+		mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+		if (!env_get("ethaddr")) {
+			printf("<ethaddr> not set. Use first E-fuse MAC\n");
+
+			if (is_valid_ethaddr(mac_addr))
+				eth_env_set_enetaddr("ethaddr", mac_addr);
+		}
+
+		mac_lo = readl(&cdev->macid1l);
+		mac_hi = readl(&cdev->macid1h);
+		mac_addr[0] = mac_hi & 0xFF;
+		mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+		mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+		mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+		mac_addr[4] = mac_lo & 0xFF;
+		mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+		if (!env_get("eth1addr")) {
+			if (is_valid_ethaddr(mac_addr))
+				eth_env_set_enetaddr("eth1addr", mac_addr);
+		}
+	}
+
+	ret = cbc_select_mmcboot_dev();
+	if (ret)
+		printf("%s: Default mmcboot device selected!", __func__);
+
+	ret = cbc_encode_address_switch(&cbc_id);
+	if (ret)
+		printf("%s: Error with address switch read!", __func__);
+
+	/* Get CBC variant from eeprom */
+	if (cbc_eeprom_valid) {
+		const char *c = ";";
+
+		memcpy(safe_string_hwrev, header.cbc_hwrev, HDR_HWREV_ALEN);
+		cbc_variant = strtok((char *)&safe_string_hwrev, c);
+
+		if (cbc_variant) {
+			printf("CBC Variant found: %s\n", cbc_variant);
+			env_set("board_name", cbc_variant);
+		} else {
+			printf("Invalid EEPROM Content\n");
+		}
+	}
+
+	sprintf(id, "%d", cbc_id);
+	env_set("board_id", id);
+
+	return 0;
+}
+#endif
diff --git a/board/bosch/cbc/board.h b/board/bosch/cbc/board.h
new file mode 100644
index 0000000000..d95d6e5112
--- /dev/null
+++ b/board/bosch/cbc/board.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * TI AM335x parts define a system EEPROM that defines certain sub-fields.
+ * We use these fields to in turn see what board we are on, and what
+ * that might require us to set or not set.
+ */
+#define HDR_NO_OF_MAC_ADDR	3
+#define HDR_ETH_ALEN		6
+#define HDR_NAME_LEN		8
+
+#define HDR_MAGIC	0x43424342
+#define HDR_ETH_ALEN	6
+#define HDR_FORGET_ALEN	270
+#define HDR_HWREV_ALEN	64
+
+/* CBC Variant Coding */
+#define CBC_VARIANT_CBC	"CBC"
+#define CBC_VARIANT_BCT531	"BCT531"
+#define CBC_VARIANT_BC531	"BC531"
+#define CBC_VARIANT_BCT831	"BCT831"
+#define CBC_VARIANT_BC831	"BC831"
+
+/*
+ * CBC parameters held in On-Board I²C EEPROM device.
+ *
+ * Header Format
+ *
+ *  Name     Size   Contents
+ *-------------------------------------------------------------
+ *  Magic     4     0x42 0x43 0x42 0x43  [BCBC]
+ *
+ *
+ *  Length    2     The length of the complete structure, not only this header
+ *
+ *  Eth-MAC   6     Ethernet 0 MAC Address
+ *
+ *  Eth-MAC   6     Ethernet 1 MAC Address
+ *
+ *  ....	 270	Mixed, not needed data
+ *
+ *  HW-Rev	 64	CBC Hardware revision string
+ *
+ *  --- Further values follow, not important for Bootloader ---
+ */
+
+struct  cbc_baseboard_id {
+	u32  magic;
+	u16  length;
+	char mac_addr[HDR_ETH_ALEN];
+	char mac1_addr[HDR_ETH_ALEN];
+	char forget_data[HDR_FORGET_ALEN];
+	char cbc_hwrev[HDR_HWREV_ALEN];
+};
+
+void enable_uart0_pin_mux(void);
+void enable_uart1_pin_mux(void);
+void enable_uart2_pin_mux(void);
+void enable_uart3_pin_mux(void);
+void enable_uart4_pin_mux(void);
+void enable_uart5_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(void);
+#endif
diff --git a/board/bosch/cbc/mux.c b/board/bosch/cbc/mux.c
new file mode 100644
index 0000000000..22fe04e722
--- /dev/null
+++ b/board/bosch/cbc/mux.c
@@ -0,0 +1,171 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * mux.c for am335x-cbc
+ *
+ * Copyright (C) 2022 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+
+#include "board.h"
+
+/* debug uart */
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},		/* UART0_TXD */
+	{-1},
+};
+
+/* rs485 */
+static struct module_pin_mux uart1_pin_mux[] = {
+	{OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART1_RXD */
+	{OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},		/* UART1_TXD */
+	{OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDEN)},	/* TRANSMIT_ENABLE */
+	{-1},
+};
+
+/* rs485 */
+static struct module_pin_mux uart2_pin_mux[] = {
+	{OFFSET(mii1_txclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
+	{OFFSET(mii1_rxclk), (MODE(1) | PULLUDEN)},		/* UART2_TXD */
+	{OFFSET(mii1_rxdv), (MODE(7) | PULLUDEN)},	/* TRANSMIT_ENABLE */
+	{-1},
+};
+
+/* fb bus */
+static struct module_pin_mux uart3_pin_mux[] = {
+	{OFFSET(mii1_rxd3), (MODE(1) | PULLUP_EN | RXACTIVE)},	/* UART3_RXD */
+	{OFFSET(mii1_rxd2), (MODE(1) | PULLUDEN)},		/* UART3_TXD */
+	{-1},
+};
+
+/* µsd */
+static struct module_pin_mux mmc0_pin_mux[] = {
+	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
+	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
+	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
+	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
+	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
+	{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)},	/* MMC0_CD */
+	{-1},
+};
+
+/* emmc */
+static struct module_pin_mux emmc_pin_mux[] = {
+	{OFFSET(gpmc_ad7),  (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT7 */
+	{OFFSET(gpmc_ad6),  (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT6 */
+	{OFFSET(gpmc_ad5),  (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT5 */
+	{OFFSET(gpmc_ad4),  (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT4 */
+	{OFFSET(gpmc_ad3),  (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad2),  (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT2 */
+	{OFFSET(gpmc_ad1),  (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT1 */
+	{OFFSET(gpmc_ad0),  (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT0 */
+	{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CLK */
+	{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CMD */
+	{-1},
+};
+
+/* sd */
+static struct module_pin_mux mmc2_pin_mux[] = {
+	{OFFSET(gpmc_be1n),   (MODE(3) | RXACTIVE | PULLUP_EN)}, /* MMC2_DAT3 */
+	{OFFSET(gpmc_a3),     (MODE(3) | RXACTIVE | PULLUP_EN)}, /* MMC2_DAT2 */
+	{OFFSET(gpmc_a2),     (MODE(3) | RXACTIVE | PULLUP_EN)}, /* MMC2_DAT1 */
+	{OFFSET(gpmc_a1),     (MODE(3) | RXACTIVE | PULLUP_EN)}, /* MMC2_DAT0 */
+	{OFFSET(gpmc_clk),    (MODE(3) | RXACTIVE | PULLUP_EN)}, /* MMC2_CLK */
+	{OFFSET(gpmc_csn3),   (MODE(3) | RXACTIVE | PULLUP_EN)}, /* MMC2_CMD */
+	{OFFSET(mcasp0_axr0), (MODE(4) | RXACTIVE | PULLUP_EN)}, /* MMC2_CD */
+	{OFFSET(mcasp0_fsx),  (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC2_WP */
+	{-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+			PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+			PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
+	{-1},
+};
+
+static struct module_pin_mux i2c1_pin_mux[] = {
+	{OFFSET(uart0_ctsn), (MODE(3) | RXACTIVE |
+			PULLUDEN | SLEWCTRL)},	/* I2C_DATA */
+	{OFFSET(uart0_rtsn), (MODE(3) | RXACTIVE |
+			PULLUDEN | SLEWCTRL)},	/* I2C_SCLK */
+	{-1},
+};
+
+static struct module_pin_mux rmii1_pin_mux[] = {
+	{OFFSET(mii1_crs),     MODE(1) | RXACTIVE}, /* RMII1_CRS_DV */
+	{OFFSET(mii1_rxerr),   MODE(1) | RXACTIVE}, /* RMII1_RXERR */
+	{OFFSET(mii1_txen),    MODE(1)},	    /* RMII1_TXEN */
+	{OFFSET(mii1_txd1),    MODE(1)},	    /* RMII1_TxD1 */
+	{OFFSET(mii1_txd0),    MODE(1)},	    /* RMII1_TXD0 */
+	{OFFSET(mii1_rxd1),    MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
+	{OFFSET(mii1_rxd0),    MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
+	{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
+	{-1},
+};
+
+static struct module_pin_mux rmii2_pin_mux[] = {
+	{OFFSET(gpmc_a0),    MODE(3)},		   /* RMII2_TXEN */
+	{OFFSET(gpmc_a4),    MODE(3)},		   /* RMII2_TXD1 */
+	{OFFSET(gpmc_a5),    MODE(3)},		   /* RMII2_TXD0 */
+	{OFFSET(gpmc_a10),   MODE(3) | RXACTIVE},  /* RMII2_RXD1 */
+	{OFFSET(gpmc_a11),   MODE(3) | RXACTIVE},  /* RMII2_RXD0 */
+	{OFFSET(gpmc_wait0), MODE(3) | RXACTIVE},  /* RMII2_CRS_DV */
+	{OFFSET(gpmc_wpn),   MODE(3) | RXACTIVE},  /* RMII2_RXER */
+	{OFFSET(mii1_col),   MODE(1) | RXACTIVE},  /* RMII2_REFCLK */
+	{-1},
+};
+
+static struct module_pin_mux mdio_pin_mux[] = {
+	{OFFSET(mdio_data),  MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+	{OFFSET(mdio_clk),   MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_uart1_pin_mux(void)
+{
+	configure_module_pin_mux(uart1_pin_mux);
+}
+
+void enable_uart2_pin_mux(void)
+{
+	configure_module_pin_mux(uart2_pin_mux);
+}
+
+void enable_uart3_pin_mux(void)
+{
+	configure_module_pin_mux(uart3_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+	configure_module_pin_mux(i2c1_pin_mux);
+	configure_module_pin_mux(mdio_pin_mux);
+	configure_module_pin_mux(rmii1_pin_mux);
+	configure_module_pin_mux(rmii2_pin_mux);
+	configure_module_pin_mux(mmc0_pin_mux);
+	configure_module_pin_mux(emmc_pin_mux);
+	configure_module_pin_mux(mmc2_pin_mux);
+	configure_module_pin_mux(uart1_pin_mux);
+	configure_module_pin_mux(uart2_pin_mux);
+	configure_module_pin_mux(uart3_pin_mux);
+}
diff --git a/configs/am335x_cbc_defconfig b/configs/am335x_cbc_defconfig
new file mode 100644
index 0000000000..f4cb322c1a
--- /dev/null
+++ b/configs/am335x_cbc_defconfig
@@ -0,0 +1,81 @@
+CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x20000
+CONFIG_DEFAULT_DEVICE_TREE="am335x-cbc"
+CONFIG_AM33XX=y
+CONFIG_TARGET_AM335X_CBC=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL=y
+CONFIG_ENV_OFFSET_REDUND=0x22000
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_TIMESTAMP=y
+CONFIG_BOOTDELAY=1
+CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_ARCH_MISC_INIT=y
+# CONFIG_SPL_BANNER_PRINT is not set
+CONFIG_SPL_I2C=y
+# CONFIG_SPL_NAND_SUPPORT is not set
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_BOOTP_BOOTPATH is not set
+# CONFIG_BOOTP_DNS is not set
+# CONFIG_BOOTP_GATEWAY is not set
+# CONFIG_BOOTP_HOSTNAME is not set
+# CONFIG_BOOTP_SUBNETMASK is not set
+CONFIG_CMD_PMIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+# CONFIG_SPL_BLK is not set
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_GPIO=y
+CONFIG_CLK=y
+CONFIG_CLK_CCF=y
+CONFIG_CLK_TI_AM3_DPLL=y
+CONFIG_CLK_TI_CTRL=y
+CONFIG_CLK_TI_DIVIDER=y
+CONFIG_CLK_TI_GATE=y
+CONFIG_CLK_TI_MUX=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
+# CONFIG_SPL_DM_MMC is not set
+CONFIG_MMC_OMAP_HS=y
+CONFIG_PHY_SMSC=y
+CONFIG_DM_ETH=y
+CONFIG_MII=y
+CONFIG_DRIVER_TI_CPSW=y
+CONFIG_DM_PMIC=y
+# CONFIG_SPL_DM_PMIC is not set
+CONFIG_PMIC_TPS65217=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_OMAP3_SPI=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_EXT4_WRITE=y
+CONFIG_FAT_WRITE=y
+CONFIG_LZO=y
+# CONFIG_EFI_LOADER is not set
diff --git a/include/configs/am335x_cbc.h b/include/configs/am335x_cbc.h
new file mode 100644
index 0000000000..603716d025
--- /dev/null
+++ b/include/configs/am335x_cbc.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+
+#ifndef __CONFIG_AM335X_CBC_H
+#define __CONFIG_AM335X_CBC_H
+
+#include <configs/ti_am335x_common.h>
+
+/* Clock Defines */
+#define V_OSCK				24000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+#if CONFIG_IS_ENABLED(CMD_DHCP)
+# define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na)
+#else
+# define BOOT_TARGET_DHCP(func)
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 2) \
+	func(MMC, mmc, 0) \
+	BOOT_TARGET_DHCP(func)
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	DEFAULT_LINUX_BOOT_ENV \
+	"fdtfile=undefined\0" \
+	"finduuid=part uuid mmc 0:2 uuid\0" \
+	"console=ttyO0,115200n8\0" \
+	"partitions=" \
+		"uuid_disk=${uuid_gpt_disk};" \
+		"name=bootloader,start=384K,size=1792K," \
+			"uuid=${uuid_gpt_bootloader};" \
+		"name=rootfs,start=2688K,size=-,uuid=${uuid_gpt_rootfs}\0" \
+	"optargs=\0" \
+	"findfdt="\
+		"if test $board_name = BC531 || test $board_name = BC831; " \
+		"then setenv fdtfile am335x-cbc-bc-lan-switch.dtb; fi; " \
+		"if test $board_name = BCT531 && test $board_id = 0; then " \
+			"setenv fdtfile am335x-cbc-bct-lan-dual.dtb; fi; " \
+		"if test $board_name = BCT831 && test $board_id = 0; then " \
+			"setenv fdtfile am335x-cbc-bct-lan-dual.dtb; fi; " \
+		"if test $board_name = CBC && test $board_id = 0; then " \
+			"setenv fdtfile am335x-cbc-bct-lan-dual.dtb; fi; " \
+		"if test $board_name = BCT531 && test $board_id != 0; then " \
+			"setenv fdtfile am335x-cbc-bct-lan-switch.dtb; fi; " \
+		"if test $board_name = BCT831 && test $board_id != 0; then " \
+			"setenv fdtfile am335x-cbc-bct-lan-switch.dtb; fi; " \
+		"if test $board_name = CBC && test $board_id != 0; then " \
+			"setenv fdtfile am335x-cbc-bct-lan-switch.dtb; fi; " \
+		"if test $fdtfile = undefined; then " \
+			"echo WARNING: Using default device tree!;" \
+			"if test $board_id = 0; then " \
+			       "setenv fdtfile am335x-cbc-bct-lan-dual.dtb;" \
+			"else" \
+			       "setenv fdtfile am335x-cbc-bct-lan-switch.dtb;" \
+			"fi;" \
+		"fi; \0" \
+	NETARGS \
+	BOOTENV
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* UART0 */
+#define CONFIG_SYS_NS16550_COM2		0x48022000	/* UART1 */
+#define CONFIG_SYS_NS16550_COM3		0x48024000	/* UART2 */
+#define CONFIG_SYS_NS16550_COM4		0x481a6000	/* UART3 */
+#define CONFIG_SYS_NS16550_COM5		0x481a8000	/* UART4 */
+#define CONFIG_SYS_NS16550_COM6		0x481aa000	/* UART5 */
+
+/*
+ * Disable MMC DM for SPL build and can be re-enabled after adding
+ * DM support in SPL
+ */
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_DM_MMC
+#undef CONFIG_TIMER
+#endif
+
+#endif	/* ! __CONFIG_AM335X_CBC_H */
-- 
2.20.1


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