From: Jonathan Cameron <Jonathan.Cameron@huawei.com> To: "Alex Bennée" <alex.bennee@linaro.org> Cc: qemu-devel@nongnu.org, "Marcel Apfelbaum" <marcel@redhat.com>, "Michael S . Tsirkin" <mst@redhat.com>, "Igor Mammedov" <imammedo@redhat.com>, linux-cxl@vger.kernel.org, "Ben Widawsky" <ben.widawsky@intel.com>, "Peter Maydell" <peter.maydell@linaro.org>, linuxarm@huawei.com, "Shameerali Kolothum Thodi" <shameerali.kolothum.thodi@huawei.com>, "Philippe Mathieu-Daudé" <f4bug@amsat.org>, "Saransh Gupta1" <saransh@ibm.com>, "Shreyas Shah" <shreyas.shah@elastics.cloud>, "Chris Browy" <cbrowy@avery-design.com>, "Samarth Saxena" <samarths@cadence.com>, "Dan Williams" <dan.j.williams@intel.com> Subject: Re: [PATCH v6 21/43] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing Date: Fri, 4 Mar 2022 13:30:54 +0000 [thread overview] Message-ID: <20220304133054.000039bd@huawei.com> (raw) In-Reply-To: <871qzkllj1.fsf@linaro.org> On Wed, 02 Mar 2022 10:01:48 +0000 Alex Bennée <alex.bennee@linaro.org> wrote: > Jonathan Cameron <Jonathan.Cameron@huawei.com> writes: > > > From: Ben Widawsky <ben.widawsky@intel.com> > > > > This should introduce no change. Subsequent work will make use of this > > new class member. > > > > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> > > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > > --- > > hw/cxl/cxl-mailbox-utils.c | 3 +++ > > hw/mem/cxl_type3.c | 24 +++++++++--------------- > > include/hw/cxl/cxl_device.h | 29 +++++++++++++++++++++++++++++ > > 3 files changed, 41 insertions(+), 15 deletions(-) > > > > diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c > > index d022711b2a..ccf9c3d794 100644 > > --- a/hw/cxl/cxl-mailbox-utils.c > > +++ b/hw/cxl/cxl-mailbox-utils.c > > @@ -278,6 +278,8 @@ static ret_code cmd_identify_memory_device(struct cxl_cmd *cmd, > > } __attribute__((packed)) *id; > > _Static_assert(sizeof(*id) == 0x43, "Bad identify size"); > > > > + CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, cxl_dstate); > > + CXLType3Class *cvc = CXL_TYPE3_DEV_GET_CLASS(ct3d); > > uint64_t size = cxl_dstate->pmem_size; > > > > if (!QEMU_IS_ALIGNED(size, 256 << 20)) { > > @@ -292,6 +294,7 @@ static ret_code cmd_identify_memory_device(struct cxl_cmd *cmd, > > > > id->total_capacity = size / (256 << 20); > > id->persistent_capacity = size / (256 << 20); > > + id->lsa_size = cvc->get_lsa_size(ct3d); > > > > *len = sizeof(*id); > > return CXL_MBOX_SUCCESS; > > diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c > > index da091157f2..b16262d3cc 100644 > > --- a/hw/mem/cxl_type3.c > > +++ b/hw/mem/cxl_type3.c > > @@ -13,21 +13,6 @@ > > #include "sysemu/hostmem.h" > > #include "hw/cxl/cxl.h" > > > > -typedef struct cxl_type3_dev { > > - /* Private */ > > - PCIDevice parent_obj; > > - > > - /* Properties */ > > - uint64_t size; > > - HostMemoryBackend *hostmem; > > - > > - /* State */ > > - CXLComponentState cxl_cstate; > > - CXLDeviceState cxl_dstate; > > -} CXLType3Dev; > > - > > -#define CT3(obj) OBJECT_CHECK(CXLType3Dev, (obj), TYPE_CXL_TYPE3_DEV) > > - > > If the structure had been in the header to start with it would be easier > to see the changes added for this bit. > Moved.. One other thing below. > > > static void build_dvsecs(CXLType3Dev *ct3d) > > { > > CXLComponentState *cxl_cstate = &ct3d->cxl_cstate; > > @@ -186,10 +171,16 @@ static Property ct3_props[] = { > > DEFINE_PROP_END_OF_LIST(), > > }; > > > > +static uint64_t get_lsa_size(CXLType3Dev *ct3d) > > +{ > > + return 0; > > +} > > + > > static void ct3_class_init(ObjectClass *oc, void *data) > > { > > DeviceClass *dc = DEVICE_CLASS(oc); > > PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc); > > + CXLType3Class *cvc = CXL_TYPE3_DEV_CLASS(oc); > > > > pc->realize = ct3_realize; > > pc->class_id = PCI_CLASS_STORAGE_EXPRESS; > > @@ -201,11 +192,14 @@ static void ct3_class_init(ObjectClass *oc, void *data) > > dc->desc = "CXL PMEM Device (Type 3)"; > > dc->reset = ct3d_reset; > > device_class_set_props(dc, ct3_props); > > + > > + cvc->get_lsa_size = get_lsa_size; > > } > > > > static const TypeInfo ct3d_info = { > > .name = TYPE_CXL_TYPE3_DEV, > > .parent = TYPE_PCI_DEVICE, > > + .class_size = sizeof(struct CXLType3Class), > > .class_init = ct3_class_init, > > .instance_size = sizeof(CXLType3Dev), > > .instance_finalize = ct3_finalize, > > diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h > > index 8102d2a813..ebb391153a 100644 > > --- a/include/hw/cxl/cxl_device.h > > +++ b/include/hw/cxl/cxl_device.h > > @@ -230,4 +230,33 @@ REG64(CXL_MEM_DEV_STS, 0) > > FIELD(CXL_MEM_DEV_STS, MBOX_READY, 4, 1) > > FIELD(CXL_MEM_DEV_STS, RESET_NEEDED, 5, 3) > > > > +typedef struct cxl_type3_dev { > > + /* Private */ > > + PCIDevice parent_obj; > > + > > + /* Properties */ > > + uint64_t size; > > + HostMemoryBackend *hostmem; > > + HostMemoryBackend *lsa; > > + > > + /* State */ > > + CXLComponentState cxl_cstate; > > + CXLDeviceState cxl_dstate; > > +} CXLType3Dev; > > + > > +#ifndef TYPE_CXL_TYPE3_DEV > > +#define TYPE_CXL_TYPE3_DEV "cxl-type3" > > +#endif I'm not sure why the ifndef is needed. Probably a legacy of some refactoring, so I've dropped that and the other definition of this in cxl.h > > + > > +#define CT3(obj) OBJECT_CHECK(CXLType3Dev, (obj), TYPE_CXL_TYPE3_DEV) > > +OBJECT_DECLARE_TYPE(CXLType3Device, CXLType3Class, CXL_TYPE3_DEV) > > + > > +struct CXLType3Class { > > + /* Private */ > > + PCIDeviceClass parent_class; > > + > > + /* public */ > > + uint64_t (*get_lsa_size)(CXLType3Dev *ct3d); > > +}; > > + > > #endif > >
WARNING: multiple messages have this Message-ID (diff)
From: Jonathan Cameron via <qemu-devel@nongnu.org> To: "Alex Bennée" <alex.bennee@linaro.org> Cc: qemu-devel@nongnu.org, "Marcel Apfelbaum" <marcel@redhat.com>, "Michael S . Tsirkin" <mst@redhat.com>, "Igor Mammedov" <imammedo@redhat.com>, linux-cxl@vger.kernel.org, "Ben Widawsky" <ben.widawsky@intel.com>, "Peter Maydell" <peter.maydell@linaro.org>, linuxarm@huawei.com, "Shameerali Kolothum Thodi" <shameerali.kolothum.thodi@huawei.com>, "Philippe Mathieu-Daudé" <f4bug@amsat.org>, "Saransh Gupta1" <saransh@ibm.com>, "Shreyas Shah" <shreyas.shah@elastics.cloud>, "Chris Browy" <cbrowy@avery-design.com>, "Samarth Saxena" <samarths@cadence.com>, "Dan Williams" <dan.j.williams@intel.com> Subject: Re: [PATCH v6 21/43] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing Date: Fri, 4 Mar 2022 13:30:54 +0000 [thread overview] Message-ID: <20220304133054.000039bd@huawei.com> (raw) In-Reply-To: <871qzkllj1.fsf@linaro.org> On Wed, 02 Mar 2022 10:01:48 +0000 Alex Bennée <alex.bennee@linaro.org> wrote: > Jonathan Cameron <Jonathan.Cameron@huawei.com> writes: > > > From: Ben Widawsky <ben.widawsky@intel.com> > > > > This should introduce no change. Subsequent work will make use of this > > new class member. > > > > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> > > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > > --- > > hw/cxl/cxl-mailbox-utils.c | 3 +++ > > hw/mem/cxl_type3.c | 24 +++++++++--------------- > > include/hw/cxl/cxl_device.h | 29 +++++++++++++++++++++++++++++ > > 3 files changed, 41 insertions(+), 15 deletions(-) > > > > diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c > > index d022711b2a..ccf9c3d794 100644 > > --- a/hw/cxl/cxl-mailbox-utils.c > > +++ b/hw/cxl/cxl-mailbox-utils.c > > @@ -278,6 +278,8 @@ static ret_code cmd_identify_memory_device(struct cxl_cmd *cmd, > > } __attribute__((packed)) *id; > > _Static_assert(sizeof(*id) == 0x43, "Bad identify size"); > > > > + CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, cxl_dstate); > > + CXLType3Class *cvc = CXL_TYPE3_DEV_GET_CLASS(ct3d); > > uint64_t size = cxl_dstate->pmem_size; > > > > if (!QEMU_IS_ALIGNED(size, 256 << 20)) { > > @@ -292,6 +294,7 @@ static ret_code cmd_identify_memory_device(struct cxl_cmd *cmd, > > > > id->total_capacity = size / (256 << 20); > > id->persistent_capacity = size / (256 << 20); > > + id->lsa_size = cvc->get_lsa_size(ct3d); > > > > *len = sizeof(*id); > > return CXL_MBOX_SUCCESS; > > diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c > > index da091157f2..b16262d3cc 100644 > > --- a/hw/mem/cxl_type3.c > > +++ b/hw/mem/cxl_type3.c > > @@ -13,21 +13,6 @@ > > #include "sysemu/hostmem.h" > > #include "hw/cxl/cxl.h" > > > > -typedef struct cxl_type3_dev { > > - /* Private */ > > - PCIDevice parent_obj; > > - > > - /* Properties */ > > - uint64_t size; > > - HostMemoryBackend *hostmem; > > - > > - /* State */ > > - CXLComponentState cxl_cstate; > > - CXLDeviceState cxl_dstate; > > -} CXLType3Dev; > > - > > -#define CT3(obj) OBJECT_CHECK(CXLType3Dev, (obj), TYPE_CXL_TYPE3_DEV) > > - > > If the structure had been in the header to start with it would be easier > to see the changes added for this bit. > Moved.. One other thing below. > > > static void build_dvsecs(CXLType3Dev *ct3d) > > { > > CXLComponentState *cxl_cstate = &ct3d->cxl_cstate; > > @@ -186,10 +171,16 @@ static Property ct3_props[] = { > > DEFINE_PROP_END_OF_LIST(), > > }; > > > > +static uint64_t get_lsa_size(CXLType3Dev *ct3d) > > +{ > > + return 0; > > +} > > + > > static void ct3_class_init(ObjectClass *oc, void *data) > > { > > DeviceClass *dc = DEVICE_CLASS(oc); > > PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc); > > + CXLType3Class *cvc = CXL_TYPE3_DEV_CLASS(oc); > > > > pc->realize = ct3_realize; > > pc->class_id = PCI_CLASS_STORAGE_EXPRESS; > > @@ -201,11 +192,14 @@ static void ct3_class_init(ObjectClass *oc, void *data) > > dc->desc = "CXL PMEM Device (Type 3)"; > > dc->reset = ct3d_reset; > > device_class_set_props(dc, ct3_props); > > + > > + cvc->get_lsa_size = get_lsa_size; > > } > > > > static const TypeInfo ct3d_info = { > > .name = TYPE_CXL_TYPE3_DEV, > > .parent = TYPE_PCI_DEVICE, > > + .class_size = sizeof(struct CXLType3Class), > > .class_init = ct3_class_init, > > .instance_size = sizeof(CXLType3Dev), > > .instance_finalize = ct3_finalize, > > diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h > > index 8102d2a813..ebb391153a 100644 > > --- a/include/hw/cxl/cxl_device.h > > +++ b/include/hw/cxl/cxl_device.h > > @@ -230,4 +230,33 @@ REG64(CXL_MEM_DEV_STS, 0) > > FIELD(CXL_MEM_DEV_STS, MBOX_READY, 4, 1) > > FIELD(CXL_MEM_DEV_STS, RESET_NEEDED, 5, 3) > > > > +typedef struct cxl_type3_dev { > > + /* Private */ > > + PCIDevice parent_obj; > > + > > + /* Properties */ > > + uint64_t size; > > + HostMemoryBackend *hostmem; > > + HostMemoryBackend *lsa; > > + > > + /* State */ > > + CXLComponentState cxl_cstate; > > + CXLDeviceState cxl_dstate; > > +} CXLType3Dev; > > + > > +#ifndef TYPE_CXL_TYPE3_DEV > > +#define TYPE_CXL_TYPE3_DEV "cxl-type3" > > +#endif I'm not sure why the ifndef is needed. Probably a legacy of some refactoring, so I've dropped that and the other definition of this in cxl.h > > + > > +#define CT3(obj) OBJECT_CHECK(CXLType3Dev, (obj), TYPE_CXL_TYPE3_DEV) > > +OBJECT_DECLARE_TYPE(CXLType3Device, CXLType3Class, CXL_TYPE3_DEV) > > + > > +struct CXLType3Class { > > + /* Private */ > > + PCIDeviceClass parent_class; > > + > > + /* public */ > > + uint64_t (*get_lsa_size)(CXLType3Dev *ct3d); > > +}; > > + > > #endif > >
next prev parent reply other threads:[~2022-03-04 13:31 UTC|newest] Thread overview: 152+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-02-11 12:07 [PATCH v6 00/43] CXl 2.0 emulation Support Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-02-11 12:07 ` [PATCH v6 01/43] hw/pci/cxl: Add a CXL component type (interface) Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-02-11 12:07 ` [PATCH v6 02/43] hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5) Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-02-11 12:07 ` [PATCH v6 03/43] MAINTAINERS: Add entry for Compute Express Link Emulation Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-02-11 12:07 ` [PATCH v6 04/43] hw/cxl/device: Introduce a CXL device (8.2.8) Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-02-11 12:07 ` [PATCH v6 05/43] hw/cxl/device: Implement the CAP array (8.2.8.1-2) Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-02-11 12:07 ` [PATCH v6 06/43] hw/cxl/device: Implement basic mailbox (8.2.8.4) Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-03-01 15:32 ` Alex Bennée 2022-03-01 15:32 ` Alex Bennée 2022-03-03 16:31 ` Jonathan Cameron 2022-03-03 16:31 ` Jonathan Cameron via 2022-02-11 12:07 ` [PATCH v6 07/43] hw/cxl/device: Add memory device utilities Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-02-11 12:07 ` [PATCH v6 08/43] hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1) Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-02-11 12:07 ` [PATCH v6 09/43] hw/cxl/device: Timestamp implementation (8.2.9.3) Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-03-01 15:54 ` Alex Bennée 2022-03-01 15:54 ` Alex Bennée 2022-02-11 12:07 ` [PATCH v6 10/43] hw/cxl/device: Add log commands (8.2.9.4) + CEL Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-03-01 17:45 ` Alex Bennée 2022-03-01 17:45 ` Alex Bennée 2022-02-11 12:07 ` [PATCH v6 11/43] hw/pxb: Use a type for realizing expanders Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-02-11 12:07 ` [PATCH v6 12/43] hw/pci/cxl: Create a CXL bus type Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-02-11 12:07 ` [PATCH v6 13/43] cxl: Machine level control on whether CXL support is enabled Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-02-11 12:07 ` [PATCH v6 14/43] hw/pxb: Allow creation of a CXL PXB (host bridge) Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-03-01 17:47 ` Alex Bennée 2022-03-01 17:47 ` Alex Bennée 2022-02-11 12:07 ` [PATCH v6 15/43] qtest/cxl: Introduce initial test for pxb-cxl only Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-03-01 18:00 ` Alex Bennée 2022-03-01 18:00 ` Alex Bennée 2022-02-11 12:07 ` [PATCH v6 16/43] hw/cxl/rp: Add a root port Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-03-01 18:08 ` Alex Bennée 2022-03-01 18:08 ` Alex Bennée 2022-03-03 17:22 ` Jonathan Cameron 2022-03-03 17:22 ` Jonathan Cameron via 2022-02-11 12:07 ` [PATCH v6 17/43] hw/cxl/device: Add a memory device (8.2.8.5) Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-02-11 16:50 ` Jonathan Cameron 2022-02-11 16:50 ` Jonathan Cameron via 2022-02-11 12:07 ` [PATCH v6 18/43] qtests/cxl: Add initial root port and CXL type3 tests Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-03-01 18:11 ` Alex Bennée 2022-03-01 18:11 ` Alex Bennée 2022-03-03 17:53 ` Jonathan Cameron 2022-03-03 17:53 ` Jonathan Cameron via 2022-02-11 12:07 ` [PATCH v6 19/43] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12) Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-03-01 18:17 ` Alex Bennée 2022-03-01 18:17 ` Alex Bennée 2022-03-03 18:07 ` Jonathan Cameron 2022-03-03 18:07 ` Jonathan Cameron via 2022-02-11 12:07 ` [PATCH v6 20/43] hw/cxl/device: Add some trivial commands Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-03-01 18:46 ` Alex Bennée 2022-03-01 18:46 ` Alex Bennée 2022-03-04 13:16 ` Jonathan Cameron 2022-03-04 13:16 ` Jonathan Cameron via 2022-02-11 12:07 ` [PATCH v6 21/43] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-03-02 10:01 ` Alex Bennée 2022-03-02 10:01 ` Alex Bennée 2022-03-04 13:30 ` Jonathan Cameron [this message] 2022-03-04 13:30 ` Jonathan Cameron via 2022-02-11 12:07 ` [PATCH v6 22/43] hw/cxl/device: Implement get/set Label Storage Area (LSA) Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-03-02 10:03 ` Alex Bennée 2022-03-02 10:03 ` Alex Bennée 2022-03-04 14:16 ` Jonathan Cameron 2022-03-04 14:16 ` Jonathan Cameron via 2022-03-04 14:26 ` Jonathan Cameron 2022-03-04 14:26 ` Jonathan Cameron via 2022-02-11 12:07 ` [PATCH v6 23/43] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142) Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-03-02 10:20 ` Alex Bennée 2022-03-02 10:20 ` Alex Bennée 2022-02-11 12:07 ` [PATCH v6 24/43] acpi/cxl: Add _OSC implementation (9.14.2) Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-03-02 12:14 ` Alex Bennée 2022-03-02 12:14 ` Alex Bennée 2022-02-11 12:07 ` [PATCH v6 25/43] acpi/cxl: Create the CEDT (9.14.1) Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-03-02 12:16 ` Alex Bennée 2022-03-02 12:16 ` Alex Bennée 2022-02-11 12:07 ` [PATCH v6 26/43] hw/cxl/component: Add utils for interleave parameter encoding/decoding Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-03-02 12:17 ` Alex Bennée 2022-03-02 12:17 ` Alex Bennée 2022-02-11 12:07 ` [PATCH v6 27/43] hw/cxl/host: Add support for CXL Fixed Memory Windows Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-03-02 6:55 ` Markus Armbruster 2022-03-02 6:55 ` Markus Armbruster 2022-03-04 15:56 ` Jonathan Cameron 2022-03-04 15:56 ` Jonathan Cameron via 2022-03-04 17:13 ` Jonathan Cameron 2022-03-04 17:13 ` Jonathan Cameron via 2022-02-11 12:07 ` [PATCH v6 28/43] acpi/cxl: Introduce CFMWS structures in CEDT Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-03-02 12:18 ` Alex Bennée 2022-03-02 12:18 ` Alex Bennée 2022-02-11 12:07 ` [PATCH v6 29/43] hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxl Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-03-02 13:53 ` Alex Bennée 2022-03-02 13:53 ` Alex Bennée 2022-02-11 12:07 ` [PATCH v6 30/43] pci/pcie_port: Add pci_find_port_by_pn() Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-03-02 16:07 ` Alex Bennée 2022-03-02 16:07 ` Alex Bennée 2022-02-11 12:07 ` [PATCH v6 31/43] CXL/cxl_component: Add cxl_get_hb_cstate() Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-03-02 16:07 ` Alex Bennée 2022-03-02 16:07 ` Alex Bennée 2022-02-11 12:07 ` [PATCH v6 32/43] mem/cxl_type3: Add read and write functions for associated hostmem Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-02-11 12:07 ` [PATCH v6 33/43] cxl/cxl-host: Add memops for CFMWS region Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-02-11 12:07 ` [PATCH v6 34/43] RFC: softmmu/memory: Add ops to memory_region_ram_init_from_file Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-02-11 12:07 ` [PATCH v6 35/43] hw/cxl/component Add a dumb HDM decoder handler Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-02-11 12:07 ` [PATCH v6 36/43] i386/pc: Enable CXL fixed memory windows Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-02-11 12:07 ` [PATCH v6 37/43] tests/acpi: q35: Allow addition of a CXL test Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-02-11 12:07 ` [PATCH v6 38/43] qtests/bios-tables-test: Add a test for CXL emulation Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-02-11 12:07 ` [PATCH v6 39/43] tests/acpi: Add tables " Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-02-11 12:07 ` [PATCH v6 40/43] qtest/cxl: Add more complex test cases with CFMWs Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-02-11 12:07 ` [PATCH v6 41/43] hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-02-11 12:07 ` [PATCH v6 42/43] qtest/cxl: Add aarch64 virt test for CXL Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-02-11 12:07 ` [PATCH v6 43/43] docs/cxl: Add initial Compute eXpress Link (CXL) documentation Jonathan Cameron 2022-02-11 12:07 ` Jonathan Cameron via 2022-02-18 18:17 ` [PATCH v6 00/43] CXl 2.0 emulation Support Jonathan Cameron 2022-02-18 18:17 ` Jonathan Cameron via
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