* [PULL v2 00/21] tcg patch queue
@ 2022-03-04 19:09 Richard Henderson
2022-03-05 18:02 ` Peter Maydell
0 siblings, 1 reply; 2+ messages in thread
From: Richard Henderson @ 2022-03-04 19:09 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Version 2: Drop signed 32-bit guest patches while CI failure examined.
The following changes since commit 3d1fbc59665ff8a5d74b0fd30583044fe99e1117:
Merge remote-tracking branch 'remotes/nvme/tags/nvme-next-pull-request' into staging (2022-03-04 15:31:23 +0000)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220304
for you to fetch changes up to cf320769476c3e2820be2a6280bfa1e15baf396f:
tcg/i386: Implement bitsel for avx512 (2022-03-04 08:50:41 -1000)
----------------------------------------------------------------
Reorder do_constant_folding_cond test to satisfy valgrind.
Fix value of MAX_OPC_PARAM_IARGS.
Add opcodes for vector nand, nor, eqv.
Support vector nand, nor, eqv on PPC and S390X hosts.
Support AVX512VL, AVX512BW, AVX512DQ, and AVX512VBMI2.
----------------------------------------------------------------
Alex Bennée (1):
tcg/optimize: only read val after const check
Richard Henderson (19):
tcg: Add opcodes for vector nand, nor, eqv
tcg/ppc: Implement vector NAND, NOR, EQV
tcg/s390x: Implement vector NAND, NOR, EQV
tcg/i386: Detect AVX512
tcg/i386: Add tcg_out_evex_opc
tcg/i386: Use tcg_can_emit_vec_op in expand_vec_cmp_noinv
tcg/i386: Implement avx512 variable shifts
tcg/i386: Implement avx512 scalar shift
tcg/i386: Implement avx512 immediate sari shift
tcg/i386: Implement avx512 immediate rotate
tcg/i386: Implement avx512 variable rotate
tcg/i386: Support avx512vbmi2 vector shift-double instructions
tcg/i386: Expand vector word rotate as avx512vbmi2 shift-double
tcg/i386: Remove rotls_vec from tcg_target_op_def
tcg/i386: Expand scalar rotate with avx512 insns
tcg/i386: Implement avx512 min/max/abs
tcg/i386: Implement avx512 multiply
tcg/i386: Implement more logical operations for avx512
tcg/i386: Implement bitsel for avx512
Ziqiao Kong (1):
tcg: Set MAX_OPC_PARAM_IARGS to 7
include/qemu/cpuid.h | 20 ++-
include/tcg/tcg-opc.h | 3 +
include/tcg/tcg.h | 5 +-
tcg/aarch64/tcg-target.h | 3 +
tcg/arm/tcg-target.h | 3 +
tcg/i386/tcg-target-con-set.h | 1 +
tcg/i386/tcg-target.h | 17 +-
tcg/i386/tcg-target.opc.h | 3 +
tcg/ppc/tcg-target.h | 3 +
tcg/s390x/tcg-target.h | 3 +
tcg/optimize.c | 20 +--
tcg/tcg-op-vec.c | 27 ++-
tcg/tcg.c | 6 +
tcg/i386/tcg-target.c.inc | 387 +++++++++++++++++++++++++++++++++++-------
tcg/ppc/tcg-target.c.inc | 15 ++
tcg/s390x/tcg-target.c.inc | 17 ++
tcg/tci/tcg-target.c.inc | 2 +-
17 files changed, 441 insertions(+), 94 deletions(-)
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PULL v2 00/21] tcg patch queue
2022-03-04 19:09 [PULL v2 00/21] tcg patch queue Richard Henderson
@ 2022-03-05 18:02 ` Peter Maydell
0 siblings, 0 replies; 2+ messages in thread
From: Peter Maydell @ 2022-03-05 18:02 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Fri, 4 Mar 2022 at 19:09, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Version 2: Drop signed 32-bit guest patches while CI failure examined.
>
>
>
> The following changes since commit 3d1fbc59665ff8a5d74b0fd30583044fe99e1117:
>
> Merge remote-tracking branch 'remotes/nvme/tags/nvme-next-pull-request' into staging (2022-03-04 15:31:23 +0000)
>
> are available in the Git repository at:
>
> https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220304
>
> for you to fetch changes up to cf320769476c3e2820be2a6280bfa1e15baf396f:
>
> tcg/i386: Implement bitsel for avx512 (2022-03-04 08:50:41 -1000)
>
> ----------------------------------------------------------------
> Reorder do_constant_folding_cond test to satisfy valgrind.
> Fix value of MAX_OPC_PARAM_IARGS.
> Add opcodes for vector nand, nor, eqv.
> Support vector nand, nor, eqv on PPC and S390X hosts.
> Support AVX512VL, AVX512BW, AVX512DQ, and AVX512VBMI2.
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.0
for any user-visible changes.
-- PMM
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