* [Intel-gfx] [PATCH v2 0/8] drm/i915: Clean up some dpll stuff
@ 2022-03-07 23:39 Ville Syrjala
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 1/8] drm/i915: Store the /5 target clock in struct dpll on vlv/chv Ville Syrjala
` (16 more replies)
0 siblings, 17 replies; 26+ messages in thread
From: Ville Syrjala @ 2022-03-07 23:39 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Clean up a bunch of struct dpll usage, and a few other
random things around the same area.
v2: Clean up the BXT PLL registers and pimp a bunch of comments
Ville Syrjälä (8):
drm/i915: Store the /5 target clock in struct dpll on vlv/chv
drm/i915: Remove redundant/wrong comments
drm/i915: Clean up bxt/glk PLL registers
drm/i915: Store the m2 divider as a whole in bxt_clk_div
drm/i915: Replace bxt_clk_div with struct dpll
drm/i915: Replace hand rolled bxt vco calculation with
chv_calc_dpll_params()
drm/i915: Populate bxt/glk DPLL clock limits a bit more
drm/i915: Remove struct dp_link_dpll
drivers/gpu/drm/i915/display/g4x_dp.c | 55 ++++-------
drivers/gpu/drm/i915/display/intel_dpll.c | 37 +++-----
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 94 ++++++++-----------
drivers/gpu/drm/i915/gvt/handlers.c | 19 ++--
drivers/gpu/drm/i915/i915_reg.h | 61 ++++++------
5 files changed, 113 insertions(+), 153 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH v2 1/8] drm/i915: Store the /5 target clock in struct dpll on vlv/chv
2022-03-07 23:39 [Intel-gfx] [PATCH v2 0/8] drm/i915: Clean up some dpll stuff Ville Syrjala
@ 2022-03-07 23:39 ` Ville Syrjala
2022-03-09 9:53 ` Jani Nikula
2022-03-09 21:43 ` [Intel-gfx] [PATCH v3 " Ville Syrjala
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 2/8] drm/i915: Remove redundant/wrong comments Ville Syrjala
` (15 subsequent siblings)
16 siblings, 2 replies; 26+ messages in thread
From: Ville Syrjala @ 2022-03-07 23:39 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Unify vlv/chv with earlier platforms so that the sturct dpll::dot
represents the /5 clock frequency (ie. DP symbol rate or HDMI
TMDS rate) rather than the *5 fast clock (/2 of the bitrate).
Makes life a little less confusing to get the same number back
in .dot which we fed into the DPLL algorithm.
v2: Actually just include the 5x in the final P divider
Do the same change to the hand rolled gvt code
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll.c | 19 ++++++++-----------
drivers/gpu/drm/i915/gvt/handlers.c | 4 ++--
2 files changed, 10 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 0ae37fdbf2a5..b3fd94538c44 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -254,12 +254,12 @@ static const struct intel_limit ilk_limits_dual_lvds_100m = {
static const struct intel_limit intel_limits_vlv = {
/*
- * These are the data rate limits (measured in fast clocks)
+ * These are based on the data rate limits (measured in fast clocks)
* since those are the strictest limits we have. The fast
* clock and actual rate limits are more relaxed, so checking
* them would make no difference.
*/
- .dot = { .min = 25000 * 5, .max = 270000 * 5 },
+ .dot = { .min = 25000, .max = 270000 },
.vco = { .min = 4000000, .max = 6000000 },
.n = { .min = 1, .max = 7 },
.m1 = { .min = 2, .max = 3 },
@@ -270,12 +270,12 @@ static const struct intel_limit intel_limits_vlv = {
static const struct intel_limit intel_limits_chv = {
/*
- * These are the data rate limits (measured in fast clocks)
+ * These are based on the data rate limits (measured in fast clocks)
* since those are the strictest limits we have. The fast
* clock and actual rate limits are more relaxed, so checking
* them would make no difference.
*/
- .dot = { .min = 25000 * 5, .max = 540000 * 5},
+ .dot = { .min = 25000, .max = 540000 },
.vco = { .min = 4800000, .max = 6480000 },
.n = { .min = 1, .max = 1 },
.m1 = { .min = 2, .max = 2 },
@@ -337,26 +337,26 @@ int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
int vlv_calc_dpll_params(int refclk, struct dpll *clock)
{
clock->m = clock->m1 * clock->m2;
- clock->p = clock->p1 * clock->p2;
+ clock->p = clock->p1 * clock->p2 * 5;
if (WARN_ON(clock->n == 0 || clock->p == 0))
return 0;
clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
- return clock->dot / 5;
+ return clock->dot;
}
int chv_calc_dpll_params(int refclk, struct dpll *clock)
{
clock->m = clock->m1 * clock->m2;
- clock->p = clock->p1 * clock->p2;
+ clock->p = clock->p1 * clock->p2 * 5;
if (WARN_ON(clock->n == 0 || clock->p == 0))
return 0;
clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),
clock->n << 22);
clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
- return clock->dot / 5;
+ return clock->dot;
}
/*
@@ -659,8 +659,6 @@ vlv_find_best_dpll(const struct intel_limit *limit,
int max_n = min(limit->n.max, refclk / 19200);
bool found = false;
- target *= 5; /* fast clock */
-
memset(best_clock, 0, sizeof(*best_clock));
/* based on hardware requirement, prefer smaller n to precision */
@@ -729,7 +727,6 @@ chv_find_best_dpll(const struct intel_limit *limit,
*/
clock.n = 1;
clock.m1 = 2;
- target *= 5; /* fast clock */
for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
for (clock.p2 = limit->p2.p2_fast;
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 520a7e1942f3..efdd2f3f9d73 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -583,7 +583,7 @@ static u32 bxt_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port)
clock.p1 = (vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch)) & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
clock.p2 = (vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch)) & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
clock.m = clock.m1 * clock.m2;
- clock.p = clock.p1 * clock.p2;
+ clock.p = clock.p1 * clock.p2 * 5;
if (clock.n == 0 || clock.p == 0) {
gvt_dbg_dpy("vgpu-%d PORT_%c PLL has invalid divider\n", vgpu->id, port_name(port));
@@ -593,7 +593,7 @@ static u32 bxt_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port)
clock.vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock.m), clock.n << 22);
clock.dot = DIV_ROUND_CLOSEST(clock.vco, clock.p);
- dp_br = clock.dot / 5;
+ dp_br = clock.dot;
out:
return dp_br;
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH v2 2/8] drm/i915: Remove redundant/wrong comments
2022-03-07 23:39 [Intel-gfx] [PATCH v2 0/8] drm/i915: Clean up some dpll stuff Ville Syrjala
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 1/8] drm/i915: Store the /5 target clock in struct dpll on vlv/chv Ville Syrjala
@ 2022-03-07 23:39 ` Ville Syrjala
2022-03-09 9:50 ` Jani Nikula
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 3/8] drm/i915: Clean up bxt/glk PLL registers Ville Syrjala
` (14 subsequent siblings)
16 siblings, 1 reply; 26+ messages in thread
From: Ville Syrjala @ 2022-03-07 23:39 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Remove the comment specifying the exact formulat for calculating
the DPLL frequency from the *_find_best_dpll() functions. Each
platform variant has its own way to calculate these and we have
the code already to do that. These comments are entirely redundant
and often even wrong so just get rid of them.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll.c | 15 +++++----------
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index b3fd94538c44..f4e5290b86a4 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -425,8 +425,7 @@ i9xx_select_p2_div(const struct intel_limit *limit,
/*
* Returns a set of divisors for the desired target clock with the given
- * refclk, or FALSE. The returned values represent the clock equation:
- * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
+ * refclk, or FALSE.
*
* Target and reference clocks are specified in kHz.
*
@@ -484,8 +483,7 @@ i9xx_find_best_dpll(const struct intel_limit *limit,
/*
* Returns a set of divisors for the desired target clock with the given
- * refclk, or FALSE. The returned values represent the clock equation:
- * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
+ * refclk, or FALSE.
*
* Target and reference clocks are specified in kHz.
*
@@ -541,8 +539,7 @@ pnv_find_best_dpll(const struct intel_limit *limit,
/*
* Returns a set of divisors for the desired target clock with the given
- * refclk, or FALSE. The returned values represent the clock equation:
- * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
+ * refclk, or FALSE.
*
* Target and reference clocks are specified in kHz.
*
@@ -641,8 +638,7 @@ static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
/*
* Returns a set of divisors for the desired target clock with the given
- * refclk, or FALSE. The returned values represent the clock equation:
- * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
+ * refclk, or FALSE.
*/
static bool
vlv_find_best_dpll(const struct intel_limit *limit,
@@ -700,8 +696,7 @@ vlv_find_best_dpll(const struct intel_limit *limit,
/*
* Returns a set of divisors for the desired target clock with the given
- * refclk, or FALSE. The returned values represent the clock equation:
- * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
+ * refclk, or FALSE.
*/
static bool
chv_find_best_dpll(const struct intel_limit *limit,
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH v2 3/8] drm/i915: Clean up bxt/glk PLL registers
2022-03-07 23:39 [Intel-gfx] [PATCH v2 0/8] drm/i915: Clean up some dpll stuff Ville Syrjala
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 1/8] drm/i915: Store the /5 target clock in struct dpll on vlv/chv Ville Syrjala
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 2/8] drm/i915: Remove redundant/wrong comments Ville Syrjala
@ 2022-03-07 23:39 ` Ville Syrjala
2022-03-09 9:22 ` Jani Nikula
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 4/8] drm/i915: Store the m2 divider as a whole in bxt_clk_div Ville Syrjala
` (13 subsequent siblings)
16 siblings, 1 reply; 26+ messages in thread
From: Ville Syrjala @ 2022-03-07 23:39 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Use REG_BIT() & co. for bxt/glk PLL registers.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 32 +++++-----
drivers/gpu/drm/i915/gvt/handlers.c | 15 +++--
drivers/gpu/drm/i915/i915_reg.h | 61 ++++++++++---------
3 files changed, 57 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 4595795d694f..2a88c6fa1f34 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -1898,7 +1898,7 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
/* Write M2 integer */
temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 0));
- temp &= ~PORT_PLL_M2_MASK;
+ temp &= ~PORT_PLL_M2_INT_MASK;
temp |= pll->state.hw_state.pll0;
intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 0), temp);
@@ -2034,7 +2034,7 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
hw_state->pll0 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 0));
- hw_state->pll0 &= PORT_PLL_M2_MASK;
+ hw_state->pll0 &= PORT_PLL_M2_INT_MASK;
hw_state->pll1 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 1));
hw_state->pll1 &= PORT_PLL_N_MASK;
@@ -2200,23 +2200,23 @@ static bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
lanestagger = 0x02;
dpll_hw_state->ebb0 = PORT_PLL_P1(clk_div->p1) | PORT_PLL_P2(clk_div->p2);
- dpll_hw_state->pll0 = clk_div->m2_int;
+ dpll_hw_state->pll0 = PORT_PLL_M2_INT(clk_div->m2_int);
dpll_hw_state->pll1 = PORT_PLL_N(clk_div->n);
- dpll_hw_state->pll2 = clk_div->m2_frac;
+ dpll_hw_state->pll2 = PORT_PLL_M2_FRAC(clk_div->m2_frac);
if (clk_div->m2_frac)
dpll_hw_state->pll3 = PORT_PLL_M2_FRAC_ENABLE;
- dpll_hw_state->pll6 = prop_coef | PORT_PLL_INT_COEFF(int_coef);
- dpll_hw_state->pll6 |= PORT_PLL_GAIN_CTL(gain_ctl);
+ dpll_hw_state->pll6 = PORT_PLL_PROP_COEFF(prop_coef) |
+ PORT_PLL_INT_COEFF(int_coef) |
+ PORT_PLL_GAIN_CTL(gain_ctl);
- dpll_hw_state->pll8 = targ_cnt;
+ dpll_hw_state->pll8 = PORT_PLL_TARGET_CNT(targ_cnt);
- dpll_hw_state->pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
+ dpll_hw_state->pll9 = PORT_PLL_LOCK_THRESHOLD(5);
- dpll_hw_state->pll10 =
- PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT)
- | PORT_PLL_DCO_AMP_OVR_EN_H;
+ dpll_hw_state->pll10 = PORT_PLL_DCO_AMP(15) |
+ PORT_PLL_DCO_AMP_OVR_EN_H;
dpll_hw_state->ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
@@ -2252,12 +2252,12 @@ static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
struct dpll clock;
clock.m1 = 2;
- clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22;
+ clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK, pll_state->pll0) << 22;
if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
- clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK;
- clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
- clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
- clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
+ clock.m2 |= REG_FIELD_GET(PORT_PLL_M2_FRAC_MASK, pll_state->pll2);
+ clock.n = REG_FIELD_GET(PORT_PLL_N_MASK, pll_state->pll1);
+ clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK, pll_state->ebb0);
+ clock.p2 = REG_FIELD_GET(PORT_PLL_P2_MASK, pll_state->ebb0);
return chv_calc_dpll_params(i915->dpll.ref_clks.nssc, &clock);
}
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index efdd2f3f9d73..0ee3ecc83234 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -576,12 +576,17 @@ static u32 bxt_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port)
}
clock.m1 = 2;
- clock.m2 = (vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 0)) & PORT_PLL_M2_MASK) << 22;
+ clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK,
+ vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 0))) << 22;
if (vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 3)) & PORT_PLL_M2_FRAC_ENABLE)
- clock.m2 |= vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 2)) & PORT_PLL_M2_FRAC_MASK;
- clock.n = (vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 1)) & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
- clock.p1 = (vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch)) & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
- clock.p2 = (vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch)) & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
+ clock.m2 |= REG_FIELD_GET(PORT_PLL_M2_FRAC_MASK,
+ vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 2)));
+ clock.n = REG_FIELD_GET(PORT_PLL_N_MASK,
+ vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 1)));
+ clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK,
+ vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch)));
+ clock.p2 = REG_FIELD_GET(PORT_PLL_P2_MASK,
+ vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch)));
clock.m = clock.m1 * clock.m2;
clock.p = clock.p1 * clock.p2 * 5;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 70484f6f2b8b..80be197cd6eb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -644,22 +644,20 @@
#define _PORT_PLL_A 0x46074
#define _PORT_PLL_B 0x46078
#define _PORT_PLL_C 0x4607c
-#define PORT_PLL_ENABLE (1 << 31)
-#define PORT_PLL_LOCK (1 << 30)
-#define PORT_PLL_REF_SEL (1 << 27)
-#define PORT_PLL_POWER_ENABLE (1 << 26)
-#define PORT_PLL_POWER_STATE (1 << 25)
+#define PORT_PLL_ENABLE REG_BIT(31)
+#define PORT_PLL_LOCK REG_BIT(30)
+#define PORT_PLL_REF_SEL REG_BIT(27)
+#define PORT_PLL_POWER_ENABLE REG_BIT(26)
+#define PORT_PLL_POWER_STATE REG_BIT(25)
#define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
#define _PORT_PLL_EBB_0_A 0x162034
#define _PORT_PLL_EBB_0_B 0x6C034
#define _PORT_PLL_EBB_0_C 0x6C340
-#define PORT_PLL_P1_SHIFT 13
-#define PORT_PLL_P1_MASK (0x07 << PORT_PLL_P1_SHIFT)
-#define PORT_PLL_P1(x) ((x) << PORT_PLL_P1_SHIFT)
-#define PORT_PLL_P2_SHIFT 8
-#define PORT_PLL_P2_MASK (0x1f << PORT_PLL_P2_SHIFT)
-#define PORT_PLL_P2(x) ((x) << PORT_PLL_P2_SHIFT)
+#define PORT_PLL_P1_MASK REG_GENMASK(15, 13)
+#define PORT_PLL_P1(p1) REG_FIELD_PREP(PORT_PLL_P1_MASK, (p1))
+#define PORT_PLL_P2_MASK REG_GENMASK(12, 8)
+#define PORT_PLL_P2(p2) REG_FIELD_PREP(PORT_PLL_P2_MASK, (p2))
#define BXT_PORT_PLL_EBB_0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
_PORT_PLL_EBB_0_B, \
_PORT_PLL_EBB_0_C)
@@ -667,8 +665,8 @@
#define _PORT_PLL_EBB_4_A 0x162038
#define _PORT_PLL_EBB_4_B 0x6C038
#define _PORT_PLL_EBB_4_C 0x6C344
-#define PORT_PLL_10BIT_CLK_ENABLE (1 << 13)
-#define PORT_PLL_RECALIBRATE (1 << 14)
+#define PORT_PLL_RECALIBRATE REG_BIT(14)
+#define PORT_PLL_10BIT_CLK_ENABLE REG_BIT(13)
#define BXT_PORT_PLL_EBB_4(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
_PORT_PLL_EBB_4_B, \
_PORT_PLL_EBB_4_C)
@@ -677,31 +675,34 @@
#define _PORT_PLL_0_B 0x6C100
#define _PORT_PLL_0_C 0x6C380
/* PORT_PLL_0_A */
-#define PORT_PLL_M2_MASK 0xFF
+#define PORT_PLL_M2_INT_MASK REG_GENMASK(7, 0)
+#define PORT_PLL_M2_INT(m2_int) REG_FIELD_PREP(PORT_PLL_M2_INT_MASK, (m2_int))
/* PORT_PLL_1_A */
-#define PORT_PLL_N_SHIFT 8
-#define PORT_PLL_N_MASK (0x0F << PORT_PLL_N_SHIFT)
-#define PORT_PLL_N(x) ((x) << PORT_PLL_N_SHIFT)
+#define PORT_PLL_N_MASK REG_GENMASK(11, 8)
+#define PORT_PLL_N(n) REG_FIELD_PREP(PORT_PLL_N_MASK, (n))
/* PORT_PLL_2_A */
-#define PORT_PLL_M2_FRAC_MASK 0x3FFFFF
+#define PORT_PLL_M2_FRAC_MASK REG_GENMASK(21, 0)
+#define PORT_PLL_M2_FRAC(m2_frac) REG_FIELD_PREP(PORT_PLL_M2_FRAC_MASK, (m2_frac))
/* PORT_PLL_3_A */
-#define PORT_PLL_M2_FRAC_ENABLE (1 << 16)
+#define PORT_PLL_M2_FRAC_ENABLE REG_BIT(16)
/* PORT_PLL_6_A */
-#define PORT_PLL_PROP_COEFF_MASK 0xF
-#define PORT_PLL_INT_COEFF_MASK (0x1F << 8)
-#define PORT_PLL_INT_COEFF(x) ((x) << 8)
-#define PORT_PLL_GAIN_CTL_MASK (0x07 << 16)
-#define PORT_PLL_GAIN_CTL(x) ((x) << 16)
+#define PORT_PLL_PROP_COEFF_MASK REG_GENMASK(3, 0)
+#define PORT_PLL_PROP_COEFF(x) REG_FIELD_PREP(PORT_PLL_PROP_COEFF_MASK, (x))
+#define PORT_PLL_INT_COEFF_MASK REG_GENMASK(12, 8)
+#define PORT_PLL_INT_COEFF(x) REG_FIELD_PREP(PORT_PLL_INT_COEFF_MASK, (x))
+#define PORT_PLL_GAIN_CTL_MASK REG_GENMASK(18, 16)
+#define PORT_PLL_GAIN_CTL(x) REG_FIELD_PREP(PORT_PLL_GAIN_CTL_MASK, (x))
/* PORT_PLL_8_A */
-#define PORT_PLL_TARGET_CNT_MASK 0x3FF
+#define PORT_PLL_TARGET_CNT_MASK REG_GENMASK(9, 0)
+#define PORT_PLL_TARGET_CNT(x) REG_FIELD_PREP(PORT_PLL_TARGET_CNT_MASK, (x))
/* PORT_PLL_9_A */
-#define PORT_PLL_LOCK_THRESHOLD_SHIFT 1
-#define PORT_PLL_LOCK_THRESHOLD_MASK (0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT)
+#define PORT_PLL_LOCK_THRESHOLD_MASK REG_GENMASK(3, 1)
+#define PORT_PLL_LOCK_THRESHOLD(x) REG_FIELD_PREP(PORT_PLL_LOCK_THRESHOLD_MASK, (x))
/* PORT_PLL_10_A */
-#define PORT_PLL_DCO_AMP_OVR_EN_H (1 << 27)
+#define PORT_PLL_DCO_AMP_OVR_EN_H REG_BIT(27)
#define PORT_PLL_DCO_AMP_DEFAULT 15
-#define PORT_PLL_DCO_AMP_MASK 0x3c00
-#define PORT_PLL_DCO_AMP(x) ((x) << 10)
+#define PORT_PLL_DCO_AMP_MASK REG_GENMASK(13, 10)
+#define PORT_PLL_DCO_AMP(x) REG_FIELD_PREP(PORT_PLL_DCO_AMP_MASK, (x))
#define _PORT_PLL_BASE(phy, ch) _BXT_PHY_CH(phy, ch, \
_PORT_PLL_0_B, \
_PORT_PLL_0_C)
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH v2 4/8] drm/i915: Store the m2 divider as a whole in bxt_clk_div
2022-03-07 23:39 [Intel-gfx] [PATCH v2 0/8] drm/i915: Clean up some dpll stuff Ville Syrjala
` (2 preceding siblings ...)
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 3/8] drm/i915: Clean up bxt/glk PLL registers Ville Syrjala
@ 2022-03-07 23:39 ` Ville Syrjala
2022-03-09 9:27 ` Jani Nikula
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 5/8] drm/i915: Replace bxt_clk_div with struct dpll Ville Syrjala
` (12 subsequent siblings)
16 siblings, 1 reply; 26+ messages in thread
From: Ville Syrjala @ 2022-03-07 23:39 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Get rid of the pointless m2 int vs. frac split in bxt_clk_div
and just store the whole divider as one.
v2: Document the full divider as a proper decimal number
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 27 +++++++++----------
1 file changed, 13 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 2a88c6fa1f34..ae3c07cc2eaa 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2088,8 +2088,7 @@ struct bxt_clk_div {
int clock;
u32 p1;
u32 p2;
- u32 m2_int;
- u32 m2_frac;
+ u32 m2;
u32 n;
int vco;
@@ -2097,13 +2096,14 @@ struct bxt_clk_div {
/* pre-calculated values for DP linkrates */
static const struct bxt_clk_div bxt_dp_clk_val[] = {
- { .clock = 162000, .p1 = 4, .p2 = 2, .m2_int = 32, .m2_frac = 1677722, .n = 1, },
- { .clock = 270000, .p1 = 4, .p2 = 1, .m2_int = 27, .m2_frac = 0, .n = 1, },
- { .clock = 540000, .p1 = 2, .p2 = 1, .m2_int = 27, .m2_frac = 0, .n = 1, },
- { .clock = 216000, .p1 = 3, .p2 = 2, .m2_int = 32, .m2_frac = 1677722, .n = 1, },
- { .clock = 243000, .p1 = 4, .p2 = 1, .m2_int = 24, .m2_frac = 1258291, .n = 1, },
- { .clock = 324000, .p1 = 4, .p2 = 1, .m2_int = 32, .m2_frac = 1677722, .n = 1, },
- { .clock = 432000, .p1 = 3, .p2 = 1, .m2_int = 32, .m2_frac = 1677722, .n = 1, },
+ /* m2 is .22 binary fixed point */
+ { .clock = 162000, .p1 = 4, .p2 = 2, .n = 1, .m2 = 0x819999a /* 32.4 */ },
+ { .clock = 270000, .p1 = 4, .p2 = 1, .n = 1, .m2 = 0x6c00000 /* 27.0 */ },
+ { .clock = 540000, .p1 = 2, .p2 = 1, .n = 1, .m2 = 0x6c00000 /* 27.0 */ },
+ { .clock = 216000, .p1 = 3, .p2 = 2, .n = 1, .m2 = 0x819999a /* 32.4 */ },
+ { .clock = 243000, .p1 = 4, .p2 = 1, .n = 1, .m2 = 0x6133333 /* 24.3 */ },
+ { .clock = 324000, .p1 = 4, .p2 = 1, .n = 1, .m2 = 0x819999a /* 32.4 */ },
+ { .clock = 432000, .p1 = 3, .p2 = 1, .n = 1, .m2 = 0x819999a /* 32.4 */ },
};
static bool
@@ -2130,8 +2130,7 @@ bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
clk_div->p2 = best_clock.p2;
drm_WARN_ON(&i915->drm, best_clock.m1 != 2);
clk_div->n = best_clock.n;
- clk_div->m2_int = best_clock.m2 >> 22;
- clk_div->m2_frac = best_clock.m2 & ((1 << 22) - 1);
+ clk_div->m2 = best_clock.m2;
clk_div->vco = best_clock.vco;
@@ -2200,11 +2199,11 @@ static bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
lanestagger = 0x02;
dpll_hw_state->ebb0 = PORT_PLL_P1(clk_div->p1) | PORT_PLL_P2(clk_div->p2);
- dpll_hw_state->pll0 = PORT_PLL_M2_INT(clk_div->m2_int);
+ dpll_hw_state->pll0 = PORT_PLL_M2_INT(clk_div->m2 >> 22);
dpll_hw_state->pll1 = PORT_PLL_N(clk_div->n);
- dpll_hw_state->pll2 = PORT_PLL_M2_FRAC(clk_div->m2_frac);
+ dpll_hw_state->pll2 = PORT_PLL_M2_FRAC(clk_div->m2 & 0x3fffff);
- if (clk_div->m2_frac)
+ if (clk_div->m2 & 0x3fffff)
dpll_hw_state->pll3 = PORT_PLL_M2_FRAC_ENABLE;
dpll_hw_state->pll6 = PORT_PLL_PROP_COEFF(prop_coef) |
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH v2 5/8] drm/i915: Replace bxt_clk_div with struct dpll
2022-03-07 23:39 [Intel-gfx] [PATCH v2 0/8] drm/i915: Clean up some dpll stuff Ville Syrjala
` (3 preceding siblings ...)
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 4/8] drm/i915: Store the m2 divider as a whole in bxt_clk_div Ville Syrjala
@ 2022-03-07 23:39 ` Ville Syrjala
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 6/8] drm/i915: Replace hand rolled bxt vco calculation with chv_calc_dpll_params() Ville Syrjala
` (11 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Ville Syrjala @ 2022-03-07 23:39 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
bxt_clk_div is basically the same as struct dpll. Just use the latter.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 50 ++++++-------------
1 file changed, 16 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index ae3c07cc2eaa..4b52086aa9e9 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2083,69 +2083,51 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
return ret;
}
-/* bxt clock parameters */
-struct bxt_clk_div {
- int clock;
- u32 p1;
- u32 p2;
- u32 m2;
- u32 n;
-
- int vco;
-};
-
/* pre-calculated values for DP linkrates */
-static const struct bxt_clk_div bxt_dp_clk_val[] = {
+static const struct dpll bxt_dp_clk_val[] = {
/* m2 is .22 binary fixed point */
- { .clock = 162000, .p1 = 4, .p2 = 2, .n = 1, .m2 = 0x819999a /* 32.4 */ },
- { .clock = 270000, .p1 = 4, .p2 = 1, .n = 1, .m2 = 0x6c00000 /* 27.0 */ },
- { .clock = 540000, .p1 = 2, .p2 = 1, .n = 1, .m2 = 0x6c00000 /* 27.0 */ },
- { .clock = 216000, .p1 = 3, .p2 = 2, .n = 1, .m2 = 0x819999a /* 32.4 */ },
- { .clock = 243000, .p1 = 4, .p2 = 1, .n = 1, .m2 = 0x6133333 /* 24.3 */ },
- { .clock = 324000, .p1 = 4, .p2 = 1, .n = 1, .m2 = 0x819999a /* 32.4 */ },
- { .clock = 432000, .p1 = 3, .p2 = 1, .n = 1, .m2 = 0x819999a /* 32.4 */ },
+ { .dot = 162000, .p1 = 4, .p2 = 2, .n = 1, .m2 = 0x819999a /* 32.4 */ },
+ { .dot = 270000, .p1 = 4, .p2 = 1, .n = 1, .m2 = 0x6c00000 /* 27.0 */ },
+ { .dot = 540000, .p1 = 2, .p2 = 1, .n = 1, .m2 = 0x6c00000 /* 27.0 */ },
+ { .dot = 216000, .p1 = 3, .p2 = 2, .n = 1, .m2 = 0x819999a /* 32.4 */ },
+ { .dot = 243000, .p1 = 4, .p2 = 1, .n = 1, .m2 = 0x6133333 /* 24.3 */ },
+ { .dot = 324000, .p1 = 4, .p2 = 1, .n = 1, .m2 = 0x819999a /* 32.4 */ },
+ { .dot = 432000, .p1 = 3, .p2 = 1, .n = 1, .m2 = 0x819999a /* 32.4 */ },
};
static bool
bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
- struct bxt_clk_div *clk_div)
+ struct dpll *clk_div)
{
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct dpll best_clock;
/* Calculate HDMI div */
/*
* FIXME: tie the following calculation into
* i9xx_crtc_compute_clock
*/
- if (!bxt_find_best_dpll(crtc_state, &best_clock)) {
+ if (!bxt_find_best_dpll(crtc_state, clk_div)) {
drm_dbg(&i915->drm, "no PLL dividers found for clock %d pipe %c\n",
crtc_state->port_clock,
pipe_name(crtc->pipe));
return false;
}
- clk_div->p1 = best_clock.p1;
- clk_div->p2 = best_clock.p2;
- drm_WARN_ON(&i915->drm, best_clock.m1 != 2);
- clk_div->n = best_clock.n;
- clk_div->m2 = best_clock.m2;
-
- clk_div->vco = best_clock.vco;
+ drm_WARN_ON(&i915->drm, clk_div->m1 != 2);
return true;
}
static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state,
- struct bxt_clk_div *clk_div)
+ struct dpll *clk_div)
{
int clock = crtc_state->port_clock;
int i;
*clk_div = bxt_dp_clk_val[0];
for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
- if (bxt_dp_clk_val[i].clock == clock) {
+ if (bxt_dp_clk_val[i].dot == clock) {
*clk_div = bxt_dp_clk_val[i];
break;
}
@@ -2155,7 +2137,7 @@ static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state,
}
static bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
- const struct bxt_clk_div *clk_div)
+ const struct dpll *clk_div)
{
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
struct intel_dpll_hw_state *dpll_hw_state = &crtc_state->dpll_hw_state;
@@ -2227,7 +2209,7 @@ static bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
static bool
bxt_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
{
- struct bxt_clk_div clk_div = {};
+ struct dpll clk_div = {};
bxt_ddi_dp_pll_dividers(crtc_state, &clk_div);
@@ -2237,7 +2219,7 @@ bxt_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
static bool
bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
{
- struct bxt_clk_div clk_div = {};
+ struct dpll clk_div = {};
bxt_ddi_hdmi_pll_dividers(crtc_state, &clk_div);
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH v2 6/8] drm/i915: Replace hand rolled bxt vco calculation with chv_calc_dpll_params()
2022-03-07 23:39 [Intel-gfx] [PATCH v2 0/8] drm/i915: Clean up some dpll stuff Ville Syrjala
` (4 preceding siblings ...)
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 5/8] drm/i915: Replace bxt_clk_div with struct dpll Ville Syrjala
@ 2022-03-07 23:39 ` Ville Syrjala
2022-03-09 9:46 ` Jani Nikula
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 7/8] drm/i915: Populate bxt/glk DPLL clock limits a bit more Ville Syrjala
` (10 subsequent siblings)
16 siblings, 1 reply; 26+ messages in thread
From: Ville Syrjala @ 2022-03-07 23:39 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Use chv_calc_dpll_params() to calculate the BXT DP DPLL VCO
frequency.
We need to add the m1 divider into bxt_dp_clk_val[] for this to work.
v2: Make the WARN_ON() sensible
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 23 +++++++++++--------
1 file changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 4b52086aa9e9..b7071da4b7e5 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2086,13 +2086,13 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
/* pre-calculated values for DP linkrates */
static const struct dpll bxt_dp_clk_val[] = {
/* m2 is .22 binary fixed point */
- { .dot = 162000, .p1 = 4, .p2 = 2, .n = 1, .m2 = 0x819999a /* 32.4 */ },
- { .dot = 270000, .p1 = 4, .p2 = 1, .n = 1, .m2 = 0x6c00000 /* 27.0 */ },
- { .dot = 540000, .p1 = 2, .p2 = 1, .n = 1, .m2 = 0x6c00000 /* 27.0 */ },
- { .dot = 216000, .p1 = 3, .p2 = 2, .n = 1, .m2 = 0x819999a /* 32.4 */ },
- { .dot = 243000, .p1 = 4, .p2 = 1, .n = 1, .m2 = 0x6133333 /* 24.3 */ },
- { .dot = 324000, .p1 = 4, .p2 = 1, .n = 1, .m2 = 0x819999a /* 32.4 */ },
- { .dot = 432000, .p1 = 3, .p2 = 1, .n = 1, .m2 = 0x819999a /* 32.4 */ },
+ { .dot = 162000, .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },
+ { .dot = 270000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 /* 27.0 */ },
+ { .dot = 540000, .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 /* 27.0 */ },
+ { .dot = 216000, .p1 = 3, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },
+ { .dot = 243000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6133333 /* 24.3 */ },
+ { .dot = 324000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },
+ { .dot = 432000, .p1 = 3, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },
};
static bool
@@ -2122,18 +2122,21 @@ bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state,
struct dpll *clk_div)
{
- int clock = crtc_state->port_clock;
+ struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
int i;
*clk_div = bxt_dp_clk_val[0];
for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
- if (bxt_dp_clk_val[i].dot == clock) {
+ if (crtc_state->port_clock == bxt_dp_clk_val[i].dot) {
*clk_div = bxt_dp_clk_val[i];
break;
}
}
- clk_div->vco = clock * 10 / 2 * clk_div->p1 * clk_div->p2;
+ chv_calc_dpll_params(i915->dpll.ref_clks.nssc, clk_div);
+
+ drm_WARN_ON(&i915->drm, clk_div->vco == 0 ||
+ clk_div->dot != crtc_state->port_clock);
}
static bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH v2 7/8] drm/i915: Populate bxt/glk DPLL clock limits a bit more
2022-03-07 23:39 [Intel-gfx] [PATCH v2 0/8] drm/i915: Clean up some dpll stuff Ville Syrjala
` (5 preceding siblings ...)
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 6/8] drm/i915: Replace hand rolled bxt vco calculation with chv_calc_dpll_params() Ville Syrjala
@ 2022-03-07 23:39 ` Ville Syrjala
2022-03-09 9:30 ` Jani Nikula
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 8/8] drm/i915: Remove struct dp_link_dpll Ville Syrjala
` (9 subsequent siblings)
16 siblings, 1 reply; 26+ messages in thread
From: Ville Syrjala @ 2022-03-07 23:39 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Set the bxt/glk DPLL min dotclock to 25MHz (HDMI minimum)
and the max to 594 MHz (HDMI max). The supported DP frequencies
(162MHz-540MHz) fit within the same range.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index f4e5290b86a4..7377f1f009ba 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -285,8 +285,7 @@ static const struct intel_limit intel_limits_chv = {
};
static const struct intel_limit intel_limits_bxt = {
- /* FIXME: find real dot limits */
- .dot = { .min = 0, .max = INT_MAX },
+ .dot = { .min = 25000, .max = 594000 },
.vco = { .min = 4800000, .max = 6700000 },
.n = { .min = 1, .max = 1 },
.m1 = { .min = 2, .max = 2 },
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH v2 8/8] drm/i915: Remove struct dp_link_dpll
2022-03-07 23:39 [Intel-gfx] [PATCH v2 0/8] drm/i915: Clean up some dpll stuff Ville Syrjala
` (6 preceding siblings ...)
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 7/8] drm/i915: Populate bxt/glk DPLL clock limits a bit more Ville Syrjala
@ 2022-03-07 23:39 ` Ville Syrjala
2022-03-09 9:34 ` Jani Nikula
2022-03-07 23:50 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Clean up some dpll stuff (rev3) Patchwork
` (8 subsequent siblings)
16 siblings, 1 reply; 26+ messages in thread
From: Ville Syrjala @ 2022-03-07 23:39 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
struct dp_link_dpll is a pointless wrapper around struct dpll.
Just store the desired link rate into struct dpll::dot and
we're done.
v2: Document the full divider as a proper decimal number on chv
Nuke bogus eDP 1.4 comments for chv while at it
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/g4x_dp.c | 55 +++++++++------------------
1 file changed, 17 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
index 22345051e667..8e1338678d91 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -24,58 +24,37 @@
#include "intel_pps.h"
#include "vlv_sideband.h"
-struct dp_link_dpll {
- int clock;
- struct dpll dpll;
+static const struct dpll g4x_dpll[] = {
+ { .dot = 162000, .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8, },
+ { .dot = 270000, .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2, },
};
-static const struct dp_link_dpll g4x_dpll[] = {
- { 162000,
- { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
- { 270000,
- { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
+static const struct dpll pch_dpll[] = {
+ { .dot = 162000, .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9, },
+ { .dot = 270000, .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8, },
};
-static const struct dp_link_dpll pch_dpll[] = {
- { 162000,
- { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
- { 270000,
- { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
+static const struct dpll vlv_dpll[] = {
+ { .dot = 162000, .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81, },
+ { .dot = 270000, .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27, },
};
-static const struct dp_link_dpll vlv_dpll[] = {
- { 162000,
- { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
- { 270000,
- { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
-};
-
-/*
- * CHV supports eDP 1.4 that have more link rates.
- * Below only provides the fixed rate but exclude variable rate.
- */
-static const struct dp_link_dpll chv_dpll[] = {
- /*
- * CHV requires to program fractional division for m2.
- * m2 is stored in fixed point format using formula below
- * (m2_int << 22) | m2_fraction
- */
- { 162000, /* m2_int = 32, m2_fraction = 1677722 */
- { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
- { 270000, /* m2_int = 27, m2_fraction = 0 */
- { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
+static const struct dpll chv_dpll[] = {
+ /* m2 is .22 binary fixed point */
+ { .dot = 162000, .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },
+ { .dot = 270000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 /* 27.0 */ },
};
const struct dpll *vlv_get_dpll(struct drm_i915_private *i915)
{
- return IS_CHERRYVIEW(i915) ? &chv_dpll[0].dpll : &vlv_dpll[0].dpll;
+ return IS_CHERRYVIEW(i915) ? &chv_dpll[0] : &vlv_dpll[0];
}
void g4x_dp_set_clock(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- const struct dp_link_dpll *divisor = NULL;
+ const struct dpll *divisor = NULL;
int i, count = 0;
if (IS_G4X(dev_priv)) {
@@ -94,8 +73,8 @@ void g4x_dp_set_clock(struct intel_encoder *encoder,
if (divisor && count) {
for (i = 0; i < count; i++) {
- if (pipe_config->port_clock == divisor[i].clock) {
- pipe_config->dpll = divisor[i].dpll;
+ if (pipe_config->port_clock == divisor[i].dot) {
+ pipe_config->dpll = divisor[i];
pipe_config->clock_set = true;
break;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Clean up some dpll stuff (rev3)
2022-03-07 23:39 [Intel-gfx] [PATCH v2 0/8] drm/i915: Clean up some dpll stuff Ville Syrjala
` (7 preceding siblings ...)
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 8/8] drm/i915: Remove struct dp_link_dpll Ville Syrjala
@ 2022-03-07 23:50 ` Patchwork
2022-03-08 13:31 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
` (7 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2022-03-07 23:50 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Clean up some dpll stuff (rev3)
URL : https://patchwork.freedesktop.org/series/100899/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 26+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Clean up some dpll stuff (rev3)
2022-03-07 23:39 [Intel-gfx] [PATCH v2 0/8] drm/i915: Clean up some dpll stuff Ville Syrjala
` (8 preceding siblings ...)
2022-03-07 23:50 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Clean up some dpll stuff (rev3) Patchwork
@ 2022-03-08 13:31 ` Patchwork
2022-03-09 2:48 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Clean up some dpll stuff (rev4) Patchwork
` (6 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2022-03-08 13:31 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 22007 bytes --]
== Series Details ==
Series: drm/i915: Clean up some dpll stuff (rev3)
URL : https://patchwork.freedesktop.org/series/100899/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11334 -> Patchwork_22508
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_22508 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22508, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/index.html
Participating hosts (44 -> 46)
------------------------------
Additional (5): fi-cml-u2 fi-skl-guc fi-icl-u2 bat-jsl-2 fi-bsw-nick
Missing (3): fi-bsw-cyan fi-bdw-samus bat-dg1-5
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22508:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@gt_timelines:
- fi-cml-u2: NOTRUN -> [INCOMPLETE][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/fi-cml-u2/igt@i915_selftest@live@gt_timelines.html
* igt@runner@aborted:
- fi-bsw-n3050: NOTRUN -> [FAIL][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/fi-bsw-n3050/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_22508 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2: NOTRUN -> [SKIP][3] ([fdo#109315]) +17 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/fi-icl-u2/igt@amdgpu/amd_cs_nop@fork-gfx0.html
* igt@core_hotunplug@unbind-rebind:
- fi-tgl-1115g4: [PASS][4] -> [DMESG-WARN][5] ([i915#4002])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11334/fi-tgl-1115g4/igt@core_hotunplug@unbind-rebind.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/fi-tgl-1115g4/igt@core_hotunplug@unbind-rebind.html
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-cml-u2: NOTRUN -> [SKIP][6] ([i915#1208]) +1 similar issue
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/fi-cml-u2/igt@gem_exec_fence@basic-busy@bcs0.html
* igt@gem_flink_basic@bad-flink:
- fi-skl-6600u: [PASS][7] -> [FAIL][8] ([i915#4547])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11334/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html
* igt@gem_huc_copy@huc-copy:
- fi-icl-u2: NOTRUN -> [SKIP][9] ([i915#2190])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/fi-icl-u2/igt@gem_huc_copy@huc-copy.html
- fi-cml-u2: NOTRUN -> [SKIP][10] ([i915#2190])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/fi-cml-u2/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2: NOTRUN -> [SKIP][11] ([i915#4613]) +3 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/fi-icl-u2/igt@gem_lmem_swapping@parallel-random-engines.html
- fi-cml-u2: NOTRUN -> [SKIP][12] ([i915#4613]) +3 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/fi-cml-u2/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_lmem_swapping@random-engines:
- fi-skl-guc: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4613]) +3 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/fi-skl-guc/igt@gem_lmem_swapping@random-engines.html
* igt@gem_lmem_swapping@verify-random:
- fi-bsw-nick: NOTRUN -> [SKIP][14] ([fdo#109271]) +67 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/fi-bsw-nick/igt@gem_lmem_swapping@verify-random.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-skl-guc: NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) +8 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/fi-skl-guc/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-cml-u2: NOTRUN -> [SKIP][16] ([fdo#109284] / [fdo#111827]) +8 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/fi-cml-u2/igt@kms_chamelium@dp-hpd-fast.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: NOTRUN -> [SKIP][17] ([fdo#111827]) +8 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_chamelium@vga-edid-read:
- fi-bsw-nick: NOTRUN -> [SKIP][18] ([fdo#109271] / [fdo#111827]) +8 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/fi-bsw-nick/igt@kms_chamelium@vga-edid-read.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-icl-u2: NOTRUN -> [SKIP][19] ([fdo#109278]) +2 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-cml-u2: NOTRUN -> [SKIP][20] ([fdo#109278]) +1 similar issue
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/fi-cml-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-cml-u2: NOTRUN -> [SKIP][21] ([fdo#109285])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/fi-cml-u2/igt@kms_force_connector_basic@force-load-detect.html
- fi-icl-u2: NOTRUN -> [SKIP][22] ([fdo#109285])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/fi-icl-u2/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-cml-u2: NOTRUN -> [SKIP][23] ([fdo#109278] / [i915#533])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/fi-cml-u2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
- fi-skl-guc: NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#533])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/fi-skl-guc/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_psr@primary_mmap_gtt:
- fi-skl-guc: NOTRUN -> [SKIP][25] ([fdo#109271]) +28 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/fi-skl-guc/igt@kms_psr@primary_mmap_gtt.html
* igt@prime_vgem@basic-userptr:
- fi-cml-u2: NOTRUN -> [SKIP][26] ([i915#3301])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/fi-cml-u2/igt@prime_vgem@basic-userptr.html
- fi-icl-u2: NOTRUN -> [SKIP][27] ([i915#3301])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/fi-icl-u2/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-glk-j4005: NOTRUN -> [FAIL][28] ([i915#5257] / [k.org#202321])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/fi-glk-j4005/igt@runner@aborted.html
- fi-bdw-5557u: NOTRUN -> [FAIL][29] ([i915#2426] / [i915#4312])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/fi-bdw-5557u/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_eio@unwedge-stress:
- {shard-tglu}: [TIMEOUT][30] ([i915#3063] / [i915#3648]) -> [PASS][31]
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11334/shard-tglu-4/igt@gem_eio@unwedge-stress.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/shard-tglu-4/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_suspend@basic-s3@smem:
- fi-bdw-5557u: [INCOMPLETE][32] ([i915#146]) -> [PASS][33]
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11334/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3@smem.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3@smem.html
* igt@i915_pm_rps@basic-api:
- bat-dg1-6: [FAIL][34] ([i915#4032]) -> ([PASS][35], [PASS][36])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11334/bat-dg1-6/igt@i915_pm_rps@basic-api.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/bat-dg1-6/igt@i915_pm_rps@basic-api.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/bat-dg1-6/igt@i915_pm_rps@basic-api.html
- fi-tgl-1115g4: [DMESG-WARN][37] ([i915#4002]) -> [PASS][38] +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11334/fi-tgl-1115g4/igt@i915_pm_rps@basic-api.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/fi-tgl-1115g4/igt@i915_pm_rps@basic-api.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [DMESG-FAIL][39] ([i915#4957]) -> ([PASS][40], [PASS][41])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11334/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@reset:
- {bat-rpls-2}: [DMESG-FAIL][42] ([i915#4983]) -> [PASS][43]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11334/bat-rpls-2/igt@i915_selftest@live@reset.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/bat-rpls-2/igt@i915_selftest@live@reset.html
* igt@kms_big_fb@linear-16bpp-rotate-0:
- {shard-tglu}: [DMESG-WARN][44] ([i915#402]) -> [PASS][45]
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11334/shard-tglu-6/igt@kms_big_fb@linear-16bpp-rotate-0.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/shard-tglu-5/igt@kms_big_fb@linear-16bpp-rotate-0.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-180:
- {shard-dg1}: [DMESG-WARN][46] ([i915#3891] / [i915#4935]) -> [PASS][47]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11334/shard-dg1-12/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/shard-dg1-13/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
* igt@kms_busy@basic@modeset:
- {bat-adlp-6}: [DMESG-WARN][48] ([i915#3576]) -> [PASS][49] +1 similar issue
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11334/bat-adlp-6/igt@kms_busy@basic@modeset.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/bat-adlp-6/igt@kms_busy@basic@modeset.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-ytiled:
- {shard-rkl}: [SKIP][50] ([i915#4098]) -> [PASS][51]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11334/shard-rkl-4/igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-ytiled.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/shard-rkl-6/igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-ytiled.html
* igt@kms_flip@basic-flip-vs-wf_vblank@b-dsi1:
- {fi-tgl-dsi}: [FAIL][52] ([i915#2122]) -> [PASS][53]
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11334/fi-tgl-dsi/igt@kms_flip@basic-flip-vs-wf_vblank@b-dsi1.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/fi-tgl-dsi/igt@kms_flip@basic-flip-vs-wf_vblank@b-dsi1.html
#### Warnings ####
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770: [INCOMPLETE][54] ([i915#4785]) -> [INCOMPLETE][55] ([i915#3303])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11334/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112022]: https://bugs.freedesktop.org/show_bug.cgi?id=112022
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1187]: https://gitlab.freedesktop.org/drm/intel/issues/1187
[i915#1208]: https://gitlab.freedesktop.org/drm/intel/issues/1208
[i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
[i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3319]: https://gitlab.freedesktop.org/drm/intel/issues/3319
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3464]: https://gitlab.freedesktop.org/drm/intel/issues/3464
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3580]: https://gitlab.freedesktop.org/drm/intel/issues/3580
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3648]: https://gitlab.freedesktop.org/drm/intel/issues/3648
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3719]: https://gitlab.freedesktop.org/drm/intel/issues/3719
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3828]: https://gitlab.freedesktop.org/drm/intel/issues/3828
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3891]: https://gitlab.freedesktop.org/drm/intel/issues/3891
[i915#4002]: https://gitlab.freedesktop.org/drm/intel/issues/4002
[i915#4016]: https://gitlab.freedesktop.org/drm/intel/issues/4016
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#4032]: https://gitlab.freedesktop.org/drm/intel/issues/4032
[i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4278]: https://gitlab.freedesktop.org/drm/intel/issues/4278
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4807]: https://gitlab.freedesktop.org/drm/intel/issues/4807
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4842]: https://gitlab.freedesktop.org/drm/intel/issues/4842
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4853]: https://gitlab.freedesktop.org/drm/intel/issues/4853
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4877]: https://gitlab.freedesktop.org/drm/intel/issues/4877
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4886]: https://gitlab.freedesktop.org/drm/intel/issues/4886
[i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893
[i915#4935]: https://gitlab.freedesktop.org/drm/intel/issues/4935
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5076]: https://gitlab.freedesktop.org/drm/intel/issues/5076
[i915#5098]: https://gitlab.freedesktop.org/drm/intel/issues/5098
[i915#5127]: https://gitlab.freedesktop.org/drm/intel/issues/5127
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Build changes
-------------
* Linux: CI_DRM_11334 -> Patchwork_22508
CI-20190529: 20190529
CI_DRM_11334: e7af229f52672104f4b170304c80e2d6849a2489 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6367: f8eac64564b12326721f1d5bea692bde4fe1ef15 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22508: f11a71f39000212623c0797897e3d3d2e21228b6 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f11a71f39000 drm/i915: Remove struct dp_link_dpll
c814d8a61ace drm/i915: Populate bxt/glk DPLL clock limits a bit more
87bbf9ba3795 drm/i915: Replace hand rolled bxt vco calculation with chv_calc_dpll_params()
24abb66186d6 drm/i915: Replace bxt_clk_div with struct dpll
ad5d1abd6c5b drm/i915: Store the m2 divider as a whole in bxt_clk_div
8589fa15d9b9 drm/i915: Clean up bxt/glk PLL registers
cc4ac797963e drm/i915: Remove redundant/wrong comments
ee79022d3faa drm/i915: Store the /5 target clock in struct dpll on vlv/chv
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22508/index.html
[-- Attachment #2: Type: text/html, Size: 18023 bytes --]
^ permalink raw reply [flat|nested] 26+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Clean up some dpll stuff (rev4)
2022-03-07 23:39 [Intel-gfx] [PATCH v2 0/8] drm/i915: Clean up some dpll stuff Ville Syrjala
` (9 preceding siblings ...)
2022-03-08 13:31 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2022-03-09 2:48 ` Patchwork
2022-03-09 3:22 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
` (5 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2022-03-09 2:48 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Clean up some dpll stuff (rev4)
URL : https://patchwork.freedesktop.org/series/100899/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 26+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Clean up some dpll stuff (rev4)
2022-03-07 23:39 [Intel-gfx] [PATCH v2 0/8] drm/i915: Clean up some dpll stuff Ville Syrjala
` (10 preceding siblings ...)
2022-03-09 2:48 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Clean up some dpll stuff (rev4) Patchwork
@ 2022-03-09 3:22 ` Patchwork
2022-03-09 18:23 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Clean up some dpll stuff (rev5) Patchwork
` (4 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2022-03-09 3:22 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 10185 bytes --]
== Series Details ==
Series: drm/i915: Clean up some dpll stuff (rev4)
URL : https://patchwork.freedesktop.org/series/100899/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11338 -> Patchwork_22519
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_22519 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22519, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22519/index.html
Participating hosts (46 -> 42)
------------------------------
Additional (1): bat-dg1-6
Missing (5): shard-tglu fi-tgl-1115g4 fi-bsw-cyan fi-ctg-p8600 fi-pnv-d510
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22519:
### IGT changes ###
#### Possible regressions ####
* igt@fbdev@read:
- fi-icl-u2: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11338/fi-icl-u2/igt@fbdev@read.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22519/fi-icl-u2/igt@fbdev@read.html
* igt@runner@aborted:
- fi-bsw-n3050: NOTRUN -> [FAIL][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22519/fi-bsw-n3050/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_22519 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_gttfill@basic:
- bat-dg1-6: NOTRUN -> [SKIP][4] ([i915#4086])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22519/bat-dg1-6/igt@gem_exec_gttfill@basic.html
* igt@gem_flink_basic@bad-flink:
- fi-skl-6600u: NOTRUN -> [INCOMPLETE][5] ([i915#4547])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22519/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html
* igt@gem_mmap@basic:
- bat-dg1-6: NOTRUN -> [SKIP][6] ([i915#4083])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22519/bat-dg1-6/igt@gem_mmap@basic.html
* igt@gem_tiled_blits@basic:
- bat-dg1-6: NOTRUN -> [SKIP][7] ([i915#4077]) +2 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22519/bat-dg1-6/igt@gem_tiled_blits@basic.html
* igt@gem_tiled_pread_basic:
- bat-dg1-6: NOTRUN -> [SKIP][8] ([i915#4079]) +1 similar issue
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22519/bat-dg1-6/igt@gem_tiled_pread_basic.html
* igt@i915_pm_backlight@basic-brightness:
- bat-dg1-6: NOTRUN -> [SKIP][9] ([i915#1155])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22519/bat-dg1-6/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_pm_rps@basic-api:
- bat-dg1-6: NOTRUN -> [FAIL][10] ([i915#4032])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22519/bat-dg1-6/igt@i915_pm_rps@basic-api.html
* igt@i915_selftest@live@gt_engines:
- bat-dg1-5: [PASS][11] -> [INCOMPLETE][12] ([i915#4418])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11338/bat-dg1-5/igt@i915_selftest@live@gt_engines.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22519/bat-dg1-5/igt@i915_selftest@live@gt_engines.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: NOTRUN -> [DMESG-FAIL][13] ([i915#4494] / [i915#4957])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22519/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
* igt@kms_addfb_basic@addfb25-x-tiled-legacy:
- bat-dg1-6: NOTRUN -> [SKIP][14] ([i915#4212]) +7 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22519/bat-dg1-6/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg1-6: NOTRUN -> [SKIP][15] ([i915#4215])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22519/bat-dg1-6/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_chamelium@hdmi-edid-read:
- bat-dg1-6: NOTRUN -> [SKIP][16] ([fdo#111827]) +8 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22519/bat-dg1-6/igt@kms_chamelium@hdmi-edid-read.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- bat-dg1-6: NOTRUN -> [SKIP][17] ([i915#4103] / [i915#4213]) +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22519/bat-dg1-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-dg1-6: NOTRUN -> [SKIP][18] ([fdo#109285])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22519/bat-dg1-6/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_psr@cursor_plane_move:
- bat-dg1-6: NOTRUN -> [SKIP][19] ([i915#1072] / [i915#4078]) +3 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22519/bat-dg1-6/igt@kms_psr@cursor_plane_move.html
* igt@prime_vgem@basic-fence-flip:
- bat-dg1-6: NOTRUN -> [SKIP][20] ([i915#3708]) +3 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22519/bat-dg1-6/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-gtt:
- bat-dg1-6: NOTRUN -> [SKIP][21] ([i915#3708] / [i915#4077]) +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22519/bat-dg1-6/igt@prime_vgem@basic-gtt.html
* igt@prime_vgem@basic-userptr:
- bat-dg1-6: NOTRUN -> [SKIP][22] ([i915#3708] / [i915#4873])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22519/bat-dg1-6/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-icl-u2: NOTRUN -> [FAIL][23] ([i915#2426] / [i915#3690])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22519/fi-icl-u2/igt@runner@aborted.html
- fi-glk-j4005: NOTRUN -> [FAIL][24] ([i915#5257] / [k.org#202321])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22519/fi-glk-j4005/igt@runner@aborted.html
- bat-dg1-5: NOTRUN -> [FAIL][25] ([i915#4312] / [i915#5257])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22519/bat-dg1-5/igt@runner@aborted.html
- fi-bdw-5557u: NOTRUN -> [FAIL][26] ([i915#2426] / [i915#4312])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22519/fi-bdw-5557u/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3690]: https://gitlab.freedesktop.org/drm/intel/issues/3690
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4032]: https://gitlab.freedesktop.org/drm/intel/issues/4032
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4086]: https://gitlab.freedesktop.org/drm/intel/issues/4086
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4418]: https://gitlab.freedesktop.org/drm/intel/issues/4418
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5127]: https://gitlab.freedesktop.org/drm/intel/issues/5127
[i915#5193]: https://gitlab.freedesktop.org/drm/intel/issues/5193
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Build changes
-------------
* Linux: CI_DRM_11338 -> Patchwork_22519
CI-20190529: 20190529
CI_DRM_11338: 10d23ef3d24468332f37689a99d707e57c4d9a3f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6368: 60e5ffca027b38398c279fba0f5a1b7517aa6061 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22519: 9e960edd06e426a2db60d571bd68bb934d605f4c @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
9e960edd06e4 drm/i915: Remove struct dp_link_dpll
e34846f1debb drm/i915: Populate bxt/glk DPLL clock limits a bit more
ae76f1c7d194 drm/i915: Replace hand rolled bxt vco calculation with chv_calc_dpll_params()
260df2db4bd6 drm/i915: Replace bxt_clk_div with struct dpll
82e532601527 drm/i915: Store the m2 divider as a whole in bxt_clk_div
0281dfc0ba74 drm/i915: Clean up bxt/glk PLL registers
a5a66d2c79c9 drm/i915: Remove redundant/wrong comments
b3b645163a09 drm/i915: Store the /5 target clock in struct dpll on vlv/chv
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22519/index.html
[-- Attachment #2: Type: text/html, Size: 11143 bytes --]
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH v2 3/8] drm/i915: Clean up bxt/glk PLL registers
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 3/8] drm/i915: Clean up bxt/glk PLL registers Ville Syrjala
@ 2022-03-09 9:22 ` Jani Nikula
0 siblings, 0 replies; 26+ messages in thread
From: Jani Nikula @ 2022-03-09 9:22 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Tue, 08 Mar 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use REG_BIT() & co. for bxt/glk PLL registers.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 32 +++++-----
> drivers/gpu/drm/i915/gvt/handlers.c | 15 +++--
> drivers/gpu/drm/i915/i915_reg.h | 61 ++++++++++---------
> 3 files changed, 57 insertions(+), 51 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 4595795d694f..2a88c6fa1f34 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -1898,7 +1898,7 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
>
> /* Write M2 integer */
> temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 0));
> - temp &= ~PORT_PLL_M2_MASK;
> + temp &= ~PORT_PLL_M2_INT_MASK;
> temp |= pll->state.hw_state.pll0;
> intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 0), temp);
>
> @@ -2034,7 +2034,7 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
> hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
>
> hw_state->pll0 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 0));
> - hw_state->pll0 &= PORT_PLL_M2_MASK;
> + hw_state->pll0 &= PORT_PLL_M2_INT_MASK;
>
> hw_state->pll1 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 1));
> hw_state->pll1 &= PORT_PLL_N_MASK;
> @@ -2200,23 +2200,23 @@ static bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
> lanestagger = 0x02;
>
> dpll_hw_state->ebb0 = PORT_PLL_P1(clk_div->p1) | PORT_PLL_P2(clk_div->p2);
> - dpll_hw_state->pll0 = clk_div->m2_int;
> + dpll_hw_state->pll0 = PORT_PLL_M2_INT(clk_div->m2_int);
> dpll_hw_state->pll1 = PORT_PLL_N(clk_div->n);
> - dpll_hw_state->pll2 = clk_div->m2_frac;
> + dpll_hw_state->pll2 = PORT_PLL_M2_FRAC(clk_div->m2_frac);
>
> if (clk_div->m2_frac)
> dpll_hw_state->pll3 = PORT_PLL_M2_FRAC_ENABLE;
>
> - dpll_hw_state->pll6 = prop_coef | PORT_PLL_INT_COEFF(int_coef);
> - dpll_hw_state->pll6 |= PORT_PLL_GAIN_CTL(gain_ctl);
> + dpll_hw_state->pll6 = PORT_PLL_PROP_COEFF(prop_coef) |
> + PORT_PLL_INT_COEFF(int_coef) |
> + PORT_PLL_GAIN_CTL(gain_ctl);
>
> - dpll_hw_state->pll8 = targ_cnt;
> + dpll_hw_state->pll8 = PORT_PLL_TARGET_CNT(targ_cnt);
>
> - dpll_hw_state->pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
> + dpll_hw_state->pll9 = PORT_PLL_LOCK_THRESHOLD(5);
>
> - dpll_hw_state->pll10 =
> - PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT)
> - | PORT_PLL_DCO_AMP_OVR_EN_H;
> + dpll_hw_state->pll10 = PORT_PLL_DCO_AMP(15) |
> + PORT_PLL_DCO_AMP_OVR_EN_H;
>
> dpll_hw_state->ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
>
> @@ -2252,12 +2252,12 @@ static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
> struct dpll clock;
>
> clock.m1 = 2;
> - clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22;
> + clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK, pll_state->pll0) << 22;
> if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
> - clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK;
> - clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
> - clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
> - clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
> + clock.m2 |= REG_FIELD_GET(PORT_PLL_M2_FRAC_MASK, pll_state->pll2);
> + clock.n = REG_FIELD_GET(PORT_PLL_N_MASK, pll_state->pll1);
> + clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK, pll_state->ebb0);
> + clock.p2 = REG_FIELD_GET(PORT_PLL_P2_MASK, pll_state->ebb0);
>
> return chv_calc_dpll_params(i915->dpll.ref_clks.nssc, &clock);
> }
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index efdd2f3f9d73..0ee3ecc83234 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -576,12 +576,17 @@ static u32 bxt_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port)
> }
>
> clock.m1 = 2;
> - clock.m2 = (vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 0)) & PORT_PLL_M2_MASK) << 22;
> + clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK,
> + vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 0))) << 22;
> if (vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 3)) & PORT_PLL_M2_FRAC_ENABLE)
> - clock.m2 |= vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 2)) & PORT_PLL_M2_FRAC_MASK;
> - clock.n = (vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 1)) & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
> - clock.p1 = (vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch)) & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
> - clock.p2 = (vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch)) & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
> + clock.m2 |= REG_FIELD_GET(PORT_PLL_M2_FRAC_MASK,
> + vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 2)));
> + clock.n = REG_FIELD_GET(PORT_PLL_N_MASK,
> + vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 1)));
> + clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK,
> + vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch)));
> + clock.p2 = REG_FIELD_GET(PORT_PLL_P2_MASK,
> + vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch)));
> clock.m = clock.m1 * clock.m2;
> clock.p = clock.p1 * clock.p2 * 5;
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 70484f6f2b8b..80be197cd6eb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -644,22 +644,20 @@
> #define _PORT_PLL_A 0x46074
> #define _PORT_PLL_B 0x46078
> #define _PORT_PLL_C 0x4607c
> -#define PORT_PLL_ENABLE (1 << 31)
> -#define PORT_PLL_LOCK (1 << 30)
> -#define PORT_PLL_REF_SEL (1 << 27)
> -#define PORT_PLL_POWER_ENABLE (1 << 26)
> -#define PORT_PLL_POWER_STATE (1 << 25)
> +#define PORT_PLL_ENABLE REG_BIT(31)
> +#define PORT_PLL_LOCK REG_BIT(30)
> +#define PORT_PLL_REF_SEL REG_BIT(27)
> +#define PORT_PLL_POWER_ENABLE REG_BIT(26)
> +#define PORT_PLL_POWER_STATE REG_BIT(25)
> #define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
>
> #define _PORT_PLL_EBB_0_A 0x162034
> #define _PORT_PLL_EBB_0_B 0x6C034
> #define _PORT_PLL_EBB_0_C 0x6C340
> -#define PORT_PLL_P1_SHIFT 13
> -#define PORT_PLL_P1_MASK (0x07 << PORT_PLL_P1_SHIFT)
> -#define PORT_PLL_P1(x) ((x) << PORT_PLL_P1_SHIFT)
> -#define PORT_PLL_P2_SHIFT 8
> -#define PORT_PLL_P2_MASK (0x1f << PORT_PLL_P2_SHIFT)
> -#define PORT_PLL_P2(x) ((x) << PORT_PLL_P2_SHIFT)
> +#define PORT_PLL_P1_MASK REG_GENMASK(15, 13)
> +#define PORT_PLL_P1(p1) REG_FIELD_PREP(PORT_PLL_P1_MASK, (p1))
> +#define PORT_PLL_P2_MASK REG_GENMASK(12, 8)
> +#define PORT_PLL_P2(p2) REG_FIELD_PREP(PORT_PLL_P2_MASK, (p2))
> #define BXT_PORT_PLL_EBB_0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
> _PORT_PLL_EBB_0_B, \
> _PORT_PLL_EBB_0_C)
> @@ -667,8 +665,8 @@
> #define _PORT_PLL_EBB_4_A 0x162038
> #define _PORT_PLL_EBB_4_B 0x6C038
> #define _PORT_PLL_EBB_4_C 0x6C344
> -#define PORT_PLL_10BIT_CLK_ENABLE (1 << 13)
> -#define PORT_PLL_RECALIBRATE (1 << 14)
> +#define PORT_PLL_RECALIBRATE REG_BIT(14)
> +#define PORT_PLL_10BIT_CLK_ENABLE REG_BIT(13)
> #define BXT_PORT_PLL_EBB_4(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
> _PORT_PLL_EBB_4_B, \
> _PORT_PLL_EBB_4_C)
> @@ -677,31 +675,34 @@
> #define _PORT_PLL_0_B 0x6C100
> #define _PORT_PLL_0_C 0x6C380
> /* PORT_PLL_0_A */
> -#define PORT_PLL_M2_MASK 0xFF
> +#define PORT_PLL_M2_INT_MASK REG_GENMASK(7, 0)
> +#define PORT_PLL_M2_INT(m2_int) REG_FIELD_PREP(PORT_PLL_M2_INT_MASK, (m2_int))
> /* PORT_PLL_1_A */
> -#define PORT_PLL_N_SHIFT 8
> -#define PORT_PLL_N_MASK (0x0F << PORT_PLL_N_SHIFT)
> -#define PORT_PLL_N(x) ((x) << PORT_PLL_N_SHIFT)
> +#define PORT_PLL_N_MASK REG_GENMASK(11, 8)
> +#define PORT_PLL_N(n) REG_FIELD_PREP(PORT_PLL_N_MASK, (n))
> /* PORT_PLL_2_A */
> -#define PORT_PLL_M2_FRAC_MASK 0x3FFFFF
> +#define PORT_PLL_M2_FRAC_MASK REG_GENMASK(21, 0)
> +#define PORT_PLL_M2_FRAC(m2_frac) REG_FIELD_PREP(PORT_PLL_M2_FRAC_MASK, (m2_frac))
> /* PORT_PLL_3_A */
> -#define PORT_PLL_M2_FRAC_ENABLE (1 << 16)
> +#define PORT_PLL_M2_FRAC_ENABLE REG_BIT(16)
> /* PORT_PLL_6_A */
> -#define PORT_PLL_PROP_COEFF_MASK 0xF
> -#define PORT_PLL_INT_COEFF_MASK (0x1F << 8)
> -#define PORT_PLL_INT_COEFF(x) ((x) << 8)
> -#define PORT_PLL_GAIN_CTL_MASK (0x07 << 16)
> -#define PORT_PLL_GAIN_CTL(x) ((x) << 16)
> +#define PORT_PLL_PROP_COEFF_MASK REG_GENMASK(3, 0)
> +#define PORT_PLL_PROP_COEFF(x) REG_FIELD_PREP(PORT_PLL_PROP_COEFF_MASK, (x))
> +#define PORT_PLL_INT_COEFF_MASK REG_GENMASK(12, 8)
> +#define PORT_PLL_INT_COEFF(x) REG_FIELD_PREP(PORT_PLL_INT_COEFF_MASK, (x))
> +#define PORT_PLL_GAIN_CTL_MASK REG_GENMASK(18, 16)
> +#define PORT_PLL_GAIN_CTL(x) REG_FIELD_PREP(PORT_PLL_GAIN_CTL_MASK, (x))
> /* PORT_PLL_8_A */
> -#define PORT_PLL_TARGET_CNT_MASK 0x3FF
> +#define PORT_PLL_TARGET_CNT_MASK REG_GENMASK(9, 0)
> +#define PORT_PLL_TARGET_CNT(x) REG_FIELD_PREP(PORT_PLL_TARGET_CNT_MASK, (x))
> /* PORT_PLL_9_A */
> -#define PORT_PLL_LOCK_THRESHOLD_SHIFT 1
> -#define PORT_PLL_LOCK_THRESHOLD_MASK (0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT)
> +#define PORT_PLL_LOCK_THRESHOLD_MASK REG_GENMASK(3, 1)
> +#define PORT_PLL_LOCK_THRESHOLD(x) REG_FIELD_PREP(PORT_PLL_LOCK_THRESHOLD_MASK, (x))
> /* PORT_PLL_10_A */
> -#define PORT_PLL_DCO_AMP_OVR_EN_H (1 << 27)
> +#define PORT_PLL_DCO_AMP_OVR_EN_H REG_BIT(27)
> #define PORT_PLL_DCO_AMP_DEFAULT 15
> -#define PORT_PLL_DCO_AMP_MASK 0x3c00
> -#define PORT_PLL_DCO_AMP(x) ((x) << 10)
> +#define PORT_PLL_DCO_AMP_MASK REG_GENMASK(13, 10)
> +#define PORT_PLL_DCO_AMP(x) REG_FIELD_PREP(PORT_PLL_DCO_AMP_MASK, (x))
> #define _PORT_PLL_BASE(phy, ch) _BXT_PHY_CH(phy, ch, \
> _PORT_PLL_0_B, \
> _PORT_PLL_0_C)
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH v2 4/8] drm/i915: Store the m2 divider as a whole in bxt_clk_div
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 4/8] drm/i915: Store the m2 divider as a whole in bxt_clk_div Ville Syrjala
@ 2022-03-09 9:27 ` Jani Nikula
0 siblings, 0 replies; 26+ messages in thread
From: Jani Nikula @ 2022-03-09 9:27 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Tue, 08 Mar 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Get rid of the pointless m2 int vs. frac split in bxt_clk_div
> and just store the whole divider as one.
>
> v2: Document the full divider as a proper decimal number
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 27 +++++++++----------
> 1 file changed, 13 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 2a88c6fa1f34..ae3c07cc2eaa 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2088,8 +2088,7 @@ struct bxt_clk_div {
> int clock;
> u32 p1;
> u32 p2;
> - u32 m2_int;
> - u32 m2_frac;
> + u32 m2;
> u32 n;
>
> int vco;
> @@ -2097,13 +2096,14 @@ struct bxt_clk_div {
>
> /* pre-calculated values for DP linkrates */
> static const struct bxt_clk_div bxt_dp_clk_val[] = {
> - { .clock = 162000, .p1 = 4, .p2 = 2, .m2_int = 32, .m2_frac = 1677722, .n = 1, },
> - { .clock = 270000, .p1 = 4, .p2 = 1, .m2_int = 27, .m2_frac = 0, .n = 1, },
> - { .clock = 540000, .p1 = 2, .p2 = 1, .m2_int = 27, .m2_frac = 0, .n = 1, },
> - { .clock = 216000, .p1 = 3, .p2 = 2, .m2_int = 32, .m2_frac = 1677722, .n = 1, },
> - { .clock = 243000, .p1 = 4, .p2 = 1, .m2_int = 24, .m2_frac = 1258291, .n = 1, },
> - { .clock = 324000, .p1 = 4, .p2 = 1, .m2_int = 32, .m2_frac = 1677722, .n = 1, },
> - { .clock = 432000, .p1 = 3, .p2 = 1, .m2_int = 32, .m2_frac = 1677722, .n = 1, },
> + /* m2 is .22 binary fixed point */
> + { .clock = 162000, .p1 = 4, .p2 = 2, .n = 1, .m2 = 0x819999a /* 32.4 */ },
> + { .clock = 270000, .p1 = 4, .p2 = 1, .n = 1, .m2 = 0x6c00000 /* 27.0 */ },
> + { .clock = 540000, .p1 = 2, .p2 = 1, .n = 1, .m2 = 0x6c00000 /* 27.0 */ },
> + { .clock = 216000, .p1 = 3, .p2 = 2, .n = 1, .m2 = 0x819999a /* 32.4 */ },
> + { .clock = 243000, .p1 = 4, .p2 = 1, .n = 1, .m2 = 0x6133333 /* 24.3 */ },
> + { .clock = 324000, .p1 = 4, .p2 = 1, .n = 1, .m2 = 0x819999a /* 32.4 */ },
> + { .clock = 432000, .p1 = 3, .p2 = 1, .n = 1, .m2 = 0x819999a /* 32.4 */ },
> };
>
> static bool
> @@ -2130,8 +2130,7 @@ bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
> clk_div->p2 = best_clock.p2;
> drm_WARN_ON(&i915->drm, best_clock.m1 != 2);
> clk_div->n = best_clock.n;
> - clk_div->m2_int = best_clock.m2 >> 22;
> - clk_div->m2_frac = best_clock.m2 & ((1 << 22) - 1);
> + clk_div->m2 = best_clock.m2;
>
> clk_div->vco = best_clock.vco;
>
> @@ -2200,11 +2199,11 @@ static bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
> lanestagger = 0x02;
>
> dpll_hw_state->ebb0 = PORT_PLL_P1(clk_div->p1) | PORT_PLL_P2(clk_div->p2);
> - dpll_hw_state->pll0 = PORT_PLL_M2_INT(clk_div->m2_int);
> + dpll_hw_state->pll0 = PORT_PLL_M2_INT(clk_div->m2 >> 22);
> dpll_hw_state->pll1 = PORT_PLL_N(clk_div->n);
> - dpll_hw_state->pll2 = PORT_PLL_M2_FRAC(clk_div->m2_frac);
> + dpll_hw_state->pll2 = PORT_PLL_M2_FRAC(clk_div->m2 & 0x3fffff);
>
> - if (clk_div->m2_frac)
> + if (clk_div->m2 & 0x3fffff)
> dpll_hw_state->pll3 = PORT_PLL_M2_FRAC_ENABLE;
>
> dpll_hw_state->pll6 = PORT_PLL_PROP_COEFF(prop_coef) |
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH v2 7/8] drm/i915: Populate bxt/glk DPLL clock limits a bit more
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 7/8] drm/i915: Populate bxt/glk DPLL clock limits a bit more Ville Syrjala
@ 2022-03-09 9:30 ` Jani Nikula
0 siblings, 0 replies; 26+ messages in thread
From: Jani Nikula @ 2022-03-09 9:30 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Tue, 08 Mar 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Set the bxt/glk DPLL min dotclock to 25MHz (HDMI minimum)
> and the max to 594 MHz (HDMI max). The supported DP frequencies
> (162MHz-540MHz) fit within the same range.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dpll.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index f4e5290b86a4..7377f1f009ba 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -285,8 +285,7 @@ static const struct intel_limit intel_limits_chv = {
> };
>
> static const struct intel_limit intel_limits_bxt = {
> - /* FIXME: find real dot limits */
> - .dot = { .min = 0, .max = INT_MAX },
> + .dot = { .min = 25000, .max = 594000 },
> .vco = { .min = 4800000, .max = 6700000 },
> .n = { .min = 1, .max = 1 },
> .m1 = { .min = 2, .max = 2 },
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH v2 8/8] drm/i915: Remove struct dp_link_dpll
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 8/8] drm/i915: Remove struct dp_link_dpll Ville Syrjala
@ 2022-03-09 9:34 ` Jani Nikula
0 siblings, 0 replies; 26+ messages in thread
From: Jani Nikula @ 2022-03-09 9:34 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Tue, 08 Mar 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> struct dp_link_dpll is a pointless wrapper around struct dpll.
> Just store the desired link rate into struct dpll::dot and
> we're done.
>
> v2: Document the full divider as a proper decimal number on chv
> Nuke bogus eDP 1.4 comments for chv while at it
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/g4x_dp.c | 55 +++++++++------------------
> 1 file changed, 17 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
> index 22345051e667..8e1338678d91 100644
> --- a/drivers/gpu/drm/i915/display/g4x_dp.c
> +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
> @@ -24,58 +24,37 @@
> #include "intel_pps.h"
> #include "vlv_sideband.h"
>
> -struct dp_link_dpll {
> - int clock;
> - struct dpll dpll;
> +static const struct dpll g4x_dpll[] = {
> + { .dot = 162000, .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8, },
> + { .dot = 270000, .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2, },
> };
>
> -static const struct dp_link_dpll g4x_dpll[] = {
> - { 162000,
> - { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
> - { 270000,
> - { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
> +static const struct dpll pch_dpll[] = {
> + { .dot = 162000, .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9, },
> + { .dot = 270000, .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8, },
> };
>
> -static const struct dp_link_dpll pch_dpll[] = {
> - { 162000,
> - { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
> - { 270000,
> - { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
> +static const struct dpll vlv_dpll[] = {
> + { .dot = 162000, .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81, },
> + { .dot = 270000, .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27, },
> };
>
> -static const struct dp_link_dpll vlv_dpll[] = {
> - { 162000,
> - { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
> - { 270000,
> - { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
> -};
> -
> -/*
> - * CHV supports eDP 1.4 that have more link rates.
> - * Below only provides the fixed rate but exclude variable rate.
> - */
> -static const struct dp_link_dpll chv_dpll[] = {
> - /*
> - * CHV requires to program fractional division for m2.
> - * m2 is stored in fixed point format using formula below
> - * (m2_int << 22) | m2_fraction
> - */
> - { 162000, /* m2_int = 32, m2_fraction = 1677722 */
> - { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
> - { 270000, /* m2_int = 27, m2_fraction = 0 */
> - { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
> +static const struct dpll chv_dpll[] = {
> + /* m2 is .22 binary fixed point */
> + { .dot = 162000, .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },
> + { .dot = 270000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 /* 27.0 */ },
> };
>
> const struct dpll *vlv_get_dpll(struct drm_i915_private *i915)
> {
> - return IS_CHERRYVIEW(i915) ? &chv_dpll[0].dpll : &vlv_dpll[0].dpll;
> + return IS_CHERRYVIEW(i915) ? &chv_dpll[0] : &vlv_dpll[0];
> }
>
> void g4x_dp_set_clock(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - const struct dp_link_dpll *divisor = NULL;
> + const struct dpll *divisor = NULL;
> int i, count = 0;
>
> if (IS_G4X(dev_priv)) {
> @@ -94,8 +73,8 @@ void g4x_dp_set_clock(struct intel_encoder *encoder,
>
> if (divisor && count) {
> for (i = 0; i < count; i++) {
> - if (pipe_config->port_clock == divisor[i].clock) {
> - pipe_config->dpll = divisor[i].dpll;
> + if (pipe_config->port_clock == divisor[i].dot) {
> + pipe_config->dpll = divisor[i];
> pipe_config->clock_set = true;
> break;
> }
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH v2 6/8] drm/i915: Replace hand rolled bxt vco calculation with chv_calc_dpll_params()
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 6/8] drm/i915: Replace hand rolled bxt vco calculation with chv_calc_dpll_params() Ville Syrjala
@ 2022-03-09 9:46 ` Jani Nikula
0 siblings, 0 replies; 26+ messages in thread
From: Jani Nikula @ 2022-03-09 9:46 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Tue, 08 Mar 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use chv_calc_dpll_params() to calculate the BXT DP DPLL VCO
> frequency.
>
> We need to add the m1 divider into bxt_dp_clk_val[] for this to work.
>
> v2: Make the WARN_ON() sensible
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
I admit I didn't check all the computations, but the drm_WARN_ON()
should catch any functional changes AFAICT.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 23 +++++++++++--------
> 1 file changed, 13 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 4b52086aa9e9..b7071da4b7e5 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2086,13 +2086,13 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
> /* pre-calculated values for DP linkrates */
> static const struct dpll bxt_dp_clk_val[] = {
> /* m2 is .22 binary fixed point */
> - { .dot = 162000, .p1 = 4, .p2 = 2, .n = 1, .m2 = 0x819999a /* 32.4 */ },
> - { .dot = 270000, .p1 = 4, .p2 = 1, .n = 1, .m2 = 0x6c00000 /* 27.0 */ },
> - { .dot = 540000, .p1 = 2, .p2 = 1, .n = 1, .m2 = 0x6c00000 /* 27.0 */ },
> - { .dot = 216000, .p1 = 3, .p2 = 2, .n = 1, .m2 = 0x819999a /* 32.4 */ },
> - { .dot = 243000, .p1 = 4, .p2 = 1, .n = 1, .m2 = 0x6133333 /* 24.3 */ },
> - { .dot = 324000, .p1 = 4, .p2 = 1, .n = 1, .m2 = 0x819999a /* 32.4 */ },
> - { .dot = 432000, .p1 = 3, .p2 = 1, .n = 1, .m2 = 0x819999a /* 32.4 */ },
> + { .dot = 162000, .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },
> + { .dot = 270000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 /* 27.0 */ },
> + { .dot = 540000, .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 /* 27.0 */ },
> + { .dot = 216000, .p1 = 3, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },
> + { .dot = 243000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6133333 /* 24.3 */ },
> + { .dot = 324000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },
> + { .dot = 432000, .p1 = 3, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },
> };
>
> static bool
> @@ -2122,18 +2122,21 @@ bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
> static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state,
> struct dpll *clk_div)
> {
> - int clock = crtc_state->port_clock;
> + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> int i;
>
> *clk_div = bxt_dp_clk_val[0];
> for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
> - if (bxt_dp_clk_val[i].dot == clock) {
> + if (crtc_state->port_clock == bxt_dp_clk_val[i].dot) {
> *clk_div = bxt_dp_clk_val[i];
> break;
> }
> }
>
> - clk_div->vco = clock * 10 / 2 * clk_div->p1 * clk_div->p2;
> + chv_calc_dpll_params(i915->dpll.ref_clks.nssc, clk_div);
> +
> + drm_WARN_ON(&i915->drm, clk_div->vco == 0 ||
> + clk_div->dot != crtc_state->port_clock);
> }
>
> static bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH v2 2/8] drm/i915: Remove redundant/wrong comments
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 2/8] drm/i915: Remove redundant/wrong comments Ville Syrjala
@ 2022-03-09 9:50 ` Jani Nikula
0 siblings, 0 replies; 26+ messages in thread
From: Jani Nikula @ 2022-03-09 9:50 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Tue, 08 Mar 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Remove the comment specifying the exact formulat for calculating
> the DPLL frequency from the *_find_best_dpll() functions. Each
> platform variant has its own way to calculate these and we have
> the code already to do that. These comments are entirely redundant
> and often even wrong so just get rid of them.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dpll.c | 15 +++++----------
> 1 file changed, 5 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index b3fd94538c44..f4e5290b86a4 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -425,8 +425,7 @@ i9xx_select_p2_div(const struct intel_limit *limit,
>
> /*
> * Returns a set of divisors for the desired target clock with the given
> - * refclk, or FALSE. The returned values represent the clock equation:
> - * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
> + * refclk, or FALSE.
> *
> * Target and reference clocks are specified in kHz.
> *
> @@ -484,8 +483,7 @@ i9xx_find_best_dpll(const struct intel_limit *limit,
>
> /*
> * Returns a set of divisors for the desired target clock with the given
> - * refclk, or FALSE. The returned values represent the clock equation:
> - * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
> + * refclk, or FALSE.
> *
> * Target and reference clocks are specified in kHz.
> *
> @@ -541,8 +539,7 @@ pnv_find_best_dpll(const struct intel_limit *limit,
>
> /*
> * Returns a set of divisors for the desired target clock with the given
> - * refclk, or FALSE. The returned values represent the clock equation:
> - * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
> + * refclk, or FALSE.
> *
> * Target and reference clocks are specified in kHz.
> *
> @@ -641,8 +638,7 @@ static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
>
> /*
> * Returns a set of divisors for the desired target clock with the given
> - * refclk, or FALSE. The returned values represent the clock equation:
> - * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
> + * refclk, or FALSE.
> */
> static bool
> vlv_find_best_dpll(const struct intel_limit *limit,
> @@ -700,8 +696,7 @@ vlv_find_best_dpll(const struct intel_limit *limit,
>
> /*
> * Returns a set of divisors for the desired target clock with the given
> - * refclk, or FALSE. The returned values represent the clock equation:
> - * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
> + * refclk, or FALSE.
> */
> static bool
> chv_find_best_dpll(const struct intel_limit *limit,
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH v2 1/8] drm/i915: Store the /5 target clock in struct dpll on vlv/chv
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 1/8] drm/i915: Store the /5 target clock in struct dpll on vlv/chv Ville Syrjala
@ 2022-03-09 9:53 ` Jani Nikula
2022-03-09 21:43 ` [Intel-gfx] [PATCH v3 " Ville Syrjala
1 sibling, 0 replies; 26+ messages in thread
From: Jani Nikula @ 2022-03-09 9:53 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Tue, 08 Mar 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Unify vlv/chv with earlier platforms so that the sturct dpll::dot
> represents the /5 clock frequency (ie. DP symbol rate or HDMI
> TMDS rate) rather than the *5 fast clock (/2 of the bitrate).
> Makes life a little less confusing to get the same number back
> in .dot which we fed into the DPLL algorithm.
>
> v2: Actually just include the 5x in the final P divider
> Do the same change to the hand rolled gvt code
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
For some reason it was really hard for me to convince myself that I'd
checked every code path for the right amount of *5 and /5 in the right
places... I'll just say I didn't spot anything obviously wrong
here. Fingers crossed.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dpll.c | 19 ++++++++-----------
> drivers/gpu/drm/i915/gvt/handlers.c | 4 ++--
> 2 files changed, 10 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 0ae37fdbf2a5..b3fd94538c44 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -254,12 +254,12 @@ static const struct intel_limit ilk_limits_dual_lvds_100m = {
>
> static const struct intel_limit intel_limits_vlv = {
> /*
> - * These are the data rate limits (measured in fast clocks)
> + * These are based on the data rate limits (measured in fast clocks)
> * since those are the strictest limits we have. The fast
> * clock and actual rate limits are more relaxed, so checking
> * them would make no difference.
> */
> - .dot = { .min = 25000 * 5, .max = 270000 * 5 },
> + .dot = { .min = 25000, .max = 270000 },
> .vco = { .min = 4000000, .max = 6000000 },
> .n = { .min = 1, .max = 7 },
> .m1 = { .min = 2, .max = 3 },
> @@ -270,12 +270,12 @@ static const struct intel_limit intel_limits_vlv = {
>
> static const struct intel_limit intel_limits_chv = {
> /*
> - * These are the data rate limits (measured in fast clocks)
> + * These are based on the data rate limits (measured in fast clocks)
> * since those are the strictest limits we have. The fast
> * clock and actual rate limits are more relaxed, so checking
> * them would make no difference.
> */
> - .dot = { .min = 25000 * 5, .max = 540000 * 5},
> + .dot = { .min = 25000, .max = 540000 },
> .vco = { .min = 4800000, .max = 6480000 },
> .n = { .min = 1, .max = 1 },
> .m1 = { .min = 2, .max = 2 },
> @@ -337,26 +337,26 @@ int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
> int vlv_calc_dpll_params(int refclk, struct dpll *clock)
> {
> clock->m = clock->m1 * clock->m2;
> - clock->p = clock->p1 * clock->p2;
> + clock->p = clock->p1 * clock->p2 * 5;
> if (WARN_ON(clock->n == 0 || clock->p == 0))
> return 0;
> clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
> clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
>
> - return clock->dot / 5;
> + return clock->dot;
> }
>
> int chv_calc_dpll_params(int refclk, struct dpll *clock)
> {
> clock->m = clock->m1 * clock->m2;
> - clock->p = clock->p1 * clock->p2;
> + clock->p = clock->p1 * clock->p2 * 5;
> if (WARN_ON(clock->n == 0 || clock->p == 0))
> return 0;
> clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),
> clock->n << 22);
> clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
>
> - return clock->dot / 5;
> + return clock->dot;
> }
>
> /*
> @@ -659,8 +659,6 @@ vlv_find_best_dpll(const struct intel_limit *limit,
> int max_n = min(limit->n.max, refclk / 19200);
> bool found = false;
>
> - target *= 5; /* fast clock */
> -
> memset(best_clock, 0, sizeof(*best_clock));
>
> /* based on hardware requirement, prefer smaller n to precision */
> @@ -729,7 +727,6 @@ chv_find_best_dpll(const struct intel_limit *limit,
> */
> clock.n = 1;
> clock.m1 = 2;
> - target *= 5; /* fast clock */
>
> for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
> for (clock.p2 = limit->p2.p2_fast;
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index 520a7e1942f3..efdd2f3f9d73 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -583,7 +583,7 @@ static u32 bxt_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port)
> clock.p1 = (vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch)) & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
> clock.p2 = (vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch)) & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
> clock.m = clock.m1 * clock.m2;
> - clock.p = clock.p1 * clock.p2;
> + clock.p = clock.p1 * clock.p2 * 5;
>
> if (clock.n == 0 || clock.p == 0) {
> gvt_dbg_dpy("vgpu-%d PORT_%c PLL has invalid divider\n", vgpu->id, port_name(port));
> @@ -593,7 +593,7 @@ static u32 bxt_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port)
> clock.vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock.m), clock.n << 22);
> clock.dot = DIV_ROUND_CLOSEST(clock.vco, clock.p);
>
> - dp_br = clock.dot / 5;
> + dp_br = clock.dot;
>
> out:
> return dp_br;
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 26+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Clean up some dpll stuff (rev5)
2022-03-07 23:39 [Intel-gfx] [PATCH v2 0/8] drm/i915: Clean up some dpll stuff Ville Syrjala
` (11 preceding siblings ...)
2022-03-09 3:22 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2022-03-09 18:23 ` Patchwork
2022-03-09 18:59 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
` (3 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2022-03-09 18:23 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Clean up some dpll stuff (rev5)
URL : https://patchwork.freedesktop.org/series/100899/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 26+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Clean up some dpll stuff (rev5)
2022-03-07 23:39 [Intel-gfx] [PATCH v2 0/8] drm/i915: Clean up some dpll stuff Ville Syrjala
` (12 preceding siblings ...)
2022-03-09 18:23 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Clean up some dpll stuff (rev5) Patchwork
@ 2022-03-09 18:59 ` Patchwork
2022-03-09 22:02 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Clean up some dpll stuff (rev6) Patchwork
` (2 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2022-03-09 18:59 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5953 bytes --]
== Series Details ==
Series: drm/i915: Clean up some dpll stuff (rev5)
URL : https://patchwork.freedesktop.org/series/100899/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11346 -> Patchwork_22522
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_22522 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22522, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22522/index.html
Participating hosts (43 -> 36)
------------------------------
Additional (2): fi-icl-u2 fi-pnv-d510
Missing (9): bat-dg1-6 bat-dg1-5 bat-dg2-9 fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-ctg-p8600 bat-jsl-2 bat-jsl-1
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22522:
### IGT changes ###
#### Possible regressions ####
* igt@runner@aborted:
- fi-bsw-n3050: NOTRUN -> [FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22522/fi-bsw-n3050/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_22522 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2: NOTRUN -> [SKIP][2] ([fdo#109315]) +17 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22522/fi-icl-u2/igt@amdgpu/amd_cs_nop@fork-gfx0.html
* igt@gem_huc_copy@huc-copy:
- fi-icl-u2: NOTRUN -> [SKIP][3] ([i915#2190])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22522/fi-icl-u2/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2: NOTRUN -> [SKIP][4] ([i915#4613]) +3 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22522/fi-icl-u2/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: NOTRUN -> [SKIP][5] ([fdo#111827]) +8 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22522/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2: NOTRUN -> [SKIP][6] ([fdo#109278]) +2 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22522/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2: NOTRUN -> [SKIP][7] ([fdo#109285])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22522/fi-icl-u2/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-icl-u2: NOTRUN -> [SKIP][8] ([i915#3555])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22522/fi-icl-u2/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-userptr:
- fi-pnv-d510: NOTRUN -> [SKIP][9] ([fdo#109271]) +58 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22522/fi-pnv-d510/igt@prime_vgem@basic-userptr.html
- fi-icl-u2: NOTRUN -> [SKIP][10] ([i915#3301])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22522/fi-icl-u2/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-glk-j4005: NOTRUN -> [FAIL][11] ([i915#5257] / [k.org#202321])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22522/fi-glk-j4005/igt@runner@aborted.html
#### Possible fixes ####
* igt@core_hotunplug@unbind-rebind:
- fi-blb-e6850: [FAIL][12] ([i915#3194]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/fi-blb-e6850/igt@core_hotunplug@unbind-rebind.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22522/fi-blb-e6850/igt@core_hotunplug@unbind-rebind.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#3194]: https://gitlab.freedesktop.org/drm/intel/issues/3194
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Build changes
-------------
* Linux: CI_DRM_11346 -> Patchwork_22522
CI-20190529: 20190529
CI_DRM_11346: ab6456d23719e60c20e8cef05a5f322eea134b88 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6373: 82306f1903c0fee8371f43a156d8b63163ca61c1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22522: 4e4731b80638e8ebc109bec470fc9c88531d9857 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
4e4731b80638 drm/i915: Remove struct dp_link_dpll
f34aa622ddc3 drm/i915: Populate bxt/glk DPLL clock limits a bit more
eac8052ba31c drm/i915: Replace hand rolled bxt vco calculation with chv_calc_dpll_params()
c8e385c6d172 drm/i915: Replace bxt_clk_div with struct dpll
a1c82a00d170 drm/i915: Store the m2 divider as a whole in bxt_clk_div
55f115fbf893 drm/i915: Clean up bxt/glk PLL registers
7e632d8ad2c0 drm/i915: Remove redundant/wrong comments
56ddff2b45db drm/i915: Store the /5 target clock in struct dpll on vlv/chv
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22522/index.html
[-- Attachment #2: Type: text/html, Size: 6896 bytes --]
^ permalink raw reply [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH v3 1/8] drm/i915: Store the /5 target clock in struct dpll on vlv/chv
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 1/8] drm/i915: Store the /5 target clock in struct dpll on vlv/chv Ville Syrjala
2022-03-09 9:53 ` Jani Nikula
@ 2022-03-09 21:43 ` Ville Syrjala
1 sibling, 0 replies; 26+ messages in thread
From: Ville Syrjala @ 2022-03-09 21:43 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Unify vlv/chv with earlier platforms so that the sturct dpll::dot
represents the /5 clock frequency (ie. DP symbol rate or HDMI
TMDS rate) rather than the *5 fast clock (/2 of the bitrate).
Makes life a little less confusing to get the same number back
in .dot which we fed into the DPLL algorithm.
v2: Actually just include the 5x in the final P divider
Do the same change to the hand rolled gvt code
v3: Missed a few *5 in *_find_best_dpll()
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll.c | 23 ++++++++++-------------
drivers/gpu/drm/i915/gvt/handlers.c | 4 ++--
2 files changed, 12 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 0ae37fdbf2a5..53184154bc5d 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -254,12 +254,12 @@ static const struct intel_limit ilk_limits_dual_lvds_100m = {
static const struct intel_limit intel_limits_vlv = {
/*
- * These are the data rate limits (measured in fast clocks)
+ * These are based on the data rate limits (measured in fast clocks)
* since those are the strictest limits we have. The fast
* clock and actual rate limits are more relaxed, so checking
* them would make no difference.
*/
- .dot = { .min = 25000 * 5, .max = 270000 * 5 },
+ .dot = { .min = 25000, .max = 270000 },
.vco = { .min = 4000000, .max = 6000000 },
.n = { .min = 1, .max = 7 },
.m1 = { .min = 2, .max = 3 },
@@ -270,12 +270,12 @@ static const struct intel_limit intel_limits_vlv = {
static const struct intel_limit intel_limits_chv = {
/*
- * These are the data rate limits (measured in fast clocks)
+ * These are based on the data rate limits (measured in fast clocks)
* since those are the strictest limits we have. The fast
* clock and actual rate limits are more relaxed, so checking
* them would make no difference.
*/
- .dot = { .min = 25000 * 5, .max = 540000 * 5},
+ .dot = { .min = 25000, .max = 540000 },
.vco = { .min = 4800000, .max = 6480000 },
.n = { .min = 1, .max = 1 },
.m1 = { .min = 2, .max = 2 },
@@ -337,26 +337,26 @@ int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
int vlv_calc_dpll_params(int refclk, struct dpll *clock)
{
clock->m = clock->m1 * clock->m2;
- clock->p = clock->p1 * clock->p2;
+ clock->p = clock->p1 * clock->p2 * 5;
if (WARN_ON(clock->n == 0 || clock->p == 0))
return 0;
clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
- return clock->dot / 5;
+ return clock->dot;
}
int chv_calc_dpll_params(int refclk, struct dpll *clock)
{
clock->m = clock->m1 * clock->m2;
- clock->p = clock->p1 * clock->p2;
+ clock->p = clock->p1 * clock->p2 * 5;
if (WARN_ON(clock->n == 0 || clock->p == 0))
return 0;
clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),
clock->n << 22);
clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
- return clock->dot / 5;
+ return clock->dot;
}
/*
@@ -659,8 +659,6 @@ vlv_find_best_dpll(const struct intel_limit *limit,
int max_n = min(limit->n.max, refclk / 19200);
bool found = false;
- target *= 5; /* fast clock */
-
memset(best_clock, 0, sizeof(*best_clock));
/* based on hardware requirement, prefer smaller n to precision */
@@ -668,7 +666,7 @@ vlv_find_best_dpll(const struct intel_limit *limit,
for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
clock.p2 -= clock.p2 > 10 ? 2 : 1) {
- clock.p = clock.p1 * clock.p2;
+ clock.p = clock.p1 * clock.p2 * 5;
/* based on hardware requirement, prefer bigger m1,m2 values */
for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
unsigned int ppm;
@@ -729,7 +727,6 @@ chv_find_best_dpll(const struct intel_limit *limit,
*/
clock.n = 1;
clock.m1 = 2;
- target *= 5; /* fast clock */
for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
for (clock.p2 = limit->p2.p2_fast;
@@ -737,7 +734,7 @@ chv_find_best_dpll(const struct intel_limit *limit,
clock.p2 -= clock.p2 > 10 ? 2 : 1) {
unsigned int error_ppm;
- clock.p = clock.p1 * clock.p2;
+ clock.p = clock.p1 * clock.p2 * 5;
m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,
refclk * clock.m1);
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 520a7e1942f3..efdd2f3f9d73 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -583,7 +583,7 @@ static u32 bxt_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port)
clock.p1 = (vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch)) & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
clock.p2 = (vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch)) & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
clock.m = clock.m1 * clock.m2;
- clock.p = clock.p1 * clock.p2;
+ clock.p = clock.p1 * clock.p2 * 5;
if (clock.n == 0 || clock.p == 0) {
gvt_dbg_dpy("vgpu-%d PORT_%c PLL has invalid divider\n", vgpu->id, port_name(port));
@@ -593,7 +593,7 @@ static u32 bxt_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port)
clock.vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock.m), clock.n << 22);
clock.dot = DIV_ROUND_CLOSEST(clock.vco, clock.p);
- dp_br = clock.dot / 5;
+ dp_br = clock.dot;
out:
return dp_br;
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Clean up some dpll stuff (rev6)
2022-03-07 23:39 [Intel-gfx] [PATCH v2 0/8] drm/i915: Clean up some dpll stuff Ville Syrjala
` (13 preceding siblings ...)
2022-03-09 18:59 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2022-03-09 22:02 ` Patchwork
2022-03-09 22:35 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-03-10 7:29 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
16 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2022-03-09 22:02 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Clean up some dpll stuff (rev6)
URL : https://patchwork.freedesktop.org/series/100899/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 26+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Clean up some dpll stuff (rev6)
2022-03-07 23:39 [Intel-gfx] [PATCH v2 0/8] drm/i915: Clean up some dpll stuff Ville Syrjala
` (14 preceding siblings ...)
2022-03-09 22:02 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Clean up some dpll stuff (rev6) Patchwork
@ 2022-03-09 22:35 ` Patchwork
2022-03-10 7:29 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
16 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2022-03-09 22:35 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 10429 bytes --]
== Series Details ==
Series: drm/i915: Clean up some dpll stuff (rev6)
URL : https://patchwork.freedesktop.org/series/100899/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11346 -> Patchwork_22526
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/index.html
Participating hosts (43 -> 44)
------------------------------
Additional (3): bat-rpls-2 fi-icl-u2 fi-pnv-d510
Missing (2): fi-ctg-p8600 fi-bsw-cyan
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22526:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_setmode@basic-clone-single-crtc:
- {bat-rpls-2}: NOTRUN -> [SKIP][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/bat-rpls-2/igt@kms_setmode@basic-clone-single-crtc.html
Known issues
------------
Here are the changes found in Patchwork_22526 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2: NOTRUN -> [SKIP][2] ([fdo#109315]) +17 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/fi-icl-u2/igt@amdgpu/amd_cs_nop@fork-gfx0.html
* igt@gem_huc_copy@huc-copy:
- fi-icl-u2: NOTRUN -> [SKIP][3] ([i915#2190])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/fi-icl-u2/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2: NOTRUN -> [SKIP][4] ([i915#4613]) +3 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/fi-icl-u2/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@i915_selftest@live@requests:
- fi-pnv-d510: NOTRUN -> [DMESG-FAIL][5] ([i915#2927] / [i915#4528])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/fi-pnv-d510/igt@i915_selftest@live@requests.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: NOTRUN -> [SKIP][6] ([fdo#111827]) +8 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2: NOTRUN -> [SKIP][7] ([fdo#109278]) +2 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_flip@basic-plain-flip@a-edp1:
- bat-adlp-4: [PASS][8] -> [DMESG-WARN][9] ([i915#3576]) +1 similar issue
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/bat-adlp-4/igt@kms_flip@basic-plain-flip@a-edp1.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/bat-adlp-4/igt@kms_flip@basic-plain-flip@a-edp1.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2: NOTRUN -> [SKIP][10] ([fdo#109285])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/fi-icl-u2/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-icl-u2: NOTRUN -> [SKIP][11] ([i915#3555])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/fi-icl-u2/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-userptr:
- fi-pnv-d510: NOTRUN -> [SKIP][12] ([fdo#109271]) +40 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/fi-pnv-d510/igt@prime_vgem@basic-userptr.html
- fi-icl-u2: NOTRUN -> [SKIP][13] ([i915#3301])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/fi-icl-u2/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-pnv-d510: NOTRUN -> [FAIL][14] ([fdo#109271] / [i915#2403] / [i915#4312])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/fi-pnv-d510/igt@runner@aborted.html
- fi-bdw-5557u: NOTRUN -> [FAIL][15] ([i915#2426] / [i915#4312])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/fi-bdw-5557u/igt@runner@aborted.html
#### Possible fixes ####
* igt@core_hotunplug@unbind-rebind:
- fi-blb-e6850: [FAIL][16] ([i915#3194]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/fi-blb-e6850/igt@core_hotunplug@unbind-rebind.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/fi-blb-e6850/igt@core_hotunplug@unbind-rebind.html
* igt@gem_exec_suspend@basic-s3@smem:
- fi-bdw-5557u: [INCOMPLETE][18] ([i915#146]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3@smem.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3@smem.html
- {fi-rkl-11600}: [INCOMPLETE][20] ([i915#5127]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/fi-rkl-11600/igt@gem_exec_suspend@basic-s3@smem.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/fi-rkl-11600/igt@gem_exec_suspend@basic-s3@smem.html
* igt@kms_busy@basic@flip:
- {bat-dg2-9}: [DMESG-WARN][22] ([i915#5195]) -> [PASS][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/bat-dg2-9/igt@kms_busy@basic@flip.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/bat-dg2-9/igt@kms_busy@basic@flip.html
- {bat-adlp-6}: [DMESG-WARN][24] ([i915#3576]) -> [PASS][25] +2 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/bat-adlp-6/igt@kms_busy@basic@flip.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/bat-adlp-6/igt@kms_busy@basic@flip.html
#### Warnings ####
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [DMESG-FAIL][26] ([i915#4494] / [i915#4957]) -> [DMESG-FAIL][27] ([i915#4957])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3194]: https://gitlab.freedesktop.org/drm/intel/issues/3194
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#5127]: https://gitlab.freedesktop.org/drm/intel/issues/5127
[i915#5193]: https://gitlab.freedesktop.org/drm/intel/issues/5193
[i915#5195]: https://gitlab.freedesktop.org/drm/intel/issues/5195
[i915#5270]: https://gitlab.freedesktop.org/drm/intel/issues/5270
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5275]: https://gitlab.freedesktop.org/drm/intel/issues/5275
[i915#5276]: https://gitlab.freedesktop.org/drm/intel/issues/5276
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Build changes
-------------
* Linux: CI_DRM_11346 -> Patchwork_22526
CI-20190529: 20190529
CI_DRM_11346: ab6456d23719e60c20e8cef05a5f322eea134b88 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6373: 82306f1903c0fee8371f43a156d8b63163ca61c1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22526: 1192ea7b170328a24d043c026b37b46b78244688 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
1192ea7b1703 drm/i915: Remove struct dp_link_dpll
e2ff2096ebf3 drm/i915: Populate bxt/glk DPLL clock limits a bit more
03dfc7d984d8 drm/i915: Replace hand rolled bxt vco calculation with chv_calc_dpll_params()
d6cb6536d605 drm/i915: Replace bxt_clk_div with struct dpll
097a9983f499 drm/i915: Store the m2 divider as a whole in bxt_clk_div
8ef9ac7d77e4 drm/i915: Clean up bxt/glk PLL registers
d49cf6feb4ba drm/i915: Remove redundant/wrong comments
efe5dc7c11e2 drm/i915: Store the /5 target clock in struct dpll on vlv/chv
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/index.html
[-- Attachment #2: Type: text/html, Size: 10328 bytes --]
^ permalink raw reply [flat|nested] 26+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Clean up some dpll stuff (rev6)
2022-03-07 23:39 [Intel-gfx] [PATCH v2 0/8] drm/i915: Clean up some dpll stuff Ville Syrjala
` (15 preceding siblings ...)
2022-03-09 22:35 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-03-10 7:29 ` Patchwork
16 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2022-03-10 7:29 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30261 bytes --]
== Series Details ==
Series: drm/i915: Clean up some dpll stuff (rev6)
URL : https://patchwork.freedesktop.org/series/100899/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11346_full -> Patchwork_22526_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_22526_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22526_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (13 -> 13)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22526_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_hdr@bpc-switch-suspend@bpc-switch-suspend-edp-1-pipe-a:
- shard-skl: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-skl8/igt@kms_hdr@bpc-switch-suspend@bpc-switch-suspend-edp-1-pipe-a.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-skl9/igt@kms_hdr@bpc-switch-suspend@bpc-switch-suspend-edp-1-pipe-a.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_mmap_write_crc@main:
- {shard-dg1}: NOTRUN -> [FAIL][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-dg1-19/igt@kms_mmap_write_crc@main.html
* igt@kms_plane_lowres@pipe-a-tiling-4:
- {shard-rkl}: NOTRUN -> [SKIP][4]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-rkl-1/igt@kms_plane_lowres@pipe-a-tiling-4.html
* {igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-25@pipe-c-hdmi-a-3-downscale-with-pixel-format}:
- {shard-dg1}: NOTRUN -> [SKIP][5] +4 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-dg1-18/igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-25@pipe-c-hdmi-a-3-downscale-with-pixel-format.html
Known issues
------------
Here are the changes found in Patchwork_22526_full that come from known issues:
### CI changes ###
#### Possible fixes ####
* boot:
- shard-glk: ([PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [FAIL][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30]) ([i915#4392]) -> ([PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53], [PASS][54], [PASS][55])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-glk5/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-glk3/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-glk3/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-glk9/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-glk9/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-glk9/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-glk8/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-glk8/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-glk4/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-glk4/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-glk4/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-glk8/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-glk7/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-glk7/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-glk6/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-glk6/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-glk6/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-glk5/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-glk1/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-glk1/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-glk1/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-glk2/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-glk2/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-glk2/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-glk3/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-glk9/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-glk9/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-glk8/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-glk8/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-glk7/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-glk7/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-glk7/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-glk6/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-glk6/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-glk6/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-glk5/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-glk5/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-glk5/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-glk4/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-glk4/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-glk4/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-glk3/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-glk3/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-glk3/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-glk2/boot.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-glk2/boot.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-glk2/boot.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-glk1/boot.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-glk1/boot.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-glk1/boot.html
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@psr2:
- shard-iclb: [PASS][56] -> [SKIP][57] ([i915#658])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-iclb2/igt@feature_discovery@psr2.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-iclb7/igt@feature_discovery@psr2.html
* igt@gem_create@create-massive:
- shard-kbl: NOTRUN -> [DMESG-WARN][58] ([i915#4991])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-kbl1/igt@gem_create@create-massive.html
* igt@gem_exec_balancer@parallel:
- shard-tglb: NOTRUN -> [DMESG-WARN][59] ([i915#5076])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-tglb5/igt@gem_exec_balancer@parallel.html
* igt@gem_exec_balancer@parallel-ordering:
- shard-tglb: NOTRUN -> [DMESG-FAIL][60] ([i915#5076])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-tglb6/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-skl: NOTRUN -> [SKIP][61] ([fdo#109271]) +140 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-skl7/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][62] -> [FAIL][63] ([i915#2842])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-iclb2/igt@gem_exec_fair@basic-none-share@rcs0.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-iclb3/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-glk: [PASS][64] -> [FAIL][65] ([i915#2842]) +1 similar issue
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-glk6/igt@gem_exec_fair@basic-pace@vecs0.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-glk9/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_lmem_swapping@parallel-random:
- shard-skl: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#4613]) +1 similar issue
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-skl7/igt@gem_lmem_swapping@parallel-random.html
* igt@gem_lmem_swapping@random:
- shard-glk: NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#4613])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-glk5/igt@gem_lmem_swapping@random.html
* igt@gem_pwrite@basic-exhaustion:
- shard-skl: NOTRUN -> [WARN][68] ([i915#2658])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-skl10/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_pxp@create-regular-context-1:
- shard-tglb: NOTRUN -> [SKIP][69] ([i915#4270])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-tglb6/igt@gem_pxp@create-regular-context-1.html
* igt@gem_pxp@verify-pxp-execution-after-suspend-resume:
- shard-iclb: NOTRUN -> [SKIP][70] ([i915#4270])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-iclb6/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html
* igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled:
- shard-iclb: NOTRUN -> [SKIP][71] ([i915#768]) +1 similar issue
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-iclb7/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled.html
* igt@gem_softpin@allocator-evict-all-engines:
- shard-glk: [PASS][72] -> [FAIL][73] ([i915#4171])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-glk1/igt@gem_softpin@allocator-evict-all-engines.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-glk1/igt@gem_softpin@allocator-evict-all-engines.html
* igt@gem_softpin@evict-snoop:
- shard-iclb: NOTRUN -> [SKIP][74] ([fdo#109312])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-iclb6/igt@gem_softpin@evict-snoop.html
* igt@gem_userptr_blits@create-destroy-unsync:
- shard-tglb: NOTRUN -> [SKIP][75] ([i915#3297])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-tglb3/igt@gem_userptr_blits@create-destroy-unsync.html
- shard-iclb: NOTRUN -> [SKIP][76] ([i915#3297])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-iclb7/igt@gem_userptr_blits@create-destroy-unsync.html
* igt@gem_userptr_blits@input-checking:
- shard-skl: NOTRUN -> [DMESG-WARN][77] ([i915#4991])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-skl9/igt@gem_userptr_blits@input-checking.html
* igt@gen7_exec_parse@oacontrol-tracking:
- shard-iclb: NOTRUN -> [SKIP][78] ([fdo#109289]) +1 similar issue
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-iclb6/igt@gen7_exec_parse@oacontrol-tracking.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [PASS][79] -> [DMESG-WARN][80] ([i915#1436] / [i915#716])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-skl7/igt@gen9_exec_parse@allowed-single.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-skl9/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@secure-batches:
- shard-iclb: NOTRUN -> [SKIP][81] ([i915#2856])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-iclb7/igt@gen9_exec_parse@secure-batches.html
- shard-tglb: NOTRUN -> [SKIP][82] ([i915#2527] / [i915#2856])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-tglb3/igt@gen9_exec_parse@secure-batches.html
* igt@i915_pm_rpm@modeset-pc8-residency-stress:
- shard-apl: NOTRUN -> [SKIP][83] ([fdo#109271]) +46 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-apl4/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [PASS][84] -> [INCOMPLETE][85] ([i915#3921])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-snb7/igt@i915_selftest@live@hangcheck.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-snb4/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@mock@requests:
- shard-skl: [PASS][86] -> [INCOMPLETE][87] ([i915#5183] / [i915#5187])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-skl7/igt@i915_selftest@mock@requests.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-skl5/igt@i915_selftest@mock@requests.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-tglb: NOTRUN -> [SKIP][88] ([i915#5286])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-tglb3/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-iclb: NOTRUN -> [SKIP][89] ([i915#5286])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-iclb6/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-skl: NOTRUN -> [FAIL][90] ([i915#3743])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-skl3/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
- shard-glk: NOTRUN -> [SKIP][91] ([fdo#109271] / [i915#3777])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-glk5/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-skl: NOTRUN -> [SKIP][92] ([fdo#109271] / [i915#3777]) +2 similar issues
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-skl3/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-addfb:
- shard-tglb: NOTRUN -> [SKIP][93] ([fdo#111615])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-tglb5/igt@kms_big_fb@yf-tiled-addfb.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-iclb: NOTRUN -> [SKIP][94] ([fdo#110723])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-iclb7/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
- shard-glk: NOTRUN -> [SKIP][95] ([fdo#109271] / [i915#3886]) +1 similar issue
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-glk5/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][96] ([fdo#111615] / [i915#3689])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-tglb3/igt@kms_ccs@pipe-a-crc-primary-rotation-180-yf_tiled_ccs.html
* igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][97] ([fdo#109271] / [i915#1888] / [i915#3886])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-skl3/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
- shard-iclb: NOTRUN -> [SKIP][98] ([fdo#109278] / [i915#3886])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-iclb6/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
- shard-apl: NOTRUN -> [SKIP][99] ([fdo#109271] / [i915#3886])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-apl4/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][100] ([fdo#109271] / [i915#3886]) +7 similar issues
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-skl7/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-d-random-ccs-data-yf_tiled_ccs:
- shard-iclb: NOTRUN -> [SKIP][101] ([fdo#109278]) +11 similar issues
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-iclb6/igt@kms_ccs@pipe-d-random-ccs-data-yf_tiled_ccs.html
* igt@kms_chamelium@dp-frame-dump:
- shard-iclb: NOTRUN -> [SKIP][102] ([fdo#109284] / [fdo#111827]) +2 similar issues
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-iclb6/igt@kms_chamelium@dp-frame-dump.html
* igt@kms_chamelium@dp-mode-timings:
- shard-glk: NOTRUN -> [SKIP][103] ([fdo#109271] / [fdo#111827]) +3 similar issues
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-glk5/igt@kms_chamelium@dp-mode-timings.html
* igt@kms_chamelium@hdmi-hpd:
- shard-skl: NOTRUN -> [SKIP][104] ([fdo#109271] / [fdo#111827]) +8 similar issues
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-skl3/igt@kms_chamelium@hdmi-hpd.html
* igt@kms_color_chamelium@pipe-a-ctm-0-5:
- shard-kbl: NOTRUN -> [SKIP][105] ([fdo#109271] / [fdo#111827])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-kbl1/igt@kms_color_chamelium@pipe-a-ctm-0-5.html
* igt@kms_color_chamelium@pipe-c-ctm-red-to-blue:
- shard-tglb: NOTRUN -> [SKIP][106] ([fdo#109284] / [fdo#111827])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-tglb5/igt@kms_color_chamelium@pipe-c-ctm-red-to-blue.html
* igt@kms_color_chamelium@pipe-d-ctm-negative:
- shard-iclb: NOTRUN -> [SKIP][107] ([fdo#109278] / [fdo#109284] / [fdo#111827])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-iclb6/igt@kms_color_chamelium@pipe-d-ctm-negative.html
- shard-apl: NOTRUN -> [SKIP][108] ([fdo#109271] / [fdo#111827]) +3 similar issues
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-apl4/igt@kms_color_chamelium@pipe-d-ctm-negative.html
* igt@kms_cursor_crc@pipe-a-cursor-512x512-offscreen:
- shard-iclb: NOTRUN -> [SKIP][109] ([fdo#109278] / [fdo#109279]) +2 similar issues
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-iclb7/igt@kms_cursor_crc@pipe-a-cursor-512x512-offscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-32x10-random:
- shard-kbl: NOTRUN -> [SKIP][110] ([fdo#109271]) +32 similar issues
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-kbl1/igt@kms_cursor_crc@pipe-b-cursor-32x10-random.html
* igt@kms_cursor_crc@pipe-b-cursor-512x512-rapid-movement:
- shard-tglb: NOTRUN -> [SKIP][111] ([fdo#109279] / [i915#3359]) +1 similar issue
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-tglb3/igt@kms_cursor_crc@pipe-b-cursor-512x512-rapid-movement.html
* igt@kms_cursor_crc@pipe-d-cursor-max-size-offscreen:
- shard-tglb: NOTRUN -> [SKIP][112] ([i915#3359])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-tglb6/igt@kms_cursor_crc@pipe-d-cursor-max-size-offscreen.html
* igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
- shard-iclb: NOTRUN -> [SKIP][113] ([fdo#109274] / [fdo#109278]) +1 similar issue
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-iclb7/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-skl: NOTRUN -> [FAIL][114] ([i915#2346])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank:
- shard-tglb: NOTRUN -> [SKIP][115] ([fdo#109274] / [fdo#111825]) +2 similar issues
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-tglb5/igt@kms_flip@2x-flip-vs-absolute-wf_vblank.html
* igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-edp1:
- shard-skl: [PASS][116] -> [FAIL][117] ([i915#2122])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-skl2/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-edp1.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-skl2/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-apl: [PASS][118] -> [DMESG-WARN][119] ([i915#180]) +2 similar issues
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_flip@plain-flip-ts-check@a-hdmi-a1:
- shard-glk: [PASS][120] -> [FAIL][121] ([i915#2122])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-glk5/igt@kms_flip@plain-flip-ts-check@a-hdmi-a1.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-glk9/igt@kms_flip@plain-flip-ts-check@a-hdmi-a1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling:
- shard-iclb: [PASS][122] -> [SKIP][123] ([i915#3701])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-iclb7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-blt:
- shard-iclb: NOTRUN -> [SKIP][124] ([fdo#109280]) +9 similar issues
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-render:
- shard-tglb: NOTRUN -> [SKIP][125] ([fdo#109280] / [fdo#111825]) +9 similar issues
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-render.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-iclb: NOTRUN -> [SKIP][126] ([i915#1839])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-iclb6/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- shard-glk: NOTRUN -> [FAIL][127] ([fdo#108145] / [i915#265])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-glk5/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
- shard-skl: NOTRUN -> [FAIL][128] ([i915#265])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-skl3/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-apl: NOTRUN -> [FAIL][129] ([fdo#108145] / [i915#265])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-apl4/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: NOTRUN -> [FAIL][130] ([fdo#108145] / [i915#265])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_plane_scaling@2x-scaler-multi-pipe:
- shard-iclb: NOTRUN -> [SKIP][131] ([fdo#109274]) +4 similar issues
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-iclb7/igt@kms_plane_scaling@2x-scaler-multi-pipe.html
* igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
- shard-skl: NOTRUN -> [SKIP][132] ([fdo#109271] / [i915#658])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-skl7/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
* igt@kms_psr@psr2_cursor_blt:
- shard-iclb: NOTRUN -> [SKIP][133] ([fdo#109441])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-iclb6/igt@kms_psr@psr2_cursor_blt.html
* igt@kms_psr@psr2_primary_mmap_gtt:
- shard-glk: NOTRUN -> [SKIP][134] ([fdo#109271]) +40 similar issues
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-glk5/igt@kms_psr@psr2_primary_mmap_gtt.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [PASS][135] -> [SKIP][136] ([fdo#109441]) +2 similar issues
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-iclb7/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-skl: NOTRUN -> [SKIP][137] ([fdo#109271] / [i915#2437])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-skl10/igt@kms_writeback@writeback-invalid-parameters.html
* igt@nouveau_crc@pipe-b-ctx-flip-detection:
- shard-tglb: NOTRUN -> [SKIP][138] ([i915#2530]) +1 similar issue
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-tglb6/igt@nouveau_crc@pipe-b-ctx-flip-detection.html
* igt@nouveau_crc@pipe-d-source-rg:
- shard-iclb: NOTRUN -> [SKIP][139] ([fdo#109278] / [i915#2530])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-iclb6/igt@nouveau_crc@pipe-d-source-rg.html
* igt@perf@mi-rpc:
- shard-tglb: NOTRUN -> [SKIP][140] ([fdo#109289]) +1 similar issue
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-tglb3/igt@perf@mi-rpc.html
* igt@prime_vgem@fence-flip-hang:
- shard-iclb: NOTRUN -> [SKIP][141] ([fdo#109295])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-iclb6/igt@prime_vgem@fence-flip-hang.html
* igt@syncobj_timeline@transfer-timeline-point:
- shard-glk: NOTRUN -> [DMESG-FAIL][142] ([i915#5098])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-glk5/igt@syncobj_timeline@transfer-timeline-point.html
* igt@sysfs_clients@busy:
- shard-skl: NOTRUN -> [SKIP][143] ([fdo#109271] / [i915#2994]) +2 similar issues
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-skl7/igt@sysfs_clients@busy.html
* igt@sysfs_clients@fair-7:
- shard-tglb: NOTRUN -> [SKIP][144] ([i915#2994])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-tglb5/igt@sysfs_clients@fair-7.html
* igt@sysfs_clients@split-25:
- shard-apl: NOTRUN -> [SKIP][145] ([fdo#109271] / [i915#2994])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-apl4/igt@sysfs_clients@split-25.html
#### Possible fixes ####
* igt@gem_ctx_persistence@many-contexts:
- {shard-rkl}: [FAIL][146] ([i915#2410]) -> [PASS][147]
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-rkl-5/igt@gem_ctx_persistence@many-contexts.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-rkl-2/igt@gem_ctx_persistence@many-contexts.html
* igt@gem_ctx_persistence@smoketest:
- shard-iclb: [FAIL][148] -> [PASS][149]
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-iclb5/igt@gem_ctx_persistence@smoketest.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-iclb2/igt@gem_ctx_persistence@smoketest.html
* igt@gem_exec_balancer@parallel-balancer:
- shard-iclb: [SKIP][150] ([i915#4525]) -> [PASS][151]
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-iclb6/igt@gem_exec_balancer@parallel-balancer.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-iclb4/igt@gem_exec_balancer@parallel-balancer.html
* igt@gem_exec_capture@pi@rcs0:
- shard-tglb: [INCOMPLETE][152] ([i915#3371]) -> [PASS][153]
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-tglb5/igt@gem_exec_capture@pi@rcs0.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-tglb5/igt@gem_exec_capture@pi@rcs0.html
- {shard-rkl}: [INCOMPLETE][154] ([i915#3371]) -> [PASS][155]
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11346/shard-rkl-5/igt@gem_exec_capture@pi@rcs0.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/shard-rkl-5/igt@gem_exec_capture@pi@rcs0.html
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22526/index.html
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end of thread, other threads:[~2022-03-10 7:29 UTC | newest]
Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-03-07 23:39 [Intel-gfx] [PATCH v2 0/8] drm/i915: Clean up some dpll stuff Ville Syrjala
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 1/8] drm/i915: Store the /5 target clock in struct dpll on vlv/chv Ville Syrjala
2022-03-09 9:53 ` Jani Nikula
2022-03-09 21:43 ` [Intel-gfx] [PATCH v3 " Ville Syrjala
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 2/8] drm/i915: Remove redundant/wrong comments Ville Syrjala
2022-03-09 9:50 ` Jani Nikula
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 3/8] drm/i915: Clean up bxt/glk PLL registers Ville Syrjala
2022-03-09 9:22 ` Jani Nikula
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 4/8] drm/i915: Store the m2 divider as a whole in bxt_clk_div Ville Syrjala
2022-03-09 9:27 ` Jani Nikula
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 5/8] drm/i915: Replace bxt_clk_div with struct dpll Ville Syrjala
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 6/8] drm/i915: Replace hand rolled bxt vco calculation with chv_calc_dpll_params() Ville Syrjala
2022-03-09 9:46 ` Jani Nikula
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 7/8] drm/i915: Populate bxt/glk DPLL clock limits a bit more Ville Syrjala
2022-03-09 9:30 ` Jani Nikula
2022-03-07 23:39 ` [Intel-gfx] [PATCH v2 8/8] drm/i915: Remove struct dp_link_dpll Ville Syrjala
2022-03-09 9:34 ` Jani Nikula
2022-03-07 23:50 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Clean up some dpll stuff (rev3) Patchwork
2022-03-08 13:31 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-03-09 2:48 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Clean up some dpll stuff (rev4) Patchwork
2022-03-09 3:22 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-03-09 18:23 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Clean up some dpll stuff (rev5) Patchwork
2022-03-09 18:59 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-03-09 22:02 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Clean up some dpll stuff (rev6) Patchwork
2022-03-09 22:35 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-03-10 7:29 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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