From: Dan Carpenter <dan.carpenter@oracle.com>
To: kbuild@lists.01.org, Lizhi Hou <lizhi.hou@xilinx.com>,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
robh@kernel.org
Cc: lkp@intel.com, kbuild-all@lists.01.org,
Lizhi Hou <lizhi.hou@xilinx.com>,
yilun.xu@intel.com, maxz@xilinx.com, sonal.santan@xilinx.com,
yliu@xilinx.com, michal.simek@xilinx.com, stefanos@xilinx.com,
trix@redhat.com, mdf@kernel.org, dwmw2@infradead.org,
linux-kernel@vger.kernel.org, Max Zhen <max.zhen@xilinx.com>
Subject: Re: [PATCH V1 RESEND 1/4] pci: add interface to create pci-ep device tree node
Date: Thu, 10 Mar 2022 13:02:40 +0300 [thread overview]
Message-ID: <202203100338.8jox1rCr-lkp@intel.com> (raw)
In-Reply-To: <20220305052304.726050-2-lizhi.hou@xilinx.com>
Hi Lizhi,
url: https://github.com/0day-ci/linux/commits/Lizhi-Hou/Infrastructure-to-define-apertures-in-a-PCIe-device-with-a-flattened-device-tree/20220307-141939
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: i386-randconfig-m021-20220307 (https://download.01.org/0day-ci/archive/20220310/202203100338.8jox1rCr-lkp@intel.com/config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
smatch warnings:
drivers/pci/of.c:762 devm_of_pci_create_bus_endpoint() error: double free of 'prop'
vim +/prop +762 drivers/pci/of.c
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 677 int devm_of_pci_create_bus_endpoint(struct pci_dev *pdev)
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 678 {
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 679 struct property *proplist = NULL;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 680 struct device *dev = &pdev->dev;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 681 int range_ncells, addr_ncells;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 682 struct device_node *node;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 683 void *prop = NULL;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 684 u32 *range_cell;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 685 __be32 val;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 686 int i, ret;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 687
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 688 node = of_ep_alloc_node(pdev, "pci-ep-bus");
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 689 if (!node)
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 690 return -ENOMEM;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 691
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 692 /* the endpoint node works as 'simple-bus' to translate aperture addresses. */
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 693 prop = "simple-bus";
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 694 ret = of_ep_add_property(dev, &proplist, "compatible", strlen(prop) + 1, prop);
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 695 if (ret)
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 696 goto cleanup;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 697
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 698 /* The address and size cells of nodes underneath are 2 */
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 699 val = cpu_to_be32(2);
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 700 ret = of_ep_add_property(dev, &proplist, "#address-cells", sizeof(u32), &val);
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 701 if (ret)
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 702 goto cleanup;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 703
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 704 ret = of_ep_add_property(dev, &proplist, "#size-cells", sizeof(u32), &val);
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 705 if (ret)
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 706 goto cleanup;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 707
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 708 /* child address format: 0xIooooooo oooooooo, I = bar index, o = offset on bar */
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 709 addr_ncells = of_n_addr_cells(node);
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 710 if (addr_ncells > 2) {
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 711 /* does not support number of address cells greater than 2 */
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 712 ret = -EINVAL;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 713 goto cleanup;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 714 }
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 715
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 716 /* range cells include <node addr cells> <child addr cells> <child size cells> */
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 717 range_ncells = addr_ncells + 4;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 718 prop = kzalloc(range_ncells * sizeof(u32) * PCI_STD_NUM_BARS, GFP_KERNEL);
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 719 if (!prop) {
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 720 ret = -ENOMEM;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 721 goto cleanup;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 722 }
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 723
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 724 range_cell = prop;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 725 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 726 if (!pci_resource_len(pdev, i))
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 727 continue;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 728 /* highest 4 bits of address are bar index */
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 729 *(__be64 *)range_cell = cpu_to_be64((u64)i << 60);
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 730 range_cell += 2;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 731 if (addr_ncells == 2)
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 732 *(__be64 *)range_cell = cpu_to_be64((u64)pci_resource_start(pdev, i));
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 733 else
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 734 *(__be32 *)range_cell = cpu_to_be32((u32)pci_resource_start(pdev, i));
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 735
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 736 range_cell += addr_ncells;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 737 *(__be64 *)range_cell = cpu_to_be64((u64)pci_resource_len(pdev, i));
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 738 range_cell += 2;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 739 }
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 740
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 741 /* error out if there is not PCI BAR been found */
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 742 if ((void *)range_cell == prop) {
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 743 ret = -EINVAL;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 744 goto cleanup;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 745 }
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 746
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 747 ret = of_ep_add_property(dev, &proplist, "ranges", (void *)range_cell - prop, prop);
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 748 kfree(prop);
^^^^^^^^^^^^
Free
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 749 if (ret)
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 750 goto cleanup;
^^^^^^^^^^^^^
Double free after goto.
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 751
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 752 node->properties = proplist;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 753 ret = of_attach_node(node);
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 754 if (ret)
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 755 goto cleanup;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 756
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 757 devres_add(dev, node);
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 758
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 759 return 0;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 760
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 761 cleanup:
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 @762 kfree(prop);
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 763 if (node)
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 764 devres_free(node);
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 765
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 766 return ret;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 767 }
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
WARNING: multiple messages have this Message-ID (diff)
From: kernel test robot <lkp@intel.com>
To: kbuild@lists.01.org
Subject: Re: [PATCH V1 RESEND 1/4] pci: add interface to create pci-ep device tree node
Date: Thu, 10 Mar 2022 03:14:30 +0800 [thread overview]
Message-ID: <202203100338.8jox1rCr-lkp@intel.com> (raw)
[-- Attachment #1: Type: text/plain, Size: 9585 bytes --]
CC: kbuild-all(a)lists.01.org
BCC: lkp(a)intel.com
In-Reply-To: <20220305052304.726050-2-lizhi.hou@xilinx.com>
References: <20220305052304.726050-2-lizhi.hou@xilinx.com>
TO: Lizhi Hou <lizhi.hou@xilinx.com>
TO: linux-pci(a)vger.kernel.org
TO: devicetree(a)vger.kernel.org
TO: robh(a)kernel.org
CC: Lizhi Hou <lizhi.hou@xilinx.com>
CC: yilun.xu(a)intel.com
CC: maxz(a)xilinx.com
CC: sonal.santan(a)xilinx.com
CC: yliu(a)xilinx.com
CC: michal.simek(a)xilinx.com
CC: stefanos(a)xilinx.com
CC: trix(a)redhat.com
CC: mdf(a)kernel.org
CC: dwmw2(a)infradead.org
CC: linux-kernel(a)vger.kernel.org
CC: Max Zhen <max.zhen@xilinx.com>
Hi Lizhi,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on robh/for-next]
[also build test WARNING on helgaas-pci/next linus/master pinchartl-media/drm/du/next v5.17-rc7 next-20220309]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Lizhi-Hou/Infrastructure-to-define-apertures-in-a-PCIe-device-with-a-flattened-device-tree/20220307-141939
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
:::::: branch date: 3 days ago
:::::: commit date: 3 days ago
config: i386-randconfig-m021-20220307 (https://download.01.org/0day-ci/archive/20220310/202203100338.8jox1rCr-lkp(a)intel.com/config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
smatch warnings:
drivers/pci/of.c:762 devm_of_pci_create_bus_endpoint() error: double free of 'prop'
vim +/prop +762 drivers/pci/of.c
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 663
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 664 /**
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 665 * devm_of_pci_create_bus_endpoint - Create a device node for the given pci device.
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 666 * @pdev: PCI device pointer.
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 667 *
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 668 * For PCI device which uses flattened device tree to describe apertures in its BARs,
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 669 * a device node for the given pci device is required. Then the flattened device tree
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 670 * overlay from the device can be applied to the base tree.
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 671 * The device node is under root node and act like bus node. It contains a "ranges"
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 672 * property which is used for address translation of its children. Each child node
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 673 * corresponds an aperture and use BAR index and offset as its address.
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 674
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 675 * Returns 0 on success or a negative error-code on failure.
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 676 */
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 677 int devm_of_pci_create_bus_endpoint(struct pci_dev *pdev)
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 678 {
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 679 struct property *proplist = NULL;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 680 struct device *dev = &pdev->dev;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 681 int range_ncells, addr_ncells;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 682 struct device_node *node;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 683 void *prop = NULL;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 684 u32 *range_cell;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 685 __be32 val;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 686 int i, ret;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 687
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 688 node = of_ep_alloc_node(pdev, "pci-ep-bus");
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 689 if (!node)
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 690 return -ENOMEM;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 691
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 692 /* the endpoint node works as 'simple-bus' to translate aperture addresses. */
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 693 prop = "simple-bus";
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 694 ret = of_ep_add_property(dev, &proplist, "compatible", strlen(prop) + 1, prop);
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 695 if (ret)
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 696 goto cleanup;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 697
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 698 /* The address and size cells of nodes underneath are 2 */
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 699 val = cpu_to_be32(2);
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 700 ret = of_ep_add_property(dev, &proplist, "#address-cells", sizeof(u32), &val);
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 701 if (ret)
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 702 goto cleanup;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 703
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 704 ret = of_ep_add_property(dev, &proplist, "#size-cells", sizeof(u32), &val);
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 705 if (ret)
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 706 goto cleanup;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 707
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 708 /* child address format: 0xIooooooo oooooooo, I = bar index, o = offset on bar */
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 709 addr_ncells = of_n_addr_cells(node);
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 710 if (addr_ncells > 2) {
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 711 /* does not support number of address cells greater than 2 */
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 712 ret = -EINVAL;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 713 goto cleanup;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 714 }
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 715
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 716 /* range cells include <node addr cells> <child addr cells> <child size cells> */
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 717 range_ncells = addr_ncells + 4;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 718 prop = kzalloc(range_ncells * sizeof(u32) * PCI_STD_NUM_BARS, GFP_KERNEL);
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 719 if (!prop) {
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 720 ret = -ENOMEM;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 721 goto cleanup;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 722 }
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 723
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 724 range_cell = prop;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 725 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 726 if (!pci_resource_len(pdev, i))
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 727 continue;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 728 /* highest 4 bits of address are bar index */
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 729 *(__be64 *)range_cell = cpu_to_be64((u64)i << 60);
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 730 range_cell += 2;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 731 if (addr_ncells == 2)
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 732 *(__be64 *)range_cell = cpu_to_be64((u64)pci_resource_start(pdev, i));
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 733 else
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 734 *(__be32 *)range_cell = cpu_to_be32((u32)pci_resource_start(pdev, i));
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 735
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 736 range_cell += addr_ncells;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 737 *(__be64 *)range_cell = cpu_to_be64((u64)pci_resource_len(pdev, i));
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 738 range_cell += 2;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 739 }
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 740
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 741 /* error out if there is not PCI BAR been found */
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 742 if ((void *)range_cell == prop) {
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 743 ret = -EINVAL;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 744 goto cleanup;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 745 }
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 746
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 747 ret = of_ep_add_property(dev, &proplist, "ranges", (void *)range_cell - prop, prop);
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 748 kfree(prop);
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 749 if (ret)
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 750 goto cleanup;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 751
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 752 node->properties = proplist;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 753 ret = of_attach_node(node);
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 754 if (ret)
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 755 goto cleanup;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 756
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 757 devres_add(dev, node);
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 758
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 759 return 0;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 760
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 761 cleanup:
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 @762 kfree(prop);
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 763 if (node)
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 764 devres_free(node);
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 765
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 766 return ret;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 767 }
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 768 EXPORT_SYMBOL_GPL(devm_of_pci_create_bus_endpoint);
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 769
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
WARNING: multiple messages have this Message-ID (diff)
From: Dan Carpenter <dan.carpenter@oracle.com>
To: kbuild-all@lists.01.org
Subject: Re: [PATCH V1 RESEND 1/4] pci: add interface to create pci-ep device tree node
Date: Thu, 10 Mar 2022 13:02:40 +0300 [thread overview]
Message-ID: <202203100338.8jox1rCr-lkp@intel.com> (raw)
In-Reply-To: <20220305052304.726050-2-lizhi.hou@xilinx.com>
[-- Attachment #1: Type: text/plain, Size: 7241 bytes --]
Hi Lizhi,
url: https://github.com/0day-ci/linux/commits/Lizhi-Hou/Infrastructure-to-define-apertures-in-a-PCIe-device-with-a-flattened-device-tree/20220307-141939
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: i386-randconfig-m021-20220307 (https://download.01.org/0day-ci/archive/20220310/202203100338.8jox1rCr-lkp(a)intel.com/config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
smatch warnings:
drivers/pci/of.c:762 devm_of_pci_create_bus_endpoint() error: double free of 'prop'
vim +/prop +762 drivers/pci/of.c
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 677 int devm_of_pci_create_bus_endpoint(struct pci_dev *pdev)
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 678 {
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 679 struct property *proplist = NULL;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 680 struct device *dev = &pdev->dev;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 681 int range_ncells, addr_ncells;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 682 struct device_node *node;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 683 void *prop = NULL;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 684 u32 *range_cell;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 685 __be32 val;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 686 int i, ret;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 687
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 688 node = of_ep_alloc_node(pdev, "pci-ep-bus");
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 689 if (!node)
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 690 return -ENOMEM;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 691
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 692 /* the endpoint node works as 'simple-bus' to translate aperture addresses. */
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 693 prop = "simple-bus";
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 694 ret = of_ep_add_property(dev, &proplist, "compatible", strlen(prop) + 1, prop);
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 695 if (ret)
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 696 goto cleanup;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 697
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 698 /* The address and size cells of nodes underneath are 2 */
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 699 val = cpu_to_be32(2);
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 700 ret = of_ep_add_property(dev, &proplist, "#address-cells", sizeof(u32), &val);
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 701 if (ret)
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 702 goto cleanup;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 703
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 704 ret = of_ep_add_property(dev, &proplist, "#size-cells", sizeof(u32), &val);
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 705 if (ret)
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 706 goto cleanup;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 707
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 708 /* child address format: 0xIooooooo oooooooo, I = bar index, o = offset on bar */
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 709 addr_ncells = of_n_addr_cells(node);
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 710 if (addr_ncells > 2) {
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 711 /* does not support number of address cells greater than 2 */
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 712 ret = -EINVAL;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 713 goto cleanup;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 714 }
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 715
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 716 /* range cells include <node addr cells> <child addr cells> <child size cells> */
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 717 range_ncells = addr_ncells + 4;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 718 prop = kzalloc(range_ncells * sizeof(u32) * PCI_STD_NUM_BARS, GFP_KERNEL);
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 719 if (!prop) {
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 720 ret = -ENOMEM;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 721 goto cleanup;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 722 }
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 723
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 724 range_cell = prop;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 725 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 726 if (!pci_resource_len(pdev, i))
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 727 continue;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 728 /* highest 4 bits of address are bar index */
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 729 *(__be64 *)range_cell = cpu_to_be64((u64)i << 60);
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 730 range_cell += 2;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 731 if (addr_ncells == 2)
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 732 *(__be64 *)range_cell = cpu_to_be64((u64)pci_resource_start(pdev, i));
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 733 else
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 734 *(__be32 *)range_cell = cpu_to_be32((u32)pci_resource_start(pdev, i));
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 735
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 736 range_cell += addr_ncells;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 737 *(__be64 *)range_cell = cpu_to_be64((u64)pci_resource_len(pdev, i));
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 738 range_cell += 2;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 739 }
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 740
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 741 /* error out if there is not PCI BAR been found */
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 742 if ((void *)range_cell == prop) {
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 743 ret = -EINVAL;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 744 goto cleanup;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 745 }
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 746
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 747 ret = of_ep_add_property(dev, &proplist, "ranges", (void *)range_cell - prop, prop);
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 748 kfree(prop);
^^^^^^^^^^^^
Free
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 749 if (ret)
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 750 goto cleanup;
^^^^^^^^^^^^^
Double free after goto.
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 751
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 752 node->properties = proplist;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 753 ret = of_attach_node(node);
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 754 if (ret)
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 755 goto cleanup;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 756
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 757 devres_add(dev, node);
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 758
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 759 return 0;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 760
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 761 cleanup:
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 @762 kfree(prop);
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 763 if (node)
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 764 devres_free(node);
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 765
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 766 return ret;
3a2c08c0f0ef77 Lizhi Hou 2022-03-04 767 }
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
next parent reply other threads:[~2022-03-10 10:03 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-09 19:14 kernel test robot [this message]
2022-03-10 10:02 ` [PATCH V1 RESEND 1/4] pci: add interface to create pci-ep device tree node Dan Carpenter
2022-03-10 10:02 ` Dan Carpenter
-- strict thread matches above, loose matches on Subject: below --
2022-03-09 6:51 kernel test robot
2022-03-05 5:23 [PATCH V1 RESEND 0/4] Infrastructure to define apertures in a PCIe device with a flattened device tree Lizhi Hou
2022-03-05 5:23 ` [PATCH V1 RESEND 1/4] pci: add interface to create pci-ep device tree node Lizhi Hou
2022-03-10 19:34 ` Bjorn Helgaas
2022-06-21 15:12 ` Manivannan Sadhasivam
2022-03-05 5:23 ` [PATCH V1 RESEND 2/4] Documentation: devicetree: bindings: add binding for PCIe endpoint bus Lizhi Hou
2022-03-06 15:37 ` Tom Rix
2022-03-07 14:07 ` Rob Herring
2022-04-22 21:57 ` Lizhi Hou
2022-05-13 15:19 ` Lizhi Hou
2022-06-21 15:06 ` Manivannan Sadhasivam
2022-03-05 5:23 ` [PATCH V1 RESEND 3/4] fpga: xrt: management physical function driver Lizhi Hou
2022-06-21 15:16 ` Manivannan Sadhasivam
2023-06-30 16:38 ` Bjorn Helgaas
2022-03-05 5:23 ` [PATCH V1 RESEND 4/4] of: enhance overlay applying interface to specific target base node Lizhi Hou
2022-03-10 20:07 ` Rob Herring
2022-03-10 19:27 ` [PATCH V1 RESEND 0/4] Infrastructure to define apertures in a PCIe device with a flattened device tree Bjorn Helgaas
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=202203100338.8jox1rCr-lkp@intel.com \
--to=dan.carpenter@oracle.com \
--cc=devicetree@vger.kernel.org \
--cc=dwmw2@infradead.org \
--cc=kbuild-all@lists.01.org \
--cc=kbuild@lists.01.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lizhi.hou@xilinx.com \
--cc=lkp@intel.com \
--cc=max.zhen@xilinx.com \
--cc=maxz@xilinx.com \
--cc=mdf@kernel.org \
--cc=michal.simek@xilinx.com \
--cc=robh@kernel.org \
--cc=sonal.santan@xilinx.com \
--cc=stefanos@xilinx.com \
--cc=trix@redhat.com \
--cc=yilun.xu@intel.com \
--cc=yliu@xilinx.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.