* [PATCH v10 0/6] Clock and PCIe support for Airoha EN7523 SoC @ 2022-03-14 8:44 ` Felix Fietkau 0 siblings, 0 replies; 39+ messages in thread From: Felix Fietkau @ 2022-03-14 8:44 UTC (permalink / raw) To: soc, Matthias Brugger; +Cc: linux-mediatek, linux-arm-kernel This patchset adds the remaining patches needed from the last Airoha EN7523 SoC support series Felix Fietkau (4): clk: en7523: Add clock driver for Airoha EN7523 SoC ARM: dts: add clock support for Airoha EN7523 PCI: mediatek: Allow building for ARCH_AIROHA ARM: dts: Add PCIe support for Airoha EN7523 John Crispin (2): dt-bindings: Add en7523-scu device tree binding documentation dt-bindings: PCI: Add support for Airoha EN7532 .../bindings/clock/airoha,en7523-scu.yaml | 58 +++ .../devicetree/bindings/pci/mediatek-pcie.txt | 1 + arch/arm/boot/dts/en7523-evb.dts | 8 + arch/arm/boot/dts/en7523.dtsi | 66 ++++ drivers/clk/Kconfig | 9 + drivers/clk/Makefile | 1 + drivers/clk/clk-en7523.c | 351 ++++++++++++++++++ drivers/pci/controller/Kconfig | 2 +- include/dt-bindings/clock/en7523-clk.h | 17 + 9 files changed, 512 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml create mode 100644 drivers/clk/clk-en7523.c create mode 100644 include/dt-bindings/clock/en7523-clk.h -- 2.35.1 ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v10 0/6] Clock and PCIe support for Airoha EN7523 SoC @ 2022-03-14 8:44 ` Felix Fietkau 0 siblings, 0 replies; 39+ messages in thread From: Felix Fietkau @ 2022-03-14 8:44 UTC (permalink / raw) To: soc, Matthias Brugger; +Cc: linux-mediatek, linux-arm-kernel This patchset adds the remaining patches needed from the last Airoha EN7523 SoC support series Felix Fietkau (4): clk: en7523: Add clock driver for Airoha EN7523 SoC ARM: dts: add clock support for Airoha EN7523 PCI: mediatek: Allow building for ARCH_AIROHA ARM: dts: Add PCIe support for Airoha EN7523 John Crispin (2): dt-bindings: Add en7523-scu device tree binding documentation dt-bindings: PCI: Add support for Airoha EN7532 .../bindings/clock/airoha,en7523-scu.yaml | 58 +++ .../devicetree/bindings/pci/mediatek-pcie.txt | 1 + arch/arm/boot/dts/en7523-evb.dts | 8 + arch/arm/boot/dts/en7523.dtsi | 66 ++++ drivers/clk/Kconfig | 9 + drivers/clk/Makefile | 1 + drivers/clk/clk-en7523.c | 351 ++++++++++++++++++ drivers/pci/controller/Kconfig | 2 +- include/dt-bindings/clock/en7523-clk.h | 17 + 9 files changed, 512 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml create mode 100644 drivers/clk/clk-en7523.c create mode 100644 include/dt-bindings/clock/en7523-clk.h -- 2.35.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v10 0/6] Clock and PCIe support for Airoha EN7523 SoC @ 2022-03-14 8:44 ` Felix Fietkau 0 siblings, 0 replies; 39+ messages in thread From: Felix Fietkau @ 2022-03-14 8:44 UTC (permalink / raw) To: soc, Matthias Brugger; +Cc: linux-mediatek, linux-arm-kernel This patchset adds the remaining patches needed from the last Airoha EN7523 SoC support series Felix Fietkau (4): clk: en7523: Add clock driver for Airoha EN7523 SoC ARM: dts: add clock support for Airoha EN7523 PCI: mediatek: Allow building for ARCH_AIROHA ARM: dts: Add PCIe support for Airoha EN7523 John Crispin (2): dt-bindings: Add en7523-scu device tree binding documentation dt-bindings: PCI: Add support for Airoha EN7532 .../bindings/clock/airoha,en7523-scu.yaml | 58 +++ .../devicetree/bindings/pci/mediatek-pcie.txt | 1 + arch/arm/boot/dts/en7523-evb.dts | 8 + arch/arm/boot/dts/en7523.dtsi | 66 ++++ drivers/clk/Kconfig | 9 + drivers/clk/Makefile | 1 + drivers/clk/clk-en7523.c | 351 ++++++++++++++++++ drivers/pci/controller/Kconfig | 2 +- include/dt-bindings/clock/en7523-clk.h | 17 + 9 files changed, 512 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml create mode 100644 drivers/clk/clk-en7523.c create mode 100644 include/dt-bindings/clock/en7523-clk.h -- 2.35.1 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v10 1/6] dt-bindings: Add en7523-scu device tree binding documentation 2022-03-14 8:44 ` Felix Fietkau (?) @ 2022-03-14 8:44 ` Felix Fietkau -1 siblings, 0 replies; 39+ messages in thread From: Felix Fietkau @ 2022-03-14 8:44 UTC (permalink / raw) To: soc, Michael Turquette, Stephen Boyd, Rob Herring Cc: linux-mediatek, linux-arm-kernel, John Crispin, Rob Herring, linux-clk, devicetree, linux-kernel From: John Crispin <john@phrozen.org> Adds device tree binding documentation for clocks in the EN7523 SOC. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Felix Fietkau <nbd@nbd.name> Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Felix Fietkau <nbd@nbd.name> --- .../bindings/clock/airoha,en7523-scu.yaml | 58 +++++++++++++++++++ include/dt-bindings/clock/en7523-clk.h | 17 ++++++ 2 files changed, 75 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml create mode 100644 include/dt-bindings/clock/en7523-clk.h diff --git a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml new file mode 100644 index 000000000000..d60e74654809 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/airoha,en7523-scu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: EN7523 Clock Device Tree Bindings + +maintainers: + - Felix Fietkau <nbd@nbd.name> + - John Crispin <nbd@nbd.name> + +description: | + This node defines the System Control Unit of the EN7523 SoC, + a collection of registers configuring many different aspects of the SoC. + + The clock driver uses it to read and configure settings of the + PLL controller, which provides clocks for the CPU, the bus and + other SoC internal peripherals. + + Each clock is assigned an identifier and client nodes use this identifier + to specify which clock they consume. + + All these identifiers can be found in: + [1]: <include/dt-bindings/clock/en7523-clk.h>. + + The clocks are provided inside a system controller node. + +properties: + compatible: + items: + - const: airoha,en7523-scu + + reg: + maxItems: 2 + + "#clock-cells": + description: + The first cell indicates the clock number, see [1] for available + clocks. + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/en7523-clk.h> + scu: system-controller@1fa20000 { + compatible = "airoha,en7523-scu"; + reg = <0x1fa20000 0x400>, + <0x1fb00000 0x1000>; + #clock-cells = <1>; + }; diff --git a/include/dt-bindings/clock/en7523-clk.h b/include/dt-bindings/clock/en7523-clk.h new file mode 100644 index 000000000000..717d23a5e5ae --- /dev/null +++ b/include/dt-bindings/clock/en7523-clk.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ +#define _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ + +#define EN7523_CLK_GSW 0 +#define EN7523_CLK_EMI 1 +#define EN7523_CLK_BUS 2 +#define EN7523_CLK_SLIC 3 +#define EN7523_CLK_SPI 4 +#define EN7523_CLK_NPU 5 +#define EN7523_CLK_CRYPTO 6 +#define EN7523_CLK_PCIE 7 + +#define EN7523_NUM_CLOCKS 8 + +#endif /* _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ */ -- 2.35.1 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v10 1/6] dt-bindings: Add en7523-scu device tree binding documentation @ 2022-03-14 8:44 ` Felix Fietkau 0 siblings, 0 replies; 39+ messages in thread From: Felix Fietkau @ 2022-03-14 8:44 UTC (permalink / raw) To: soc, Michael Turquette, Stephen Boyd, Rob Herring Cc: linux-mediatek, linux-arm-kernel, John Crispin, Rob Herring, linux-clk, devicetree, linux-kernel From: John Crispin <john@phrozen.org> Adds device tree binding documentation for clocks in the EN7523 SOC. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Felix Fietkau <nbd@nbd.name> Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Felix Fietkau <nbd@nbd.name> --- .../bindings/clock/airoha,en7523-scu.yaml | 58 +++++++++++++++++++ include/dt-bindings/clock/en7523-clk.h | 17 ++++++ 2 files changed, 75 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml create mode 100644 include/dt-bindings/clock/en7523-clk.h diff --git a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml new file mode 100644 index 000000000000..d60e74654809 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/airoha,en7523-scu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: EN7523 Clock Device Tree Bindings + +maintainers: + - Felix Fietkau <nbd@nbd.name> + - John Crispin <nbd@nbd.name> + +description: | + This node defines the System Control Unit of the EN7523 SoC, + a collection of registers configuring many different aspects of the SoC. + + The clock driver uses it to read and configure settings of the + PLL controller, which provides clocks for the CPU, the bus and + other SoC internal peripherals. + + Each clock is assigned an identifier and client nodes use this identifier + to specify which clock they consume. + + All these identifiers can be found in: + [1]: <include/dt-bindings/clock/en7523-clk.h>. + + The clocks are provided inside a system controller node. + +properties: + compatible: + items: + - const: airoha,en7523-scu + + reg: + maxItems: 2 + + "#clock-cells": + description: + The first cell indicates the clock number, see [1] for available + clocks. + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/en7523-clk.h> + scu: system-controller@1fa20000 { + compatible = "airoha,en7523-scu"; + reg = <0x1fa20000 0x400>, + <0x1fb00000 0x1000>; + #clock-cells = <1>; + }; diff --git a/include/dt-bindings/clock/en7523-clk.h b/include/dt-bindings/clock/en7523-clk.h new file mode 100644 index 000000000000..717d23a5e5ae --- /dev/null +++ b/include/dt-bindings/clock/en7523-clk.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ +#define _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ + +#define EN7523_CLK_GSW 0 +#define EN7523_CLK_EMI 1 +#define EN7523_CLK_BUS 2 +#define EN7523_CLK_SLIC 3 +#define EN7523_CLK_SPI 4 +#define EN7523_CLK_NPU 5 +#define EN7523_CLK_CRYPTO 6 +#define EN7523_CLK_PCIE 7 + +#define EN7523_NUM_CLOCKS 8 + +#endif /* _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ */ -- 2.35.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v10 1/6] dt-bindings: Add en7523-scu device tree binding documentation @ 2022-03-14 8:44 ` Felix Fietkau 0 siblings, 0 replies; 39+ messages in thread From: Felix Fietkau @ 2022-03-14 8:44 UTC (permalink / raw) To: soc, Michael Turquette, Stephen Boyd, Rob Herring Cc: linux-mediatek, linux-arm-kernel, John Crispin, Rob Herring, linux-clk, devicetree, linux-kernel From: John Crispin <john@phrozen.org> Adds device tree binding documentation for clocks in the EN7523 SOC. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Felix Fietkau <nbd@nbd.name> Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Felix Fietkau <nbd@nbd.name> --- .../bindings/clock/airoha,en7523-scu.yaml | 58 +++++++++++++++++++ include/dt-bindings/clock/en7523-clk.h | 17 ++++++ 2 files changed, 75 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml create mode 100644 include/dt-bindings/clock/en7523-clk.h diff --git a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml new file mode 100644 index 000000000000..d60e74654809 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/airoha,en7523-scu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: EN7523 Clock Device Tree Bindings + +maintainers: + - Felix Fietkau <nbd@nbd.name> + - John Crispin <nbd@nbd.name> + +description: | + This node defines the System Control Unit of the EN7523 SoC, + a collection of registers configuring many different aspects of the SoC. + + The clock driver uses it to read and configure settings of the + PLL controller, which provides clocks for the CPU, the bus and + other SoC internal peripherals. + + Each clock is assigned an identifier and client nodes use this identifier + to specify which clock they consume. + + All these identifiers can be found in: + [1]: <include/dt-bindings/clock/en7523-clk.h>. + + The clocks are provided inside a system controller node. + +properties: + compatible: + items: + - const: airoha,en7523-scu + + reg: + maxItems: 2 + + "#clock-cells": + description: + The first cell indicates the clock number, see [1] for available + clocks. + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/en7523-clk.h> + scu: system-controller@1fa20000 { + compatible = "airoha,en7523-scu"; + reg = <0x1fa20000 0x400>, + <0x1fb00000 0x1000>; + #clock-cells = <1>; + }; diff --git a/include/dt-bindings/clock/en7523-clk.h b/include/dt-bindings/clock/en7523-clk.h new file mode 100644 index 000000000000..717d23a5e5ae --- /dev/null +++ b/include/dt-bindings/clock/en7523-clk.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ +#define _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ + +#define EN7523_CLK_GSW 0 +#define EN7523_CLK_EMI 1 +#define EN7523_CLK_BUS 2 +#define EN7523_CLK_SLIC 3 +#define EN7523_CLK_SPI 4 +#define EN7523_CLK_NPU 5 +#define EN7523_CLK_CRYPTO 6 +#define EN7523_CLK_PCIE 7 + +#define EN7523_NUM_CLOCKS 8 + +#endif /* _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ */ -- 2.35.1 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [PATCH v10 1/6] dt-bindings: Add en7523-scu device tree binding documentation 2022-03-14 8:44 ` Felix Fietkau (?) @ 2022-04-23 2:12 ` Stephen Boyd -1 siblings, 0 replies; 39+ messages in thread From: Stephen Boyd @ 2022-04-23 2:12 UTC (permalink / raw) To: Felix Fietkau, Michael Turquette, Rob Herring, soc Cc: linux-mediatek, linux-arm-kernel, John Crispin, Rob Herring, linux-clk, devicetree, linux-kernel Quoting Felix Fietkau (2022-03-14 01:44:03) > From: John Crispin <john@phrozen.org> > > Adds device tree binding documentation for clocks in the EN7523 SOC. > > Reviewed-by: Rob Herring <robh@kernel.org> > Signed-off-by: Felix Fietkau <nbd@nbd.name> > Signed-off-by: John Crispin <john@phrozen.org> > Signed-off-by: Felix Fietkau <nbd@nbd.name> > --- Applied to clk-next ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v10 1/6] dt-bindings: Add en7523-scu device tree binding documentation @ 2022-04-23 2:12 ` Stephen Boyd 0 siblings, 0 replies; 39+ messages in thread From: Stephen Boyd @ 2022-04-23 2:12 UTC (permalink / raw) To: Felix Fietkau, Michael Turquette, Rob Herring, soc Cc: linux-mediatek, linux-arm-kernel, John Crispin, Rob Herring, linux-clk, devicetree, linux-kernel Quoting Felix Fietkau (2022-03-14 01:44:03) > From: John Crispin <john@phrozen.org> > > Adds device tree binding documentation for clocks in the EN7523 SOC. > > Reviewed-by: Rob Herring <robh@kernel.org> > Signed-off-by: Felix Fietkau <nbd@nbd.name> > Signed-off-by: John Crispin <john@phrozen.org> > Signed-off-by: Felix Fietkau <nbd@nbd.name> > --- Applied to clk-next _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v10 1/6] dt-bindings: Add en7523-scu device tree binding documentation @ 2022-04-23 2:12 ` Stephen Boyd 0 siblings, 0 replies; 39+ messages in thread From: Stephen Boyd @ 2022-04-23 2:12 UTC (permalink / raw) To: Felix Fietkau, Michael Turquette, Rob Herring, soc Cc: linux-mediatek, linux-arm-kernel, John Crispin, Rob Herring, linux-clk, devicetree, linux-kernel Quoting Felix Fietkau (2022-03-14 01:44:03) > From: John Crispin <john@phrozen.org> > > Adds device tree binding documentation for clocks in the EN7523 SOC. > > Reviewed-by: Rob Herring <robh@kernel.org> > Signed-off-by: Felix Fietkau <nbd@nbd.name> > Signed-off-by: John Crispin <john@phrozen.org> > Signed-off-by: Felix Fietkau <nbd@nbd.name> > --- Applied to clk-next _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v10 1/6] dt-bindings: Add en7523-scu device tree binding documentation 2022-03-14 8:44 ` Felix Fietkau (?) @ 2022-04-23 2:13 ` Stephen Boyd -1 siblings, 0 replies; 39+ messages in thread From: Stephen Boyd @ 2022-04-23 2:13 UTC (permalink / raw) To: Felix Fietkau, Michael Turquette, Rob Herring, soc Cc: linux-mediatek, linux-arm-kernel, John Crispin, Rob Herring, linux-clk, devicetree, linux-kernel Quoting Felix Fietkau (2022-03-14 01:44:03) > From: John Crispin <john@phrozen.org> > > Adds device tree binding documentation for clocks in the EN7523 SOC. > > Reviewed-by: Rob Herring <robh@kernel.org> > Signed-off-by: Felix Fietkau <nbd@nbd.name> > Signed-off-by: John Crispin <john@phrozen.org> > Signed-off-by: Felix Fietkau <nbd@nbd.name> > --- I removed the duplicate SoB ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v10 1/6] dt-bindings: Add en7523-scu device tree binding documentation @ 2022-04-23 2:13 ` Stephen Boyd 0 siblings, 0 replies; 39+ messages in thread From: Stephen Boyd @ 2022-04-23 2:13 UTC (permalink / raw) To: Felix Fietkau, Michael Turquette, Rob Herring, soc Cc: linux-mediatek, linux-arm-kernel, John Crispin, Rob Herring, linux-clk, devicetree, linux-kernel Quoting Felix Fietkau (2022-03-14 01:44:03) > From: John Crispin <john@phrozen.org> > > Adds device tree binding documentation for clocks in the EN7523 SOC. > > Reviewed-by: Rob Herring <robh@kernel.org> > Signed-off-by: Felix Fietkau <nbd@nbd.name> > Signed-off-by: John Crispin <john@phrozen.org> > Signed-off-by: Felix Fietkau <nbd@nbd.name> > --- I removed the duplicate SoB _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v10 1/6] dt-bindings: Add en7523-scu device tree binding documentation @ 2022-04-23 2:13 ` Stephen Boyd 0 siblings, 0 replies; 39+ messages in thread From: Stephen Boyd @ 2022-04-23 2:13 UTC (permalink / raw) To: Felix Fietkau, Michael Turquette, Rob Herring, soc Cc: linux-mediatek, linux-arm-kernel, John Crispin, Rob Herring, linux-clk, devicetree, linux-kernel Quoting Felix Fietkau (2022-03-14 01:44:03) > From: John Crispin <john@phrozen.org> > > Adds device tree binding documentation for clocks in the EN7523 SOC. > > Reviewed-by: Rob Herring <robh@kernel.org> > Signed-off-by: Felix Fietkau <nbd@nbd.name> > Signed-off-by: John Crispin <john@phrozen.org> > Signed-off-by: Felix Fietkau <nbd@nbd.name> > --- I removed the duplicate SoB _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v10 2/6] clk: en7523: Add clock driver for Airoha EN7523 SoC 2022-03-14 8:44 ` Felix Fietkau (?) @ 2022-03-14 8:44 ` Felix Fietkau -1 siblings, 0 replies; 39+ messages in thread From: Felix Fietkau @ 2022-03-14 8:44 UTC (permalink / raw) To: soc, Michael Turquette, Stephen Boyd Cc: linux-mediatek, linux-arm-kernel, linux-kernel, linux-clk This driver only registers fixed rate clocks, since the clocks are fully initialized by the boot loader and should not be changed later, according to Airoha. Signed-off-by: Felix Fietkau <nbd@nbd.name> --- drivers/clk/Kconfig | 9 + drivers/clk/Makefile | 1 + drivers/clk/clk-en7523.c | 351 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 361 insertions(+) create mode 100644 drivers/clk/clk-en7523.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index ad4256d54361..4765e4c6f2a1 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -200,6 +200,15 @@ config COMMON_CLK_CS2000_CP help If you say yes here you get support for the CS2000 clock multiplier. +config COMMON_CLK_EN7523 + bool "Clock driver for Airoha EN7523 SoC system clocks" + depends on OF + depends on ARCH_AIROHA || COMPILE_TEST + default ARCH_AIROHA + help + This driver provides the fixed clocks and gates present on Airoha + ARM silicon. + config COMMON_CLK_FSL_FLEXSPI tristate "Clock driver for FlexSPI on Layerscape SoCs" depends on ARCH_LAYERSCAPE || COMPILE_TEST diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 16e588630472..da8dd3ab304f 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o obj-$(CONFIG_ARCH_SPARX5) += clk-sparx5.o +obj-$(CONFIG_COMMON_CLK_EN7523) += clk-en7523.o obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o obj-$(CONFIG_COMMON_CLK_FSL_FLEXSPI) += clk-fsl-flexspi.o obj-$(CONFIG_COMMON_CLK_FSL_SAI) += clk-fsl-sai.o diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c new file mode 100644 index 000000000000..076a70c2e173 --- /dev/null +++ b/drivers/clk/clk-en7523.c @@ -0,0 +1,351 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <linux/delay.h> +#include <linux/clk-provider.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <dt-bindings/clock/en7523-clk.h> + +#define REG_PCI_CONTROL 0x88 +#define REG_PCI_CONTROL_PERSTOUT BIT(29) +#define REG_PCI_CONTROL_PERSTOUT1 BIT(26) +#define REG_PCI_CONTROL_REFCLK_EN1 BIT(22) +#define REG_GSW_CLK_DIV_SEL 0x1b4 +#define REG_EMI_CLK_DIV_SEL 0x1b8 +#define REG_BUS_CLK_DIV_SEL 0x1bc +#define REG_SPI_CLK_DIV_SEL 0x1c4 +#define REG_SPI_CLK_FREQ_SEL 0x1c8 +#define REG_NPU_CLK_DIV_SEL 0x1fc +#define REG_CRYPTO_CLKSRC 0x200 +#define REG_RESET_CONTROL 0x834 +#define REG_RESET_CONTROL_PCIEHB BIT(29) +#define REG_RESET_CONTROL_PCIE1 BIT(27) +#define REG_RESET_CONTROL_PCIE2 BIT(26) + +struct en_clk_desc { + int id; + const char *name; + u32 base_reg; + u8 base_bits; + u8 base_shift; + union { + const unsigned int *base_values; + unsigned int base_value; + }; + size_t n_base_values; + + u16 div_reg; + u8 div_bits; + u8 div_shift; + u16 div_val0; + u8 div_step; +}; + +struct en_clk_gate { + void __iomem *base; + struct clk_hw hw; +}; + +static const u32 gsw_base[] = { 400000000, 500000000 }; +static const u32 emi_base[] = { 333000000, 400000000 }; +static const u32 bus_base[] = { 500000000, 540000000 }; +static const u32 slic_base[] = { 100000000, 3125000 }; +static const u32 npu_base[] = { 333000000, 400000000, 500000000 }; + +static const struct en_clk_desc en7523_base_clks[] = { + { + .id = EN7523_CLK_GSW, + .name = "gsw", + + .base_reg = REG_GSW_CLK_DIV_SEL, + .base_bits = 1, + .base_shift = 8, + .base_values = gsw_base, + .n_base_values = ARRAY_SIZE(gsw_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + }, { + .id = EN7523_CLK_EMI, + .name = "emi", + + .base_reg = REG_EMI_CLK_DIV_SEL, + .base_bits = 1, + .base_shift = 8, + .base_values = emi_base, + .n_base_values = ARRAY_SIZE(emi_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + }, { + .id = EN7523_CLK_BUS, + .name = "bus", + + .base_reg = REG_BUS_CLK_DIV_SEL, + .base_bits = 1, + .base_shift = 8, + .base_values = bus_base, + .n_base_values = ARRAY_SIZE(bus_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + }, { + .id = EN7523_CLK_SLIC, + .name = "slic", + + .base_reg = REG_SPI_CLK_FREQ_SEL, + .base_bits = 1, + .base_shift = 0, + .base_values = slic_base, + .n_base_values = ARRAY_SIZE(slic_base), + + .div_reg = REG_SPI_CLK_DIV_SEL, + .div_bits = 5, + .div_shift = 24, + .div_val0 = 20, + .div_step = 2, + }, { + .id = EN7523_CLK_SPI, + .name = "spi", + + .base_reg = REG_SPI_CLK_DIV_SEL, + + .base_value = 400000000, + + .div_bits = 5, + .div_shift = 8, + .div_val0 = 40, + .div_step = 2, + }, { + .id = EN7523_CLK_NPU, + .name = "npu", + + .base_reg = REG_NPU_CLK_DIV_SEL, + .base_bits = 2, + .base_shift = 8, + .base_values = npu_base, + .n_base_values = ARRAY_SIZE(npu_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + }, { + .id = EN7523_CLK_CRYPTO, + .name = "crypto", + + .base_reg = REG_CRYPTO_CLKSRC, + .base_bits = 1, + .base_shift = 8, + .base_values = emi_base, + .n_base_values = ARRAY_SIZE(emi_base), + } +}; + +static const struct of_device_id of_match_clk_en7523[] = { + { .compatible = "airoha,en7523-scu", }, + { /* sentinel */ } +}; + +static unsigned int en7523_get_base_rate(void __iomem *base, unsigned int i) +{ + const struct en_clk_desc *desc = &en7523_base_clks[i]; + u32 val; + + if (!desc->base_bits) + return desc->base_value; + + val = readl(base + desc->base_reg); + val >>= desc->base_shift; + val &= (1 << desc->base_bits) - 1; + + if (val >= desc->n_base_values) + return 0; + + return desc->base_values[val]; +} + +static u32 en7523_get_div(void __iomem *base, int i) +{ + const struct en_clk_desc *desc = &en7523_base_clks[i]; + u32 reg, val; + + if (!desc->div_bits) + return 1; + + reg = desc->div_reg ? desc->div_reg : desc->base_reg; + val = readl(base + reg); + val >>= desc->div_shift; + val &= (1 << desc->div_bits) - 1; + + if (!val && desc->div_val0) + return desc->div_val0; + + return (val + 1) * desc->div_step; +} + +static int en7523_pci_is_enabled(struct clk_hw *hw) +{ + struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); + + return !!(readl(cg->base + REG_PCI_CONTROL) & REG_PCI_CONTROL_REFCLK_EN1); +} + +static int en7523_pci_prepare(struct clk_hw *hw) +{ + struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); + void __iomem *np_base = cg->base; + u32 val, mask; + + /* Need to pull device low before reset */ + val = readl(np_base + REG_PCI_CONTROL); + val &= ~(REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT); + writel(val, np_base + REG_PCI_CONTROL); + usleep_range(1000, 2000); + + /* Enable PCIe port 1 */ + val |= REG_PCI_CONTROL_REFCLK_EN1; + writel(val, np_base + REG_PCI_CONTROL); + usleep_range(1000, 2000); + + /* Reset to default */ + val = readl(np_base + REG_RESET_CONTROL); + mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 | + REG_RESET_CONTROL_PCIEHB; + writel(val & ~mask, np_base + REG_RESET_CONTROL); + usleep_range(1000, 2000); + writel(val | mask, np_base + REG_RESET_CONTROL); + msleep(100); + writel(val & ~mask, np_base + REG_RESET_CONTROL); + usleep_range(5000, 10000); + + /* Release device */ + mask = REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT; + val = readl(np_base + REG_PCI_CONTROL); + writel(val & ~mask, np_base + REG_PCI_CONTROL); + usleep_range(1000, 2000); + writel(val | mask, np_base + REG_PCI_CONTROL); + msleep(250); + + return 0; +} + +static void en7523_pci_unprepare(struct clk_hw *hw) +{ + struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); + void __iomem *np_base = cg->base; + u32 val; + + val = readl(np_base + REG_PCI_CONTROL); + val &= ~REG_PCI_CONTROL_REFCLK_EN1; + writel(val, np_base + REG_PCI_CONTROL); +} + +static struct clk_hw *en7523_register_pcie_clk(struct device *dev, + void __iomem *np_base) +{ + static const struct clk_ops pcie_gate_ops = { + .is_enabled = en7523_pci_is_enabled, + .prepare = en7523_pci_prepare, + .unprepare = en7523_pci_unprepare, + }; + struct clk_init_data init = { + .name = "pcie", + .ops = &pcie_gate_ops, + }; + struct en_clk_gate *cg; + + cg = devm_kzalloc(dev, sizeof(*cg), GFP_KERNEL); + if (!cg) + return NULL; + + cg->base = np_base; + cg->hw.init = &init; + en7523_pci_unprepare(&cg->hw); + + if (clk_hw_register(dev, &cg->hw)) + return NULL; + + return &cg->hw; +} + +static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data, + void __iomem *base, void __iomem *np_base) +{ + struct clk_hw *hw; + u32 rate; + int i; + + for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) { + const struct en_clk_desc *desc = &en7523_base_clks[i]; + + rate = en7523_get_base_rate(base, i); + rate /= en7523_get_div(base, i); + + hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); + if (IS_ERR(hw)) { + pr_err("Failed to register clk %s: %ld\n", + desc->name, PTR_ERR(hw)); + continue; + } + + clk_data->hws[desc->id] = hw; + } + + hw = en7523_register_pcie_clk(dev, np_base); + clk_data->hws[EN7523_CLK_PCIE] = hw; + + clk_data->num = EN7523_NUM_CLOCKS; +} + +static int en7523_clk_probe(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + struct clk_hw_onecell_data *clk_data; + void __iomem *base, *np_base; + int r; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + np_base = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(base)) + return PTR_ERR(np_base); + + clk_data = devm_kzalloc(&pdev->dev, + struct_size(clk_data, hws, EN7523_NUM_CLOCKS), + GFP_KERNEL); + if (!clk_data) + return -ENOMEM; + + en7523_register_clocks(&pdev->dev, clk_data, base, np_base); + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (r) + dev_err(&pdev->dev, + "could not register clock provider: %s: %d\n", + pdev->name, r); + + return r; +} + +static struct platform_driver clk_en7523_drv = { + .probe = en7523_clk_probe, + .driver = { + .name = "clk-en7523", + .of_match_table = of_match_clk_en7523, + .suppress_bind_attrs = true, + }, +}; + +static int __init clk_en7523_init(void) +{ + return platform_driver_register(&clk_en7523_drv); +} + +arch_initcall(clk_en7523_init); -- 2.35.1 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v10 2/6] clk: en7523: Add clock driver for Airoha EN7523 SoC @ 2022-03-14 8:44 ` Felix Fietkau 0 siblings, 0 replies; 39+ messages in thread From: Felix Fietkau @ 2022-03-14 8:44 UTC (permalink / raw) To: soc, Michael Turquette, Stephen Boyd Cc: linux-mediatek, linux-arm-kernel, linux-kernel, linux-clk This driver only registers fixed rate clocks, since the clocks are fully initialized by the boot loader and should not be changed later, according to Airoha. Signed-off-by: Felix Fietkau <nbd@nbd.name> --- drivers/clk/Kconfig | 9 + drivers/clk/Makefile | 1 + drivers/clk/clk-en7523.c | 351 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 361 insertions(+) create mode 100644 drivers/clk/clk-en7523.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index ad4256d54361..4765e4c6f2a1 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -200,6 +200,15 @@ config COMMON_CLK_CS2000_CP help If you say yes here you get support for the CS2000 clock multiplier. +config COMMON_CLK_EN7523 + bool "Clock driver for Airoha EN7523 SoC system clocks" + depends on OF + depends on ARCH_AIROHA || COMPILE_TEST + default ARCH_AIROHA + help + This driver provides the fixed clocks and gates present on Airoha + ARM silicon. + config COMMON_CLK_FSL_FLEXSPI tristate "Clock driver for FlexSPI on Layerscape SoCs" depends on ARCH_LAYERSCAPE || COMPILE_TEST diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 16e588630472..da8dd3ab304f 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o obj-$(CONFIG_ARCH_SPARX5) += clk-sparx5.o +obj-$(CONFIG_COMMON_CLK_EN7523) += clk-en7523.o obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o obj-$(CONFIG_COMMON_CLK_FSL_FLEXSPI) += clk-fsl-flexspi.o obj-$(CONFIG_COMMON_CLK_FSL_SAI) += clk-fsl-sai.o diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c new file mode 100644 index 000000000000..076a70c2e173 --- /dev/null +++ b/drivers/clk/clk-en7523.c @@ -0,0 +1,351 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <linux/delay.h> +#include <linux/clk-provider.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <dt-bindings/clock/en7523-clk.h> + +#define REG_PCI_CONTROL 0x88 +#define REG_PCI_CONTROL_PERSTOUT BIT(29) +#define REG_PCI_CONTROL_PERSTOUT1 BIT(26) +#define REG_PCI_CONTROL_REFCLK_EN1 BIT(22) +#define REG_GSW_CLK_DIV_SEL 0x1b4 +#define REG_EMI_CLK_DIV_SEL 0x1b8 +#define REG_BUS_CLK_DIV_SEL 0x1bc +#define REG_SPI_CLK_DIV_SEL 0x1c4 +#define REG_SPI_CLK_FREQ_SEL 0x1c8 +#define REG_NPU_CLK_DIV_SEL 0x1fc +#define REG_CRYPTO_CLKSRC 0x200 +#define REG_RESET_CONTROL 0x834 +#define REG_RESET_CONTROL_PCIEHB BIT(29) +#define REG_RESET_CONTROL_PCIE1 BIT(27) +#define REG_RESET_CONTROL_PCIE2 BIT(26) + +struct en_clk_desc { + int id; + const char *name; + u32 base_reg; + u8 base_bits; + u8 base_shift; + union { + const unsigned int *base_values; + unsigned int base_value; + }; + size_t n_base_values; + + u16 div_reg; + u8 div_bits; + u8 div_shift; + u16 div_val0; + u8 div_step; +}; + +struct en_clk_gate { + void __iomem *base; + struct clk_hw hw; +}; + +static const u32 gsw_base[] = { 400000000, 500000000 }; +static const u32 emi_base[] = { 333000000, 400000000 }; +static const u32 bus_base[] = { 500000000, 540000000 }; +static const u32 slic_base[] = { 100000000, 3125000 }; +static const u32 npu_base[] = { 333000000, 400000000, 500000000 }; + +static const struct en_clk_desc en7523_base_clks[] = { + { + .id = EN7523_CLK_GSW, + .name = "gsw", + + .base_reg = REG_GSW_CLK_DIV_SEL, + .base_bits = 1, + .base_shift = 8, + .base_values = gsw_base, + .n_base_values = ARRAY_SIZE(gsw_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + }, { + .id = EN7523_CLK_EMI, + .name = "emi", + + .base_reg = REG_EMI_CLK_DIV_SEL, + .base_bits = 1, + .base_shift = 8, + .base_values = emi_base, + .n_base_values = ARRAY_SIZE(emi_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + }, { + .id = EN7523_CLK_BUS, + .name = "bus", + + .base_reg = REG_BUS_CLK_DIV_SEL, + .base_bits = 1, + .base_shift = 8, + .base_values = bus_base, + .n_base_values = ARRAY_SIZE(bus_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + }, { + .id = EN7523_CLK_SLIC, + .name = "slic", + + .base_reg = REG_SPI_CLK_FREQ_SEL, + .base_bits = 1, + .base_shift = 0, + .base_values = slic_base, + .n_base_values = ARRAY_SIZE(slic_base), + + .div_reg = REG_SPI_CLK_DIV_SEL, + .div_bits = 5, + .div_shift = 24, + .div_val0 = 20, + .div_step = 2, + }, { + .id = EN7523_CLK_SPI, + .name = "spi", + + .base_reg = REG_SPI_CLK_DIV_SEL, + + .base_value = 400000000, + + .div_bits = 5, + .div_shift = 8, + .div_val0 = 40, + .div_step = 2, + }, { + .id = EN7523_CLK_NPU, + .name = "npu", + + .base_reg = REG_NPU_CLK_DIV_SEL, + .base_bits = 2, + .base_shift = 8, + .base_values = npu_base, + .n_base_values = ARRAY_SIZE(npu_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + }, { + .id = EN7523_CLK_CRYPTO, + .name = "crypto", + + .base_reg = REG_CRYPTO_CLKSRC, + .base_bits = 1, + .base_shift = 8, + .base_values = emi_base, + .n_base_values = ARRAY_SIZE(emi_base), + } +}; + +static const struct of_device_id of_match_clk_en7523[] = { + { .compatible = "airoha,en7523-scu", }, + { /* sentinel */ } +}; + +static unsigned int en7523_get_base_rate(void __iomem *base, unsigned int i) +{ + const struct en_clk_desc *desc = &en7523_base_clks[i]; + u32 val; + + if (!desc->base_bits) + return desc->base_value; + + val = readl(base + desc->base_reg); + val >>= desc->base_shift; + val &= (1 << desc->base_bits) - 1; + + if (val >= desc->n_base_values) + return 0; + + return desc->base_values[val]; +} + +static u32 en7523_get_div(void __iomem *base, int i) +{ + const struct en_clk_desc *desc = &en7523_base_clks[i]; + u32 reg, val; + + if (!desc->div_bits) + return 1; + + reg = desc->div_reg ? desc->div_reg : desc->base_reg; + val = readl(base + reg); + val >>= desc->div_shift; + val &= (1 << desc->div_bits) - 1; + + if (!val && desc->div_val0) + return desc->div_val0; + + return (val + 1) * desc->div_step; +} + +static int en7523_pci_is_enabled(struct clk_hw *hw) +{ + struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); + + return !!(readl(cg->base + REG_PCI_CONTROL) & REG_PCI_CONTROL_REFCLK_EN1); +} + +static int en7523_pci_prepare(struct clk_hw *hw) +{ + struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); + void __iomem *np_base = cg->base; + u32 val, mask; + + /* Need to pull device low before reset */ + val = readl(np_base + REG_PCI_CONTROL); + val &= ~(REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT); + writel(val, np_base + REG_PCI_CONTROL); + usleep_range(1000, 2000); + + /* Enable PCIe port 1 */ + val |= REG_PCI_CONTROL_REFCLK_EN1; + writel(val, np_base + REG_PCI_CONTROL); + usleep_range(1000, 2000); + + /* Reset to default */ + val = readl(np_base + REG_RESET_CONTROL); + mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 | + REG_RESET_CONTROL_PCIEHB; + writel(val & ~mask, np_base + REG_RESET_CONTROL); + usleep_range(1000, 2000); + writel(val | mask, np_base + REG_RESET_CONTROL); + msleep(100); + writel(val & ~mask, np_base + REG_RESET_CONTROL); + usleep_range(5000, 10000); + + /* Release device */ + mask = REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT; + val = readl(np_base + REG_PCI_CONTROL); + writel(val & ~mask, np_base + REG_PCI_CONTROL); + usleep_range(1000, 2000); + writel(val | mask, np_base + REG_PCI_CONTROL); + msleep(250); + + return 0; +} + +static void en7523_pci_unprepare(struct clk_hw *hw) +{ + struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); + void __iomem *np_base = cg->base; + u32 val; + + val = readl(np_base + REG_PCI_CONTROL); + val &= ~REG_PCI_CONTROL_REFCLK_EN1; + writel(val, np_base + REG_PCI_CONTROL); +} + +static struct clk_hw *en7523_register_pcie_clk(struct device *dev, + void __iomem *np_base) +{ + static const struct clk_ops pcie_gate_ops = { + .is_enabled = en7523_pci_is_enabled, + .prepare = en7523_pci_prepare, + .unprepare = en7523_pci_unprepare, + }; + struct clk_init_data init = { + .name = "pcie", + .ops = &pcie_gate_ops, + }; + struct en_clk_gate *cg; + + cg = devm_kzalloc(dev, sizeof(*cg), GFP_KERNEL); + if (!cg) + return NULL; + + cg->base = np_base; + cg->hw.init = &init; + en7523_pci_unprepare(&cg->hw); + + if (clk_hw_register(dev, &cg->hw)) + return NULL; + + return &cg->hw; +} + +static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data, + void __iomem *base, void __iomem *np_base) +{ + struct clk_hw *hw; + u32 rate; + int i; + + for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) { + const struct en_clk_desc *desc = &en7523_base_clks[i]; + + rate = en7523_get_base_rate(base, i); + rate /= en7523_get_div(base, i); + + hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); + if (IS_ERR(hw)) { + pr_err("Failed to register clk %s: %ld\n", + desc->name, PTR_ERR(hw)); + continue; + } + + clk_data->hws[desc->id] = hw; + } + + hw = en7523_register_pcie_clk(dev, np_base); + clk_data->hws[EN7523_CLK_PCIE] = hw; + + clk_data->num = EN7523_NUM_CLOCKS; +} + +static int en7523_clk_probe(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + struct clk_hw_onecell_data *clk_data; + void __iomem *base, *np_base; + int r; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + np_base = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(base)) + return PTR_ERR(np_base); + + clk_data = devm_kzalloc(&pdev->dev, + struct_size(clk_data, hws, EN7523_NUM_CLOCKS), + GFP_KERNEL); + if (!clk_data) + return -ENOMEM; + + en7523_register_clocks(&pdev->dev, clk_data, base, np_base); + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (r) + dev_err(&pdev->dev, + "could not register clock provider: %s: %d\n", + pdev->name, r); + + return r; +} + +static struct platform_driver clk_en7523_drv = { + .probe = en7523_clk_probe, + .driver = { + .name = "clk-en7523", + .of_match_table = of_match_clk_en7523, + .suppress_bind_attrs = true, + }, +}; + +static int __init clk_en7523_init(void) +{ + return platform_driver_register(&clk_en7523_drv); +} + +arch_initcall(clk_en7523_init); -- 2.35.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v10 2/6] clk: en7523: Add clock driver for Airoha EN7523 SoC @ 2022-03-14 8:44 ` Felix Fietkau 0 siblings, 0 replies; 39+ messages in thread From: Felix Fietkau @ 2022-03-14 8:44 UTC (permalink / raw) To: soc, Michael Turquette, Stephen Boyd Cc: linux-mediatek, linux-arm-kernel, linux-kernel, linux-clk This driver only registers fixed rate clocks, since the clocks are fully initialized by the boot loader and should not be changed later, according to Airoha. Signed-off-by: Felix Fietkau <nbd@nbd.name> --- drivers/clk/Kconfig | 9 + drivers/clk/Makefile | 1 + drivers/clk/clk-en7523.c | 351 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 361 insertions(+) create mode 100644 drivers/clk/clk-en7523.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index ad4256d54361..4765e4c6f2a1 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -200,6 +200,15 @@ config COMMON_CLK_CS2000_CP help If you say yes here you get support for the CS2000 clock multiplier. +config COMMON_CLK_EN7523 + bool "Clock driver for Airoha EN7523 SoC system clocks" + depends on OF + depends on ARCH_AIROHA || COMPILE_TEST + default ARCH_AIROHA + help + This driver provides the fixed clocks and gates present on Airoha + ARM silicon. + config COMMON_CLK_FSL_FLEXSPI tristate "Clock driver for FlexSPI on Layerscape SoCs" depends on ARCH_LAYERSCAPE || COMPILE_TEST diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 16e588630472..da8dd3ab304f 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o obj-$(CONFIG_ARCH_SPARX5) += clk-sparx5.o +obj-$(CONFIG_COMMON_CLK_EN7523) += clk-en7523.o obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o obj-$(CONFIG_COMMON_CLK_FSL_FLEXSPI) += clk-fsl-flexspi.o obj-$(CONFIG_COMMON_CLK_FSL_SAI) += clk-fsl-sai.o diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c new file mode 100644 index 000000000000..076a70c2e173 --- /dev/null +++ b/drivers/clk/clk-en7523.c @@ -0,0 +1,351 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <linux/delay.h> +#include <linux/clk-provider.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <dt-bindings/clock/en7523-clk.h> + +#define REG_PCI_CONTROL 0x88 +#define REG_PCI_CONTROL_PERSTOUT BIT(29) +#define REG_PCI_CONTROL_PERSTOUT1 BIT(26) +#define REG_PCI_CONTROL_REFCLK_EN1 BIT(22) +#define REG_GSW_CLK_DIV_SEL 0x1b4 +#define REG_EMI_CLK_DIV_SEL 0x1b8 +#define REG_BUS_CLK_DIV_SEL 0x1bc +#define REG_SPI_CLK_DIV_SEL 0x1c4 +#define REG_SPI_CLK_FREQ_SEL 0x1c8 +#define REG_NPU_CLK_DIV_SEL 0x1fc +#define REG_CRYPTO_CLKSRC 0x200 +#define REG_RESET_CONTROL 0x834 +#define REG_RESET_CONTROL_PCIEHB BIT(29) +#define REG_RESET_CONTROL_PCIE1 BIT(27) +#define REG_RESET_CONTROL_PCIE2 BIT(26) + +struct en_clk_desc { + int id; + const char *name; + u32 base_reg; + u8 base_bits; + u8 base_shift; + union { + const unsigned int *base_values; + unsigned int base_value; + }; + size_t n_base_values; + + u16 div_reg; + u8 div_bits; + u8 div_shift; + u16 div_val0; + u8 div_step; +}; + +struct en_clk_gate { + void __iomem *base; + struct clk_hw hw; +}; + +static const u32 gsw_base[] = { 400000000, 500000000 }; +static const u32 emi_base[] = { 333000000, 400000000 }; +static const u32 bus_base[] = { 500000000, 540000000 }; +static const u32 slic_base[] = { 100000000, 3125000 }; +static const u32 npu_base[] = { 333000000, 400000000, 500000000 }; + +static const struct en_clk_desc en7523_base_clks[] = { + { + .id = EN7523_CLK_GSW, + .name = "gsw", + + .base_reg = REG_GSW_CLK_DIV_SEL, + .base_bits = 1, + .base_shift = 8, + .base_values = gsw_base, + .n_base_values = ARRAY_SIZE(gsw_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + }, { + .id = EN7523_CLK_EMI, + .name = "emi", + + .base_reg = REG_EMI_CLK_DIV_SEL, + .base_bits = 1, + .base_shift = 8, + .base_values = emi_base, + .n_base_values = ARRAY_SIZE(emi_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + }, { + .id = EN7523_CLK_BUS, + .name = "bus", + + .base_reg = REG_BUS_CLK_DIV_SEL, + .base_bits = 1, + .base_shift = 8, + .base_values = bus_base, + .n_base_values = ARRAY_SIZE(bus_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + }, { + .id = EN7523_CLK_SLIC, + .name = "slic", + + .base_reg = REG_SPI_CLK_FREQ_SEL, + .base_bits = 1, + .base_shift = 0, + .base_values = slic_base, + .n_base_values = ARRAY_SIZE(slic_base), + + .div_reg = REG_SPI_CLK_DIV_SEL, + .div_bits = 5, + .div_shift = 24, + .div_val0 = 20, + .div_step = 2, + }, { + .id = EN7523_CLK_SPI, + .name = "spi", + + .base_reg = REG_SPI_CLK_DIV_SEL, + + .base_value = 400000000, + + .div_bits = 5, + .div_shift = 8, + .div_val0 = 40, + .div_step = 2, + }, { + .id = EN7523_CLK_NPU, + .name = "npu", + + .base_reg = REG_NPU_CLK_DIV_SEL, + .base_bits = 2, + .base_shift = 8, + .base_values = npu_base, + .n_base_values = ARRAY_SIZE(npu_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + }, { + .id = EN7523_CLK_CRYPTO, + .name = "crypto", + + .base_reg = REG_CRYPTO_CLKSRC, + .base_bits = 1, + .base_shift = 8, + .base_values = emi_base, + .n_base_values = ARRAY_SIZE(emi_base), + } +}; + +static const struct of_device_id of_match_clk_en7523[] = { + { .compatible = "airoha,en7523-scu", }, + { /* sentinel */ } +}; + +static unsigned int en7523_get_base_rate(void __iomem *base, unsigned int i) +{ + const struct en_clk_desc *desc = &en7523_base_clks[i]; + u32 val; + + if (!desc->base_bits) + return desc->base_value; + + val = readl(base + desc->base_reg); + val >>= desc->base_shift; + val &= (1 << desc->base_bits) - 1; + + if (val >= desc->n_base_values) + return 0; + + return desc->base_values[val]; +} + +static u32 en7523_get_div(void __iomem *base, int i) +{ + const struct en_clk_desc *desc = &en7523_base_clks[i]; + u32 reg, val; + + if (!desc->div_bits) + return 1; + + reg = desc->div_reg ? desc->div_reg : desc->base_reg; + val = readl(base + reg); + val >>= desc->div_shift; + val &= (1 << desc->div_bits) - 1; + + if (!val && desc->div_val0) + return desc->div_val0; + + return (val + 1) * desc->div_step; +} + +static int en7523_pci_is_enabled(struct clk_hw *hw) +{ + struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); + + return !!(readl(cg->base + REG_PCI_CONTROL) & REG_PCI_CONTROL_REFCLK_EN1); +} + +static int en7523_pci_prepare(struct clk_hw *hw) +{ + struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); + void __iomem *np_base = cg->base; + u32 val, mask; + + /* Need to pull device low before reset */ + val = readl(np_base + REG_PCI_CONTROL); + val &= ~(REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT); + writel(val, np_base + REG_PCI_CONTROL); + usleep_range(1000, 2000); + + /* Enable PCIe port 1 */ + val |= REG_PCI_CONTROL_REFCLK_EN1; + writel(val, np_base + REG_PCI_CONTROL); + usleep_range(1000, 2000); + + /* Reset to default */ + val = readl(np_base + REG_RESET_CONTROL); + mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 | + REG_RESET_CONTROL_PCIEHB; + writel(val & ~mask, np_base + REG_RESET_CONTROL); + usleep_range(1000, 2000); + writel(val | mask, np_base + REG_RESET_CONTROL); + msleep(100); + writel(val & ~mask, np_base + REG_RESET_CONTROL); + usleep_range(5000, 10000); + + /* Release device */ + mask = REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT; + val = readl(np_base + REG_PCI_CONTROL); + writel(val & ~mask, np_base + REG_PCI_CONTROL); + usleep_range(1000, 2000); + writel(val | mask, np_base + REG_PCI_CONTROL); + msleep(250); + + return 0; +} + +static void en7523_pci_unprepare(struct clk_hw *hw) +{ + struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); + void __iomem *np_base = cg->base; + u32 val; + + val = readl(np_base + REG_PCI_CONTROL); + val &= ~REG_PCI_CONTROL_REFCLK_EN1; + writel(val, np_base + REG_PCI_CONTROL); +} + +static struct clk_hw *en7523_register_pcie_clk(struct device *dev, + void __iomem *np_base) +{ + static const struct clk_ops pcie_gate_ops = { + .is_enabled = en7523_pci_is_enabled, + .prepare = en7523_pci_prepare, + .unprepare = en7523_pci_unprepare, + }; + struct clk_init_data init = { + .name = "pcie", + .ops = &pcie_gate_ops, + }; + struct en_clk_gate *cg; + + cg = devm_kzalloc(dev, sizeof(*cg), GFP_KERNEL); + if (!cg) + return NULL; + + cg->base = np_base; + cg->hw.init = &init; + en7523_pci_unprepare(&cg->hw); + + if (clk_hw_register(dev, &cg->hw)) + return NULL; + + return &cg->hw; +} + +static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data, + void __iomem *base, void __iomem *np_base) +{ + struct clk_hw *hw; + u32 rate; + int i; + + for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) { + const struct en_clk_desc *desc = &en7523_base_clks[i]; + + rate = en7523_get_base_rate(base, i); + rate /= en7523_get_div(base, i); + + hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); + if (IS_ERR(hw)) { + pr_err("Failed to register clk %s: %ld\n", + desc->name, PTR_ERR(hw)); + continue; + } + + clk_data->hws[desc->id] = hw; + } + + hw = en7523_register_pcie_clk(dev, np_base); + clk_data->hws[EN7523_CLK_PCIE] = hw; + + clk_data->num = EN7523_NUM_CLOCKS; +} + +static int en7523_clk_probe(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + struct clk_hw_onecell_data *clk_data; + void __iomem *base, *np_base; + int r; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + np_base = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(base)) + return PTR_ERR(np_base); + + clk_data = devm_kzalloc(&pdev->dev, + struct_size(clk_data, hws, EN7523_NUM_CLOCKS), + GFP_KERNEL); + if (!clk_data) + return -ENOMEM; + + en7523_register_clocks(&pdev->dev, clk_data, base, np_base); + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (r) + dev_err(&pdev->dev, + "could not register clock provider: %s: %d\n", + pdev->name, r); + + return r; +} + +static struct platform_driver clk_en7523_drv = { + .probe = en7523_clk_probe, + .driver = { + .name = "clk-en7523", + .of_match_table = of_match_clk_en7523, + .suppress_bind_attrs = true, + }, +}; + +static int __init clk_en7523_init(void) +{ + return platform_driver_register(&clk_en7523_drv); +} + +arch_initcall(clk_en7523_init); -- 2.35.1 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [PATCH v10 2/6] clk: en7523: Add clock driver for Airoha EN7523 SoC 2022-03-14 8:44 ` Felix Fietkau (?) @ 2022-03-15 16:34 ` Matthias Brugger -1 siblings, 0 replies; 39+ messages in thread From: Matthias Brugger @ 2022-03-15 16:34 UTC (permalink / raw) To: Felix Fietkau, soc, Michael Turquette, Stephen Boyd Cc: linux-mediatek, linux-arm-kernel, linux-kernel, linux-clk On 14/03/2022 09:44, Felix Fietkau wrote: > This driver only registers fixed rate clocks, since the clocks are fully > initialized by the boot loader and should not be changed later, according > to Airoha. > > Signed-off-by: Felix Fietkau <nbd@nbd.name> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> > --- > drivers/clk/Kconfig | 9 + > drivers/clk/Makefile | 1 + > drivers/clk/clk-en7523.c | 351 +++++++++++++++++++++++++++++++++++++++ > 3 files changed, 361 insertions(+) > create mode 100644 drivers/clk/clk-en7523.c > > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig > index ad4256d54361..4765e4c6f2a1 100644 > --- a/drivers/clk/Kconfig > +++ b/drivers/clk/Kconfig > @@ -200,6 +200,15 @@ config COMMON_CLK_CS2000_CP > help > If you say yes here you get support for the CS2000 clock multiplier. > > +config COMMON_CLK_EN7523 > + bool "Clock driver for Airoha EN7523 SoC system clocks" > + depends on OF > + depends on ARCH_AIROHA || COMPILE_TEST > + default ARCH_AIROHA > + help > + This driver provides the fixed clocks and gates present on Airoha > + ARM silicon. > + > config COMMON_CLK_FSL_FLEXSPI > tristate "Clock driver for FlexSPI on Layerscape SoCs" > depends on ARCH_LAYERSCAPE || COMPILE_TEST > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile > index 16e588630472..da8dd3ab304f 100644 > --- a/drivers/clk/Makefile > +++ b/drivers/clk/Makefile > @@ -27,6 +27,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o > obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o > obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o > obj-$(CONFIG_ARCH_SPARX5) += clk-sparx5.o > +obj-$(CONFIG_COMMON_CLK_EN7523) += clk-en7523.o > obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o > obj-$(CONFIG_COMMON_CLK_FSL_FLEXSPI) += clk-fsl-flexspi.o > obj-$(CONFIG_COMMON_CLK_FSL_SAI) += clk-fsl-sai.o > diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c > new file mode 100644 > index 000000000000..076a70c2e173 > --- /dev/null > +++ b/drivers/clk/clk-en7523.c > @@ -0,0 +1,351 @@ > +// SPDX-License-Identifier: GPL-2.0-only > + > +#include <linux/delay.h> > +#include <linux/clk-provider.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/of_device.h> > +#include <linux/platform_device.h> > +#include <dt-bindings/clock/en7523-clk.h> > + > +#define REG_PCI_CONTROL 0x88 > +#define REG_PCI_CONTROL_PERSTOUT BIT(29) > +#define REG_PCI_CONTROL_PERSTOUT1 BIT(26) > +#define REG_PCI_CONTROL_REFCLK_EN1 BIT(22) > +#define REG_GSW_CLK_DIV_SEL 0x1b4 > +#define REG_EMI_CLK_DIV_SEL 0x1b8 > +#define REG_BUS_CLK_DIV_SEL 0x1bc > +#define REG_SPI_CLK_DIV_SEL 0x1c4 > +#define REG_SPI_CLK_FREQ_SEL 0x1c8 > +#define REG_NPU_CLK_DIV_SEL 0x1fc > +#define REG_CRYPTO_CLKSRC 0x200 > +#define REG_RESET_CONTROL 0x834 > +#define REG_RESET_CONTROL_PCIEHB BIT(29) > +#define REG_RESET_CONTROL_PCIE1 BIT(27) > +#define REG_RESET_CONTROL_PCIE2 BIT(26) > + > +struct en_clk_desc { > + int id; > + const char *name; > + u32 base_reg; > + u8 base_bits; > + u8 base_shift; > + union { > + const unsigned int *base_values; > + unsigned int base_value; > + }; > + size_t n_base_values; > + > + u16 div_reg; > + u8 div_bits; > + u8 div_shift; > + u16 div_val0; > + u8 div_step; > +}; > + > +struct en_clk_gate { > + void __iomem *base; > + struct clk_hw hw; > +}; > + > +static const u32 gsw_base[] = { 400000000, 500000000 }; > +static const u32 emi_base[] = { 333000000, 400000000 }; > +static const u32 bus_base[] = { 500000000, 540000000 }; > +static const u32 slic_base[] = { 100000000, 3125000 }; > +static const u32 npu_base[] = { 333000000, 400000000, 500000000 }; > + > +static const struct en_clk_desc en7523_base_clks[] = { > + { > + .id = EN7523_CLK_GSW, > + .name = "gsw", > + > + .base_reg = REG_GSW_CLK_DIV_SEL, > + .base_bits = 1, > + .base_shift = 8, > + .base_values = gsw_base, > + .n_base_values = ARRAY_SIZE(gsw_base), > + > + .div_bits = 3, > + .div_shift = 0, > + .div_step = 1, > + }, { > + .id = EN7523_CLK_EMI, > + .name = "emi", > + > + .base_reg = REG_EMI_CLK_DIV_SEL, > + .base_bits = 1, > + .base_shift = 8, > + .base_values = emi_base, > + .n_base_values = ARRAY_SIZE(emi_base), > + > + .div_bits = 3, > + .div_shift = 0, > + .div_step = 1, > + }, { > + .id = EN7523_CLK_BUS, > + .name = "bus", > + > + .base_reg = REG_BUS_CLK_DIV_SEL, > + .base_bits = 1, > + .base_shift = 8, > + .base_values = bus_base, > + .n_base_values = ARRAY_SIZE(bus_base), > + > + .div_bits = 3, > + .div_shift = 0, > + .div_step = 1, > + }, { > + .id = EN7523_CLK_SLIC, > + .name = "slic", > + > + .base_reg = REG_SPI_CLK_FREQ_SEL, > + .base_bits = 1, > + .base_shift = 0, > + .base_values = slic_base, > + .n_base_values = ARRAY_SIZE(slic_base), > + > + .div_reg = REG_SPI_CLK_DIV_SEL, > + .div_bits = 5, > + .div_shift = 24, > + .div_val0 = 20, > + .div_step = 2, > + }, { > + .id = EN7523_CLK_SPI, > + .name = "spi", > + > + .base_reg = REG_SPI_CLK_DIV_SEL, > + > + .base_value = 400000000, > + > + .div_bits = 5, > + .div_shift = 8, > + .div_val0 = 40, > + .div_step = 2, > + }, { > + .id = EN7523_CLK_NPU, > + .name = "npu", > + > + .base_reg = REG_NPU_CLK_DIV_SEL, > + .base_bits = 2, > + .base_shift = 8, > + .base_values = npu_base, > + .n_base_values = ARRAY_SIZE(npu_base), > + > + .div_bits = 3, > + .div_shift = 0, > + .div_step = 1, > + }, { > + .id = EN7523_CLK_CRYPTO, > + .name = "crypto", > + > + .base_reg = REG_CRYPTO_CLKSRC, > + .base_bits = 1, > + .base_shift = 8, > + .base_values = emi_base, > + .n_base_values = ARRAY_SIZE(emi_base), > + } > +}; > + > +static const struct of_device_id of_match_clk_en7523[] = { > + { .compatible = "airoha,en7523-scu", }, > + { /* sentinel */ } > +}; > + > +static unsigned int en7523_get_base_rate(void __iomem *base, unsigned int i) > +{ > + const struct en_clk_desc *desc = &en7523_base_clks[i]; > + u32 val; > + > + if (!desc->base_bits) > + return desc->base_value; > + > + val = readl(base + desc->base_reg); > + val >>= desc->base_shift; > + val &= (1 << desc->base_bits) - 1; > + > + if (val >= desc->n_base_values) > + return 0; > + > + return desc->base_values[val]; > +} > + > +static u32 en7523_get_div(void __iomem *base, int i) > +{ > + const struct en_clk_desc *desc = &en7523_base_clks[i]; > + u32 reg, val; > + > + if (!desc->div_bits) > + return 1; > + > + reg = desc->div_reg ? desc->div_reg : desc->base_reg; > + val = readl(base + reg); > + val >>= desc->div_shift; > + val &= (1 << desc->div_bits) - 1; > + > + if (!val && desc->div_val0) > + return desc->div_val0; > + > + return (val + 1) * desc->div_step; > +} > + > +static int en7523_pci_is_enabled(struct clk_hw *hw) > +{ > + struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); > + > + return !!(readl(cg->base + REG_PCI_CONTROL) & REG_PCI_CONTROL_REFCLK_EN1); > +} > + > +static int en7523_pci_prepare(struct clk_hw *hw) > +{ > + struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); > + void __iomem *np_base = cg->base; > + u32 val, mask; > + > + /* Need to pull device low before reset */ > + val = readl(np_base + REG_PCI_CONTROL); > + val &= ~(REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT); > + writel(val, np_base + REG_PCI_CONTROL); > + usleep_range(1000, 2000); > + > + /* Enable PCIe port 1 */ > + val |= REG_PCI_CONTROL_REFCLK_EN1; > + writel(val, np_base + REG_PCI_CONTROL); > + usleep_range(1000, 2000); > + > + /* Reset to default */ > + val = readl(np_base + REG_RESET_CONTROL); > + mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 | > + REG_RESET_CONTROL_PCIEHB; > + writel(val & ~mask, np_base + REG_RESET_CONTROL); > + usleep_range(1000, 2000); > + writel(val | mask, np_base + REG_RESET_CONTROL); > + msleep(100); > + writel(val & ~mask, np_base + REG_RESET_CONTROL); > + usleep_range(5000, 10000); > + > + /* Release device */ > + mask = REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT; > + val = readl(np_base + REG_PCI_CONTROL); > + writel(val & ~mask, np_base + REG_PCI_CONTROL); > + usleep_range(1000, 2000); > + writel(val | mask, np_base + REG_PCI_CONTROL); > + msleep(250); > + > + return 0; > +} > + > +static void en7523_pci_unprepare(struct clk_hw *hw) > +{ > + struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); > + void __iomem *np_base = cg->base; > + u32 val; > + > + val = readl(np_base + REG_PCI_CONTROL); > + val &= ~REG_PCI_CONTROL_REFCLK_EN1; > + writel(val, np_base + REG_PCI_CONTROL); > +} > + > +static struct clk_hw *en7523_register_pcie_clk(struct device *dev, > + void __iomem *np_base) > +{ > + static const struct clk_ops pcie_gate_ops = { > + .is_enabled = en7523_pci_is_enabled, > + .prepare = en7523_pci_prepare, > + .unprepare = en7523_pci_unprepare, > + }; > + struct clk_init_data init = { > + .name = "pcie", > + .ops = &pcie_gate_ops, > + }; > + struct en_clk_gate *cg; > + > + cg = devm_kzalloc(dev, sizeof(*cg), GFP_KERNEL); > + if (!cg) > + return NULL; > + > + cg->base = np_base; > + cg->hw.init = &init; > + en7523_pci_unprepare(&cg->hw); > + > + if (clk_hw_register(dev, &cg->hw)) > + return NULL; > + > + return &cg->hw; > +} > + > +static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data, > + void __iomem *base, void __iomem *np_base) > +{ > + struct clk_hw *hw; > + u32 rate; > + int i; > + > + for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) { > + const struct en_clk_desc *desc = &en7523_base_clks[i]; > + > + rate = en7523_get_base_rate(base, i); > + rate /= en7523_get_div(base, i); > + > + hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); > + if (IS_ERR(hw)) { > + pr_err("Failed to register clk %s: %ld\n", > + desc->name, PTR_ERR(hw)); > + continue; > + } > + > + clk_data->hws[desc->id] = hw; > + } > + > + hw = en7523_register_pcie_clk(dev, np_base); > + clk_data->hws[EN7523_CLK_PCIE] = hw; > + > + clk_data->num = EN7523_NUM_CLOCKS; > +} > + > +static int en7523_clk_probe(struct platform_device *pdev) > +{ > + struct device_node *node = pdev->dev.of_node; > + struct clk_hw_onecell_data *clk_data; > + void __iomem *base, *np_base; > + int r; > + > + base = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(base)) > + return PTR_ERR(base); > + > + np_base = devm_platform_ioremap_resource(pdev, 1); > + if (IS_ERR(base)) > + return PTR_ERR(np_base); > + > + clk_data = devm_kzalloc(&pdev->dev, > + struct_size(clk_data, hws, EN7523_NUM_CLOCKS), > + GFP_KERNEL); > + if (!clk_data) > + return -ENOMEM; > + > + en7523_register_clocks(&pdev->dev, clk_data, base, np_base); > + > + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); > + if (r) > + dev_err(&pdev->dev, > + "could not register clock provider: %s: %d\n", > + pdev->name, r); > + > + return r; > +} > + > +static struct platform_driver clk_en7523_drv = { > + .probe = en7523_clk_probe, > + .driver = { > + .name = "clk-en7523", > + .of_match_table = of_match_clk_en7523, > + .suppress_bind_attrs = true, > + }, > +}; > + > +static int __init clk_en7523_init(void) > +{ > + return platform_driver_register(&clk_en7523_drv); > +} > + > +arch_initcall(clk_en7523_init); ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v10 2/6] clk: en7523: Add clock driver for Airoha EN7523 SoC @ 2022-03-15 16:34 ` Matthias Brugger 0 siblings, 0 replies; 39+ messages in thread From: Matthias Brugger @ 2022-03-15 16:34 UTC (permalink / raw) To: Felix Fietkau, soc, Michael Turquette, Stephen Boyd Cc: linux-mediatek, linux-arm-kernel, linux-kernel, linux-clk On 14/03/2022 09:44, Felix Fietkau wrote: > This driver only registers fixed rate clocks, since the clocks are fully > initialized by the boot loader and should not be changed later, according > to Airoha. > > Signed-off-by: Felix Fietkau <nbd@nbd.name> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> > --- > drivers/clk/Kconfig | 9 + > drivers/clk/Makefile | 1 + > drivers/clk/clk-en7523.c | 351 +++++++++++++++++++++++++++++++++++++++ > 3 files changed, 361 insertions(+) > create mode 100644 drivers/clk/clk-en7523.c > > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig > index ad4256d54361..4765e4c6f2a1 100644 > --- a/drivers/clk/Kconfig > +++ b/drivers/clk/Kconfig > @@ -200,6 +200,15 @@ config COMMON_CLK_CS2000_CP > help > If you say yes here you get support for the CS2000 clock multiplier. > > +config COMMON_CLK_EN7523 > + bool "Clock driver for Airoha EN7523 SoC system clocks" > + depends on OF > + depends on ARCH_AIROHA || COMPILE_TEST > + default ARCH_AIROHA > + help > + This driver provides the fixed clocks and gates present on Airoha > + ARM silicon. > + > config COMMON_CLK_FSL_FLEXSPI > tristate "Clock driver for FlexSPI on Layerscape SoCs" > depends on ARCH_LAYERSCAPE || COMPILE_TEST > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile > index 16e588630472..da8dd3ab304f 100644 > --- a/drivers/clk/Makefile > +++ b/drivers/clk/Makefile > @@ -27,6 +27,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o > obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o > obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o > obj-$(CONFIG_ARCH_SPARX5) += clk-sparx5.o > +obj-$(CONFIG_COMMON_CLK_EN7523) += clk-en7523.o > obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o > obj-$(CONFIG_COMMON_CLK_FSL_FLEXSPI) += clk-fsl-flexspi.o > obj-$(CONFIG_COMMON_CLK_FSL_SAI) += clk-fsl-sai.o > diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c > new file mode 100644 > index 000000000000..076a70c2e173 > --- /dev/null > +++ b/drivers/clk/clk-en7523.c > @@ -0,0 +1,351 @@ > +// SPDX-License-Identifier: GPL-2.0-only > + > +#include <linux/delay.h> > +#include <linux/clk-provider.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/of_device.h> > +#include <linux/platform_device.h> > +#include <dt-bindings/clock/en7523-clk.h> > + > +#define REG_PCI_CONTROL 0x88 > +#define REG_PCI_CONTROL_PERSTOUT BIT(29) > +#define REG_PCI_CONTROL_PERSTOUT1 BIT(26) > +#define REG_PCI_CONTROL_REFCLK_EN1 BIT(22) > +#define REG_GSW_CLK_DIV_SEL 0x1b4 > +#define REG_EMI_CLK_DIV_SEL 0x1b8 > +#define REG_BUS_CLK_DIV_SEL 0x1bc > +#define REG_SPI_CLK_DIV_SEL 0x1c4 > +#define REG_SPI_CLK_FREQ_SEL 0x1c8 > +#define REG_NPU_CLK_DIV_SEL 0x1fc > +#define REG_CRYPTO_CLKSRC 0x200 > +#define REG_RESET_CONTROL 0x834 > +#define REG_RESET_CONTROL_PCIEHB BIT(29) > +#define REG_RESET_CONTROL_PCIE1 BIT(27) > +#define REG_RESET_CONTROL_PCIE2 BIT(26) > + > +struct en_clk_desc { > + int id; > + const char *name; > + u32 base_reg; > + u8 base_bits; > + u8 base_shift; > + union { > + const unsigned int *base_values; > + unsigned int base_value; > + }; > + size_t n_base_values; > + > + u16 div_reg; > + u8 div_bits; > + u8 div_shift; > + u16 div_val0; > + u8 div_step; > +}; > + > +struct en_clk_gate { > + void __iomem *base; > + struct clk_hw hw; > +}; > + > +static const u32 gsw_base[] = { 400000000, 500000000 }; > +static const u32 emi_base[] = { 333000000, 400000000 }; > +static const u32 bus_base[] = { 500000000, 540000000 }; > +static const u32 slic_base[] = { 100000000, 3125000 }; > +static const u32 npu_base[] = { 333000000, 400000000, 500000000 }; > + > +static const struct en_clk_desc en7523_base_clks[] = { > + { > + .id = EN7523_CLK_GSW, > + .name = "gsw", > + > + .base_reg = REG_GSW_CLK_DIV_SEL, > + .base_bits = 1, > + .base_shift = 8, > + .base_values = gsw_base, > + .n_base_values = ARRAY_SIZE(gsw_base), > + > + .div_bits = 3, > + .div_shift = 0, > + .div_step = 1, > + }, { > + .id = EN7523_CLK_EMI, > + .name = "emi", > + > + .base_reg = REG_EMI_CLK_DIV_SEL, > + .base_bits = 1, > + .base_shift = 8, > + .base_values = emi_base, > + .n_base_values = ARRAY_SIZE(emi_base), > + > + .div_bits = 3, > + .div_shift = 0, > + .div_step = 1, > + }, { > + .id = EN7523_CLK_BUS, > + .name = "bus", > + > + .base_reg = REG_BUS_CLK_DIV_SEL, > + .base_bits = 1, > + .base_shift = 8, > + .base_values = bus_base, > + .n_base_values = ARRAY_SIZE(bus_base), > + > + .div_bits = 3, > + .div_shift = 0, > + .div_step = 1, > + }, { > + .id = EN7523_CLK_SLIC, > + .name = "slic", > + > + .base_reg = REG_SPI_CLK_FREQ_SEL, > + .base_bits = 1, > + .base_shift = 0, > + .base_values = slic_base, > + .n_base_values = ARRAY_SIZE(slic_base), > + > + .div_reg = REG_SPI_CLK_DIV_SEL, > + .div_bits = 5, > + .div_shift = 24, > + .div_val0 = 20, > + .div_step = 2, > + }, { > + .id = EN7523_CLK_SPI, > + .name = "spi", > + > + .base_reg = REG_SPI_CLK_DIV_SEL, > + > + .base_value = 400000000, > + > + .div_bits = 5, > + .div_shift = 8, > + .div_val0 = 40, > + .div_step = 2, > + }, { > + .id = EN7523_CLK_NPU, > + .name = "npu", > + > + .base_reg = REG_NPU_CLK_DIV_SEL, > + .base_bits = 2, > + .base_shift = 8, > + .base_values = npu_base, > + .n_base_values = ARRAY_SIZE(npu_base), > + > + .div_bits = 3, > + .div_shift = 0, > + .div_step = 1, > + }, { > + .id = EN7523_CLK_CRYPTO, > + .name = "crypto", > + > + .base_reg = REG_CRYPTO_CLKSRC, > + .base_bits = 1, > + .base_shift = 8, > + .base_values = emi_base, > + .n_base_values = ARRAY_SIZE(emi_base), > + } > +}; > + > +static const struct of_device_id of_match_clk_en7523[] = { > + { .compatible = "airoha,en7523-scu", }, > + { /* sentinel */ } > +}; > + > +static unsigned int en7523_get_base_rate(void __iomem *base, unsigned int i) > +{ > + const struct en_clk_desc *desc = &en7523_base_clks[i]; > + u32 val; > + > + if (!desc->base_bits) > + return desc->base_value; > + > + val = readl(base + desc->base_reg); > + val >>= desc->base_shift; > + val &= (1 << desc->base_bits) - 1; > + > + if (val >= desc->n_base_values) > + return 0; > + > + return desc->base_values[val]; > +} > + > +static u32 en7523_get_div(void __iomem *base, int i) > +{ > + const struct en_clk_desc *desc = &en7523_base_clks[i]; > + u32 reg, val; > + > + if (!desc->div_bits) > + return 1; > + > + reg = desc->div_reg ? desc->div_reg : desc->base_reg; > + val = readl(base + reg); > + val >>= desc->div_shift; > + val &= (1 << desc->div_bits) - 1; > + > + if (!val && desc->div_val0) > + return desc->div_val0; > + > + return (val + 1) * desc->div_step; > +} > + > +static int en7523_pci_is_enabled(struct clk_hw *hw) > +{ > + struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); > + > + return !!(readl(cg->base + REG_PCI_CONTROL) & REG_PCI_CONTROL_REFCLK_EN1); > +} > + > +static int en7523_pci_prepare(struct clk_hw *hw) > +{ > + struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); > + void __iomem *np_base = cg->base; > + u32 val, mask; > + > + /* Need to pull device low before reset */ > + val = readl(np_base + REG_PCI_CONTROL); > + val &= ~(REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT); > + writel(val, np_base + REG_PCI_CONTROL); > + usleep_range(1000, 2000); > + > + /* Enable PCIe port 1 */ > + val |= REG_PCI_CONTROL_REFCLK_EN1; > + writel(val, np_base + REG_PCI_CONTROL); > + usleep_range(1000, 2000); > + > + /* Reset to default */ > + val = readl(np_base + REG_RESET_CONTROL); > + mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 | > + REG_RESET_CONTROL_PCIEHB; > + writel(val & ~mask, np_base + REG_RESET_CONTROL); > + usleep_range(1000, 2000); > + writel(val | mask, np_base + REG_RESET_CONTROL); > + msleep(100); > + writel(val & ~mask, np_base + REG_RESET_CONTROL); > + usleep_range(5000, 10000); > + > + /* Release device */ > + mask = REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT; > + val = readl(np_base + REG_PCI_CONTROL); > + writel(val & ~mask, np_base + REG_PCI_CONTROL); > + usleep_range(1000, 2000); > + writel(val | mask, np_base + REG_PCI_CONTROL); > + msleep(250); > + > + return 0; > +} > + > +static void en7523_pci_unprepare(struct clk_hw *hw) > +{ > + struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); > + void __iomem *np_base = cg->base; > + u32 val; > + > + val = readl(np_base + REG_PCI_CONTROL); > + val &= ~REG_PCI_CONTROL_REFCLK_EN1; > + writel(val, np_base + REG_PCI_CONTROL); > +} > + > +static struct clk_hw *en7523_register_pcie_clk(struct device *dev, > + void __iomem *np_base) > +{ > + static const struct clk_ops pcie_gate_ops = { > + .is_enabled = en7523_pci_is_enabled, > + .prepare = en7523_pci_prepare, > + .unprepare = en7523_pci_unprepare, > + }; > + struct clk_init_data init = { > + .name = "pcie", > + .ops = &pcie_gate_ops, > + }; > + struct en_clk_gate *cg; > + > + cg = devm_kzalloc(dev, sizeof(*cg), GFP_KERNEL); > + if (!cg) > + return NULL; > + > + cg->base = np_base; > + cg->hw.init = &init; > + en7523_pci_unprepare(&cg->hw); > + > + if (clk_hw_register(dev, &cg->hw)) > + return NULL; > + > + return &cg->hw; > +} > + > +static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data, > + void __iomem *base, void __iomem *np_base) > +{ > + struct clk_hw *hw; > + u32 rate; > + int i; > + > + for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) { > + const struct en_clk_desc *desc = &en7523_base_clks[i]; > + > + rate = en7523_get_base_rate(base, i); > + rate /= en7523_get_div(base, i); > + > + hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); > + if (IS_ERR(hw)) { > + pr_err("Failed to register clk %s: %ld\n", > + desc->name, PTR_ERR(hw)); > + continue; > + } > + > + clk_data->hws[desc->id] = hw; > + } > + > + hw = en7523_register_pcie_clk(dev, np_base); > + clk_data->hws[EN7523_CLK_PCIE] = hw; > + > + clk_data->num = EN7523_NUM_CLOCKS; > +} > + > +static int en7523_clk_probe(struct platform_device *pdev) > +{ > + struct device_node *node = pdev->dev.of_node; > + struct clk_hw_onecell_data *clk_data; > + void __iomem *base, *np_base; > + int r; > + > + base = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(base)) > + return PTR_ERR(base); > + > + np_base = devm_platform_ioremap_resource(pdev, 1); > + if (IS_ERR(base)) > + return PTR_ERR(np_base); > + > + clk_data = devm_kzalloc(&pdev->dev, > + struct_size(clk_data, hws, EN7523_NUM_CLOCKS), > + GFP_KERNEL); > + if (!clk_data) > + return -ENOMEM; > + > + en7523_register_clocks(&pdev->dev, clk_data, base, np_base); > + > + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); > + if (r) > + dev_err(&pdev->dev, > + "could not register clock provider: %s: %d\n", > + pdev->name, r); > + > + return r; > +} > + > +static struct platform_driver clk_en7523_drv = { > + .probe = en7523_clk_probe, > + .driver = { > + .name = "clk-en7523", > + .of_match_table = of_match_clk_en7523, > + .suppress_bind_attrs = true, > + }, > +}; > + > +static int __init clk_en7523_init(void) > +{ > + return platform_driver_register(&clk_en7523_drv); > +} > + > +arch_initcall(clk_en7523_init); _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v10 2/6] clk: en7523: Add clock driver for Airoha EN7523 SoC @ 2022-03-15 16:34 ` Matthias Brugger 0 siblings, 0 replies; 39+ messages in thread From: Matthias Brugger @ 2022-03-15 16:34 UTC (permalink / raw) To: Felix Fietkau, soc, Michael Turquette, Stephen Boyd Cc: linux-mediatek, linux-arm-kernel, linux-kernel, linux-clk On 14/03/2022 09:44, Felix Fietkau wrote: > This driver only registers fixed rate clocks, since the clocks are fully > initialized by the boot loader and should not be changed later, according > to Airoha. > > Signed-off-by: Felix Fietkau <nbd@nbd.name> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> > --- > drivers/clk/Kconfig | 9 + > drivers/clk/Makefile | 1 + > drivers/clk/clk-en7523.c | 351 +++++++++++++++++++++++++++++++++++++++ > 3 files changed, 361 insertions(+) > create mode 100644 drivers/clk/clk-en7523.c > > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig > index ad4256d54361..4765e4c6f2a1 100644 > --- a/drivers/clk/Kconfig > +++ b/drivers/clk/Kconfig > @@ -200,6 +200,15 @@ config COMMON_CLK_CS2000_CP > help > If you say yes here you get support for the CS2000 clock multiplier. > > +config COMMON_CLK_EN7523 > + bool "Clock driver for Airoha EN7523 SoC system clocks" > + depends on OF > + depends on ARCH_AIROHA || COMPILE_TEST > + default ARCH_AIROHA > + help > + This driver provides the fixed clocks and gates present on Airoha > + ARM silicon. > + > config COMMON_CLK_FSL_FLEXSPI > tristate "Clock driver for FlexSPI on Layerscape SoCs" > depends on ARCH_LAYERSCAPE || COMPILE_TEST > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile > index 16e588630472..da8dd3ab304f 100644 > --- a/drivers/clk/Makefile > +++ b/drivers/clk/Makefile > @@ -27,6 +27,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o > obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o > obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o > obj-$(CONFIG_ARCH_SPARX5) += clk-sparx5.o > +obj-$(CONFIG_COMMON_CLK_EN7523) += clk-en7523.o > obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o > obj-$(CONFIG_COMMON_CLK_FSL_FLEXSPI) += clk-fsl-flexspi.o > obj-$(CONFIG_COMMON_CLK_FSL_SAI) += clk-fsl-sai.o > diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c > new file mode 100644 > index 000000000000..076a70c2e173 > --- /dev/null > +++ b/drivers/clk/clk-en7523.c > @@ -0,0 +1,351 @@ > +// SPDX-License-Identifier: GPL-2.0-only > + > +#include <linux/delay.h> > +#include <linux/clk-provider.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/of_device.h> > +#include <linux/platform_device.h> > +#include <dt-bindings/clock/en7523-clk.h> > + > +#define REG_PCI_CONTROL 0x88 > +#define REG_PCI_CONTROL_PERSTOUT BIT(29) > +#define REG_PCI_CONTROL_PERSTOUT1 BIT(26) > +#define REG_PCI_CONTROL_REFCLK_EN1 BIT(22) > +#define REG_GSW_CLK_DIV_SEL 0x1b4 > +#define REG_EMI_CLK_DIV_SEL 0x1b8 > +#define REG_BUS_CLK_DIV_SEL 0x1bc > +#define REG_SPI_CLK_DIV_SEL 0x1c4 > +#define REG_SPI_CLK_FREQ_SEL 0x1c8 > +#define REG_NPU_CLK_DIV_SEL 0x1fc > +#define REG_CRYPTO_CLKSRC 0x200 > +#define REG_RESET_CONTROL 0x834 > +#define REG_RESET_CONTROL_PCIEHB BIT(29) > +#define REG_RESET_CONTROL_PCIE1 BIT(27) > +#define REG_RESET_CONTROL_PCIE2 BIT(26) > + > +struct en_clk_desc { > + int id; > + const char *name; > + u32 base_reg; > + u8 base_bits; > + u8 base_shift; > + union { > + const unsigned int *base_values; > + unsigned int base_value; > + }; > + size_t n_base_values; > + > + u16 div_reg; > + u8 div_bits; > + u8 div_shift; > + u16 div_val0; > + u8 div_step; > +}; > + > +struct en_clk_gate { > + void __iomem *base; > + struct clk_hw hw; > +}; > + > +static const u32 gsw_base[] = { 400000000, 500000000 }; > +static const u32 emi_base[] = { 333000000, 400000000 }; > +static const u32 bus_base[] = { 500000000, 540000000 }; > +static const u32 slic_base[] = { 100000000, 3125000 }; > +static const u32 npu_base[] = { 333000000, 400000000, 500000000 }; > + > +static const struct en_clk_desc en7523_base_clks[] = { > + { > + .id = EN7523_CLK_GSW, > + .name = "gsw", > + > + .base_reg = REG_GSW_CLK_DIV_SEL, > + .base_bits = 1, > + .base_shift = 8, > + .base_values = gsw_base, > + .n_base_values = ARRAY_SIZE(gsw_base), > + > + .div_bits = 3, > + .div_shift = 0, > + .div_step = 1, > + }, { > + .id = EN7523_CLK_EMI, > + .name = "emi", > + > + .base_reg = REG_EMI_CLK_DIV_SEL, > + .base_bits = 1, > + .base_shift = 8, > + .base_values = emi_base, > + .n_base_values = ARRAY_SIZE(emi_base), > + > + .div_bits = 3, > + .div_shift = 0, > + .div_step = 1, > + }, { > + .id = EN7523_CLK_BUS, > + .name = "bus", > + > + .base_reg = REG_BUS_CLK_DIV_SEL, > + .base_bits = 1, > + .base_shift = 8, > + .base_values = bus_base, > + .n_base_values = ARRAY_SIZE(bus_base), > + > + .div_bits = 3, > + .div_shift = 0, > + .div_step = 1, > + }, { > + .id = EN7523_CLK_SLIC, > + .name = "slic", > + > + .base_reg = REG_SPI_CLK_FREQ_SEL, > + .base_bits = 1, > + .base_shift = 0, > + .base_values = slic_base, > + .n_base_values = ARRAY_SIZE(slic_base), > + > + .div_reg = REG_SPI_CLK_DIV_SEL, > + .div_bits = 5, > + .div_shift = 24, > + .div_val0 = 20, > + .div_step = 2, > + }, { > + .id = EN7523_CLK_SPI, > + .name = "spi", > + > + .base_reg = REG_SPI_CLK_DIV_SEL, > + > + .base_value = 400000000, > + > + .div_bits = 5, > + .div_shift = 8, > + .div_val0 = 40, > + .div_step = 2, > + }, { > + .id = EN7523_CLK_NPU, > + .name = "npu", > + > + .base_reg = REG_NPU_CLK_DIV_SEL, > + .base_bits = 2, > + .base_shift = 8, > + .base_values = npu_base, > + .n_base_values = ARRAY_SIZE(npu_base), > + > + .div_bits = 3, > + .div_shift = 0, > + .div_step = 1, > + }, { > + .id = EN7523_CLK_CRYPTO, > + .name = "crypto", > + > + .base_reg = REG_CRYPTO_CLKSRC, > + .base_bits = 1, > + .base_shift = 8, > + .base_values = emi_base, > + .n_base_values = ARRAY_SIZE(emi_base), > + } > +}; > + > +static const struct of_device_id of_match_clk_en7523[] = { > + { .compatible = "airoha,en7523-scu", }, > + { /* sentinel */ } > +}; > + > +static unsigned int en7523_get_base_rate(void __iomem *base, unsigned int i) > +{ > + const struct en_clk_desc *desc = &en7523_base_clks[i]; > + u32 val; > + > + if (!desc->base_bits) > + return desc->base_value; > + > + val = readl(base + desc->base_reg); > + val >>= desc->base_shift; > + val &= (1 << desc->base_bits) - 1; > + > + if (val >= desc->n_base_values) > + return 0; > + > + return desc->base_values[val]; > +} > + > +static u32 en7523_get_div(void __iomem *base, int i) > +{ > + const struct en_clk_desc *desc = &en7523_base_clks[i]; > + u32 reg, val; > + > + if (!desc->div_bits) > + return 1; > + > + reg = desc->div_reg ? desc->div_reg : desc->base_reg; > + val = readl(base + reg); > + val >>= desc->div_shift; > + val &= (1 << desc->div_bits) - 1; > + > + if (!val && desc->div_val0) > + return desc->div_val0; > + > + return (val + 1) * desc->div_step; > +} > + > +static int en7523_pci_is_enabled(struct clk_hw *hw) > +{ > + struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); > + > + return !!(readl(cg->base + REG_PCI_CONTROL) & REG_PCI_CONTROL_REFCLK_EN1); > +} > + > +static int en7523_pci_prepare(struct clk_hw *hw) > +{ > + struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); > + void __iomem *np_base = cg->base; > + u32 val, mask; > + > + /* Need to pull device low before reset */ > + val = readl(np_base + REG_PCI_CONTROL); > + val &= ~(REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT); > + writel(val, np_base + REG_PCI_CONTROL); > + usleep_range(1000, 2000); > + > + /* Enable PCIe port 1 */ > + val |= REG_PCI_CONTROL_REFCLK_EN1; > + writel(val, np_base + REG_PCI_CONTROL); > + usleep_range(1000, 2000); > + > + /* Reset to default */ > + val = readl(np_base + REG_RESET_CONTROL); > + mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 | > + REG_RESET_CONTROL_PCIEHB; > + writel(val & ~mask, np_base + REG_RESET_CONTROL); > + usleep_range(1000, 2000); > + writel(val | mask, np_base + REG_RESET_CONTROL); > + msleep(100); > + writel(val & ~mask, np_base + REG_RESET_CONTROL); > + usleep_range(5000, 10000); > + > + /* Release device */ > + mask = REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT; > + val = readl(np_base + REG_PCI_CONTROL); > + writel(val & ~mask, np_base + REG_PCI_CONTROL); > + usleep_range(1000, 2000); > + writel(val | mask, np_base + REG_PCI_CONTROL); > + msleep(250); > + > + return 0; > +} > + > +static void en7523_pci_unprepare(struct clk_hw *hw) > +{ > + struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); > + void __iomem *np_base = cg->base; > + u32 val; > + > + val = readl(np_base + REG_PCI_CONTROL); > + val &= ~REG_PCI_CONTROL_REFCLK_EN1; > + writel(val, np_base + REG_PCI_CONTROL); > +} > + > +static struct clk_hw *en7523_register_pcie_clk(struct device *dev, > + void __iomem *np_base) > +{ > + static const struct clk_ops pcie_gate_ops = { > + .is_enabled = en7523_pci_is_enabled, > + .prepare = en7523_pci_prepare, > + .unprepare = en7523_pci_unprepare, > + }; > + struct clk_init_data init = { > + .name = "pcie", > + .ops = &pcie_gate_ops, > + }; > + struct en_clk_gate *cg; > + > + cg = devm_kzalloc(dev, sizeof(*cg), GFP_KERNEL); > + if (!cg) > + return NULL; > + > + cg->base = np_base; > + cg->hw.init = &init; > + en7523_pci_unprepare(&cg->hw); > + > + if (clk_hw_register(dev, &cg->hw)) > + return NULL; > + > + return &cg->hw; > +} > + > +static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data, > + void __iomem *base, void __iomem *np_base) > +{ > + struct clk_hw *hw; > + u32 rate; > + int i; > + > + for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) { > + const struct en_clk_desc *desc = &en7523_base_clks[i]; > + > + rate = en7523_get_base_rate(base, i); > + rate /= en7523_get_div(base, i); > + > + hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); > + if (IS_ERR(hw)) { > + pr_err("Failed to register clk %s: %ld\n", > + desc->name, PTR_ERR(hw)); > + continue; > + } > + > + clk_data->hws[desc->id] = hw; > + } > + > + hw = en7523_register_pcie_clk(dev, np_base); > + clk_data->hws[EN7523_CLK_PCIE] = hw; > + > + clk_data->num = EN7523_NUM_CLOCKS; > +} > + > +static int en7523_clk_probe(struct platform_device *pdev) > +{ > + struct device_node *node = pdev->dev.of_node; > + struct clk_hw_onecell_data *clk_data; > + void __iomem *base, *np_base; > + int r; > + > + base = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(base)) > + return PTR_ERR(base); > + > + np_base = devm_platform_ioremap_resource(pdev, 1); > + if (IS_ERR(base)) > + return PTR_ERR(np_base); > + > + clk_data = devm_kzalloc(&pdev->dev, > + struct_size(clk_data, hws, EN7523_NUM_CLOCKS), > + GFP_KERNEL); > + if (!clk_data) > + return -ENOMEM; > + > + en7523_register_clocks(&pdev->dev, clk_data, base, np_base); > + > + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); > + if (r) > + dev_err(&pdev->dev, > + "could not register clock provider: %s: %d\n", > + pdev->name, r); > + > + return r; > +} > + > +static struct platform_driver clk_en7523_drv = { > + .probe = en7523_clk_probe, > + .driver = { > + .name = "clk-en7523", > + .of_match_table = of_match_clk_en7523, > + .suppress_bind_attrs = true, > + }, > +}; > + > +static int __init clk_en7523_init(void) > +{ > + return platform_driver_register(&clk_en7523_drv); > +} > + > +arch_initcall(clk_en7523_init); _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v10 2/6] clk: en7523: Add clock driver for Airoha EN7523 SoC 2022-03-14 8:44 ` Felix Fietkau (?) @ 2022-04-23 2:13 ` Stephen Boyd -1 siblings, 0 replies; 39+ messages in thread From: Stephen Boyd @ 2022-04-23 2:13 UTC (permalink / raw) To: Felix Fietkau, Michael Turquette, soc Cc: linux-mediatek, linux-arm-kernel, linux-kernel, linux-clk Quoting Felix Fietkau (2022-03-14 01:44:04) > This driver only registers fixed rate clocks, since the clocks are fully > initialized by the boot loader and should not be changed later, according > to Airoha. > > Signed-off-by: Felix Fietkau <nbd@nbd.name> > --- Applied to clk-next ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v10 2/6] clk: en7523: Add clock driver for Airoha EN7523 SoC @ 2022-04-23 2:13 ` Stephen Boyd 0 siblings, 0 replies; 39+ messages in thread From: Stephen Boyd @ 2022-04-23 2:13 UTC (permalink / raw) To: Felix Fietkau, Michael Turquette, soc Cc: linux-mediatek, linux-arm-kernel, linux-kernel, linux-clk Quoting Felix Fietkau (2022-03-14 01:44:04) > This driver only registers fixed rate clocks, since the clocks are fully > initialized by the boot loader and should not be changed later, according > to Airoha. > > Signed-off-by: Felix Fietkau <nbd@nbd.name> > --- Applied to clk-next _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v10 2/6] clk: en7523: Add clock driver for Airoha EN7523 SoC @ 2022-04-23 2:13 ` Stephen Boyd 0 siblings, 0 replies; 39+ messages in thread From: Stephen Boyd @ 2022-04-23 2:13 UTC (permalink / raw) To: Felix Fietkau, Michael Turquette, soc Cc: linux-mediatek, linux-arm-kernel, linux-kernel, linux-clk Quoting Felix Fietkau (2022-03-14 01:44:04) > This driver only registers fixed rate clocks, since the clocks are fully > initialized by the boot loader and should not be changed later, according > to Airoha. > > Signed-off-by: Felix Fietkau <nbd@nbd.name> > --- Applied to clk-next _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v10 3/6] ARM: dts: add clock support for Airoha EN7523 2022-03-14 8:44 ` Felix Fietkau (?) @ 2022-03-14 8:44 ` Felix Fietkau -1 siblings, 0 replies; 39+ messages in thread From: Felix Fietkau @ 2022-03-14 8:44 UTC (permalink / raw) To: soc, Rob Herring Cc: linux-mediatek, linux-arm-kernel, devicetree, linux-kernel This driver only registers fixed rate clocks, since the clocks are fully initialized by the boot loader and should not be changed later, according to Airoha. Signed-off-by: Felix Fietkau <nbd@nbd.name> --- arch/arm/boot/dts/en7523.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/en7523.dtsi b/arch/arm/boot/dts/en7523.dtsi index 36597f587f46..2e705b87b6c1 100644 --- a/arch/arm/boot/dts/en7523.dtsi +++ b/arch/arm/boot/dts/en7523.dtsi @@ -3,6 +3,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/en7523-clk.h> / { interrupt-parent = <&gic>; @@ -83,6 +84,13 @@ L2_0: l2-cache0 { }; }; + scu: system-controller@1fa20000 { + compatible = "airoha,en7523-scu"; + reg = <0x1fa20000 0x400>, + <0x1fb00000 0x1000>; + #clock-cells = <1>; + }; + gic: interrupt-controller@9000000 { compatible = "arm,gic-v3"; interrupt-controller; -- 2.35.1 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v10 3/6] ARM: dts: add clock support for Airoha EN7523 @ 2022-03-14 8:44 ` Felix Fietkau 0 siblings, 0 replies; 39+ messages in thread From: Felix Fietkau @ 2022-03-14 8:44 UTC (permalink / raw) To: soc, Rob Herring Cc: linux-mediatek, linux-arm-kernel, devicetree, linux-kernel This driver only registers fixed rate clocks, since the clocks are fully initialized by the boot loader and should not be changed later, according to Airoha. Signed-off-by: Felix Fietkau <nbd@nbd.name> --- arch/arm/boot/dts/en7523.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/en7523.dtsi b/arch/arm/boot/dts/en7523.dtsi index 36597f587f46..2e705b87b6c1 100644 --- a/arch/arm/boot/dts/en7523.dtsi +++ b/arch/arm/boot/dts/en7523.dtsi @@ -3,6 +3,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/en7523-clk.h> / { interrupt-parent = <&gic>; @@ -83,6 +84,13 @@ L2_0: l2-cache0 { }; }; + scu: system-controller@1fa20000 { + compatible = "airoha,en7523-scu"; + reg = <0x1fa20000 0x400>, + <0x1fb00000 0x1000>; + #clock-cells = <1>; + }; + gic: interrupt-controller@9000000 { compatible = "arm,gic-v3"; interrupt-controller; -- 2.35.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v10 3/6] ARM: dts: add clock support for Airoha EN7523 @ 2022-03-14 8:44 ` Felix Fietkau 0 siblings, 0 replies; 39+ messages in thread From: Felix Fietkau @ 2022-03-14 8:44 UTC (permalink / raw) To: soc, Rob Herring Cc: linux-mediatek, linux-arm-kernel, devicetree, linux-kernel This driver only registers fixed rate clocks, since the clocks are fully initialized by the boot loader and should not be changed later, according to Airoha. Signed-off-by: Felix Fietkau <nbd@nbd.name> --- arch/arm/boot/dts/en7523.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/en7523.dtsi b/arch/arm/boot/dts/en7523.dtsi index 36597f587f46..2e705b87b6c1 100644 --- a/arch/arm/boot/dts/en7523.dtsi +++ b/arch/arm/boot/dts/en7523.dtsi @@ -3,6 +3,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/en7523-clk.h> / { interrupt-parent = <&gic>; @@ -83,6 +84,13 @@ L2_0: l2-cache0 { }; }; + scu: system-controller@1fa20000 { + compatible = "airoha,en7523-scu"; + reg = <0x1fa20000 0x400>, + <0x1fb00000 0x1000>; + #clock-cells = <1>; + }; + gic: interrupt-controller@9000000 { compatible = "arm,gic-v3"; interrupt-controller; -- 2.35.1 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [PATCH v10 3/6] ARM: dts: add clock support for Airoha EN7523 2022-03-14 8:44 ` Felix Fietkau (?) @ 2022-04-25 11:51 ` Matthias Brugger -1 siblings, 0 replies; 39+ messages in thread From: Matthias Brugger @ 2022-04-25 11:51 UTC (permalink / raw) To: Felix Fietkau, soc, Rob Herring Cc: linux-mediatek, linux-arm-kernel, devicetree, linux-kernel On 14/03/2022 09:44, Felix Fietkau wrote: > This driver only registers fixed rate clocks, since the clocks are fully > initialized by the boot loader and should not be changed later, according > to Airoha. > > Signed-off-by: Felix Fietkau <nbd@nbd.name> Applied, thanks! > --- > arch/arm/boot/dts/en7523.dtsi | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/arm/boot/dts/en7523.dtsi b/arch/arm/boot/dts/en7523.dtsi > index 36597f587f46..2e705b87b6c1 100644 > --- a/arch/arm/boot/dts/en7523.dtsi > +++ b/arch/arm/boot/dts/en7523.dtsi > @@ -3,6 +3,7 @@ > #include <dt-bindings/interrupt-controller/irq.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/clock/en7523-clk.h> > > / { > interrupt-parent = <&gic>; > @@ -83,6 +84,13 @@ L2_0: l2-cache0 { > }; > }; > > + scu: system-controller@1fa20000 { > + compatible = "airoha,en7523-scu"; > + reg = <0x1fa20000 0x400>, > + <0x1fb00000 0x1000>; > + #clock-cells = <1>; > + }; > + > gic: interrupt-controller@9000000 { > compatible = "arm,gic-v3"; > interrupt-controller; ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v10 3/6] ARM: dts: add clock support for Airoha EN7523 @ 2022-04-25 11:51 ` Matthias Brugger 0 siblings, 0 replies; 39+ messages in thread From: Matthias Brugger @ 2022-04-25 11:51 UTC (permalink / raw) To: Felix Fietkau, soc, Rob Herring Cc: linux-mediatek, linux-arm-kernel, devicetree, linux-kernel On 14/03/2022 09:44, Felix Fietkau wrote: > This driver only registers fixed rate clocks, since the clocks are fully > initialized by the boot loader and should not be changed later, according > to Airoha. > > Signed-off-by: Felix Fietkau <nbd@nbd.name> Applied, thanks! > --- > arch/arm/boot/dts/en7523.dtsi | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/arm/boot/dts/en7523.dtsi b/arch/arm/boot/dts/en7523.dtsi > index 36597f587f46..2e705b87b6c1 100644 > --- a/arch/arm/boot/dts/en7523.dtsi > +++ b/arch/arm/boot/dts/en7523.dtsi > @@ -3,6 +3,7 @@ > #include <dt-bindings/interrupt-controller/irq.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/clock/en7523-clk.h> > > / { > interrupt-parent = <&gic>; > @@ -83,6 +84,13 @@ L2_0: l2-cache0 { > }; > }; > > + scu: system-controller@1fa20000 { > + compatible = "airoha,en7523-scu"; > + reg = <0x1fa20000 0x400>, > + <0x1fb00000 0x1000>; > + #clock-cells = <1>; > + }; > + > gic: interrupt-controller@9000000 { > compatible = "arm,gic-v3"; > interrupt-controller; _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v10 3/6] ARM: dts: add clock support for Airoha EN7523 @ 2022-04-25 11:51 ` Matthias Brugger 0 siblings, 0 replies; 39+ messages in thread From: Matthias Brugger @ 2022-04-25 11:51 UTC (permalink / raw) To: Felix Fietkau, soc, Rob Herring Cc: linux-mediatek, linux-arm-kernel, devicetree, linux-kernel On 14/03/2022 09:44, Felix Fietkau wrote: > This driver only registers fixed rate clocks, since the clocks are fully > initialized by the boot loader and should not be changed later, according > to Airoha. > > Signed-off-by: Felix Fietkau <nbd@nbd.name> Applied, thanks! > --- > arch/arm/boot/dts/en7523.dtsi | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/arm/boot/dts/en7523.dtsi b/arch/arm/boot/dts/en7523.dtsi > index 36597f587f46..2e705b87b6c1 100644 > --- a/arch/arm/boot/dts/en7523.dtsi > +++ b/arch/arm/boot/dts/en7523.dtsi > @@ -3,6 +3,7 @@ > #include <dt-bindings/interrupt-controller/irq.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/clock/en7523-clk.h> > > / { > interrupt-parent = <&gic>; > @@ -83,6 +84,13 @@ L2_0: l2-cache0 { > }; > }; > > + scu: system-controller@1fa20000 { > + compatible = "airoha,en7523-scu"; > + reg = <0x1fa20000 0x400>, > + <0x1fb00000 0x1000>; > + #clock-cells = <1>; > + }; > + > gic: interrupt-controller@9000000 { > compatible = "arm,gic-v3"; > interrupt-controller; _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v10 4/6] dt-bindings: PCI: Add support for Airoha EN7532 2022-03-14 8:44 ` Felix Fietkau (?) @ 2022-03-14 8:44 ` Felix Fietkau -1 siblings, 0 replies; 39+ messages in thread From: Felix Fietkau @ 2022-03-14 8:44 UTC (permalink / raw) To: soc, Ryder Lee, Jianjun Wang, Bjorn Helgaas, Rob Herring, Matthias Brugger Cc: linux-mediatek, linux-arm-kernel, John Crispin, Rob Herring, linux-pci, devicetree, linux-kernel From: John Crispin <john@phrozen.org> EN7532 is an ARM based platform SoC integrating the same PCIe IP as MT7622, add a binding for it. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Felix Fietkau <nbd@nbd.name> --- Documentation/devicetree/bindings/pci/mediatek-pcie.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt index 57ae73462272..684227522267 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt @@ -7,6 +7,7 @@ Required properties: "mediatek,mt7622-pcie" "mediatek,mt7623-pcie" "mediatek,mt7629-pcie" + "airoha,en7523-pcie" - device_type: Must be "pci" - reg: Base addresses and lengths of the root ports. - reg-names: Names of the above areas to use during resource lookup. -- 2.35.1 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v10 4/6] dt-bindings: PCI: Add support for Airoha EN7532 @ 2022-03-14 8:44 ` Felix Fietkau 0 siblings, 0 replies; 39+ messages in thread From: Felix Fietkau @ 2022-03-14 8:44 UTC (permalink / raw) To: soc, Ryder Lee, Jianjun Wang, Bjorn Helgaas, Rob Herring, Matthias Brugger Cc: linux-mediatek, linux-arm-kernel, John Crispin, Rob Herring, linux-pci, devicetree, linux-kernel From: John Crispin <john@phrozen.org> EN7532 is an ARM based platform SoC integrating the same PCIe IP as MT7622, add a binding for it. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Felix Fietkau <nbd@nbd.name> --- Documentation/devicetree/bindings/pci/mediatek-pcie.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt index 57ae73462272..684227522267 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt @@ -7,6 +7,7 @@ Required properties: "mediatek,mt7622-pcie" "mediatek,mt7623-pcie" "mediatek,mt7629-pcie" + "airoha,en7523-pcie" - device_type: Must be "pci" - reg: Base addresses and lengths of the root ports. - reg-names: Names of the above areas to use during resource lookup. -- 2.35.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v10 4/6] dt-bindings: PCI: Add support for Airoha EN7532 @ 2022-03-14 8:44 ` Felix Fietkau 0 siblings, 0 replies; 39+ messages in thread From: Felix Fietkau @ 2022-03-14 8:44 UTC (permalink / raw) To: soc, Ryder Lee, Jianjun Wang, Bjorn Helgaas, Rob Herring, Matthias Brugger Cc: linux-mediatek, linux-arm-kernel, John Crispin, Rob Herring, linux-pci, devicetree, linux-kernel From: John Crispin <john@phrozen.org> EN7532 is an ARM based platform SoC integrating the same PCIe IP as MT7622, add a binding for it. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Felix Fietkau <nbd@nbd.name> --- Documentation/devicetree/bindings/pci/mediatek-pcie.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt index 57ae73462272..684227522267 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt @@ -7,6 +7,7 @@ Required properties: "mediatek,mt7622-pcie" "mediatek,mt7623-pcie" "mediatek,mt7629-pcie" + "airoha,en7523-pcie" - device_type: Must be "pci" - reg: Base addresses and lengths of the root ports. - reg-names: Names of the above areas to use during resource lookup. -- 2.35.1 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v10 5/6] PCI: mediatek: Allow building for ARCH_AIROHA 2022-03-14 8:44 ` Felix Fietkau (?) @ 2022-03-14 8:44 ` Felix Fietkau -1 siblings, 0 replies; 39+ messages in thread From: Felix Fietkau @ 2022-03-14 8:44 UTC (permalink / raw) To: soc, Lorenzo Pieralisi, Rob Herring, Krzysztof Wilczyński, Bjorn Helgaas, Matthias Brugger Cc: linux-mediatek, linux-arm-kernel, linux-pci, linux-kernel Allow selecting the pcie-mediatek driver if ARCH_AIROHA is set, because the Airoha EN7523 SoC uses the same controller as MT7622. The driver itself is not modified. The PCIe controller DT node should use mediatek,mt7622-pcie after airoha,en7523-pcie. Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Felix Fietkau <nbd@nbd.name> --- drivers/pci/controller/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index 601f2531ee91..17d9635c7038 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -233,7 +233,7 @@ config PCIE_ROCKCHIP_EP config PCIE_MEDIATEK tristate "MediaTek PCIe controller" - depends on ARCH_MEDIATEK || COMPILE_TEST + depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST depends on OF depends on PCI_MSI_IRQ_DOMAIN help -- 2.35.1 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v10 5/6] PCI: mediatek: Allow building for ARCH_AIROHA @ 2022-03-14 8:44 ` Felix Fietkau 0 siblings, 0 replies; 39+ messages in thread From: Felix Fietkau @ 2022-03-14 8:44 UTC (permalink / raw) To: soc, Lorenzo Pieralisi, Rob Herring, Krzysztof Wilczyński, Bjorn Helgaas, Matthias Brugger Cc: linux-mediatek, linux-arm-kernel, linux-pci, linux-kernel Allow selecting the pcie-mediatek driver if ARCH_AIROHA is set, because the Airoha EN7523 SoC uses the same controller as MT7622. The driver itself is not modified. The PCIe controller DT node should use mediatek,mt7622-pcie after airoha,en7523-pcie. Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Felix Fietkau <nbd@nbd.name> --- drivers/pci/controller/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index 601f2531ee91..17d9635c7038 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -233,7 +233,7 @@ config PCIE_ROCKCHIP_EP config PCIE_MEDIATEK tristate "MediaTek PCIe controller" - depends on ARCH_MEDIATEK || COMPILE_TEST + depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST depends on OF depends on PCI_MSI_IRQ_DOMAIN help -- 2.35.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v10 5/6] PCI: mediatek: Allow building for ARCH_AIROHA @ 2022-03-14 8:44 ` Felix Fietkau 0 siblings, 0 replies; 39+ messages in thread From: Felix Fietkau @ 2022-03-14 8:44 UTC (permalink / raw) To: soc, Lorenzo Pieralisi, Rob Herring, Krzysztof Wilczyński, Bjorn Helgaas, Matthias Brugger Cc: linux-mediatek, linux-arm-kernel, linux-pci, linux-kernel Allow selecting the pcie-mediatek driver if ARCH_AIROHA is set, because the Airoha EN7523 SoC uses the same controller as MT7622. The driver itself is not modified. The PCIe controller DT node should use mediatek,mt7622-pcie after airoha,en7523-pcie. Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Felix Fietkau <nbd@nbd.name> --- drivers/pci/controller/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index 601f2531ee91..17d9635c7038 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -233,7 +233,7 @@ config PCIE_ROCKCHIP_EP config PCIE_MEDIATEK tristate "MediaTek PCIe controller" - depends on ARCH_MEDIATEK || COMPILE_TEST + depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST depends on OF depends on PCI_MSI_IRQ_DOMAIN help -- 2.35.1 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v10 6/6] ARM: dts: Add PCIe support for Airoha EN7523 2022-03-14 8:44 ` Felix Fietkau (?) @ 2022-03-14 8:44 ` Felix Fietkau -1 siblings, 0 replies; 39+ messages in thread From: Felix Fietkau @ 2022-03-14 8:44 UTC (permalink / raw) To: soc, Rob Herring, Matthias Brugger Cc: linux-mediatek, linux-arm-kernel, devicetree, linux-kernel This uses the MediaTek MT7622 PCIe driver, since the PCIe IP block is nearly identical to the one in MT7622 Signed-off-by: Felix Fietkau <nbd@nbd.name> --- arch/arm/boot/dts/en7523-evb.dts | 8 +++++ arch/arm/boot/dts/en7523.dtsi | 58 ++++++++++++++++++++++++++++++++ 2 files changed, 66 insertions(+) diff --git a/arch/arm/boot/dts/en7523-evb.dts b/arch/arm/boot/dts/en7523-evb.dts index a8d8bb0419a0..f23a25cce119 100644 --- a/arch/arm/boot/dts/en7523-evb.dts +++ b/arch/arm/boot/dts/en7523-evb.dts @@ -33,3 +33,11 @@ &gpio0 { &gpio1 { status = "okay"; }; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/en7523.dtsi b/arch/arm/boot/dts/en7523.dtsi index 2e705b87b6c1..7f839331a777 100644 --- a/arch/arm/boot/dts/en7523.dtsi +++ b/arch/arm/boot/dts/en7523.dtsi @@ -143,4 +143,62 @@ gpio1: gpio@1fbf0270 { gpio-controller; #gpio-cells = <2>; }; + + pcie0: pcie@1fa91000 { + compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie"; + device_type = "pci"; + reg = <0x1fa91000 0x1000>; + reg-names = "port0"; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pcie_irq"; + clocks = <&scu EN7523_CLK_PCIE>; + clock-names = "sys_ck0"; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x20000000 0x20000000 0 0x8000000>; + status = "disabled"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + pcie1: pcie@1fa92000 { + compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie"; + device_type = "pci"; + reg = <0x1fa92000 0x1000>; + reg-names = "port1"; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pcie_irq"; + clocks = <&scu EN7523_CLK_PCIE>; + clock-names = "sys_ck1"; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x28000000 0x28000000 0 0x8000000>; + status = "disabled"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + pcie_intc1: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; }; -- 2.35.1 ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v10 6/6] ARM: dts: Add PCIe support for Airoha EN7523 @ 2022-03-14 8:44 ` Felix Fietkau 0 siblings, 0 replies; 39+ messages in thread From: Felix Fietkau @ 2022-03-14 8:44 UTC (permalink / raw) To: soc, Rob Herring, Matthias Brugger Cc: linux-mediatek, linux-arm-kernel, devicetree, linux-kernel This uses the MediaTek MT7622 PCIe driver, since the PCIe IP block is nearly identical to the one in MT7622 Signed-off-by: Felix Fietkau <nbd@nbd.name> --- arch/arm/boot/dts/en7523-evb.dts | 8 +++++ arch/arm/boot/dts/en7523.dtsi | 58 ++++++++++++++++++++++++++++++++ 2 files changed, 66 insertions(+) diff --git a/arch/arm/boot/dts/en7523-evb.dts b/arch/arm/boot/dts/en7523-evb.dts index a8d8bb0419a0..f23a25cce119 100644 --- a/arch/arm/boot/dts/en7523-evb.dts +++ b/arch/arm/boot/dts/en7523-evb.dts @@ -33,3 +33,11 @@ &gpio0 { &gpio1 { status = "okay"; }; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/en7523.dtsi b/arch/arm/boot/dts/en7523.dtsi index 2e705b87b6c1..7f839331a777 100644 --- a/arch/arm/boot/dts/en7523.dtsi +++ b/arch/arm/boot/dts/en7523.dtsi @@ -143,4 +143,62 @@ gpio1: gpio@1fbf0270 { gpio-controller; #gpio-cells = <2>; }; + + pcie0: pcie@1fa91000 { + compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie"; + device_type = "pci"; + reg = <0x1fa91000 0x1000>; + reg-names = "port0"; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pcie_irq"; + clocks = <&scu EN7523_CLK_PCIE>; + clock-names = "sys_ck0"; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x20000000 0x20000000 0 0x8000000>; + status = "disabled"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + pcie1: pcie@1fa92000 { + compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie"; + device_type = "pci"; + reg = <0x1fa92000 0x1000>; + reg-names = "port1"; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pcie_irq"; + clocks = <&scu EN7523_CLK_PCIE>; + clock-names = "sys_ck1"; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x28000000 0x28000000 0 0x8000000>; + status = "disabled"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + pcie_intc1: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; }; -- 2.35.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v10 6/6] ARM: dts: Add PCIe support for Airoha EN7523 @ 2022-03-14 8:44 ` Felix Fietkau 0 siblings, 0 replies; 39+ messages in thread From: Felix Fietkau @ 2022-03-14 8:44 UTC (permalink / raw) To: soc, Rob Herring, Matthias Brugger Cc: linux-mediatek, linux-arm-kernel, devicetree, linux-kernel This uses the MediaTek MT7622 PCIe driver, since the PCIe IP block is nearly identical to the one in MT7622 Signed-off-by: Felix Fietkau <nbd@nbd.name> --- arch/arm/boot/dts/en7523-evb.dts | 8 +++++ arch/arm/boot/dts/en7523.dtsi | 58 ++++++++++++++++++++++++++++++++ 2 files changed, 66 insertions(+) diff --git a/arch/arm/boot/dts/en7523-evb.dts b/arch/arm/boot/dts/en7523-evb.dts index a8d8bb0419a0..f23a25cce119 100644 --- a/arch/arm/boot/dts/en7523-evb.dts +++ b/arch/arm/boot/dts/en7523-evb.dts @@ -33,3 +33,11 @@ &gpio0 { &gpio1 { status = "okay"; }; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/en7523.dtsi b/arch/arm/boot/dts/en7523.dtsi index 2e705b87b6c1..7f839331a777 100644 --- a/arch/arm/boot/dts/en7523.dtsi +++ b/arch/arm/boot/dts/en7523.dtsi @@ -143,4 +143,62 @@ gpio1: gpio@1fbf0270 { gpio-controller; #gpio-cells = <2>; }; + + pcie0: pcie@1fa91000 { + compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie"; + device_type = "pci"; + reg = <0x1fa91000 0x1000>; + reg-names = "port0"; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pcie_irq"; + clocks = <&scu EN7523_CLK_PCIE>; + clock-names = "sys_ck0"; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x20000000 0x20000000 0 0x8000000>; + status = "disabled"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + pcie1: pcie@1fa92000 { + compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie"; + device_type = "pci"; + reg = <0x1fa92000 0x1000>; + reg-names = "port1"; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pcie_irq"; + clocks = <&scu EN7523_CLK_PCIE>; + clock-names = "sys_ck1"; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x28000000 0x28000000 0 0x8000000>; + status = "disabled"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + pcie_intc1: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; }; -- 2.35.1 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [PATCH v10 0/6] Clock and PCIe support for Airoha EN7523 SoC 2022-03-14 8:44 ` Felix Fietkau (?) @ 2022-03-15 23:44 ` Stephen Boyd -1 siblings, 0 replies; 39+ messages in thread From: Stephen Boyd @ 2022-03-15 23:44 UTC (permalink / raw) To: Felix Fietkau, Matthias Brugger, soc; +Cc: linux-mediatek, linux-arm-kernel Quoting Felix Fietkau (2022-03-14 01:44:02) > This patchset adds the remaining patches needed from the last Airoha EN7523 > SoC support series Please add a changelog here, preferably with lore links to previous revisions. It helps folks recall the patch series. ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v10 0/6] Clock and PCIe support for Airoha EN7523 SoC @ 2022-03-15 23:44 ` Stephen Boyd 0 siblings, 0 replies; 39+ messages in thread From: Stephen Boyd @ 2022-03-15 23:44 UTC (permalink / raw) To: Felix Fietkau, Matthias Brugger, soc; +Cc: linux-mediatek, linux-arm-kernel Quoting Felix Fietkau (2022-03-14 01:44:02) > This patchset adds the remaining patches needed from the last Airoha EN7523 > SoC support series Please add a changelog here, preferably with lore links to previous revisions. It helps folks recall the patch series. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v10 0/6] Clock and PCIe support for Airoha EN7523 SoC @ 2022-03-15 23:44 ` Stephen Boyd 0 siblings, 0 replies; 39+ messages in thread From: Stephen Boyd @ 2022-03-15 23:44 UTC (permalink / raw) To: Felix Fietkau, Matthias Brugger, soc; +Cc: linux-mediatek, linux-arm-kernel Quoting Felix Fietkau (2022-03-14 01:44:02) > This patchset adds the remaining patches needed from the last Airoha EN7523 > SoC support series Please add a changelog here, preferably with lore links to previous revisions. It helps folks recall the patch series. _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 39+ messages in thread
end of thread, other threads:[~2022-04-25 11:52 UTC | newest] Thread overview: 39+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-03-14 8:44 [PATCH v10 0/6] Clock and PCIe support for Airoha EN7523 SoC Felix Fietkau 2022-03-14 8:44 ` Felix Fietkau 2022-03-14 8:44 ` Felix Fietkau 2022-03-14 8:44 ` [PATCH v10 1/6] dt-bindings: Add en7523-scu device tree binding documentation Felix Fietkau 2022-03-14 8:44 ` Felix Fietkau 2022-03-14 8:44 ` Felix Fietkau 2022-04-23 2:12 ` Stephen Boyd 2022-04-23 2:12 ` Stephen Boyd 2022-04-23 2:12 ` Stephen Boyd 2022-04-23 2:13 ` Stephen Boyd 2022-04-23 2:13 ` Stephen Boyd 2022-04-23 2:13 ` Stephen Boyd 2022-03-14 8:44 ` [PATCH v10 2/6] clk: en7523: Add clock driver for Airoha EN7523 SoC Felix Fietkau 2022-03-14 8:44 ` Felix Fietkau 2022-03-14 8:44 ` Felix Fietkau 2022-03-15 16:34 ` Matthias Brugger 2022-03-15 16:34 ` Matthias Brugger 2022-03-15 16:34 ` Matthias Brugger 2022-04-23 2:13 ` Stephen Boyd 2022-04-23 2:13 ` Stephen Boyd 2022-04-23 2:13 ` Stephen Boyd 2022-03-14 8:44 ` [PATCH v10 3/6] ARM: dts: add clock support for Airoha EN7523 Felix Fietkau 2022-03-14 8:44 ` Felix Fietkau 2022-03-14 8:44 ` Felix Fietkau 2022-04-25 11:51 ` Matthias Brugger 2022-04-25 11:51 ` Matthias Brugger 2022-04-25 11:51 ` Matthias Brugger 2022-03-14 8:44 ` [PATCH v10 4/6] dt-bindings: PCI: Add support for Airoha EN7532 Felix Fietkau 2022-03-14 8:44 ` Felix Fietkau 2022-03-14 8:44 ` Felix Fietkau 2022-03-14 8:44 ` [PATCH v10 5/6] PCI: mediatek: Allow building for ARCH_AIROHA Felix Fietkau 2022-03-14 8:44 ` Felix Fietkau 2022-03-14 8:44 ` Felix Fietkau 2022-03-14 8:44 ` [PATCH v10 6/6] ARM: dts: Add PCIe support for Airoha EN7523 Felix Fietkau 2022-03-14 8:44 ` Felix Fietkau 2022-03-14 8:44 ` Felix Fietkau 2022-03-15 23:44 ` [PATCH v10 0/6] Clock and PCIe support for Airoha EN7523 SoC Stephen Boyd 2022-03-15 23:44 ` Stephen Boyd 2022-03-15 23:44 ` Stephen Boyd
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